1 /******************************************************************************/
3 /* Bypass Control utility, Copyright (c) 2005-20011 Silicom */
5 /* This program is free software; you can redistribute it and/or modify */
6 /* it under the terms of the GNU General Public License as published by */
7 /* the Free Software Foundation, located in the file LICENSE. */
8 /* Copyright(c) 2007 - 2009 Intel Corporation. All rights reserved. */
11 /******************************************************************************/
13 #include <linux/kernel.h> /* We're doing kernel work */
14 #include <linux/module.h> /* Specifically, a module */
16 #include <linux/pci.h>
17 #include <linux/delay.h>
18 #include <linux/netdevice.h>
19 #include <linux/rtnetlink.h>
20 #include <linux/rcupdate.h>
21 #include <linux/etherdevice.h>
23 #include <linux/uaccess.h> /* for get_user and put_user */
24 #include <linux/sched.h>
25 #include <linux/ethtool.h>
26 #include <linux/proc_fs.h>
34 #define BP_MOD_VER "9.0.4"
35 #define BP_MOD_DESCR "Silicom Bypass-SD Control driver"
36 #define BP_SYNC_FLAG 1
40 MODULE_AUTHOR("Anna Lukin, annal@silicom.co.il");
41 MODULE_LICENSE("GPL");
42 MODULE_DESCRIPTION(BP_MOD_DESCR);
43 MODULE_VERSION(BP_MOD_VER);
46 #define unlock_bpctl() \
57 struct bypass_pfs_sd {
59 struct proc_dir_entry *bypass_entry;
65 struct pci_dev *pdev; /* PCI device */
66 struct net_device *ndev; /* net device */
67 unsigned long mem_map;
81 unsigned long bypass_wdt_on_time;
82 uint32_t bypass_timer_interval;
83 struct timer_list bp_timer;
87 enum bp_media_type media_type;
89 struct timer_list bp_tpl_timer;
90 spinlock_t bypass_wr_lock;
97 int (*hard_start_xmit_save) (struct sk_buff *skb,
98 struct net_device *dev);
99 const struct net_device_ops *old_ops;
100 struct net_device_ops new_ops;
101 int bp_self_test_flag;
103 struct bypass_pfs_sd bypass_pfs_set;
107 static struct bpctl_dev *bpctl_dev_arr;
109 static struct semaphore bpctl_sema;
110 static int device_num;
112 static int get_dev_idx(int ifindex);
113 static struct bpctl_dev *get_master_port_fn(struct bpctl_dev *pbpctl_dev);
114 static int disc_status(struct bpctl_dev *pbpctl_dev);
115 static int bypass_status(struct bpctl_dev *pbpctl_dev);
116 static int wdt_timer(struct bpctl_dev *pbpctl_dev, int *time_left);
117 static struct bpctl_dev *get_status_port_fn(struct bpctl_dev *pbpctl_dev);
118 static void if_scan_init(void);
120 int bypass_proc_create_dev_sd(struct bpctl_dev *pbp_device_block);
121 int bypass_proc_remove_dev_sd(struct bpctl_dev *pbp_device_block);
122 int bp_proc_create(void);
124 int is_bypass_fn(struct bpctl_dev *pbpctl_dev);
125 int get_dev_idx_bsf(int bus, int slot, int func);
127 static unsigned long str_to_hex(char *p);
128 static int bp_device_event(struct notifier_block *unused,
129 unsigned long event, void *ptr)
131 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
132 static struct bpctl_dev *pbpctl_dev, *pbpctl_dev_m;
133 int dev_num = 0, ret = 0, ret_d = 0, time_left = 0;
134 /* printk("BP_PROC_SUPPORT event =%d %s %d\n", event,dev->name, dev->ifindex ); */
135 /* return NOTIFY_DONE; */
138 if (event == NETDEV_REGISTER) {
140 struct ethtool_drvinfo drvinfo;
144 int i = 0, ifindex, idx_dev = 0;
145 int bus = 0, slot = 0, func = 0;
146 ifindex = dev->ifindex;
149 memset(&drvinfo, 0, sizeof(struct ethtool_drvinfo));
151 if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
152 memset(&drvinfo, 0, sizeof(drvinfo));
153 dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
156 if (!drvinfo.bus_info)
158 if (!strcmp(drvinfo.bus_info, "N/A"))
160 memcpy(&cbuf, drvinfo.bus_info, 32);
163 while (*buf++ != ':')
165 for (i = 0; i < 10; i++, buf++) {
172 bus = str_to_hex(res);
175 for (i = 0; i < 10; i++, buf++) {
182 slot = str_to_hex(res);
183 func = str_to_hex(buf);
184 idx_dev = get_dev_idx_bsf(bus, slot, func);
188 bpctl_dev_arr[idx_dev].ifindex = ifindex;
189 bpctl_dev_arr[idx_dev].ndev = dev;
191 bypass_proc_remove_dev_sd(&bpctl_dev_arr
193 bypass_proc_create_dev_sd(&bpctl_dev_arr
202 if (event == NETDEV_UNREGISTER) {
205 ((bpctl_dev_arr[idx_dev].pdev != NULL)
206 && (idx_dev < device_num)); idx_dev++) {
207 if (bpctl_dev_arr[idx_dev].ndev == dev) {
208 bypass_proc_remove_dev_sd(&bpctl_dev_arr
210 bpctl_dev_arr[idx_dev].ndev = NULL;
219 if (event == NETDEV_CHANGENAME) {
222 ((bpctl_dev_arr[idx_dev].pdev != NULL)
223 && (idx_dev < device_num)); idx_dev++) {
224 if (bpctl_dev_arr[idx_dev].ndev == dev) {
225 bypass_proc_remove_dev_sd(&bpctl_dev_arr
227 bypass_proc_create_dev_sd(&bpctl_dev_arr
242 if (netif_carrier_ok(dev))
245 if (((dev_num = get_dev_idx(dev->ifindex)) == -1) ||
246 (!(pbpctl_dev = &bpctl_dev_arr[dev_num])))
249 if ((is_bypass_fn(pbpctl_dev)) == 1)
250 pbpctl_dev_m = pbpctl_dev;
252 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
255 ret = bypass_status(pbpctl_dev_m);
257 printk("bpmod: %s is in the Bypass mode now",
259 ret_d = disc_status(pbpctl_dev_m);
262 ("bpmod: %s is in the Disconnect mode now",
265 wdt_timer(pbpctl_dev_m, &time_left);
267 printk("; WDT has expired");
283 static struct notifier_block bp_notifier_block = {
284 .notifier_call = bp_device_event,
287 int is_bypass_fn(struct bpctl_dev *pbpctl_dev);
288 int wdt_time_left(struct bpctl_dev *pbpctl_dev);
290 static void write_pulse(struct bpctl_dev *pbpctl_dev,
291 unsigned int ctrl_ext,
292 unsigned char value, unsigned char len)
294 unsigned char ctrl_val = 0;
295 unsigned int i = len;
296 unsigned int ctrl = 0;
297 struct bpctl_dev *pbpctl_dev_c = NULL;
299 if (pbpctl_dev->bp_i80)
300 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
301 if (pbpctl_dev->bp_540)
302 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
304 if (pbpctl_dev->bp_10g9) {
305 pbpctl_dev_c = get_status_port_fn(pbpctl_dev);
308 ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
312 ctrl_val = (value >> i) & 0x1;
314 if (pbpctl_dev->bp_10g9) {
316 /* To start management : MCLK 1, MDIO 1, output */
318 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext|BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9)); */
319 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
321 BP10G_MDIO_DATA_OUT9);
322 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
323 (ctrl | BP10G_MCLK_DATA_OUT9 |
324 BP10G_MCLK_DIR_OUT9));
326 } else if (pbpctl_dev->bp_fiber5) {
327 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, (ctrl_ext |
328 BPCTLI_CTRL_EXT_MCLK_DIR5
330 BPCTLI_CTRL_EXT_MDIO_DIR5
332 BPCTLI_CTRL_EXT_MDIO_DATA5
334 BPCTLI_CTRL_EXT_MCLK_DATA5));
336 } else if (pbpctl_dev->bp_i80) {
337 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, (ctrl_ext |
338 BPCTLI_CTRL_EXT_MDIO_DIR80
340 BPCTLI_CTRL_EXT_MDIO_DATA80));
342 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, (ctrl |
343 BPCTLI_CTRL_EXT_MCLK_DIR80
345 BPCTLI_CTRL_EXT_MCLK_DATA80));
347 } else if (pbpctl_dev->bp_540) {
348 BP10G_WRITE_REG(pbpctl_dev, ESDP, (ctrl |
357 } else if (pbpctl_dev->bp_10gb) {
358 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
359 (ctrl_ext | BP10GB_MDIO_SET |
366 } else if (!pbpctl_dev->bp_10g)
367 /* To start management : MCLK 1, MDIO 1, output */
368 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
370 BPCTLI_CTRL_EXT_MCLK_DIR |
371 BPCTLI_CTRL_EXT_MDIO_DIR |
372 BPCTLI_CTRL_EXT_MDIO_DATA |
373 BPCTLI_CTRL_EXT_MCLK_DATA));
376 /* To start management : MCLK 1, MDIO 1, output*/
377 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
378 (ctrl_ext | BP10G_MCLK_DATA_OUT
379 | BP10G_MDIO_DATA_OUT));
383 usec_delay(PULSE_TIME);
384 if (pbpctl_dev->bp_10g9) {
386 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, ((ctrl_ext|BP10G_MDIO_DATA_OUT9)&~(BP10G_MCLK_DATA_OUT9))); */
388 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
390 BP10G_MDIO_DATA_OUT9);
391 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
392 (ctrl | BP10G_MCLK_DIR_OUT9) &
393 ~BP10G_MCLK_DATA_OUT9);
395 } else if (pbpctl_dev->bp_fiber5) {
396 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
398 BPCTLI_CTRL_EXT_MCLK_DIR5 |
399 BPCTLI_CTRL_EXT_MDIO_DIR5 |
400 BPCTLI_CTRL_EXT_MDIO_DATA5)
403 (BPCTLI_CTRL_EXT_MCLK_DATA5)));
405 } else if (pbpctl_dev->bp_i80) {
406 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, (ctrl_ext |
407 BPCTLI_CTRL_EXT_MDIO_DIR80
409 BPCTLI_CTRL_EXT_MDIO_DATA80));
410 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
412 BPCTLI_CTRL_EXT_MCLK_DIR80)
415 (BPCTLI_CTRL_EXT_MCLK_DATA80)));
417 } else if (pbpctl_dev->bp_540) {
418 BP10G_WRITE_REG(pbpctl_dev, ESDP,
419 (ctrl | BP540_MDIO_DIR |
424 } else if (pbpctl_dev->bp_10gb) {
426 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
427 (ctrl_ext | BP10GB_MDIO_SET |
434 } else if (!pbpctl_dev->bp_10g)
436 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
438 BPCTLI_CTRL_EXT_MCLK_DIR |
439 BPCTLI_CTRL_EXT_MDIO_DIR |
440 BPCTLI_CTRL_EXT_MDIO_DATA)
443 (BPCTLI_CTRL_EXT_MCLK_DATA)));
446 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
448 BP10G_MDIO_DATA_OUT) &
449 ~(BP10G_MCLK_DATA_OUT)));
452 usec_delay(PULSE_TIME);
455 if (pbpctl_dev->bp_10g9) {
457 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, ((ctrl_ext|BP10G_MCLK_DATA_OUT9)&~BP10G_MDIO_DATA_OUT9)); */
458 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
460 ~BP10G_MDIO_DATA_OUT9));
461 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
462 (ctrl | BP10G_MCLK_DATA_OUT9 |
463 BP10G_MCLK_DIR_OUT9));
465 } else if (pbpctl_dev->bp_fiber5) {
466 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
468 BPCTLI_CTRL_EXT_MCLK_DIR5 |
469 BPCTLI_CTRL_EXT_MDIO_DIR5 |
470 BPCTLI_CTRL_EXT_MCLK_DATA5)
473 (BPCTLI_CTRL_EXT_MDIO_DATA5)));
475 } else if (pbpctl_dev->bp_i80) {
476 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
478 BPCTLI_CTRL_EXT_MDIO_DIR80)
481 (BPCTLI_CTRL_EXT_MDIO_DATA80)));
482 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
484 BPCTLI_CTRL_EXT_MCLK_DIR80 |
485 BPCTLI_CTRL_EXT_MCLK_DATA80));
487 } else if (pbpctl_dev->bp_540) {
488 BP10G_WRITE_REG(pbpctl_dev, ESDP,
489 ((ctrl | BP540_MCLK_DIR |
492 ~(BP540_MDIO_DATA)));
494 } else if (pbpctl_dev->bp_10gb) {
495 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
496 (ctrl_ext | BP10GB_MDIO_CLR |
503 } else if (!pbpctl_dev->bp_10g)
505 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
507 BPCTLI_CTRL_EXT_MCLK_DIR |
508 BPCTLI_CTRL_EXT_MDIO_DIR |
509 BPCTLI_CTRL_EXT_MCLK_DATA)
512 (BPCTLI_CTRL_EXT_MDIO_DATA)));
515 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
517 BP10G_MCLK_DATA_OUT) &
518 ~BP10G_MDIO_DATA_OUT));
521 usec_delay(PULSE_TIME);
522 if (pbpctl_dev->bp_10g9) {
524 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
525 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
527 ~BP10G_MDIO_DATA_OUT9));
528 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
529 ((ctrl | BP10G_MCLK_DIR_OUT9) &
530 ~(BP10G_MCLK_DATA_OUT9)));
532 } else if (pbpctl_dev->bp_fiber5) {
533 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
535 BPCTLI_CTRL_EXT_MCLK_DIR5 |
536 BPCTLI_CTRL_EXT_MDIO_DIR5)
538 ~(BPCTLI_CTRL_EXT_MCLK_DATA5
540 BPCTLI_CTRL_EXT_MDIO_DATA5)));
542 } else if (pbpctl_dev->bp_i80) {
543 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
545 BPCTLI_CTRL_EXT_MDIO_DIR80)
547 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
548 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
550 BPCTLI_CTRL_EXT_MCLK_DIR80)
553 (BPCTLI_CTRL_EXT_MCLK_DATA80)));
555 } else if (pbpctl_dev->bp_540) {
556 BP10G_WRITE_REG(pbpctl_dev, ESDP,
557 ((ctrl | BP540_MCLK_DIR |
561 } else if (pbpctl_dev->bp_10gb) {
563 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
564 (ctrl_ext | BP10GB_MDIO_CLR |
571 } else if (!pbpctl_dev->bp_10g)
572 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
574 BPCTLI_CTRL_EXT_MCLK_DIR |
575 BPCTLI_CTRL_EXT_MDIO_DIR) &
576 ~(BPCTLI_CTRL_EXT_MCLK_DATA
578 BPCTLI_CTRL_EXT_MDIO_DATA)));
581 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
583 ~(BP10G_MCLK_DATA_OUT |
584 BP10G_MDIO_DATA_OUT)));
587 usec_delay(PULSE_TIME);
593 static int read_pulse(struct bpctl_dev *pbpctl_dev, unsigned int ctrl_ext,
596 unsigned char ctrl_val = 0;
597 unsigned int i = len;
598 unsigned int ctrl = 0;
599 struct bpctl_dev *pbpctl_dev_c = NULL;
601 if (pbpctl_dev->bp_i80)
602 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
603 if (pbpctl_dev->bp_540)
604 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
605 if (pbpctl_dev->bp_10g9) {
606 pbpctl_dev_c = get_status_port_fn(pbpctl_dev);
609 ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
614 if (pbpctl_dev->bp_10g9) {
615 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, ((ctrl_ext|BP10G_MDIO_DATA_OUT9)&~BP10G_MCLK_DATA_OUT9)); */
617 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
618 ((ctrl | BP10G_MCLK_DIR_OUT9) &
619 ~(BP10G_MCLK_DATA_OUT9)));
621 } else if (pbpctl_dev->bp_fiber5) {
622 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
623 BPCTLI_CTRL_EXT_MCLK_DIR5)
626 (BPCTLI_CTRL_EXT_MDIO_DIR5
628 BPCTLI_CTRL_EXT_MCLK_DATA5)));
630 } else if (pbpctl_dev->bp_i80) {
631 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
633 ~BPCTLI_CTRL_EXT_MDIO_DIR80));
634 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
635 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80)
636 & ~(BPCTLI_CTRL_EXT_MCLK_DATA80)));
638 } else if (pbpctl_dev->bp_540) {
639 BP10G_WRITE_REG(pbpctl_dev, ESDP,
640 ((ctrl | BP540_MCLK_DIR) &
641 ~(BP540_MDIO_DIR | BP540_MCLK_DATA)));
643 } else if (pbpctl_dev->bp_10gb) {
645 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
646 (ctrl_ext | BP10GB_MDIO_DIR |
647 BP10GB_MCLK_CLR) & ~(BP10GB_MCLK_DIR |
652 } else if (!pbpctl_dev->bp_10g)
653 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
654 BPCTLI_CTRL_EXT_MCLK_DIR)
657 (BPCTLI_CTRL_EXT_MDIO_DIR
659 BPCTLI_CTRL_EXT_MCLK_DATA)));
662 BP10G_WRITE_REG(pbpctl_dev, EODSDP, ((ctrl_ext | BP10G_MDIO_DATA_OUT) & ~BP10G_MCLK_DATA_OUT)); /* ? */
663 /* printk("0x28=0x%x\n",BP10G_READ_REG(pbpctl_dev,EODSDP);); */
667 usec_delay(PULSE_TIME);
668 if (pbpctl_dev->bp_10g9) {
669 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext|BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9)); */
671 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
672 (ctrl | BP10G_MCLK_DATA_OUT9 |
673 BP10G_MCLK_DIR_OUT9));
675 } else if (pbpctl_dev->bp_fiber5) {
676 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
677 BPCTLI_CTRL_EXT_MCLK_DIR5
679 BPCTLI_CTRL_EXT_MCLK_DATA5)
682 (BPCTLI_CTRL_EXT_MDIO_DIR5)));
684 } else if (pbpctl_dev->bp_i80) {
685 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
687 ~(BPCTLI_CTRL_EXT_MDIO_DIR80)));
688 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
689 (ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80 |
690 BPCTLI_CTRL_EXT_MCLK_DATA80));
692 } else if (pbpctl_dev->bp_540) {
693 BP10G_WRITE_REG(pbpctl_dev, ESDP,
694 ((ctrl | BP540_MCLK_DIR |
698 } else if (pbpctl_dev->bp_10gb) {
699 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
700 (ctrl_ext | BP10GB_MDIO_DIR |
701 BP10GB_MCLK_SET) & ~(BP10GB_MCLK_DIR |
706 } else if (!pbpctl_dev->bp_10g)
707 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
708 BPCTLI_CTRL_EXT_MCLK_DIR
710 BPCTLI_CTRL_EXT_MCLK_DATA)
713 (BPCTLI_CTRL_EXT_MDIO_DIR)));
716 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
717 (ctrl_ext | BP10G_MCLK_DATA_OUT |
718 BP10G_MDIO_DATA_OUT));
722 if (pbpctl_dev->bp_10g9)
723 ctrl_ext = BP10G_READ_REG(pbpctl_dev, I2CCTL);
724 else if ((pbpctl_dev->bp_fiber5) || (pbpctl_dev->bp_i80))
725 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
726 else if (pbpctl_dev->bp_540)
727 ctrl_ext = BP10G_READ_REG(pbpctl_dev, ESDP);
728 else if (pbpctl_dev->bp_10gb)
729 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
730 else if (!pbpctl_dev->bp_10g)
731 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
733 ctrl_ext = BP10G_READ_REG(pbpctl_dev, EODSDP);
735 usec_delay(PULSE_TIME);
736 if (pbpctl_dev->bp_10g9) {
737 if (ctrl_ext & BP10G_MDIO_DATA_IN9)
740 } else if (pbpctl_dev->bp_fiber5) {
741 if (ctrl_ext & BPCTLI_CTRL_EXT_MDIO_DATA5)
743 } else if (pbpctl_dev->bp_i80) {
744 if (ctrl_ext & BPCTLI_CTRL_EXT_MDIO_DATA80)
746 } else if (pbpctl_dev->bp_540) {
747 if (ctrl_ext & BP540_MDIO_DATA)
749 } else if (pbpctl_dev->bp_10gb) {
750 if (ctrl_ext & BP10GB_MDIO_DATA)
753 } else if (!pbpctl_dev->bp_10g) {
755 if (ctrl_ext & BPCTLI_CTRL_EXT_MDIO_DATA)
759 if (ctrl_ext & BP10G_MDIO_DATA_IN)
768 static void write_reg(struct bpctl_dev *pbpctl_dev, unsigned char value,
771 uint32_t ctrl_ext = 0, ctrl = 0;
772 struct bpctl_dev *pbpctl_dev_c = NULL;
774 if (pbpctl_dev->bp_10g9) {
775 pbpctl_dev_c = get_status_port_fn(pbpctl_dev);
779 if ((pbpctl_dev->wdt_status == WDT_STATUS_EN) &&
780 (pbpctl_dev->bp_ext_ver < PXG4BPFI_VER))
781 wdt_time_left(pbpctl_dev);
784 spin_lock_irqsave(&pbpctl_dev->bypass_wr_lock, flags);
786 atomic_set(&pbpctl_dev->wdt_busy, 1);
788 if (pbpctl_dev->bp_10g9) {
790 ctrl_ext = BP10G_READ_REG(pbpctl_dev, I2CCTL);
791 ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
793 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
794 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
795 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
796 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
797 ((ctrl | BP10G_MCLK_DIR_OUT9) &
798 ~(BP10G_MCLK_DATA_OUT9)));
800 } else if (pbpctl_dev->bp_fiber5) {
801 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
802 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
803 BPCTLI_CTRL_EXT_MCLK_DIR5
805 BPCTLI_CTRL_EXT_MDIO_DIR5)
808 (BPCTLI_CTRL_EXT_MDIO_DATA5
810 BPCTLI_CTRL_EXT_MCLK_DATA5)));
811 } else if (pbpctl_dev->bp_i80) {
812 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
813 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
814 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
815 BPCTLI_CTRL_EXT_MDIO_DIR80)
817 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
818 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
819 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
820 ~BPCTLI_CTRL_EXT_MCLK_DATA80));
822 } else if (pbpctl_dev->bp_540) {
823 ctrl = ctrl_ext = BP10G_READ_REG(pbpctl_dev, ESDP);
824 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl |
830 } else if (pbpctl_dev->bp_10gb) {
831 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
833 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
834 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
835 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
836 BP10GB_MDIO_SET | BP10GB_MCLK_SET));
838 } else if (!pbpctl_dev->bp_10g) {
840 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
841 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
842 BPCTLI_CTRL_EXT_MCLK_DIR
844 BPCTLI_CTRL_EXT_MDIO_DIR)
847 (BPCTLI_CTRL_EXT_MDIO_DATA
849 BPCTLI_CTRL_EXT_MCLK_DATA)));
851 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
852 ctrl_ext = BP10G_READ_REG(pbpctl_dev, EODSDP);
853 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
855 ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
857 usec_delay(CMND_INTERVAL);
860 write_pulse(pbpctl_dev, ctrl_ext, SYNC_CMD_VAL, SYNC_CMD_LEN);
862 write_pulse(pbpctl_dev, ctrl_ext, WR_CMD_VAL, WR_CMD_LEN);
863 write_pulse(pbpctl_dev, ctrl_ext, addr, ADDR_CMD_LEN);
866 write_pulse(pbpctl_dev, ctrl_ext, value, WR_DATA_LEN);
867 if (pbpctl_dev->bp_10g9) {
868 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
870 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
871 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
872 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
873 ((ctrl | BP10G_MCLK_DIR_OUT9) &
874 ~(BP10G_MCLK_DATA_OUT9)));
876 } else if (pbpctl_dev->bp_fiber5) {
877 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
878 BPCTLI_CTRL_EXT_MCLK_DIR5
880 BPCTLI_CTRL_EXT_MDIO_DIR5)
883 (BPCTLI_CTRL_EXT_MDIO_DATA5
885 BPCTLI_CTRL_EXT_MCLK_DATA5)));
886 } else if (pbpctl_dev->bp_i80) {
887 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
888 BPCTLI_CTRL_EXT_MDIO_DIR80)
890 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
891 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
892 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
893 ~BPCTLI_CTRL_EXT_MCLK_DATA80));
894 } else if (pbpctl_dev->bp_540) {
895 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl |
900 } else if (pbpctl_dev->bp_10gb) {
901 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
902 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
903 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
904 BP10GB_MDIO_SET | BP10GB_MCLK_SET));
906 } else if (!pbpctl_dev->bp_10g)
908 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
909 BPCTLI_CTRL_EXT_MCLK_DIR
911 BPCTLI_CTRL_EXT_MDIO_DIR)
914 (BPCTLI_CTRL_EXT_MDIO_DATA
916 BPCTLI_CTRL_EXT_MCLK_DATA)));
918 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
920 ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
924 usec_delay(CMND_INTERVAL * 4);
926 if ((pbpctl_dev->wdt_status == WDT_STATUS_EN) &&
927 (pbpctl_dev->bp_ext_ver < PXG4BPFI_VER) && (addr == CMND_REG_ADDR))
928 pbpctl_dev->bypass_wdt_on_time = jiffies;
930 spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
932 atomic_set(&pbpctl_dev->wdt_busy, 0);
937 static void write_data(struct bpctl_dev *pbpctl_dev, unsigned char value)
939 write_reg(pbpctl_dev, value, CMND_REG_ADDR);
942 static int read_reg(struct bpctl_dev *pbpctl_dev, unsigned char addr)
944 uint32_t ctrl_ext = 0, ctrl = 0, ctrl_value = 0;
945 struct bpctl_dev *pbpctl_dev_c = NULL;
949 spin_lock_irqsave(&pbpctl_dev->bypass_wr_lock, flags);
951 atomic_set(&pbpctl_dev->wdt_busy, 1);
953 if (pbpctl_dev->bp_10g9) {
954 pbpctl_dev_c = get_status_port_fn(pbpctl_dev);
959 if (pbpctl_dev->bp_10g9) {
960 ctrl_ext = BP10G_READ_REG(pbpctl_dev, I2CCTL);
961 ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
963 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
965 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
966 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
967 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
968 ((ctrl | BP10G_MCLK_DIR_OUT9) &
969 ~(BP10G_MCLK_DATA_OUT9)));
971 } else if (pbpctl_dev->bp_fiber5) {
972 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
974 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
975 BPCTLI_CTRL_EXT_MCLK_DIR5
977 BPCTLI_CTRL_EXT_MDIO_DIR5)
980 (BPCTLI_CTRL_EXT_MDIO_DATA5
982 BPCTLI_CTRL_EXT_MCLK_DATA5)));
983 } else if (pbpctl_dev->bp_i80) {
984 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
985 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
987 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
988 BPCTLI_CTRL_EXT_MDIO_DIR80)
990 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
991 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
992 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
993 ~BPCTLI_CTRL_EXT_MCLK_DATA80));
994 } else if (pbpctl_dev->bp_540) {
995 ctrl_ext = BP10G_READ_REG(pbpctl_dev, ESDP);
996 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
998 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl | BP540_MCLK_DIR |
1002 } else if (pbpctl_dev->bp_10gb) {
1003 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1005 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1006 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
1007 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
1008 BP10GB_MDIO_SET | BP10GB_MCLK_SET));
1011 /*BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO, (ctrl_ext | BP10GB_MCLK_DIR | BP10GB_MDIO_DIR|
1012 BP10GB_MCLK_CLR|BP10GB_MDIO_CLR));
1013 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1014 printk("1reg=%x\n", ctrl_ext); */
1016 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO, ((ctrl_ext |
1019 & ~(BP10GB_MCLK_CLR | BP10GB_MDIO_SET |
1020 BP10GB_MCLK_DIR | BP10GB_MDIO_DIR));
1022 /* bnx2x_set_spio(pbpctl_dev, 5, MISC_REGISTERS_SPIO_OUTPUT_LOW);
1023 bnx2x_set_spio(pbpctl_dev, 4, MISC_REGISTERS_SPIO_OUTPUT_LOW);
1024 bnx2x_set_spio(pbpctl_dev, 4, MISC_REGISTERS_SPIO_INPUT_HI_Z); */
1026 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1028 printk("2reg=%x\n", ctrl_ext);
1031 spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
1033 atomic_set(&pbpctl_dev->wdt_busy, 0);
1040 } else if (!pbpctl_dev->bp_10g) {
1042 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1044 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1045 BPCTLI_CTRL_EXT_MCLK_DIR
1047 BPCTLI_CTRL_EXT_MDIO_DIR)
1050 (BPCTLI_CTRL_EXT_MDIO_DATA
1052 BPCTLI_CTRL_EXT_MCLK_DATA)));
1055 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1056 ctrl_ext = BP10G_READ_REG(pbpctl_dev, EODSDP);
1057 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1059 ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
1063 usec_delay(CMND_INTERVAL);
1066 write_pulse(pbpctl_dev, ctrl_ext, SYNC_CMD_VAL, SYNC_CMD_LEN);
1068 write_pulse(pbpctl_dev, ctrl_ext, RD_CMD_VAL, RD_CMD_LEN);
1070 write_pulse(pbpctl_dev, ctrl_ext, addr, ADDR_CMD_LEN);
1073 if (pbpctl_dev->bp_10g9) {
1075 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext|BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9)); */
1076 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1077 (ctrl_ext | BP10G_MDIO_DATA_OUT9));
1078 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1079 (ctrl | BP10G_MCLK_DATA_OUT9 |
1080 BP10G_MCLK_DIR_OUT9));
1082 } else if (pbpctl_dev->bp_fiber5) {
1083 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1084 BPCTLI_CTRL_EXT_MCLK_DIR5
1086 BPCTLI_CTRL_EXT_MCLK_DATA5)
1089 (BPCTLI_CTRL_EXT_MDIO_DIR5
1091 BPCTLI_CTRL_EXT_MDIO_DATA5)));
1093 } else if (pbpctl_dev->bp_i80) {
1094 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
1096 ~(BPCTLI_CTRL_EXT_MDIO_DATA80 |
1097 BPCTLI_CTRL_EXT_MDIO_DIR80)));
1098 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1099 (ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80 |
1100 BPCTLI_CTRL_EXT_MCLK_DATA80));
1102 } else if (pbpctl_dev->bp_540) {
1103 BP10G_WRITE_REG(pbpctl_dev, ESDP,
1104 (((ctrl | BP540_MDIO_DIR | BP540_MCLK_DIR |
1105 BP540_MCLK_DATA) & ~BP540_MDIO_DATA)));
1107 } else if (pbpctl_dev->bp_10gb) {
1109 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1110 (ctrl_ext | BP10GB_MDIO_DIR | BP10GB_MCLK_SET)
1111 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_SET |
1112 BP10GB_MDIO_CLR | BP10GB_MCLK_CLR));
1114 } else if (!pbpctl_dev->bp_10g)
1115 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1116 BPCTLI_CTRL_EXT_MCLK_DIR
1118 BPCTLI_CTRL_EXT_MCLK_DATA)
1121 (BPCTLI_CTRL_EXT_MDIO_DIR
1123 BPCTLI_CTRL_EXT_MDIO_DATA)));
1126 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1127 (ctrl_ext | BP10G_MCLK_DATA_OUT |
1128 BP10G_MDIO_DATA_OUT));
1132 usec_delay(PULSE_TIME);
1134 ctrl_value = read_pulse(pbpctl_dev, ctrl_ext, RD_DATA_LEN);
1136 if (pbpctl_dev->bp_10g9) {
1137 ctrl_ext = BP10G_READ_REG(pbpctl_dev, I2CCTL);
1138 ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
1140 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
1142 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1143 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
1144 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1145 ((ctrl | BP10G_MCLK_DIR_OUT9) &
1146 ~(BP10G_MCLK_DATA_OUT9)));
1148 } else if (pbpctl_dev->bp_fiber5) {
1149 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1150 BPCTLI_CTRL_EXT_MCLK_DIR5
1152 BPCTLI_CTRL_EXT_MDIO_DIR5)
1155 (BPCTLI_CTRL_EXT_MDIO_DATA5
1157 BPCTLI_CTRL_EXT_MCLK_DATA5)));
1158 } else if (pbpctl_dev->bp_i80) {
1159 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1160 BPCTLI_CTRL_EXT_MDIO_DIR80)
1162 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
1163 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1164 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
1165 ~BPCTLI_CTRL_EXT_MCLK_DATA80));
1167 } else if (pbpctl_dev->bp_540) {
1168 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1169 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl | BP540_MCLK_DIR |
1174 } else if (pbpctl_dev->bp_10gb) {
1175 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1176 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1177 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
1178 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
1179 BP10GB_MDIO_SET | BP10GB_MCLK_SET));
1181 } else if (!pbpctl_dev->bp_10g) {
1182 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1183 BPCTLI_CTRL_EXT_MCLK_DIR
1185 BPCTLI_CTRL_EXT_MDIO_DIR)
1188 (BPCTLI_CTRL_EXT_MDIO_DATA
1190 BPCTLI_CTRL_EXT_MCLK_DATA)));
1193 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1194 ctrl_ext = BP10G_READ_REG(pbpctl_dev, EODSDP);
1195 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1197 ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
1201 usec_delay(CMND_INTERVAL * 4);
1203 spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
1205 atomic_set(&pbpctl_dev->wdt_busy, 0);
1211 static int wdt_pulse(struct bpctl_dev *pbpctl_dev)
1213 uint32_t ctrl_ext = 0, ctrl = 0;
1214 struct bpctl_dev *pbpctl_dev_c = NULL;
1217 unsigned long flags;
1219 spin_lock_irqsave(&pbpctl_dev->bypass_wr_lock, flags);
1222 if ((atomic_read(&pbpctl_dev->wdt_busy)) == 1)
1225 if (pbpctl_dev->bp_10g9) {
1226 pbpctl_dev_c = get_status_port_fn(pbpctl_dev);
1231 if (pbpctl_dev->bp_10g9) {
1232 ctrl_ext = BP10G_READ_REG(pbpctl_dev, I2CCTL);
1233 ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
1235 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
1237 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1238 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
1239 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1240 ((ctrl | BP10G_MCLK_DIR_OUT9) &
1241 ~(BP10G_MCLK_DATA_OUT9)));
1243 } else if (pbpctl_dev->bp_fiber5) {
1244 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
1245 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1246 BPCTLI_CTRL_EXT_MCLK_DIR5
1248 BPCTLI_CTRL_EXT_MDIO_DIR5)
1251 (BPCTLI_CTRL_EXT_MDIO_DATA5
1253 BPCTLI_CTRL_EXT_MCLK_DATA5)));
1254 } else if (pbpctl_dev->bp_i80) {
1255 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
1256 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1257 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1258 BPCTLI_CTRL_EXT_MDIO_DIR80)
1260 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
1261 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1262 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
1263 ~BPCTLI_CTRL_EXT_MCLK_DATA80));
1264 } else if (pbpctl_dev->bp_540) {
1265 ctrl_ext = ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1266 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl | BP540_MCLK_DIR |
1270 } else if (pbpctl_dev->bp_10gb) {
1271 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1272 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1273 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
1274 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
1275 BP10GB_MDIO_SET | BP10GB_MCLK_SET));
1277 } else if (!pbpctl_dev->bp_10g) {
1279 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1280 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1281 BPCTLI_CTRL_EXT_MCLK_DIR
1283 BPCTLI_CTRL_EXT_MDIO_DIR)
1286 (BPCTLI_CTRL_EXT_MDIO_DATA
1288 BPCTLI_CTRL_EXT_MCLK_DATA)));
1291 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1292 ctrl_ext = BP10G_READ_REG(pbpctl_dev, EODSDP);
1293 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1295 ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
1298 if (pbpctl_dev->bp_10g9) {
1299 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, ((ctrl_ext|BP10G_MCLK_DATA_OUT9)&~BP10G_MDIO_DATA_OUT9)); */
1301 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1302 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
1303 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1304 (ctrl | BP10G_MCLK_DATA_OUT9 |
1305 BP10G_MCLK_DIR_OUT9));
1307 } else if (pbpctl_dev->bp_fiber5) {
1308 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1309 BPCTLI_CTRL_EXT_MCLK_DIR5
1311 BPCTLI_CTRL_EXT_MDIO_DIR5
1313 BPCTLI_CTRL_EXT_MCLK_DATA5)
1316 (BPCTLI_CTRL_EXT_MDIO_DATA5)));
1317 } else if (pbpctl_dev->bp_i80) {
1318 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1319 BPCTLI_CTRL_EXT_MDIO_DIR80)
1321 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
1322 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1323 (ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80 |
1324 BPCTLI_CTRL_EXT_MCLK_DATA80));
1326 } else if (pbpctl_dev->bp_540) {
1327 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl |
1333 } else if (pbpctl_dev->bp_10gb) {
1334 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1336 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1337 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_SET)
1338 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
1339 BP10GB_MDIO_SET | BP10GB_MCLK_CLR));
1341 } else if (!pbpctl_dev->bp_10g)
1342 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1343 BPCTLI_CTRL_EXT_MCLK_DIR
1345 BPCTLI_CTRL_EXT_MDIO_DIR
1347 BPCTLI_CTRL_EXT_MCLK_DATA)
1350 (BPCTLI_CTRL_EXT_MDIO_DATA)));
1353 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1354 ((ctrl_ext | BP10G_MCLK_DATA_OUT) &
1355 ~BP10G_MDIO_DATA_OUT));
1359 usec_delay(WDT_INTERVAL);
1360 if (pbpctl_dev->bp_10g9) {
1361 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
1363 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1364 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
1365 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1366 ((ctrl | BP10G_MCLK_DIR_OUT9) &
1367 ~(BP10G_MCLK_DATA_OUT9)));
1369 } else if (pbpctl_dev->bp_fiber5) {
1370 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1371 BPCTLI_CTRL_EXT_MCLK_DIR5
1373 BPCTLI_CTRL_EXT_MDIO_DIR5)
1376 (BPCTLI_CTRL_EXT_MCLK_DATA5
1378 BPCTLI_CTRL_EXT_MDIO_DATA5)));
1379 } else if (pbpctl_dev->bp_i80) {
1380 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1381 BPCTLI_CTRL_EXT_MDIO_DIR80)
1383 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
1384 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1385 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
1386 ~BPCTLI_CTRL_EXT_MCLK_DATA80));
1388 } else if (pbpctl_dev->bp_540) {
1389 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl | BP540_MCLK_DIR |
1394 } else if (pbpctl_dev->bp_10gb) {
1395 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1396 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1397 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
1398 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
1399 BP10GB_MDIO_SET | BP10GB_MCLK_SET));
1401 } else if (!pbpctl_dev->bp_10g)
1402 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1403 BPCTLI_CTRL_EXT_MCLK_DIR
1405 BPCTLI_CTRL_EXT_MDIO_DIR)
1408 (BPCTLI_CTRL_EXT_MCLK_DATA
1410 BPCTLI_CTRL_EXT_MDIO_DATA)));
1413 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1415 ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
1417 if ((pbpctl_dev->wdt_status == WDT_STATUS_EN))
1418 /*&& (pbpctl_dev->bp_ext_ver<PXG4BPFI_VER) */
1419 pbpctl_dev->bypass_wdt_on_time = jiffies;
1421 spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
1423 usec_delay(CMND_INTERVAL * 4);
1427 static void data_pulse(struct bpctl_dev *pbpctl_dev, unsigned char value)
1430 uint32_t ctrl_ext = 0;
1432 unsigned long flags;
1434 wdt_time_left(pbpctl_dev);
1436 spin_lock_irqsave(&pbpctl_dev->bypass_wr_lock, flags);
1438 atomic_set(&pbpctl_dev->wdt_busy, 1);
1441 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1442 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1443 BPCTLI_CTRL_EXT_SDP6_DIR |
1444 BPCTLI_CTRL_EXT_SDP7_DIR) &
1445 ~(BPCTLI_CTRL_EXT_SDP6_DATA |
1446 BPCTLI_CTRL_EXT_SDP7_DATA)));
1448 usec_delay(INIT_CMND_INTERVAL);
1449 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1450 BPCTLI_CTRL_EXT_SDP6_DIR |
1451 BPCTLI_CTRL_EXT_SDP7_DIR |
1452 BPCTLI_CTRL_EXT_SDP6_DATA) &
1454 (BPCTLI_CTRL_EXT_SDP7_DATA)));
1455 usec_delay(INIT_CMND_INTERVAL);
1458 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ctrl_ext |
1459 BPCTLI_CTRL_EXT_SDP6_DIR |
1460 BPCTLI_CTRL_EXT_SDP7_DIR |
1461 BPCTLI_CTRL_EXT_SDP6_DATA |
1462 BPCTLI_CTRL_EXT_SDP7_DATA);
1463 usec_delay(PULSE_INTERVAL);
1464 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1465 BPCTLI_CTRL_EXT_SDP6_DIR
1467 BPCTLI_CTRL_EXT_SDP7_DIR
1469 BPCTLI_CTRL_EXT_SDP6_DATA)
1471 ~BPCTLI_CTRL_EXT_SDP7_DATA));
1472 usec_delay(PULSE_INTERVAL);
1476 usec_delay(INIT_CMND_INTERVAL - PULSE_INTERVAL);
1477 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1478 BPCTLI_CTRL_EXT_SDP6_DIR |
1479 BPCTLI_CTRL_EXT_SDP7_DIR) &
1480 ~(BPCTLI_CTRL_EXT_SDP6_DATA |
1481 BPCTLI_CTRL_EXT_SDP7_DATA)));
1482 usec_delay(WDT_TIME_CNT);
1483 if (pbpctl_dev->wdt_status == WDT_STATUS_EN)
1484 pbpctl_dev->bypass_wdt_on_time = jiffies;
1486 spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
1488 atomic_set(&pbpctl_dev->wdt_busy, 0);
1493 static int send_wdt_pulse(struct bpctl_dev *pbpctl_dev)
1495 uint32_t ctrl_ext = 0;
1498 unsigned long flags;
1500 spin_lock_irqsave(&pbpctl_dev->bypass_wr_lock, flags);
1503 if ((atomic_read(&pbpctl_dev->wdt_busy)) == 1)
1506 wdt_time_left(pbpctl_dev);
1507 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1509 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ctrl_ext | /* 1 */
1510 BPCTLI_CTRL_EXT_SDP7_DIR |
1511 BPCTLI_CTRL_EXT_SDP7_DATA);
1512 usec_delay(PULSE_INTERVAL);
1513 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext | /* 0 */
1514 BPCTLI_CTRL_EXT_SDP7_DIR) &
1515 ~BPCTLI_CTRL_EXT_SDP7_DATA));
1517 usec_delay(PULSE_INTERVAL);
1518 if (pbpctl_dev->wdt_status == WDT_STATUS_EN)
1519 pbpctl_dev->bypass_wdt_on_time = jiffies;
1521 spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
1527 void send_bypass_clear_pulse(struct bpctl_dev *pbpctl_dev, unsigned int value)
1529 uint32_t ctrl_ext = 0;
1531 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1532 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext | /* 0 */
1533 BPCTLI_CTRL_EXT_SDP6_DIR) &
1534 ~BPCTLI_CTRL_EXT_SDP6_DATA));
1536 usec_delay(PULSE_INTERVAL);
1538 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ctrl_ext | /* 1 */
1539 BPCTLI_CTRL_EXT_SDP6_DIR |
1540 BPCTLI_CTRL_EXT_SDP6_DATA);
1541 usec_delay(PULSE_INTERVAL);
1544 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext | /* 0 */
1545 BPCTLI_CTRL_EXT_SDP6_DIR) &
1546 ~BPCTLI_CTRL_EXT_SDP6_DATA));
1547 usec_delay(PULSE_INTERVAL);
1553 int pulse_set_fn(struct bpctl_dev *pbpctl_dev, unsigned int counter)
1555 uint32_t ctrl_ext = 0;
1560 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1561 write_pulse_1(pbpctl_dev, ctrl_ext, counter, counter);
1563 pbpctl_dev->bypass_wdt_status = 0;
1564 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1565 write_pulse_1(pbpctl_dev, ctrl_ext, counter, counter);
1567 wdt_time_left(pbpctl_dev);
1568 if (pbpctl_dev->wdt_status == WDT_STATUS_EN) {
1569 pbpctl_dev->wdt_status = 0;
1570 data_pulse(pbpctl_dev, counter);
1571 pbpctl_dev->wdt_status = WDT_STATUS_EN;
1572 pbpctl_dev->bypass_wdt_on_time = jiffies;
1575 data_pulse(pbpctl_dev, counter);
1581 int zero_set_fn(struct bpctl_dev *pbpctl_dev)
1583 uint32_t ctrl_ext = 0, ctrl_value = 0;
1587 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1590 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1592 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1593 BPCTLI_CTRL_EXT_MCLK_DIR)
1596 (BPCTLI_CTRL_EXT_MCLK_DATA
1598 BPCTLI_CTRL_EXT_MDIO_DIR
1600 BPCTLI_CTRL_EXT_MDIO_DATA)));
1606 int pulse_get2_fn(struct bpctl_dev *pbpctl_dev)
1608 uint32_t ctrl_ext = 0, ctrl_value = 0;
1612 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1613 printk("pulse_get_fn\n");
1614 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1615 ctrl_value = read_pulse_2(pbpctl_dev, ctrl_ext);
1616 printk("read:%d\n", ctrl_value);
1621 int pulse_get1_fn(struct bpctl_dev *pbpctl_dev)
1623 uint32_t ctrl_ext = 0, ctrl_value = 0;
1627 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1629 printk("pulse_get_fn\n");
1631 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1632 ctrl_value = read_pulse_1(pbpctl_dev, ctrl_ext);
1633 printk("read:%d\n", ctrl_value);
1638 int gpio6_set_fn(struct bpctl_dev *pbpctl_dev)
1640 uint32_t ctrl_ext = 0;
1642 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1643 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ctrl_ext |
1644 BPCTLI_CTRL_EXT_SDP6_DIR |
1645 BPCTLI_CTRL_EXT_SDP6_DATA);
1649 int gpio7_set_fn(struct bpctl_dev *pbpctl_dev)
1651 uint32_t ctrl_ext = 0;
1653 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1654 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ctrl_ext |
1655 BPCTLI_CTRL_EXT_SDP7_DIR |
1656 BPCTLI_CTRL_EXT_SDP7_DATA);
1660 int gpio7_clear_fn(struct bpctl_dev *pbpctl_dev)
1662 uint32_t ctrl_ext = 0;
1664 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1665 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1666 BPCTLI_CTRL_EXT_SDP7_DIR) &
1667 ~BPCTLI_CTRL_EXT_SDP7_DATA));
1671 int gpio6_clear_fn(struct bpctl_dev *pbpctl_dev)
1673 uint32_t ctrl_ext = 0;
1675 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1676 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1677 BPCTLI_CTRL_EXT_SDP6_DIR) &
1678 ~BPCTLI_CTRL_EXT_SDP6_DATA));
1681 #endif /*BYPASS_DEBUG */
1683 static struct bpctl_dev *lookup_port(struct bpctl_dev *dev)
1685 struct bpctl_dev *p;
1687 for (n = 0, p = bpctl_dev_arr; n < device_num && p->pdev; n++) {
1688 if (p->bus == dev->bus
1689 && p->slot == dev->slot
1690 && p->func == (dev->func ^ 1))
1696 static struct bpctl_dev *get_status_port_fn(struct bpctl_dev *pbpctl_dev)
1699 if (pbpctl_dev->func == 0 || pbpctl_dev->func == 2)
1700 return lookup_port(pbpctl_dev);
1705 static struct bpctl_dev *get_master_port_fn(struct bpctl_dev *pbpctl_dev)
1708 if (pbpctl_dev->func == 1 || pbpctl_dev->func == 3)
1709 return lookup_port(pbpctl_dev);
1714 /**************************************/
1715 /**************INTEL API***************/
1716 /**************************************/
1718 static void write_data_port_int(struct bpctl_dev *pbpctl_dev,
1719 unsigned char ctrl_value)
1723 value = BPCTL_READ_REG(pbpctl_dev, CTRL);
1724 /* Make SDP0 Pin Directonality to Output */
1725 value |= BPCTLI_CTRL_SDP0_DIR;
1726 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, value);
1728 value &= ~BPCTLI_CTRL_SDP0_DATA;
1729 value |= ((ctrl_value & 0x1) << BPCTLI_CTRL_SDP0_SHIFT);
1730 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, value);
1732 value = (BPCTL_READ_REG(pbpctl_dev, CTRL_EXT));
1733 /* Make SDP2 Pin Directonality to Output */
1734 value |= BPCTLI_CTRL_EXT_SDP6_DIR;
1735 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, value);
1737 value &= ~BPCTLI_CTRL_EXT_SDP6_DATA;
1738 value |= (((ctrl_value & 0x2) >> 1) << BPCTLI_CTRL_EXT_SDP6_SHIFT);
1739 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, value);
1743 static int write_data_int(struct bpctl_dev *pbpctl_dev, unsigned char value)
1745 struct bpctl_dev *pbpctl_dev_b = NULL;
1747 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
1750 atomic_set(&pbpctl_dev->wdt_busy, 1);
1751 write_data_port_int(pbpctl_dev, value & 0x3);
1752 write_data_port_int(pbpctl_dev_b, ((value & 0xc) >> 2));
1753 atomic_set(&pbpctl_dev->wdt_busy, 0);
1758 static int wdt_pulse_int(struct bpctl_dev *pbpctl_dev)
1761 if ((atomic_read(&pbpctl_dev->wdt_busy)) == 1)
1764 if ((write_data_int(pbpctl_dev, RESET_WDT_INT)) < 0)
1766 msec_delay_bp(CMND_INTERVAL_INT);
1767 if ((write_data_int(pbpctl_dev, CMND_OFF_INT)) < 0)
1769 msec_delay_bp(CMND_INTERVAL_INT);
1771 if (pbpctl_dev->wdt_status == WDT_STATUS_EN)
1772 pbpctl_dev->bypass_wdt_on_time = jiffies;
1777 /*************************************/
1778 /************* COMMANDS **************/
1779 /*************************************/
1781 /* CMND_ON 0x4 (100)*/
1782 int cmnd_on(struct bpctl_dev *pbpctl_dev)
1784 int ret = BP_NOT_CAP;
1786 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
1787 if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
1789 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER)
1790 write_data(pbpctl_dev, CMND_ON);
1792 data_pulse(pbpctl_dev, CMND_ON);
1798 /* CMND_OFF 0x2 (10)*/
1799 int cmnd_off(struct bpctl_dev *pbpctl_dev)
1801 int ret = BP_NOT_CAP;
1803 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
1804 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
1805 write_data_int(pbpctl_dev, CMND_OFF_INT);
1806 msec_delay_bp(CMND_INTERVAL_INT);
1807 } else if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER)
1808 write_data(pbpctl_dev, CMND_OFF);
1810 data_pulse(pbpctl_dev, CMND_OFF);
1816 /* BYPASS_ON (0xa)*/
1817 int bypass_on(struct bpctl_dev *pbpctl_dev)
1819 int ret = BP_NOT_CAP;
1821 if (pbpctl_dev->bp_caps & BP_CAP) {
1822 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
1823 write_data_int(pbpctl_dev, BYPASS_ON_INT);
1824 msec_delay_bp(BYPASS_DELAY_INT);
1825 pbpctl_dev->bp_status_un = 0;
1826 } else if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1827 write_data(pbpctl_dev, BYPASS_ON);
1828 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
1829 msec_delay_bp(LATCH_DELAY);
1831 data_pulse(pbpctl_dev, BYPASS_ON);
1837 /* BYPASS_OFF (0x8 111)*/
1838 int bypass_off(struct bpctl_dev *pbpctl_dev)
1840 int ret = BP_NOT_CAP;
1842 if (pbpctl_dev->bp_caps & BP_CAP) {
1843 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
1844 write_data_int(pbpctl_dev, DIS_BYPASS_CAP_INT);
1845 msec_delay_bp(BYPASS_DELAY_INT);
1846 write_data_int(pbpctl_dev, PWROFF_BYPASS_ON_INT);
1847 msec_delay_bp(BYPASS_DELAY_INT);
1848 pbpctl_dev->bp_status_un = 0;
1849 } else if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1850 write_data(pbpctl_dev, BYPASS_OFF);
1851 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
1852 msec_delay_bp(LATCH_DELAY);
1854 data_pulse(pbpctl_dev, BYPASS_OFF);
1861 int tap_off(struct bpctl_dev *pbpctl_dev)
1863 int ret = BP_NOT_CAP;
1864 if ((pbpctl_dev->bp_caps & TAP_CAP)
1865 && (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)) {
1866 write_data(pbpctl_dev, TAP_OFF);
1867 msec_delay_bp(LATCH_DELAY);
1874 int tap_on(struct bpctl_dev *pbpctl_dev)
1876 int ret = BP_NOT_CAP;
1877 if ((pbpctl_dev->bp_caps & TAP_CAP)
1878 && (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)) {
1879 write_data(pbpctl_dev, TAP_ON);
1880 msec_delay_bp(LATCH_DELAY);
1887 int disc_off(struct bpctl_dev *pbpctl_dev)
1890 if ((pbpctl_dev->bp_caps & DISC_CAP) && (pbpctl_dev->bp_ext_ver >= 0x8)) {
1891 write_data(pbpctl_dev, DISC_OFF);
1892 msec_delay_bp(LATCH_DELAY);
1899 int disc_on(struct bpctl_dev *pbpctl_dev)
1902 if ((pbpctl_dev->bp_caps & DISC_CAP) && (pbpctl_dev->bp_ext_ver >= 0x8)) {
1903 write_data(pbpctl_dev, /*DISC_ON */ 0x85);
1904 msec_delay_bp(LATCH_DELAY);
1911 int disc_port_on(struct bpctl_dev *pbpctl_dev)
1914 struct bpctl_dev *pbpctl_dev_m;
1916 if ((is_bypass_fn(pbpctl_dev)) == 1)
1917 pbpctl_dev_m = pbpctl_dev;
1919 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
1920 if (pbpctl_dev_m == NULL)
1923 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
1924 if (is_bypass_fn(pbpctl_dev) == 1)
1925 write_data(pbpctl_dev_m, TX_DISA);
1927 write_data(pbpctl_dev_m, TX_DISB);
1929 msec_delay_bp(LATCH_DELAY);
1936 int disc_port_off(struct bpctl_dev *pbpctl_dev)
1939 struct bpctl_dev *pbpctl_dev_m;
1941 if ((is_bypass_fn(pbpctl_dev)) == 1)
1942 pbpctl_dev_m = pbpctl_dev;
1944 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
1945 if (pbpctl_dev_m == NULL)
1948 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
1949 if (is_bypass_fn(pbpctl_dev) == 1)
1950 write_data(pbpctl_dev_m, TX_ENA);
1952 write_data(pbpctl_dev_m, TX_ENB);
1954 msec_delay_bp(LATCH_DELAY);
1960 /*TWO_PORT_LINK_HW_EN (0xe)*/
1961 int tpl_hw_on(struct bpctl_dev *pbpctl_dev)
1963 int ret = 0, ctrl = 0;
1964 struct bpctl_dev *pbpctl_dev_b = NULL;
1966 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
1970 if (pbpctl_dev->bp_caps_ex & TPL2_CAP_EX) {
1971 cmnd_on(pbpctl_dev);
1972 write_data(pbpctl_dev, TPL2_ON);
1973 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
1974 cmnd_off(pbpctl_dev);
1978 if (TPL_IF_SERIES(pbpctl_dev->subdevice)) {
1979 ctrl = BPCTL_READ_REG(pbpctl_dev_b, CTRL);
1980 BPCTL_BP_WRITE_REG(pbpctl_dev_b, CTRL,
1981 ((ctrl | BPCTLI_CTRL_SWDPIO0) &
1982 ~BPCTLI_CTRL_SWDPIN0));
1988 /*TWO_PORT_LINK_HW_DIS (0xc)*/
1989 int tpl_hw_off(struct bpctl_dev *pbpctl_dev)
1991 int ret = 0, ctrl = 0;
1992 struct bpctl_dev *pbpctl_dev_b = NULL;
1994 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
1997 if (pbpctl_dev->bp_caps_ex & TPL2_CAP_EX) {
1998 cmnd_on(pbpctl_dev);
1999 write_data(pbpctl_dev, TPL2_OFF);
2000 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2001 cmnd_off(pbpctl_dev);
2004 if (TPL_IF_SERIES(pbpctl_dev->subdevice)) {
2005 ctrl = BPCTL_READ_REG(pbpctl_dev_b, CTRL);
2006 BPCTL_BP_WRITE_REG(pbpctl_dev_b, CTRL,
2007 (ctrl | BPCTLI_CTRL_SWDPIO0 |
2008 BPCTLI_CTRL_SWDPIN0));
2014 /* WDT_OFF (0x6 110)*/
2015 int wdt_off(struct bpctl_dev *pbpctl_dev)
2017 int ret = BP_NOT_CAP;
2019 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
2020 if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
2021 bypass_off(pbpctl_dev);
2022 else if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER)
2023 write_data(pbpctl_dev, WDT_OFF);
2025 data_pulse(pbpctl_dev, WDT_OFF);
2026 pbpctl_dev->wdt_status = WDT_STATUS_DIS;
2036 wdt_val_array[] = { 1000, 1500, 2000, 3000, 4000, 8000, 16000, 32000, 0 };
2038 int wdt_on(struct bpctl_dev *pbpctl_dev, unsigned int timeout)
2041 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
2042 unsigned int pulse = 0, temp_value = 0, temp_cnt = 0;
2043 pbpctl_dev->wdt_status = 0;
2045 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2046 for (; wdt_val_array[temp_cnt]; temp_cnt++)
2047 if (timeout <= wdt_val_array[temp_cnt])
2050 if (!wdt_val_array[temp_cnt])
2053 timeout = wdt_val_array[temp_cnt];
2056 write_data_int(pbpctl_dev, DIS_BYPASS_CAP_INT);
2057 msec_delay_bp(BYPASS_DELAY_INT);
2058 pbpctl_dev->bp_status_un = 0;
2059 write_data_int(pbpctl_dev, temp_cnt);
2060 pbpctl_dev->bypass_wdt_on_time = jiffies;
2061 msec_delay_bp(CMND_INTERVAL_INT);
2062 pbpctl_dev->bypass_timer_interval = timeout;
2066 TIMEOUT_UNIT ? TIMEOUT_UNIT : (timeout >
2070 temp_value = timeout / 100;
2071 while ((temp_value >>= 1))
2073 if (timeout > ((1 << temp_cnt) * 100))
2075 pbpctl_dev->bypass_wdt_on_time = jiffies;
2076 pulse = (WDT_ON | temp_cnt);
2077 if (pbpctl_dev->bp_ext_ver == OLD_IF_VER)
2078 data_pulse(pbpctl_dev, pulse);
2080 write_data(pbpctl_dev, pulse);
2081 pbpctl_dev->bypass_timer_interval =
2082 (1 << temp_cnt) * 100;
2084 pbpctl_dev->wdt_status = WDT_STATUS_EN;
2090 void bp75_put_hw_semaphore_generic(struct bpctl_dev *pbpctl_dev)
2094 swsm = BPCTL_READ_REG(pbpctl_dev, SWSM);
2096 swsm &= ~(BPCTLI_SWSM_SMBI | BPCTLI_SWSM_SWESMBI);
2098 BPCTL_WRITE_REG(pbpctl_dev, SWSM, swsm);
2101 s32 bp75_get_hw_semaphore_generic(struct bpctl_dev *pbpctl_dev)
2105 s32 timeout = 8192 + 1;
2108 /* Get the SW semaphore */
2109 while (i < timeout) {
2110 swsm = BPCTL_READ_REG(pbpctl_dev, SWSM);
2111 if (!(swsm & BPCTLI_SWSM_SMBI))
2120 ("bpctl_mod: Driver can't access device - SMBI bit is set.\n");
2125 /* Get the FW semaphore. */
2126 for (i = 0; i < timeout; i++) {
2127 swsm = BPCTL_READ_REG(pbpctl_dev, SWSM);
2128 BPCTL_WRITE_REG(pbpctl_dev, SWSM, swsm | BPCTLI_SWSM_SWESMBI);
2130 /* Semaphore acquired if bit latched */
2131 if (BPCTL_READ_REG(pbpctl_dev, SWSM) & BPCTLI_SWSM_SWESMBI)
2138 /* Release semaphores */
2139 bp75_put_hw_semaphore_generic(pbpctl_dev);
2140 printk("bpctl_mod: Driver can't access the NVM\n");
2149 static void bp75_release_phy(struct bpctl_dev *pbpctl_dev)
2151 u16 mask = BPCTLI_SWFW_PHY0_SM;
2155 if ((pbpctl_dev->func == 1) || (pbpctl_dev->func == 3))
2156 mask = BPCTLI_SWFW_PHY1_SM;
2159 ret_val = bp75_get_hw_semaphore_generic(pbpctl_dev);
2160 while (ret_val != 0);
2162 swfw_sync = BPCTL_READ_REG(pbpctl_dev, SW_FW_SYNC);
2164 BPCTL_WRITE_REG(pbpctl_dev, SW_FW_SYNC, swfw_sync);
2166 bp75_put_hw_semaphore_generic(pbpctl_dev);
2169 static s32 bp75_acquire_phy(struct bpctl_dev *pbpctl_dev)
2171 u16 mask = BPCTLI_SWFW_PHY0_SM;
2176 s32 i = 0, timeout = 200;
2178 if ((pbpctl_dev->func == 1) || (pbpctl_dev->func == 3))
2179 mask = BPCTLI_SWFW_PHY1_SM;
2182 fwmask = mask << 16;
2184 while (i < timeout) {
2185 if (bp75_get_hw_semaphore_generic(pbpctl_dev)) {
2190 swfw_sync = BPCTL_READ_REG(pbpctl_dev, SW_FW_SYNC);
2191 if (!(swfw_sync & (fwmask | swmask)))
2194 bp75_put_hw_semaphore_generic(pbpctl_dev);
2201 ("bpctl_mod: Driver can't access resource, SW_FW_SYNC timeout.\n");
2206 swfw_sync |= swmask;
2207 BPCTL_WRITE_REG(pbpctl_dev, SW_FW_SYNC, swfw_sync);
2209 bp75_put_hw_semaphore_generic(pbpctl_dev);
2215 s32 bp75_read_phy_reg_mdic(struct bpctl_dev *pbpctl_dev, u32 offset, u16 *data)
2221 mdic = ((offset << BPCTLI_MDIC_REG_SHIFT) |
2222 (phy_addr << BPCTLI_MDIC_PHY_SHIFT) | (BPCTLI_MDIC_OP_READ));
2224 BPCTL_WRITE_REG(pbpctl_dev, MDIC, mdic);
2226 for (i = 0; i < (BPCTLI_GEN_POLL_TIMEOUT * 3); i++) {
2228 mdic = BPCTL_READ_REG(pbpctl_dev, MDIC);
2229 if (mdic & BPCTLI_MDIC_READY)
2232 if (!(mdic & BPCTLI_MDIC_READY)) {
2233 printk("bpctl_mod: MDI Read did not complete\n");
2237 if (mdic & BPCTLI_MDIC_ERROR) {
2238 printk("bpctl_mod: MDI Error\n");
2248 s32 bp75_write_phy_reg_mdic(struct bpctl_dev *pbpctl_dev, u32 offset, u16 data)
2254 mdic = (((u32) data) |
2255 (offset << BPCTLI_MDIC_REG_SHIFT) |
2256 (phy_addr << BPCTLI_MDIC_PHY_SHIFT) | (BPCTLI_MDIC_OP_WRITE));
2258 BPCTL_WRITE_REG(pbpctl_dev, MDIC, mdic);
2260 for (i = 0; i < (BPCTLI_GEN_POLL_TIMEOUT * 3); i++) {
2262 mdic = BPCTL_READ_REG(pbpctl_dev, MDIC);
2263 if (mdic & BPCTLI_MDIC_READY)
2266 if (!(mdic & BPCTLI_MDIC_READY)) {
2267 printk("bpctl_mod: MDI Write did not complete\n");
2271 if (mdic & BPCTLI_MDIC_ERROR) {
2272 printk("bpctl_mod: MDI Error\n");
2281 static s32 bp75_read_phy_reg(struct bpctl_dev *pbpctl_dev, u32 offset, u16 *data)
2285 ret_val = bp75_acquire_phy(pbpctl_dev);
2289 if (offset > BPCTLI_MAX_PHY_MULTI_PAGE_REG) {
2290 ret_val = bp75_write_phy_reg_mdic(pbpctl_dev,
2291 BPCTLI_IGP01E1000_PHY_PAGE_SELECT,
2298 bp75_read_phy_reg_mdic(pbpctl_dev,
2299 BPCTLI_MAX_PHY_REG_ADDRESS & offset, data);
2302 bp75_release_phy(pbpctl_dev);
2307 static s32 bp75_write_phy_reg(struct bpctl_dev *pbpctl_dev, u32 offset, u16 data)
2311 ret_val = bp75_acquire_phy(pbpctl_dev);
2315 if (offset > BPCTLI_MAX_PHY_MULTI_PAGE_REG) {
2316 ret_val = bp75_write_phy_reg_mdic(pbpctl_dev,
2317 BPCTLI_IGP01E1000_PHY_PAGE_SELECT,
2324 bp75_write_phy_reg_mdic(pbpctl_dev,
2325 BPCTLI_MAX_PHY_REG_ADDRESS & offset, data);
2328 bp75_release_phy(pbpctl_dev);
2334 /* SET_TX (non-Bypass command :)) */
2335 static int set_tx(struct bpctl_dev *pbpctl_dev, int tx_state)
2337 int ret = 0, ctrl = 0;
2338 struct bpctl_dev *pbpctl_dev_m;
2339 if ((is_bypass_fn(pbpctl_dev)) == 1)
2340 pbpctl_dev_m = pbpctl_dev;
2342 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
2343 if (pbpctl_dev_m == NULL)
2345 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
2346 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL);
2348 if (pbpctl_dev->bp_540) {
2349 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
2350 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2351 (ctrl | BP10G_SDP1_DIR |
2355 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2356 (ctrl | BPCTLI_CTRL_SDP1_DIR
2357 | BPCTLI_CTRL_SWDPIN1));
2360 if (pbpctl_dev->bp_540) {
2361 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
2362 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2363 ((ctrl | BP10G_SDP1_DIR) &
2366 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2368 BPCTLI_CTRL_SDP1_DIR) &
2369 ~BPCTLI_CTRL_SWDPIN1));
2374 } else if (pbpctl_dev->bp_caps & TX_CTL_CAP) {
2375 if (PEG5_IF_SERIES(pbpctl_dev->subdevice)) {
2380 bp75_read_phy_reg(pbpctl_dev,
2383 if (mii_reg & BPCTLI_MII_CR_POWER_DOWN) {
2389 ~BPCTLI_MII_CR_POWER_DOWN);
2396 bp75_read_phy_reg(pbpctl_dev,
2400 mii_reg |= BPCTLI_MII_CR_POWER_DOWN;
2402 bp75_write_phy_reg(pbpctl_dev,
2409 if (pbpctl_dev->bp_fiber5)
2410 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
2411 else if (pbpctl_dev->bp_10gb)
2412 ctrl = BP10GB_READ_REG(pbpctl_dev, MISC_REG_GPIO);
2413 else if (!pbpctl_dev->bp_10g)
2414 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL);
2416 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
2419 if (pbpctl_dev->bp_10g9) {
2420 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2421 (ctrl | BP10G_SDP3_DATA |
2424 } else if (pbpctl_dev->bp_fiber5) {
2425 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
2427 BPCTLI_CTRL_EXT_SDP6_DIR |
2428 BPCTLI_CTRL_EXT_SDP6_DATA));
2430 } else if (pbpctl_dev->bp_10gb) {
2431 if ((pbpctl_dev->func == 1)
2432 || (pbpctl_dev->func == 3))
2433 BP10GB_WRITE_REG(pbpctl_dev,
2436 BP10GB_GPIO0_SET_P1) &
2437 ~(BP10GB_GPIO0_CLR_P1 |
2438 BP10GB_GPIO0_OE_P1));
2440 BP10GB_WRITE_REG(pbpctl_dev,
2443 BP10GB_GPIO0_OE_P0 |
2444 BP10GB_GPIO0_SET_P0));
2446 } else if (pbpctl_dev->bp_i80) {
2447 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2448 (ctrl | BPCTLI_CTRL_SDP1_DIR
2449 | BPCTLI_CTRL_SWDPIN1));
2451 } else if (pbpctl_dev->bp_540) {
2452 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
2453 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2454 (ctrl | BP10G_SDP1_DIR |
2459 else if (!pbpctl_dev->bp_10g)
2460 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2461 (ctrl | BPCTLI_CTRL_SWDPIO0 |
2462 BPCTLI_CTRL_SWDPIN0));
2465 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2466 (ctrl | BP10G_SDP0_DATA |
2470 if (pbpctl_dev->bp_10g9) {
2471 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2472 ((ctrl | BP10G_SDP3_DIR) &
2475 } else if (pbpctl_dev->bp_fiber5) {
2476 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
2478 BPCTLI_CTRL_EXT_SDP6_DIR) &
2479 ~BPCTLI_CTRL_EXT_SDP6_DATA));
2481 } else if (pbpctl_dev->bp_10gb) {
2482 if ((bpctl_dev_arr->func == 1)
2483 || (bpctl_dev_arr->func == 3))
2484 BP10GB_WRITE_REG(pbpctl_dev,
2487 BP10GB_GPIO0_CLR_P1) &
2488 ~(BP10GB_GPIO0_SET_P1 |
2489 BP10GB_GPIO0_OE_P1));
2491 BP10GB_WRITE_REG(pbpctl_dev,
2494 BP10GB_GPIO0_OE_P0 |
2495 BP10GB_GPIO0_CLR_P0));
2497 } else if (pbpctl_dev->bp_i80) {
2498 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2500 BPCTLI_CTRL_SDP1_DIR) &
2501 ~BPCTLI_CTRL_SWDPIN1));
2502 } else if (pbpctl_dev->bp_540) {
2503 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
2504 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2505 ((ctrl | BP10G_SDP1_DIR) &
2509 else if (!pbpctl_dev->bp_10g) {
2510 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2511 ((ctrl | BPCTLI_CTRL_SWDPIO0)
2512 & ~BPCTLI_CTRL_SWDPIN0));
2513 if (!PEGF_IF_SERIES(pbpctl_dev->subdevice)) {
2514 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2517 (BPCTLI_CTRL_SDP0_DATA
2519 BPCTLI_CTRL_SDP0_DIR)));
2522 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2523 ((ctrl | BP10G_SDP0_DIR) &
2534 /* SET_FORCE_LINK (non-Bypass command :)) */
2535 static int set_bp_force_link(struct bpctl_dev *pbpctl_dev, int tx_state)
2537 int ret = 0, ctrl = 0;
2539 if (DBI_IF_SERIES(pbpctl_dev->subdevice)) {
2541 if ((pbpctl_dev->bp_10g) || (pbpctl_dev->bp_10g9)) {
2543 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL);
2545 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2546 ctrl & ~BP10G_SDP1_DIR);
2548 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2549 ((ctrl | BP10G_SDP1_DIR) &
2558 /*RESET_CONT 0x20 */
2559 int reset_cont(struct bpctl_dev *pbpctl_dev)
2561 int ret = BP_NOT_CAP;
2563 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
2564 if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
2566 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER)
2567 write_data(pbpctl_dev, RESET_CONT);
2569 data_pulse(pbpctl_dev, RESET_CONT);
2575 /*DIS_BYPASS_CAP 0x22 */
2576 int dis_bypass_cap(struct bpctl_dev *pbpctl_dev)
2579 if (pbpctl_dev->bp_caps & BP_DIS_CAP) {
2580 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2581 write_data_int(pbpctl_dev, DIS_BYPASS_CAP_INT);
2582 msec_delay_bp(BYPASS_DELAY_INT);
2584 write_data(pbpctl_dev, BYPASS_OFF);
2585 msec_delay_bp(LATCH_DELAY);
2586 write_data(pbpctl_dev, DIS_BYPASS_CAP);
2587 msec_delay_bp(BYPASS_CAP_DELAY);
2594 /*EN_BYPASS_CAP 0x24 */
2595 int en_bypass_cap(struct bpctl_dev *pbpctl_dev)
2597 if (pbpctl_dev->bp_caps & BP_DIS_CAP) {
2598 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2599 write_data_int(pbpctl_dev, PWROFF_BYPASS_ON_INT);
2600 msec_delay_bp(BYPASS_DELAY_INT);
2602 write_data(pbpctl_dev, EN_BYPASS_CAP);
2603 msec_delay_bp(BYPASS_CAP_DELAY);
2610 /* BYPASS_STATE_PWRON 0x26*/
2611 int bypass_state_pwron(struct bpctl_dev *pbpctl_dev)
2613 if (pbpctl_dev->bp_caps & BP_PWUP_CTL_CAP) {
2614 write_data(pbpctl_dev, BYPASS_STATE_PWRON);
2615 if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
2616 msec_delay_bp(DFLT_PWRON_DELAY);
2618 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2624 /* NORMAL_STATE_PWRON 0x28*/
2625 int normal_state_pwron(struct bpctl_dev *pbpctl_dev)
2627 if ((pbpctl_dev->bp_caps & BP_PWUP_CTL_CAP)
2628 || (pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP)) {
2629 write_data(pbpctl_dev, NORMAL_STATE_PWRON);
2630 if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
2631 msec_delay_bp(DFLT_PWRON_DELAY);
2633 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2639 /* BYPASS_STATE_PWROFF 0x27*/
2640 int bypass_state_pwroff(struct bpctl_dev *pbpctl_dev)
2642 if (pbpctl_dev->bp_caps & BP_PWOFF_CTL_CAP) {
2643 write_data(pbpctl_dev, BYPASS_STATE_PWROFF);
2644 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2650 /* NORMAL_STATE_PWROFF 0x29*/
2651 int normal_state_pwroff(struct bpctl_dev *pbpctl_dev)
2653 if ((pbpctl_dev->bp_caps & BP_PWOFF_CTL_CAP)) {
2654 write_data(pbpctl_dev, NORMAL_STATE_PWROFF);
2655 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2661 /*TAP_STATE_PWRON 0x2a*/
2662 int tap_state_pwron(struct bpctl_dev *pbpctl_dev)
2664 if (pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP) {
2665 write_data(pbpctl_dev, TAP_STATE_PWRON);
2666 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2672 /*DIS_TAP_CAP 0x2c*/
2673 int dis_tap_cap(struct bpctl_dev *pbpctl_dev)
2675 if (pbpctl_dev->bp_caps & TAP_DIS_CAP) {
2676 write_data(pbpctl_dev, DIS_TAP_CAP);
2677 msec_delay_bp(BYPASS_CAP_DELAY);
2684 int en_tap_cap(struct bpctl_dev *pbpctl_dev)
2686 if (pbpctl_dev->bp_caps & TAP_DIS_CAP) {
2687 write_data(pbpctl_dev, EN_TAP_CAP);
2688 msec_delay_bp(BYPASS_CAP_DELAY);
2694 /*DISC_STATE_PWRON 0x2a*/
2695 int disc_state_pwron(struct bpctl_dev *pbpctl_dev)
2697 if (pbpctl_dev->bp_caps & DISC_PWUP_CTL_CAP) {
2698 if (pbpctl_dev->bp_ext_ver >= 0x8) {
2699 write_data(pbpctl_dev, DISC_STATE_PWRON);
2700 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2707 /*DIS_DISC_CAP 0x2c*/
2708 int dis_disc_cap(struct bpctl_dev *pbpctl_dev)
2710 if (pbpctl_dev->bp_caps & DISC_DIS_CAP) {
2711 if (pbpctl_dev->bp_ext_ver >= 0x8) {
2712 write_data(pbpctl_dev, DIS_DISC_CAP);
2713 msec_delay_bp(BYPASS_CAP_DELAY);
2720 /*DISC_STATE_PWRON 0x2a*/
2721 int disc_port_state_pwron(struct bpctl_dev *pbpctl_dev)
2724 struct bpctl_dev *pbpctl_dev_m;
2728 if ((is_bypass_fn(pbpctl_dev)) == 1)
2729 pbpctl_dev_m = pbpctl_dev;
2731 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
2732 if (pbpctl_dev_m == NULL)
2735 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
2736 if (is_bypass_fn(pbpctl_dev) == 1)
2737 write_data(pbpctl_dev_m, TX_DISA_PWRUP);
2739 write_data(pbpctl_dev_m, TX_DISB_PWRUP);
2741 msec_delay_bp(LATCH_DELAY);
2747 int normal_port_state_pwron(struct bpctl_dev *pbpctl_dev)
2750 struct bpctl_dev *pbpctl_dev_m;
2753 if ((is_bypass_fn(pbpctl_dev)) == 1)
2754 pbpctl_dev_m = pbpctl_dev;
2756 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
2757 if (pbpctl_dev_m == NULL)
2760 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
2761 if (is_bypass_fn(pbpctl_dev) == 1)
2762 write_data(pbpctl_dev_m, TX_ENA_PWRUP);
2764 write_data(pbpctl_dev_m, TX_ENB_PWRUP);
2766 msec_delay_bp(LATCH_DELAY);
2773 int en_disc_cap(struct bpctl_dev *pbpctl_dev)
2775 if (pbpctl_dev->bp_caps & DISC_DIS_CAP) {
2776 if (pbpctl_dev->bp_ext_ver >= 0x8) {
2777 write_data(pbpctl_dev, EN_DISC_CAP);
2778 msec_delay_bp(BYPASS_CAP_DELAY);
2785 int std_nic_on(struct bpctl_dev *pbpctl_dev)
2788 if (pbpctl_dev->bp_caps & STD_NIC_CAP) {
2790 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2791 write_data_int(pbpctl_dev, DIS_BYPASS_CAP_INT);
2792 msec_delay_bp(BYPASS_DELAY_INT);
2793 pbpctl_dev->bp_status_un = 0;
2797 if (pbpctl_dev->bp_ext_ver >= 0x8) {
2798 write_data(pbpctl_dev, STD_NIC_ON);
2799 msec_delay_bp(BYPASS_CAP_DELAY);
2804 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
2805 wdt_off(pbpctl_dev);
2807 if (pbpctl_dev->bp_caps & BP_CAP) {
2808 write_data(pbpctl_dev, BYPASS_OFF);
2809 msec_delay_bp(LATCH_DELAY);
2812 if (pbpctl_dev->bp_caps & TAP_CAP) {
2813 write_data(pbpctl_dev, TAP_OFF);
2814 msec_delay_bp(LATCH_DELAY);
2817 write_data(pbpctl_dev, NORMAL_STATE_PWRON);
2818 if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
2819 msec_delay_bp(DFLT_PWRON_DELAY);
2821 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2823 if (pbpctl_dev->bp_caps & BP_DIS_CAP) {
2824 write_data(pbpctl_dev, DIS_BYPASS_CAP);
2825 msec_delay_bp(BYPASS_CAP_DELAY);
2828 if (pbpctl_dev->bp_caps & TAP_DIS_CAP) {
2829 write_data(pbpctl_dev, DIS_TAP_CAP);
2830 msec_delay_bp(BYPASS_CAP_DELAY);
2839 int std_nic_off(struct bpctl_dev *pbpctl_dev)
2842 if (pbpctl_dev->bp_caps & STD_NIC_CAP) {
2843 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2844 write_data_int(pbpctl_dev, PWROFF_BYPASS_ON_INT);
2845 msec_delay_bp(BYPASS_DELAY_INT);
2848 if (pbpctl_dev->bp_ext_ver >= 0x8) {
2849 write_data(pbpctl_dev, STD_NIC_OFF);
2850 msec_delay_bp(BYPASS_CAP_DELAY);
2855 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
2857 if (pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP) {
2858 write_data(pbpctl_dev, TAP_STATE_PWRON);
2859 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2862 if (pbpctl_dev->bp_caps & BP_PWUP_CTL_CAP) {
2863 write_data(pbpctl_dev, BYPASS_STATE_PWRON);
2864 if (pbpctl_dev->bp_ext_ver > PXG2BPI_VER)
2865 msec_delay_bp(LATCH_DELAY +
2868 msec_delay_bp(DFLT_PWRON_DELAY);
2871 if (pbpctl_dev->bp_caps & TAP_DIS_CAP) {
2872 write_data(pbpctl_dev, EN_TAP_CAP);
2873 msec_delay_bp(BYPASS_CAP_DELAY);
2875 if (pbpctl_dev->bp_caps & DISC_DIS_CAP) {
2876 write_data(pbpctl_dev, EN_DISC_CAP);
2877 msec_delay_bp(BYPASS_CAP_DELAY);
2880 if (pbpctl_dev->bp_caps & BP_DIS_CAP) {
2881 write_data(pbpctl_dev, EN_BYPASS_CAP);
2882 msec_delay_bp(BYPASS_CAP_DELAY);
2891 int wdt_time_left(struct bpctl_dev *pbpctl_dev)
2894 /* unsigned long curr_time=((long long)(jiffies*1000))/HZ, delta_time=0,wdt_on_time=((long long)(pbpctl_dev->bypass_wdt_on_time*1000))/HZ; */
2895 unsigned long curr_time = jiffies, delta_time = 0, wdt_on_time =
2896 pbpctl_dev->bypass_wdt_on_time, delta_time_msec = 0;
2899 switch (pbpctl_dev->wdt_status) {
2900 case WDT_STATUS_DIS:
2906 wdt_on_time) ? (curr_time - wdt_on_time) : (~wdt_on_time +
2908 delta_time_msec = jiffies_to_msecs(delta_time);
2909 time_left = pbpctl_dev->bypass_timer_interval - delta_time_msec;
2910 if (time_left < 0) {
2912 pbpctl_dev->wdt_status = WDT_STATUS_EXP;
2915 case WDT_STATUS_EXP:
2923 static int wdt_timer(struct bpctl_dev *pbpctl_dev, int *time_left)
2926 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
2928 if (pbpctl_dev->wdt_status == WDT_STATUS_UNKNOWN)
2931 *time_left = wdt_time_left(pbpctl_dev);
2939 static int wdt_timer_reload(struct bpctl_dev *pbpctl_dev)
2944 if ((pbpctl_dev->bp_caps & WD_CTL_CAP) &&
2945 (pbpctl_dev->wdt_status != WDT_STATUS_UNKNOWN)) {
2946 if (pbpctl_dev->wdt_status == WDT_STATUS_DIS)
2948 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER)
2949 ret = wdt_pulse(pbpctl_dev);
2950 else if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
2951 ret = wdt_pulse_int(pbpctl_dev);
2953 ret = send_wdt_pulse(pbpctl_dev);
2955 mod_timer(&pbpctl_dev->bp_timer, jiffies+1);*/
2961 static void wd_reset_timer(unsigned long param)
2963 struct bpctl_dev *pbpctl_dev = (struct bpctl_dev *) param;
2965 struct sk_buff *skb_tmp;
2968 if ((pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) &&
2969 ((atomic_read(&pbpctl_dev->wdt_busy)) == 1)) {
2970 mod_timer(&pbpctl_dev->bp_timer, jiffies + 1);
2975 if (pbpctl_dev->bp_self_test_flag == 1) {
2976 skb_tmp = dev_alloc_skb(BPTEST_DATA_LEN + 2);
2977 if ((skb_tmp) && (pbpctl_dev->ndev) && (pbpctl_dev->bp_tx_data)) {
2978 memcpy(skb_put(skb_tmp, BPTEST_DATA_LEN),
2979 pbpctl_dev->bp_tx_data, BPTEST_DATA_LEN);
2980 skb_tmp->dev = pbpctl_dev->ndev;
2982 eth_type_trans(skb_tmp, pbpctl_dev->ndev);
2983 skb_tmp->ip_summed = CHECKSUM_UNNECESSARY;
2984 netif_receive_skb(skb_tmp);
2985 goto bp_timer_reload;
2991 wdt_timer_reload(pbpctl_dev);
2995 if (pbpctl_dev->reset_time) {
2996 mod_timer(&pbpctl_dev->bp_timer,
2997 jiffies + (HZ * pbpctl_dev->reset_time) / 1000);
3001 /*WAIT_AT_PWRUP 0x80 */
3002 int bp_wait_at_pwup_en(struct bpctl_dev *pbpctl_dev)
3005 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3006 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
3007 write_data(pbpctl_dev, BP_WAIT_AT_PWUP_EN);
3008 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
3016 /*DIS_WAIT_AT_PWRUP 0x81 */
3017 int bp_wait_at_pwup_dis(struct bpctl_dev *pbpctl_dev)
3020 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3022 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
3023 write_data(pbpctl_dev, BP_WAIT_AT_PWUP_DIS);
3024 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
3032 /*EN_HW_RESET 0x82 */
3034 int bp_hw_reset_en(struct bpctl_dev *pbpctl_dev)
3037 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3038 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
3039 write_data(pbpctl_dev, BP_HW_RESET_EN);
3040 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
3048 /*DIS_HW_RESET 0x83 */
3050 int bp_hw_reset_dis(struct bpctl_dev *pbpctl_dev)
3053 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3054 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
3055 write_data(pbpctl_dev, BP_HW_RESET_DIS);
3056 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
3065 int wdt_exp_mode(struct bpctl_dev *pbpctl_dev, int mode)
3067 uint32_t status_reg = 0, status_reg1 = 0;
3069 if ((pbpctl_dev->bp_caps & (TAP_STATUS_CAP | DISC_CAP)) &&
3070 (pbpctl_dev->bp_caps & BP_CAP)) {
3071 if (pbpctl_dev->bp_ext_ver >= PXE2TBPI_VER) {
3073 if ((pbpctl_dev->bp_ext_ver >= 0x8) &&
3074 (mode == 2) && (pbpctl_dev->bp_caps & DISC_CAP)) {
3076 read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR);
3077 if (!(status_reg1 & WDTE_DISC_BPN_MASK))
3078 write_reg(pbpctl_dev,
3081 STATUS_DISC_REG_ADDR);
3085 status_reg = read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR);
3087 if ((mode == 0) && (pbpctl_dev->bp_caps & BP_CAP)) {
3088 if (pbpctl_dev->bp_ext_ver >= 0x8) {
3090 read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR);
3091 if (status_reg1 & WDTE_DISC_BPN_MASK)
3092 write_reg(pbpctl_dev,
3094 ~WDTE_DISC_BPN_MASK,
3095 STATUS_DISC_REG_ADDR);
3097 if (status_reg & WDTE_TAP_BPN_MASK)
3098 write_reg(pbpctl_dev,
3099 status_reg & ~WDTE_TAP_BPN_MASK,
3100 STATUS_TAP_REG_ADDR);
3103 } else if ((mode == 1) && (pbpctl_dev->bp_caps & TAP_CAP)) {
3104 if (!(status_reg & WDTE_TAP_BPN_MASK))
3105 write_reg(pbpctl_dev,
3106 status_reg | WDTE_TAP_BPN_MASK,
3107 STATUS_TAP_REG_ADDR);
3108 /*else return BP_NOT_CAP; */
3116 int bypass_fw_ver(struct bpctl_dev *pbpctl_dev)
3118 if (is_bypass_fn(pbpctl_dev))
3119 return read_reg(pbpctl_dev, VER_REG_ADDR);
3124 int bypass_sign_check(struct bpctl_dev *pbpctl_dev)
3127 if (is_bypass_fn(pbpctl_dev))
3128 return (((read_reg(pbpctl_dev, PIC_SIGN_REG_ADDR)) ==
3129 PIC_SIGN_VALUE) ? 1 : 0);
3134 static int tx_status(struct bpctl_dev *pbpctl_dev)
3137 struct bpctl_dev *pbpctl_dev_m;
3138 if ((is_bypass_fn(pbpctl_dev)) == 1)
3139 pbpctl_dev_m = pbpctl_dev;
3141 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
3142 if (pbpctl_dev_m == NULL)
3144 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
3146 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL);
3147 if (pbpctl_dev->bp_i80)
3148 return ((ctrl & BPCTLI_CTRL_SWDPIN1) != 0 ? 0 : 1);
3149 if (pbpctl_dev->bp_540) {
3150 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
3152 return ((ctrl & BP10G_SDP1_DATA) != 0 ? 0 : 1);
3157 if (pbpctl_dev->bp_caps & TX_CTL_CAP) {
3158 if (PEG5_IF_SERIES(pbpctl_dev->subdevice)) {
3162 (pbpctl_dev, BPCTLI_PHY_CONTROL, &mii_reg))) {
3163 if (mii_reg & BPCTLI_MII_CR_POWER_DOWN)
3172 if (pbpctl_dev->bp_10g9) {
3173 return ((BP10G_READ_REG(pbpctl_dev, ESDP) &
3174 BP10G_SDP3_DATA) != 0 ? 0 : 1);
3176 } else if (pbpctl_dev->bp_fiber5) {
3177 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
3178 if (ctrl & BPCTLI_CTRL_EXT_SDP6_DATA)
3181 } else if (pbpctl_dev->bp_10gb) {
3182 ctrl = BP10GB_READ_REG(pbpctl_dev, MISC_REG_GPIO);
3183 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_GPIO,
3184 (ctrl | BP10GB_GPIO0_OE_P1) &
3185 ~(BP10GB_GPIO0_SET_P1 |
3186 BP10GB_GPIO0_CLR_P1));
3188 if ((pbpctl_dev->func == 1) || (pbpctl_dev->func == 3))
3189 return (((BP10GB_READ_REG
3191 MISC_REG_GPIO)) & BP10GB_GPIO0_P1) !=
3194 return (((BP10GB_READ_REG
3196 MISC_REG_GPIO)) & BP10GB_GPIO0_P0) !=
3200 if (!pbpctl_dev->bp_10g) {
3202 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL);
3203 if (pbpctl_dev->bp_i80)
3204 return ((ctrl & BPCTLI_CTRL_SWDPIN1) !=
3206 if (pbpctl_dev->bp_540) {
3207 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
3209 return ((ctrl & BP10G_SDP1_DATA) != 0 ? 0 : 1);
3212 return ((ctrl & BPCTLI_CTRL_SWDPIN0) != 0 ? 0 : 1);
3214 return ((BP10G_READ_REG(pbpctl_dev, ESDP) &
3215 BP10G_SDP0_DATA) != 0 ? 0 : 1);
3221 static int bp_force_link_status(struct bpctl_dev *pbpctl_dev)
3224 if (DBI_IF_SERIES(pbpctl_dev->subdevice)) {
3226 if ((pbpctl_dev->bp_10g) || (pbpctl_dev->bp_10g9)) {
3227 return ((BP10G_READ_REG(pbpctl_dev, ESDP) &
3228 BP10G_SDP1_DIR) != 0 ? 1 : 0);
3235 int bypass_from_last_read(struct bpctl_dev *pbpctl_dev)
3237 uint32_t ctrl_ext = 0;
3238 struct bpctl_dev *pbpctl_dev_b = NULL;
3240 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3241 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
3244 ctrl_ext = BPCTL_READ_REG(pbpctl_dev_b, CTRL_EXT);
3245 BPCTL_BP_WRITE_REG(pbpctl_dev_b, CTRL_EXT,
3246 (ctrl_ext & ~BPCTLI_CTRL_EXT_SDP7_DIR));
3247 ctrl_ext = BPCTL_READ_REG(pbpctl_dev_b, CTRL_EXT);
3248 if (ctrl_ext & BPCTLI_CTRL_EXT_SDP7_DATA)
3255 int bypass_status_clear(struct bpctl_dev *pbpctl_dev)
3257 struct bpctl_dev *pbpctl_dev_b = NULL;
3259 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3260 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
3263 send_bypass_clear_pulse(pbpctl_dev_b, 1);
3269 int bypass_flag_status(struct bpctl_dev *pbpctl_dev)
3272 if ((pbpctl_dev->bp_caps & BP_CAP)) {
3273 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3274 return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3275 BYPASS_FLAG_MASK) ==
3276 BYPASS_FLAG_MASK) ? 1 : 0);
3282 int bypass_flag_status_clear(struct bpctl_dev *pbpctl_dev)
3285 if (pbpctl_dev->bp_caps & BP_CAP) {
3286 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3287 uint32_t status_reg = 0;
3288 status_reg = read_reg(pbpctl_dev, STATUS_REG_ADDR);
3289 write_reg(pbpctl_dev, status_reg & ~BYPASS_FLAG_MASK,
3297 int bypass_change_status(struct bpctl_dev *pbpctl_dev)
3299 int ret = BP_NOT_CAP;
3301 if (pbpctl_dev->bp_caps & BP_STATUS_CHANGE_CAP) {
3302 if (pbpctl_dev->bp_ext_ver >= 0x8) {
3303 ret = bypass_flag_status(pbpctl_dev);
3304 bypass_flag_status_clear(pbpctl_dev);
3305 } else if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3306 ret = bypass_flag_status(pbpctl_dev);
3307 bypass_flag_status_clear(pbpctl_dev);
3309 ret = bypass_from_last_read(pbpctl_dev);
3310 bypass_status_clear(pbpctl_dev);
3316 int bypass_off_status(struct bpctl_dev *pbpctl_dev)
3319 if (pbpctl_dev->bp_caps & BP_CAP) {
3320 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3321 return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3322 BYPASS_OFF_MASK) == BYPASS_OFF_MASK) ? 1 : 0);
3328 static int bypass_status(struct bpctl_dev *pbpctl_dev)
3331 if (pbpctl_dev->bp_caps & BP_CAP) {
3333 struct bpctl_dev *pbpctl_dev_b = NULL;
3335 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
3339 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
3341 if (!pbpctl_dev->bp_status_un)
3342 return (((BPCTL_READ_REG
3345 BPCTLI_CTRL_EXT_SDP7_DATA) !=
3350 if (pbpctl_dev->bp_ext_ver >= 0x8) {
3352 if (pbpctl_dev->bp_10g9) {
3353 ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, I2CCTL);
3354 BP10G_WRITE_REG(pbpctl_dev_b, I2CCTL,
3355 (ctrl_ext | BP10G_I2C_CLK_OUT));
3356 return ((BP10G_READ_REG(pbpctl_dev_b, I2CCTL) &
3357 BP10G_I2C_CLK_IN) != 0 ? 0 : 1);
3359 } else if (pbpctl_dev->bp_540) {
3360 return (((BP10G_READ_REG(pbpctl_dev_b, ESDP)) &
3361 BP10G_SDP0_DATA) != 0 ? 0 : 1);
3364 else if ((pbpctl_dev->bp_fiber5)
3365 || (pbpctl_dev->bp_i80)) {
3366 return (((BPCTL_READ_REG(pbpctl_dev_b, CTRL)) &
3367 BPCTLI_CTRL_SWDPIN0) != 0 ? 0 : 1);
3368 } else if (pbpctl_dev->bp_10gb) {
3370 BP10GB_READ_REG(pbpctl_dev, MISC_REG_GPIO);
3371 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_GPIO,
3372 (ctrl_ext | BP10GB_GPIO3_OE_P0)
3373 & ~(BP10GB_GPIO3_SET_P0 |
3374 BP10GB_GPIO3_CLR_P0));
3376 return (((BP10GB_READ_REG
3378 MISC_REG_GPIO)) & BP10GB_GPIO3_P0) !=
3382 else if (!pbpctl_dev->bp_10g)
3383 return (((BPCTL_READ_REG
3386 BPCTLI_CTRL_EXT_SDP7_DATA) !=
3390 ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, EODSDP);
3391 BP10G_WRITE_REG(pbpctl_dev_b, EODSDP,
3393 BP10G_SDP7_DATA_OUT));
3394 return ((BP10G_READ_REG(pbpctl_dev_b, EODSDP) &
3395 BP10G_SDP7_DATA_IN) != 0 ? 0 : 1);
3398 } else if (pbpctl_dev->media_type == BP_COPPER) {
3400 return (((BPCTL_READ_REG(pbpctl_dev_b, CTRL)) &
3401 BPCTLI_CTRL_SWDPIN1) != 0 ? 1 : 0);
3403 if ((bypass_status_clear(pbpctl_dev)) >= 0)
3404 return bypass_from_last_read(pbpctl_dev);
3411 int default_pwron_status(struct bpctl_dev *pbpctl_dev)
3414 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3415 if (pbpctl_dev->bp_caps & BP_PWUP_CTL_CAP) {
3416 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3419 STATUS_REG_ADDR)) & DFLT_PWRON_MASK)
3420 == DFLT_PWRON_MASK) ? 0 : 1);
3422 } /*else if ((!pbpctl_dev->bp_caps&BP_DIS_CAP)&&
3423 (pbpctl_dev->bp_caps&BP_PWUP_ON_CAP))
3429 static int default_pwroff_status(struct bpctl_dev *pbpctl_dev)
3432 /*if ((!pbpctl_dev->bp_caps&BP_DIS_CAP)&&
3433 (pbpctl_dev->bp_caps&BP_PWOFF_ON_CAP))
3435 if ((pbpctl_dev->bp_caps & SW_CTL_CAP)
3436 && (pbpctl_dev->bp_caps & BP_PWOFF_CTL_CAP)) {
3437 return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3438 DFLT_PWROFF_MASK) == DFLT_PWROFF_MASK) ? 0 : 1);
3443 int dis_bypass_cap_status(struct bpctl_dev *pbpctl_dev)
3446 if (pbpctl_dev->bp_caps & BP_DIS_CAP) {
3447 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3448 return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3449 DIS_BYPASS_CAP_MASK) ==
3450 DIS_BYPASS_CAP_MASK) ? 1 : 0);
3456 int cmd_en_status(struct bpctl_dev *pbpctl_dev)
3459 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3460 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3461 return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3462 CMND_EN_MASK) == CMND_EN_MASK) ? 1 : 0);
3468 int wdt_en_status(struct bpctl_dev *pbpctl_dev)
3471 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
3472 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3473 return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3474 WDT_EN_MASK) == WDT_EN_MASK) ? 1 : 0);
3480 int wdt_programmed(struct bpctl_dev *pbpctl_dev, int *timeout)
3483 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
3484 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3485 if ((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3488 wdt_val = read_reg(pbpctl_dev, WDT_REG_ADDR);
3489 *timeout = (1 << wdt_val) * 100;
3493 int curr_wdt_status = pbpctl_dev->wdt_status;
3494 if (curr_wdt_status == WDT_STATUS_UNKNOWN)
3499 0 ? 0 : pbpctl_dev->bypass_timer_interval;
3506 int bypass_support(struct bpctl_dev *pbpctl_dev)
3510 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3511 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
3513 ((((read_reg(pbpctl_dev, PRODUCT_CAP_REG_ADDR)) &
3514 BYPASS_SUPPORT_MASK) ==
3515 BYPASS_SUPPORT_MASK) ? 1 : 0);
3516 } else if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
3523 int tap_support(struct bpctl_dev *pbpctl_dev)
3527 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3528 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
3530 ((((read_reg(pbpctl_dev, PRODUCT_CAP_REG_ADDR)) &
3531 TAP_SUPPORT_MASK) == TAP_SUPPORT_MASK) ? 1 : 0);
3532 } else if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
3539 int normal_support(struct bpctl_dev *pbpctl_dev)
3541 int ret = BP_NOT_CAP;
3543 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3544 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
3546 ((((read_reg(pbpctl_dev, PRODUCT_CAP_REG_ADDR)) &
3547 NORMAL_UNSUPPORT_MASK) ==
3548 NORMAL_UNSUPPORT_MASK) ? 0 : 1);
3555 int get_bp_prod_caps(struct bpctl_dev *pbpctl_dev)
3557 if ((pbpctl_dev->bp_caps & SW_CTL_CAP) &&
3558 (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER))
3559 return read_reg(pbpctl_dev, PRODUCT_CAP_REG_ADDR);
3564 int tap_flag_status(struct bpctl_dev *pbpctl_dev)
3567 if (pbpctl_dev->bp_caps & TAP_STATUS_CAP) {
3568 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
3569 return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3570 TAP_FLAG_MASK) == TAP_FLAG_MASK) ? 1 : 0);
3576 int tap_flag_status_clear(struct bpctl_dev *pbpctl_dev)
3578 uint32_t status_reg = 0;
3579 if (pbpctl_dev->bp_caps & TAP_STATUS_CAP) {
3580 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
3581 status_reg = read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR);
3582 write_reg(pbpctl_dev, status_reg & ~TAP_FLAG_MASK,
3583 STATUS_TAP_REG_ADDR);
3590 int tap_change_status(struct bpctl_dev *pbpctl_dev)
3592 int ret = BP_NOT_CAP;
3593 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
3594 if (pbpctl_dev->bp_caps & TAP_CAP) {
3595 if (pbpctl_dev->bp_caps & BP_CAP) {
3596 ret = tap_flag_status(pbpctl_dev);
3597 tap_flag_status_clear(pbpctl_dev);
3599 ret = bypass_from_last_read(pbpctl_dev);
3600 bypass_status_clear(pbpctl_dev);
3607 int tap_off_status(struct bpctl_dev *pbpctl_dev)
3609 if (pbpctl_dev->bp_caps & TAP_CAP) {
3610 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
3611 return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3612 TAP_OFF_MASK) == TAP_OFF_MASK) ? 1 : 0);
3617 int tap_status(struct bpctl_dev *pbpctl_dev)
3621 if (pbpctl_dev->bp_caps & TAP_CAP) {
3622 struct bpctl_dev *pbpctl_dev_b = NULL;
3624 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
3628 if (pbpctl_dev->bp_ext_ver >= 0x8) {
3629 if (!pbpctl_dev->bp_10g)
3630 return (((BPCTL_READ_REG
3633 BPCTLI_CTRL_EXT_SDP6_DATA) !=
3636 ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, EODSDP);
3637 BP10G_WRITE_REG(pbpctl_dev_b, EODSDP,
3639 BP10G_SDP6_DATA_OUT));
3640 return ((BP10G_READ_REG(pbpctl_dev_b, EODSDP) &
3641 BP10G_SDP6_DATA_IN) != 0 ? 0 : 1);
3644 } else if (pbpctl_dev->media_type == BP_COPPER)
3645 return (((BPCTL_READ_REG(pbpctl_dev, CTRL)) &
3646 BPCTLI_CTRL_SWDPIN0) != 0 ? 1 : 0);
3648 if ((bypass_status_clear(pbpctl_dev)) >= 0)
3649 return bypass_from_last_read(pbpctl_dev);
3656 int default_pwron_tap_status(struct bpctl_dev *pbpctl_dev)
3658 if (pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP) {
3659 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
3660 return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3661 DFLT_PWRON_TAP_MASK) ==
3662 DFLT_PWRON_TAP_MASK) ? 1 : 0);
3667 int dis_tap_cap_status(struct bpctl_dev *pbpctl_dev)
3669 if (pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP) {
3670 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
3671 return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3672 DIS_TAP_CAP_MASK) ==
3673 DIS_TAP_CAP_MASK) ? 1 : 0);
3678 int disc_flag_status(struct bpctl_dev *pbpctl_dev)
3681 if (pbpctl_dev->bp_caps & DISC_CAP) {
3682 if (pbpctl_dev->bp_ext_ver >= 0x8)
3683 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3684 DISC_FLAG_MASK) == DISC_FLAG_MASK) ? 1 : 0);
3690 int disc_flag_status_clear(struct bpctl_dev *pbpctl_dev)
3692 uint32_t status_reg = 0;
3693 if (pbpctl_dev->bp_caps & DISC_CAP) {
3694 if (pbpctl_dev->bp_ext_ver >= 0x8) {
3695 status_reg = read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR);
3696 write_reg(pbpctl_dev, status_reg & ~DISC_FLAG_MASK,
3697 STATUS_DISC_REG_ADDR);
3704 int disc_change_status(struct bpctl_dev *pbpctl_dev)
3706 int ret = BP_NOT_CAP;
3707 if (pbpctl_dev->bp_caps & DISC_CAP) {
3708 ret = disc_flag_status(pbpctl_dev);
3709 disc_flag_status_clear(pbpctl_dev);
3715 int disc_off_status(struct bpctl_dev *pbpctl_dev)
3717 struct bpctl_dev *pbpctl_dev_b = NULL;
3720 if (pbpctl_dev->bp_caps & DISC_CAP) {
3721 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
3724 if (DISCF_IF_SERIES(pbpctl_dev->subdevice))
3725 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3726 DISC_OFF_MASK) == DISC_OFF_MASK) ? 1 : 0);
3728 if (pbpctl_dev->bp_i80) {
3729 return (((BPCTL_READ_REG(pbpctl_dev_b, CTRL_EXT)) &
3730 BPCTLI_CTRL_EXT_SDP6_DATA) != 0 ? 1 : 0);
3733 if (pbpctl_dev->bp_540) {
3734 ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, ESDP);
3735 return ((BP10G_READ_REG(pbpctl_dev_b, ESDP) &
3736 BP10G_SDP2_DATA) != 0 ? 1 : 0);
3739 if (pbpctl_dev->media_type == BP_COPPER) {
3742 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3743 DISC_OFF_MASK) == DISC_OFF_MASK) ? 1 : 0);
3745 if (!pbpctl_dev->bp_10g)
3746 return (((BPCTL_READ_REG(pbpctl_dev_b, CTRL)) &
3747 BPCTLI_CTRL_SWDPIN1) != 0 ? 1 : 0);
3749 return ((BP10G_READ_REG(pbpctl_dev_b, ESDP) &
3750 BP10G_SDP1_DATA) != 0 ? 1 : 0);
3754 if (pbpctl_dev->bp_10g9) {
3755 ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, I2CCTL);
3756 BP10G_WRITE_REG(pbpctl_dev_b, I2CCTL,
3758 BP10G_I2C_DATA_OUT));
3759 return ((BP10G_READ_REG(pbpctl_dev_b, I2CCTL) &
3760 BP10G_I2C_DATA_IN) != 0 ? 1 : 0);
3762 } else if (pbpctl_dev->bp_fiber5) {
3763 return (((BPCTL_READ_REG(pbpctl_dev_b, CTRL)) &
3764 BPCTLI_CTRL_SWDPIN1) != 0 ? 1 : 0);
3765 } else if (pbpctl_dev->bp_10gb) {
3767 BP10GB_READ_REG(pbpctl_dev, MISC_REG_GPIO);
3768 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_GPIO,
3769 (ctrl_ext | BP10GB_GPIO3_OE_P1)
3770 & ~(BP10GB_GPIO3_SET_P1 |
3771 BP10GB_GPIO3_CLR_P1));
3773 return (((BP10GB_READ_REG
3775 MISC_REG_GPIO)) & BP10GB_GPIO3_P1) !=
3778 if (!pbpctl_dev->bp_10g) {
3780 return (((BPCTL_READ_REG
3783 BPCTLI_CTRL_EXT_SDP6_DATA) !=
3786 ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, EODSDP);
3787 BP10G_WRITE_REG(pbpctl_dev_b, EODSDP,
3789 BP10G_SDP6_DATA_OUT));
3790 return (((BP10G_READ_REG(pbpctl_dev_b, EODSDP))
3791 & BP10G_SDP6_DATA_IN) != 0 ? 1 : 0);
3799 static int disc_status(struct bpctl_dev *pbpctl_dev)
3802 if (pbpctl_dev->bp_caps & DISC_CAP) {
3803 ctrl = disc_off_status(pbpctl_dev);
3806 return ((ctrl == 0) ? 1 : 0);
3811 int default_pwron_disc_status(struct bpctl_dev *pbpctl_dev)
3813 if (pbpctl_dev->bp_caps & DISC_PWUP_CTL_CAP) {
3814 if (pbpctl_dev->bp_ext_ver >= 0x8)
3815 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3816 DFLT_PWRON_DISC_MASK) ==
3817 DFLT_PWRON_DISC_MASK) ? 1 : 0);
3822 int dis_disc_cap_status(struct bpctl_dev *pbpctl_dev)
3824 if (pbpctl_dev->bp_caps & DIS_DISC_CAP) {
3825 if (pbpctl_dev->bp_ext_ver >= 0x8)
3826 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3827 DIS_DISC_CAP_MASK) ==
3828 DIS_DISC_CAP_MASK) ? 1 : 0);
3833 int disc_port_status(struct bpctl_dev *pbpctl_dev)
3835 int ret = BP_NOT_CAP;
3836 struct bpctl_dev *pbpctl_dev_m;
3838 if ((is_bypass_fn(pbpctl_dev)) == 1)
3839 pbpctl_dev_m = pbpctl_dev;
3841 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
3842 if (pbpctl_dev_m == NULL)
3845 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
3846 if (is_bypass_fn(pbpctl_dev) == 1) {
3847 return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3848 TX_DISA_MASK) == TX_DISA_MASK) ? 1 : 0);
3850 return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3851 TX_DISB_MASK) == TX_DISB_MASK) ? 1 : 0);
3857 int default_pwron_disc_port_status(struct bpctl_dev *pbpctl_dev)
3859 int ret = BP_NOT_CAP;
3860 struct bpctl_dev *pbpctl_dev_m;
3862 if ((is_bypass_fn(pbpctl_dev)) == 1)
3863 pbpctl_dev_m = pbpctl_dev;
3865 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
3866 if (pbpctl_dev_m == NULL)
3869 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
3870 if (is_bypass_fn(pbpctl_dev) == 1)
3872 /* return((((read_reg(pbpctl_dev,STATUS_TAP_REG_ADDR)) & TX_DISA_MASK)==TX_DISA_MASK)?1:0); */
3875 /* return((((read_reg(pbpctl_dev,STATUS_TAP_REG_ADDR)) & TX_DISA_MASK)==TX_DISA_MASK)?1:0); */
3881 int wdt_exp_mode_status(struct bpctl_dev *pbpctl_dev)
3883 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
3884 if (pbpctl_dev->bp_ext_ver <= PXG2BPI_VER)
3885 return 0; /* bypass mode */
3886 else if (pbpctl_dev->bp_ext_ver == PXG2TBPI_VER)
3887 return 1; /* tap mode */
3888 else if (pbpctl_dev->bp_ext_ver >= PXE2TBPI_VER) {
3889 if (pbpctl_dev->bp_ext_ver >= 0x8) {
3892 STATUS_DISC_REG_ADDR)) &
3893 WDTE_DISC_BPN_MASK) == WDTE_DISC_BPN_MASK)
3896 return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3897 WDTE_TAP_BPN_MASK) ==
3898 WDTE_TAP_BPN_MASK) ? 1 : 0);
3904 int tpl2_flag_status(struct bpctl_dev *pbpctl_dev)
3907 if (pbpctl_dev->bp_caps_ex & TPL2_CAP_EX) {
3908 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3909 TPL2_FLAG_MASK) == TPL2_FLAG_MASK) ? 1 : 0);
3915 int tpl_hw_status(struct bpctl_dev *pbpctl_dev)
3917 struct bpctl_dev *pbpctl_dev_b = NULL;
3919 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
3923 if (TPL_IF_SERIES(pbpctl_dev->subdevice))
3924 return (((BPCTL_READ_REG(pbpctl_dev, CTRL)) &
3925 BPCTLI_CTRL_SWDPIN0) != 0 ? 1 : 0);
3930 int bp_wait_at_pwup_status(struct bpctl_dev *pbpctl_dev)
3932 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3933 if (pbpctl_dev->bp_ext_ver >= 0x8)
3934 return ((((read_reg(pbpctl_dev, CONT_CONFIG_REG_ADDR)) &
3935 WAIT_AT_PWUP_MASK) ==
3936 WAIT_AT_PWUP_MASK) ? 1 : 0);
3941 int bp_hw_reset_status(struct bpctl_dev *pbpctl_dev)
3944 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3946 if (pbpctl_dev->bp_ext_ver >= 0x8)
3947 return ((((read_reg(pbpctl_dev, CONT_CONFIG_REG_ADDR)) &
3948 EN_HW_RESET_MASK) ==
3949 EN_HW_RESET_MASK) ? 1 : 0);
3955 int std_nic_status(struct bpctl_dev *pbpctl_dev)
3959 if (pbpctl_dev->bp_caps & STD_NIC_CAP) {
3960 if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
3962 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
3963 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3964 STD_NIC_ON_MASK) == STD_NIC_ON_MASK) ? 1 : 0);
3967 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3968 if (pbpctl_dev->bp_caps & BP_CAP) {
3970 read_reg(pbpctl_dev, STATUS_REG_ADDR);
3971 if (((!(status_val & WDT_EN_MASK))
3972 && ((status_val & STD_NIC_MASK) ==
3978 if (pbpctl_dev->bp_caps & TAP_CAP) {
3980 read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR);
3981 if ((status_val & STD_NIC_TAP_MASK) ==
3987 if (pbpctl_dev->bp_caps & TAP_CAP) {
3988 if ((disc_off_status(pbpctl_dev)))
4000 /******************************************************/
4001 /**************SW_INIT*********************************/
4002 /******************************************************/
4003 void bypass_caps_init(struct bpctl_dev *pbpctl_dev)
4005 u_int32_t ctrl_ext = 0;
4006 struct bpctl_dev *pbpctl_dev_m = NULL;
4010 if (!(INTEL_IF_SERIES(adapter->bp_device_block.subdevice))) {
4011 ret = read_reg(pbpctl_dev, VER_REG_ADDR);
4012 printk("VER_REG reg1=%x\n", ret);
4013 ret = read_reg(pbpctl_dev, PRODUCT_CAP_REG_ADDR);
4014 printk("PRODUCT_CAP reg=%x\n", ret);
4015 ret = read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR);
4016 printk("STATUS_TAP reg1=%x\n", ret);
4017 ret = read_reg(pbpctl_dev, 0x7);
4018 printk("SIG_REG reg1=%x\n", ret);
4019 ret = read_reg(pbpctl_dev, STATUS_REG_ADDR);
4020 printk("STATUS_REG_ADDR=%x\n", ret);
4021 ret = read_reg(pbpctl_dev, WDT_REG_ADDR);
4022 printk("WDT_REG_ADDR=%x\n", ret);
4023 ret = read_reg(pbpctl_dev, TMRL_REG_ADDR);
4024 printk("TMRL_REG_ADDR=%x\n", ret);
4025 ret = read_reg(pbpctl_dev, TMRH_REG_ADDR);
4026 printk("TMRH_REG_ADDR=%x\n", ret);
4029 if ((pbpctl_dev->bp_fiber5) || (pbpctl_dev->bp_10g9)) {
4030 pbpctl_dev->media_type = BP_FIBER;
4031 } else if (pbpctl_dev->bp_10gb) {
4032 if (BP10GB_CX4_SERIES(pbpctl_dev->subdevice))
4033 pbpctl_dev->media_type = BP_CX4;
4035 pbpctl_dev->media_type = BP_FIBER;
4039 else if (pbpctl_dev->bp_540)
4040 pbpctl_dev->media_type = BP_NONE;
4041 else if (!pbpctl_dev->bp_10g) {
4043 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
4044 if ((ctrl_ext & BPCTLI_CTRL_EXT_LINK_MODE_MASK) == 0x0)
4045 pbpctl_dev->media_type = BP_COPPER;
4047 pbpctl_dev->media_type = BP_FIBER;
4050 if (BP10G_CX4_SERIES(pbpctl_dev->subdevice))
4051 pbpctl_dev->media_type = BP_CX4;
4053 pbpctl_dev->media_type = BP_FIBER;
4056 if (is_bypass_fn(pbpctl_dev)) {
4058 pbpctl_dev->bp_caps |= BP_PWOFF_ON_CAP;
4059 if (pbpctl_dev->media_type == BP_FIBER)
4060 pbpctl_dev->bp_caps |=
4061 (TX_CTL_CAP | TX_STATUS_CAP | TPL_CAP);
4063 if (TPL_IF_SERIES(pbpctl_dev->subdevice))
4064 pbpctl_dev->bp_caps |= TPL_CAP;
4066 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
4067 pbpctl_dev->bp_caps |=
4068 (BP_CAP | BP_STATUS_CAP | SW_CTL_CAP |
4069 BP_PWUP_ON_CAP | BP_PWUP_OFF_CAP | BP_PWOFF_OFF_CAP
4070 | WD_CTL_CAP | WD_STATUS_CAP | STD_NIC_CAP |
4073 pbpctl_dev->bp_ext_ver = OLD_IF_VER;
4077 if ((pbpctl_dev->bp_fw_ver == 0xff) &&
4078 OLD_IF_SERIES(pbpctl_dev->subdevice)) {
4080 pbpctl_dev->bp_caps |=
4081 (BP_CAP | BP_STATUS_CAP | BP_STATUS_CHANGE_CAP |
4082 SW_CTL_CAP | BP_PWUP_ON_CAP | WD_CTL_CAP |
4083 WD_STATUS_CAP | WD_TIMEOUT_CAP);
4085 pbpctl_dev->bp_ext_ver = OLD_IF_VER;
4090 switch (pbpctl_dev->bp_fw_ver) {
4093 pbpctl_dev->bp_ext_ver =
4095 bp_fw_ver & EXT_VER_MASK);
4099 if ((bypass_sign_check(pbpctl_dev)) !=
4101 pbpctl_dev->bp_caps = 0;
4104 pbpctl_dev->bp_ext_ver =
4106 bp_fw_ver & EXT_VER_MASK);
4111 if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
4112 pbpctl_dev->bp_caps |=
4113 (BP_CAP | BP_STATUS_CAP | BP_STATUS_CHANGE_CAP |
4114 SW_CTL_CAP | BP_DIS_CAP | BP_DIS_STATUS_CAP |
4115 BP_PWUP_ON_CAP | BP_PWUP_OFF_CAP | BP_PWUP_CTL_CAP
4116 | WD_CTL_CAP | STD_NIC_CAP | WD_STATUS_CAP |
4118 else if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
4121 pbpctl_dev->bp_caps |=
4122 (SW_CTL_CAP | WD_CTL_CAP | WD_STATUS_CAP |
4124 cap_reg = get_bp_prod_caps(pbpctl_dev);
4126 if ((cap_reg & NORMAL_UNSUPPORT_MASK) ==
4127 NORMAL_UNSUPPORT_MASK)
4128 pbpctl_dev->bp_caps |= NIC_CAP_NEG;
4130 pbpctl_dev->bp_caps |= STD_NIC_CAP;
4132 if ((normal_support(pbpctl_dev)) == 1)
4134 pbpctl_dev->bp_caps |= STD_NIC_CAP;
4137 pbpctl_dev->bp_caps |= NIC_CAP_NEG;
4138 if ((cap_reg & BYPASS_SUPPORT_MASK) ==
4139 BYPASS_SUPPORT_MASK) {
4140 pbpctl_dev->bp_caps |=
4141 (BP_CAP | BP_STATUS_CAP |
4142 BP_STATUS_CHANGE_CAP | BP_DIS_CAP |
4143 BP_DIS_STATUS_CAP | BP_PWUP_ON_CAP |
4144 BP_PWUP_OFF_CAP | BP_PWUP_CTL_CAP);
4145 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER7)
4146 pbpctl_dev->bp_caps |=
4147 BP_PWOFF_ON_CAP | BP_PWOFF_OFF_CAP |
4150 if ((cap_reg & TAP_SUPPORT_MASK) == TAP_SUPPORT_MASK) {
4151 pbpctl_dev->bp_caps |=
4152 (TAP_CAP | TAP_STATUS_CAP |
4153 TAP_STATUS_CHANGE_CAP | TAP_DIS_CAP |
4154 TAP_DIS_STATUS_CAP | TAP_PWUP_ON_CAP |
4155 TAP_PWUP_OFF_CAP | TAP_PWUP_CTL_CAP);
4157 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
4158 if ((cap_reg & DISC_SUPPORT_MASK) ==
4160 pbpctl_dev->bp_caps |=
4161 (DISC_CAP | DISC_DIS_CAP |
4163 if ((cap_reg & TPL2_SUPPORT_MASK) ==
4164 TPL2_SUPPORT_MASK) {
4165 pbpctl_dev->bp_caps_ex |= TPL2_CAP_EX;
4166 pbpctl_dev->bp_caps |= TPL_CAP;
4167 pbpctl_dev->bp_tpl_flag =
4168 tpl2_flag_status(pbpctl_dev);
4173 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER9) {
4174 if ((cap_reg & DISC_PORT_SUPPORT_MASK) ==
4175 DISC_PORT_SUPPORT_MASK) {
4176 pbpctl_dev->bp_caps_ex |=
4178 pbpctl_dev->bp_caps |=
4179 (TX_CTL_CAP | TX_STATUS_CAP);
4185 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
4186 if ((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
4188 pbpctl_dev->wdt_status = WDT_STATUS_EN;
4190 pbpctl_dev->wdt_status = WDT_STATUS_DIS;
4193 } else if ((P2BPFI_IF_SERIES(pbpctl_dev->subdevice)) ||
4194 (PEGF5_IF_SERIES(pbpctl_dev->subdevice)) ||
4195 (PEGF80_IF_SERIES(pbpctl_dev->subdevice)) ||
4196 (BP10G9_IF_SERIES(pbpctl_dev->subdevice))) {
4197 pbpctl_dev->bp_caps |= (TX_CTL_CAP | TX_STATUS_CAP);
4199 if ((pbpctl_dev->subdevice & 0xa00) == 0xa00)
4200 pbpctl_dev->bp_caps |= (TX_CTL_CAP | TX_STATUS_CAP);
4201 if (PEG5_IF_SERIES(pbpctl_dev->subdevice))
4202 pbpctl_dev->bp_caps |= (TX_CTL_CAP | TX_STATUS_CAP);
4204 if (BP10GB_IF_SERIES(pbpctl_dev->subdevice))
4205 pbpctl_dev->bp_caps &= ~(TX_CTL_CAP | TX_STATUS_CAP);
4207 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
4208 if (pbpctl_dev_m != NULL) {
4210 if (pbpctl_dev_m->bp_ext_ver >= 0x9) {
4211 cap_reg = get_bp_prod_caps(pbpctl_dev_m);
4212 if ((cap_reg & DISC_PORT_SUPPORT_MASK) ==
4213 DISC_PORT_SUPPORT_MASK)
4214 pbpctl_dev->bp_caps |=
4215 (TX_CTL_CAP | TX_STATUS_CAP);
4216 pbpctl_dev->bp_caps_ex |= DISC_PORT_CAP_EX;
4221 int bypass_off_init(struct bpctl_dev *pbpctl_dev)
4223 int ret = cmnd_on(pbpctl_dev);
4226 if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
4227 return dis_bypass_cap(pbpctl_dev);
4228 wdt_off(pbpctl_dev);
4229 if (pbpctl_dev->bp_caps & BP_CAP)
4230 bypass_off(pbpctl_dev);
4231 if (pbpctl_dev->bp_caps & TAP_CAP)
4232 tap_off(pbpctl_dev);
4233 cmnd_off(pbpctl_dev);
4237 void remove_bypass_wd_auto(struct bpctl_dev *pbpctl_dev)
4240 struct bpctl_dev *pbpctl_dev_sl = NULL;
4243 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4245 del_timer_sync(&pbpctl_dev->bp_timer);
4247 pbpctl_dev_sl = get_status_port_fn(pbpctl_dev);
4248 if (pbpctl_dev_sl && (pbpctl_dev_sl->ndev)) {
4249 if ((pbpctl_dev_sl->ndev->netdev_ops)
4250 && (pbpctl_dev_sl->old_ops)) {
4252 pbpctl_dev_sl->ndev->netdev_ops =
4253 pbpctl_dev_sl->old_ops;
4254 pbpctl_dev_sl->old_ops = NULL;
4266 int init_bypass_wd_auto(struct bpctl_dev *pbpctl_dev)
4268 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4269 init_timer(&pbpctl_dev->bp_timer);
4270 pbpctl_dev->bp_timer.function = &wd_reset_timer;
4271 pbpctl_dev->bp_timer.data = (unsigned long)pbpctl_dev;
4278 int bp_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
4280 struct bpctl_dev *pbpctl_dev = NULL, *pbpctl_dev_m = NULL;
4282 struct ethhdr *eth = (struct ethhdr *)skb->data;
4285 ((bpctl_dev_arr[idx_dev].ndev != NULL) && (idx_dev < device_num));
4287 if (bpctl_dev_arr[idx_dev].ndev == dev) {
4288 pbpctl_dev = &bpctl_dev_arr[idx_dev];
4294 if ((htons(ETH_P_BPTEST) == eth->h_proto)) {
4296 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
4299 if (bypass_status(pbpctl_dev_m)) {
4300 cmnd_on(pbpctl_dev_m);
4301 bypass_off(pbpctl_dev_m);
4302 cmnd_off(pbpctl_dev_m);
4304 wdt_timer_reload(pbpctl_dev_m);
4306 dev_kfree_skb_irq(skb);
4309 return pbpctl_dev->hard_start_xmit_save(skb, dev);
4313 int set_bypass_wd_auto(struct bpctl_dev *pbpctl_dev, unsigned int param)
4315 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4316 if (pbpctl_dev->reset_time != param) {
4317 if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
4318 pbpctl_dev->reset_time =
4320 WDT_AUTO_MIN_INT) ? WDT_AUTO_MIN_INT :
4323 pbpctl_dev->reset_time = param;
4325 mod_timer(&pbpctl_dev->bp_timer, jiffies);
4332 int get_bypass_wd_auto(struct bpctl_dev *pbpctl_dev)
4334 if (pbpctl_dev->bp_caps & WD_CTL_CAP)
4335 return pbpctl_dev->reset_time;
4342 int set_bp_self_test(struct bpctl_dev *pbpctl_dev, unsigned int param)
4344 struct bpctl_dev *pbpctl_dev_sl = NULL;
4346 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4347 pbpctl_dev->bp_self_test_flag = param == 0 ? 0 : 1;
4348 pbpctl_dev_sl = get_status_port_fn(pbpctl_dev);
4350 if ((pbpctl_dev_sl->ndev) && (pbpctl_dev_sl->ndev->netdev_ops)) {
4352 if (pbpctl_dev->bp_self_test_flag == 1) {
4354 pbpctl_dev_sl->old_ops =
4355 pbpctl_dev_sl->ndev->netdev_ops;
4356 pbpctl_dev_sl->new_ops =
4357 *pbpctl_dev_sl->old_ops;
4358 pbpctl_dev_sl->new_ops.ndo_start_xmit =
4360 pbpctl_dev_sl->ndev->netdev_ops =
4361 &pbpctl_dev_sl->new_ops;
4363 } else if (pbpctl_dev_sl->old_ops) {
4364 pbpctl_dev_sl->ndev->netdev_ops =
4365 pbpctl_dev_sl->old_ops;
4366 pbpctl_dev_sl->old_ops = NULL;
4371 set_bypass_wd_auto(pbpctl_dev, param);
4377 int get_bp_self_test(struct bpctl_dev *pbpctl_dev)
4380 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4381 if (pbpctl_dev->bp_self_test_flag == 1)
4382 return pbpctl_dev->reset_time;
4391 /**************************************************************/
4392 /************************* API ********************************/
4393 /**************************************************************/
4395 int is_bypass_fn(struct bpctl_dev *pbpctl_dev)
4400 return (((pbpctl_dev->func == 0) || (pbpctl_dev->func == 2)) ? 1 : 0);
4403 int set_bypass_fn(struct bpctl_dev *pbpctl_dev, int bypass_mode)
4407 if (!(pbpctl_dev->bp_caps & BP_CAP))
4409 ret = cmnd_on(pbpctl_dev);
4413 ret = bypass_off(pbpctl_dev);
4415 ret = bypass_on(pbpctl_dev);
4416 cmnd_off(pbpctl_dev);
4421 int get_bypass_fn(struct bpctl_dev *pbpctl_dev)
4423 return bypass_status(pbpctl_dev);
4426 int get_bypass_change_fn(struct bpctl_dev *pbpctl_dev)
4431 return bypass_change_status(pbpctl_dev);
4434 int set_dis_bypass_fn(struct bpctl_dev *pbpctl_dev, int dis_param)
4440 if (!(pbpctl_dev->bp_caps & BP_DIS_CAP))
4442 ret = cmnd_on(pbpctl_dev);
4446 ret = dis_bypass_cap(pbpctl_dev);
4448 ret = en_bypass_cap(pbpctl_dev);
4449 cmnd_off(pbpctl_dev);
4453 int get_dis_bypass_fn(struct bpctl_dev *pbpctl_dev)
4458 return dis_bypass_cap_status(pbpctl_dev);
4461 int set_bypass_pwoff_fn(struct bpctl_dev *pbpctl_dev, int bypass_mode)
4467 if (!(pbpctl_dev->bp_caps & BP_PWOFF_CTL_CAP))
4469 ret = cmnd_on(pbpctl_dev);
4473 ret = bypass_state_pwroff(pbpctl_dev);
4475 ret = normal_state_pwroff(pbpctl_dev);
4476 cmnd_off(pbpctl_dev);
4480 int get_bypass_pwoff_fn(struct bpctl_dev *pbpctl_dev)
4485 return default_pwroff_status(pbpctl_dev);
4488 int set_bypass_pwup_fn(struct bpctl_dev *pbpctl_dev, int bypass_mode)
4494 if (!(pbpctl_dev->bp_caps & BP_PWUP_CTL_CAP))
4496 ret = cmnd_on(pbpctl_dev);
4500 ret = bypass_state_pwron(pbpctl_dev);
4502 ret = normal_state_pwron(pbpctl_dev);
4503 cmnd_off(pbpctl_dev);
4507 int get_bypass_pwup_fn(struct bpctl_dev *pbpctl_dev)
4512 return default_pwron_status(pbpctl_dev);
4515 int set_bypass_wd_fn(struct bpctl_dev *pbpctl_dev, int timeout)
4521 if (!(pbpctl_dev->bp_caps & WD_CTL_CAP))
4524 ret = cmnd_on(pbpctl_dev);
4528 ret = wdt_off(pbpctl_dev);
4530 wdt_on(pbpctl_dev, timeout);
4531 ret = pbpctl_dev->bypass_timer_interval;
4533 cmnd_off(pbpctl_dev);
4537 int get_bypass_wd_fn(struct bpctl_dev *pbpctl_dev, int *timeout)
4542 return wdt_programmed(pbpctl_dev, timeout);
4545 int get_wd_expire_time_fn(struct bpctl_dev *pbpctl_dev, int *time_left)
4550 return wdt_timer(pbpctl_dev, time_left);
4553 int reset_bypass_wd_timer_fn(struct bpctl_dev *pbpctl_dev)
4558 return wdt_timer_reload(pbpctl_dev);
4561 int get_wd_set_caps_fn(struct bpctl_dev *pbpctl_dev)
4565 unsigned int step_value = TIMEOUT_MAX_STEP + 1, bit_cnt = 0;
4569 if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
4572 while ((step_value >>= 1))
4575 if (is_bypass_fn(pbpctl_dev)) {
4577 WD_STEP_COUNT_MASK(bit_cnt) | WDT_STEP_TIME |
4578 WD_MIN_TIME_MASK(TIMEOUT_UNIT / 100);
4585 int set_std_nic_fn(struct bpctl_dev *pbpctl_dev, int nic_mode)
4591 if (!(pbpctl_dev->bp_caps & STD_NIC_CAP))
4594 ret = cmnd_on(pbpctl_dev);
4598 ret = std_nic_on(pbpctl_dev);
4600 ret = std_nic_off(pbpctl_dev);
4601 cmnd_off(pbpctl_dev);
4605 int get_std_nic_fn(struct bpctl_dev *pbpctl_dev)
4610 return std_nic_status(pbpctl_dev);
4613 int set_tap_fn(struct bpctl_dev *pbpctl_dev, int tap_mode)
4618 if ((pbpctl_dev->bp_caps & TAP_CAP) && ((cmnd_on(pbpctl_dev)) >= 0)) {
4620 tap_off(pbpctl_dev);
4623 cmnd_off(pbpctl_dev);
4629 int get_tap_fn(struct bpctl_dev *pbpctl_dev)
4634 return tap_status(pbpctl_dev);
4637 int set_tap_pwup_fn(struct bpctl_dev *pbpctl_dev, int tap_mode)
4643 if ((pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP)
4644 && ((cmnd_on(pbpctl_dev)) >= 0)) {
4646 ret = tap_state_pwron(pbpctl_dev);
4648 ret = normal_state_pwron(pbpctl_dev);
4649 cmnd_off(pbpctl_dev);
4655 int get_tap_pwup_fn(struct bpctl_dev *pbpctl_dev)
4661 ret = default_pwron_tap_status(pbpctl_dev);
4664 return ((ret == 0) ? 1 : 0);
4667 int get_tap_change_fn(struct bpctl_dev *pbpctl_dev)
4672 return tap_change_status(pbpctl_dev);
4675 int set_dis_tap_fn(struct bpctl_dev *pbpctl_dev, int dis_param)
4681 if ((pbpctl_dev->bp_caps & TAP_DIS_CAP) && ((cmnd_on(pbpctl_dev)) >= 0)) {
4683 ret = dis_tap_cap(pbpctl_dev);
4685 ret = en_tap_cap(pbpctl_dev);
4686 cmnd_off(pbpctl_dev);
4692 int get_dis_tap_fn(struct bpctl_dev *pbpctl_dev)
4697 return dis_tap_cap_status(pbpctl_dev);
4700 int set_disc_fn(struct bpctl_dev *pbpctl_dev, int disc_mode)
4705 if ((pbpctl_dev->bp_caps & DISC_CAP) && ((cmnd_on(pbpctl_dev)) >= 0)) {
4707 disc_off(pbpctl_dev);
4709 disc_on(pbpctl_dev);
4710 cmnd_off(pbpctl_dev);
4717 int get_disc_fn(struct bpctl_dev *pbpctl_dev)
4723 ret = disc_status(pbpctl_dev);
4728 int set_disc_pwup_fn(struct bpctl_dev *pbpctl_dev, int disc_mode)
4734 if ((pbpctl_dev->bp_caps & DISC_PWUP_CTL_CAP)
4735 && ((cmnd_on(pbpctl_dev)) >= 0)) {
4737 ret = disc_state_pwron(pbpctl_dev);
4739 ret = normal_state_pwron(pbpctl_dev);
4740 cmnd_off(pbpctl_dev);
4746 int get_disc_pwup_fn(struct bpctl_dev *pbpctl_dev)
4752 ret = default_pwron_disc_status(pbpctl_dev);
4753 return (ret == 0 ? 1 : (ret < 0 ? BP_NOT_CAP : 0));
4756 int get_disc_change_fn(struct bpctl_dev *pbpctl_dev)
4762 ret = disc_change_status(pbpctl_dev);
4766 int set_dis_disc_fn(struct bpctl_dev *pbpctl_dev, int dis_param)
4772 if ((pbpctl_dev->bp_caps & DISC_DIS_CAP)
4773 && ((cmnd_on(pbpctl_dev)) >= 0)) {
4775 ret = dis_disc_cap(pbpctl_dev);
4777 ret = en_disc_cap(pbpctl_dev);
4778 cmnd_off(pbpctl_dev);
4784 int get_dis_disc_fn(struct bpctl_dev *pbpctl_dev)
4790 ret = dis_disc_cap_status(pbpctl_dev);
4795 int set_disc_port_fn(struct bpctl_dev *pbpctl_dev, int disc_mode)
4797 int ret = BP_NOT_CAP;
4802 ret = disc_port_off(pbpctl_dev);
4804 ret = disc_port_on(pbpctl_dev);
4809 int get_disc_port_fn(struct bpctl_dev *pbpctl_dev)
4814 return disc_port_status(pbpctl_dev);
4817 int set_disc_port_pwup_fn(struct bpctl_dev *pbpctl_dev, int disc_mode)
4819 int ret = BP_NOT_CAP;
4824 ret = normal_port_state_pwron(pbpctl_dev);
4826 ret = disc_port_state_pwron(pbpctl_dev);
4831 int get_disc_port_pwup_fn(struct bpctl_dev *pbpctl_dev)
4837 ret = default_pwron_disc_port_status(pbpctl_dev);
4840 return ((ret == 0) ? 1 : 0);
4843 int get_wd_exp_mode_fn(struct bpctl_dev *pbpctl_dev)
4848 return wdt_exp_mode_status(pbpctl_dev);
4851 int set_wd_exp_mode_fn(struct bpctl_dev *pbpctl_dev, int param)
4856 return wdt_exp_mode(pbpctl_dev, param);
4859 int reset_cont_fn(struct bpctl_dev *pbpctl_dev)
4865 ret = cmnd_on(pbpctl_dev);
4868 return reset_cont(pbpctl_dev);
4871 int set_tx_fn(struct bpctl_dev *pbpctl_dev, int tx_state)
4874 struct bpctl_dev *pbpctl_dev_b = NULL;
4878 if ((pbpctl_dev->bp_caps & TPL_CAP) &&
4879 (pbpctl_dev->bp_caps & SW_CTL_CAP)) {
4880 if ((pbpctl_dev->bp_tpl_flag))
4883 pbpctl_dev_b = get_master_port_fn(pbpctl_dev);
4885 (pbpctl_dev_b->bp_caps & TPL_CAP) &&
4886 (pbpctl_dev_b->bp_tpl_flag))
4889 return set_tx(pbpctl_dev, tx_state);
4892 int set_bp_force_link_fn(int dev_num, int tx_state)
4894 static struct bpctl_dev *bpctl_dev_curr;
4896 if ((dev_num < 0) || (dev_num > device_num)
4897 || (bpctl_dev_arr[dev_num].pdev == NULL))
4899 bpctl_dev_curr = &bpctl_dev_arr[dev_num];
4901 return set_bp_force_link(bpctl_dev_curr, tx_state);
4904 int set_wd_autoreset_fn(struct bpctl_dev *pbpctl_dev, int param)
4909 return set_bypass_wd_auto(pbpctl_dev, param);
4912 int get_wd_autoreset_fn(struct bpctl_dev *pbpctl_dev)
4917 return get_bypass_wd_auto(pbpctl_dev);
4921 int set_bp_self_test_fn(struct bpctl_dev *pbpctl_dev, int param)
4926 return set_bp_self_test(pbpctl_dev, param);
4929 int get_bp_self_test_fn(struct bpctl_dev *pbpctl_dev)
4934 return get_bp_self_test(pbpctl_dev);
4939 int get_bypass_caps_fn(struct bpctl_dev *pbpctl_dev)
4944 return pbpctl_dev->bp_caps;
4948 int get_bypass_slave_fn(struct bpctl_dev *pbpctl_dev, struct bpctl_dev **pbpctl_dev_out)
4954 if ((pbpctl_dev->func == 0) || (pbpctl_dev->func == 2)) {
4956 ((bpctl_dev_arr[idx_dev].pdev != NULL)
4957 && (idx_dev < device_num)); idx_dev++) {
4958 if ((bpctl_dev_arr[idx_dev].bus == pbpctl_dev->bus)
4959 && (bpctl_dev_arr[idx_dev].slot ==
4960 pbpctl_dev->slot)) {
4961 if ((pbpctl_dev->func == 0)
4962 && (bpctl_dev_arr[idx_dev].func == 1)) {
4964 &bpctl_dev_arr[idx_dev];
4967 if ((pbpctl_dev->func == 2) &&
4968 (bpctl_dev_arr[idx_dev].func == 3)) {
4970 &bpctl_dev_arr[idx_dev];
4980 int is_bypass(struct bpctl_dev *pbpctl_dev)
4985 if ((pbpctl_dev->func == 0) || (pbpctl_dev->func == 2))
4991 int get_tx_fn(struct bpctl_dev *pbpctl_dev)
4993 struct bpctl_dev *pbpctl_dev_b = NULL;
4997 if ((pbpctl_dev->bp_caps & TPL_CAP) &&
4998 (pbpctl_dev->bp_caps & SW_CTL_CAP)) {
4999 if ((pbpctl_dev->bp_tpl_flag))
5002 pbpctl_dev_b = get_master_port_fn(pbpctl_dev);
5004 (pbpctl_dev_b->bp_caps & TPL_CAP) &&
5005 (pbpctl_dev_b->bp_tpl_flag))
5008 return tx_status(pbpctl_dev);
5011 int get_bp_force_link_fn(int dev_num)
5013 static struct bpctl_dev *bpctl_dev_curr;
5015 if ((dev_num < 0) || (dev_num > device_num)
5016 || (bpctl_dev_arr[dev_num].pdev == NULL))
5018 bpctl_dev_curr = &bpctl_dev_arr[dev_num];
5020 return bp_force_link_status(bpctl_dev_curr);
5023 static int get_bypass_link_status(struct bpctl_dev *pbpctl_dev)
5028 if (pbpctl_dev->media_type == BP_FIBER)
5029 return ((BPCTL_READ_REG(pbpctl_dev, CTRL) &
5030 BPCTLI_CTRL_SWDPIN1));
5032 return ((BPCTL_READ_REG(pbpctl_dev, STATUS) &
5037 static void bp_tpl_timer_fn(unsigned long param)
5039 struct bpctl_dev *pbpctl_dev = (struct bpctl_dev *) param;
5040 uint32_t link1, link2;
5041 struct bpctl_dev *pbpctl_dev_b = NULL;
5043 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
5047 if (!pbpctl_dev->bp_tpl_flag) {
5048 set_tx(pbpctl_dev_b, 1);
5049 set_tx(pbpctl_dev, 1);
5052 link1 = get_bypass_link_status(pbpctl_dev);
5054 link2 = get_bypass_link_status(pbpctl_dev_b);
5055 if ((link1) && (tx_status(pbpctl_dev))) {
5056 if ((!link2) && (tx_status(pbpctl_dev_b)))
5057 set_tx(pbpctl_dev, 0);
5058 else if (!tx_status(pbpctl_dev_b))
5059 set_tx(pbpctl_dev_b, 1);
5060 } else if ((!link1) && (tx_status(pbpctl_dev))) {
5061 if ((link2) && (tx_status(pbpctl_dev_b)))
5062 set_tx(pbpctl_dev_b, 0);
5063 } else if ((link1) && (!tx_status(pbpctl_dev))) {
5064 if ((link2) && (tx_status(pbpctl_dev_b)))
5065 set_tx(pbpctl_dev, 1);
5066 } else if ((!link1) && (!tx_status(pbpctl_dev))) {
5067 if ((link2) && (tx_status(pbpctl_dev_b)))
5068 set_tx(pbpctl_dev, 1);
5071 mod_timer(&pbpctl_dev->bp_tpl_timer, jiffies + BP_LINK_MON_DELAY * HZ);
5074 void remove_bypass_tpl_auto(struct bpctl_dev *pbpctl_dev)
5076 struct bpctl_dev *pbpctl_dev_b = NULL;
5079 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
5081 if (pbpctl_dev->bp_caps & TPL_CAP) {
5082 del_timer_sync(&pbpctl_dev->bp_tpl_timer);
5083 pbpctl_dev->bp_tpl_flag = 0;
5084 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
5086 set_tx(pbpctl_dev_b, 1);
5087 set_tx(pbpctl_dev, 1);
5092 int init_bypass_tpl_auto(struct bpctl_dev *pbpctl_dev)
5096 if (pbpctl_dev->bp_caps & TPL_CAP) {
5097 init_timer(&pbpctl_dev->bp_tpl_timer);
5098 pbpctl_dev->bp_tpl_timer.function = &bp_tpl_timer_fn;
5099 pbpctl_dev->bp_tpl_timer.data = (unsigned long)pbpctl_dev;
5105 int set_bypass_tpl_auto(struct bpctl_dev *pbpctl_dev, unsigned int param)
5109 if (pbpctl_dev->bp_caps & TPL_CAP) {
5110 if ((param) && (!pbpctl_dev->bp_tpl_flag)) {
5111 pbpctl_dev->bp_tpl_flag = param;
5112 mod_timer(&pbpctl_dev->bp_tpl_timer, jiffies + 1);
5115 if ((!param) && (pbpctl_dev->bp_tpl_flag))
5116 remove_bypass_tpl_auto(pbpctl_dev);
5123 int get_bypass_tpl_auto(struct bpctl_dev *pbpctl_dev)
5127 if (pbpctl_dev->bp_caps & TPL_CAP)
5128 return pbpctl_dev->bp_tpl_flag;
5133 int set_tpl_fn(struct bpctl_dev *pbpctl_dev, int tpl_mode)
5136 struct bpctl_dev *pbpctl_dev_b = NULL;
5140 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
5142 if (pbpctl_dev->bp_caps & TPL_CAP) {
5144 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
5146 set_tx(pbpctl_dev_b, 1);
5147 set_tx(pbpctl_dev, 1);
5149 if ((TPL_IF_SERIES(pbpctl_dev->subdevice)) ||
5150 (pbpctl_dev->bp_caps_ex & TPL2_CAP_EX)) {
5151 pbpctl_dev->bp_tpl_flag = tpl_mode;
5153 tpl_hw_off(pbpctl_dev);
5155 tpl_hw_on(pbpctl_dev);
5157 set_bypass_tpl_auto(pbpctl_dev, tpl_mode);
5163 int get_tpl_fn(struct bpctl_dev *pbpctl_dev)
5165 int ret = BP_NOT_CAP;
5169 if (pbpctl_dev->bp_caps & TPL_CAP) {
5170 if (pbpctl_dev->bp_caps_ex & TPL2_CAP_EX)
5171 return tpl2_flag_status(pbpctl_dev);
5172 ret = pbpctl_dev->bp_tpl_flag;
5177 int set_bp_wait_at_pwup_fn(struct bpctl_dev *pbpctl_dev, int tap_mode)
5182 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
5183 /* bp_lock(pbp_device_block); */
5184 cmnd_on(pbpctl_dev);
5186 bp_wait_at_pwup_dis(pbpctl_dev);
5188 bp_wait_at_pwup_en(pbpctl_dev);
5189 cmnd_off(pbpctl_dev);
5191 /* bp_unlock(pbp_device_block); */
5197 int get_bp_wait_at_pwup_fn(struct bpctl_dev *pbpctl_dev)
5203 /* bp_lock(pbp_device_block); */
5204 ret = bp_wait_at_pwup_status(pbpctl_dev);
5205 /* bp_unlock(pbp_device_block); */
5210 int set_bp_hw_reset_fn(struct bpctl_dev *pbpctl_dev, int tap_mode)
5215 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
5216 /* bp_lock(pbp_device_block); */
5217 cmnd_on(pbpctl_dev);
5220 bp_hw_reset_dis(pbpctl_dev);
5222 bp_hw_reset_en(pbpctl_dev);
5223 cmnd_off(pbpctl_dev);
5224 /* bp_unlock(pbp_device_block); */
5230 int get_bp_hw_reset_fn(struct bpctl_dev *pbpctl_dev)
5236 /* bp_lock(pbp_device_block); */
5237 ret = bp_hw_reset_status(pbpctl_dev);
5239 /* bp_unlock(pbp_device_block); */
5245 int get_bypass_info_fn(struct bpctl_dev *pbpctl_dev, char *dev_name,
5250 if (!is_bypass_fn(pbpctl_dev))
5252 strcpy(dev_name, pbpctl_dev->name);
5253 *add_param = pbpctl_dev->bp_fw_ver;
5257 int get_dev_idx_bsf(int bus, int slot, int func)
5261 ((bpctl_dev_arr[idx_dev].pdev != NULL) && (idx_dev < device_num));
5263 if ((bus == bpctl_dev_arr[idx_dev].bus)
5264 && (slot == bpctl_dev_arr[idx_dev].slot)
5265 && (func == bpctl_dev_arr[idx_dev].func))
5272 static void str_low(char *str)
5276 for (i = 0; i < strlen(str); i++)
5277 if ((str[i] >= 65) && (str[i] <= 90))
5281 static unsigned long str_to_hex(char *p)
5283 unsigned long hex = 0;
5284 unsigned long length = strlen(p), shift = 0;
5285 unsigned char dig = 0;
5295 dig = dig < 'a' ? (dig - '0') : (dig - 'a' + 0xa);
5296 hex |= (dig << shift);
5302 static int get_dev_idx(int ifindex)
5307 ((bpctl_dev_arr[idx_dev].pdev != NULL) && (idx_dev < device_num));
5309 if (ifindex == bpctl_dev_arr[idx_dev].ifindex)
5316 static struct bpctl_dev *get_dev_idx_p(int ifindex)
5321 ((bpctl_dev_arr[idx_dev].pdev != NULL) && (idx_dev < device_num));
5323 if (ifindex == bpctl_dev_arr[idx_dev].ifindex)
5324 return &bpctl_dev_arr[idx_dev];
5330 static void if_scan_init(void)
5333 struct net_device *dev;
5335 /* rcu_read_lock(); */
5337 /* rcu_read_lock(); */
5339 for_each_netdev(&init_net, dev) {
5341 struct ethtool_drvinfo drvinfo;
5346 int bus = 0, slot = 0, func = 0;
5347 ifindex = dev->ifindex;
5350 memset(&drvinfo, 0, sizeof(struct ethtool_drvinfo));
5352 if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
5353 memset(&drvinfo, 0, sizeof(drvinfo));
5354 dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
5357 if (!strcmp(drvinfo.bus_info, "N/A"))
5359 memcpy(&cbuf, drvinfo.bus_info, 32);
5362 while (*buf++ != ':')
5364 for (i = 0; i < 10; i++, buf++) {
5371 bus = str_to_hex(res);
5374 for (i = 0; i < 10; i++, buf++) {
5381 slot = str_to_hex(res);
5382 func = str_to_hex(buf);
5383 idx_dev = get_dev_idx_bsf(bus, slot, func);
5385 if (idx_dev != -1) {
5387 bpctl_dev_arr[idx_dev].ifindex = ifindex;
5388 bpctl_dev_arr[idx_dev].ndev = dev;
5393 /* rtnl_unlock(); */
5394 /* rcu_read_unlock(); */
5398 static long device_ioctl(struct file *file, /* see include/linux/fs.h */
5399 unsigned int ioctl_num, /* number and param for ioctl */
5400 unsigned long ioctl_param)
5402 struct bpctl_cmd bpctl_cmd;
5404 struct bpctl_dev *pbpctl_dev_out;
5405 void __user *argp = (void __user *)ioctl_param;
5407 unsigned long flags;
5409 static struct bpctl_dev *pbpctl_dev;
5411 /* lock_kernel(); */
5412 if (down_interruptible(&bpctl_sema))
5413 return -ERESTARTSYS;
5414 /* local_irq_save(flags); */
5415 /* if(!spin_trylock_irqsave(&bpvm_lock)){
5416 local_irq_restore(flags);
5421 /* spin_lock_irqsave(&bpvm_lock, flags); */
5424 * Switch according to the ioctl called
5426 if (ioctl_num == IOCTL_TX_MSG(IF_SCAN)) {
5431 if (copy_from_user(&bpctl_cmd, argp, sizeof(struct bpctl_cmd))) {
5437 if (ioctl_num == IOCTL_TX_MSG(GET_DEV_NUM)) {
5438 bpctl_cmd.out_param[0] = device_num;
5440 (argp, (void *)&bpctl_cmd, sizeof(struct bpctl_cmd))) {
5449 /* preempt_disable(); */
5450 local_irq_save(flags);
5451 if (!spin_trylock(&bpvm_lock)) {
5452 local_irq_restore(flags);
5457 /* preempt_disable();
5459 spin_lock_irqsave(&bpvm_lock, flags);
5461 if ((bpctl_cmd.in_param[5]) ||
5462 (bpctl_cmd.in_param[6]) || (bpctl_cmd.in_param[7]))
5463 dev_idx = get_dev_idx_bsf(bpctl_cmd.in_param[5],
5464 bpctl_cmd.in_param[6],
5465 bpctl_cmd.in_param[7]);
5466 else if (bpctl_cmd.in_param[1] == 0)
5467 dev_idx = bpctl_cmd.in_param[0];
5469 dev_idx = get_dev_idx(bpctl_cmd.in_param[1]);
5471 if (dev_idx < 0 || dev_idx > device_num) {
5473 preempt_enable(); */
5475 /* preempt_enable();
5476 rcu_read_unlock(); */
5477 spin_unlock_irqrestore(&bpvm_lock, flags);
5481 bpctl_cmd.out_param[0] = bpctl_dev_arr[dev_idx].bus;
5482 bpctl_cmd.out_param[1] = bpctl_dev_arr[dev_idx].slot;
5483 bpctl_cmd.out_param[2] = bpctl_dev_arr[dev_idx].func;
5484 bpctl_cmd.out_param[3] = bpctl_dev_arr[dev_idx].ifindex;
5486 if ((bpctl_dev_arr[dev_idx].bp_10gb)
5487 && (!(bpctl_dev_arr[dev_idx].ifindex))) {
5488 printk("Please load network driver for %s adapter!\n",
5489 bpctl_dev_arr[dev_idx].name);
5490 bpctl_cmd.status = -1;
5492 /* preempt_enable(); */
5493 /* rcu_read_unlock(); */
5494 spin_unlock_irqrestore(&bpvm_lock, flags);
5498 if ((bpctl_dev_arr[dev_idx].bp_10gb) && (bpctl_dev_arr[dev_idx].ndev)) {
5499 if (!(bpctl_dev_arr[dev_idx].ndev->flags & IFF_UP)) {
5500 if (!(bpctl_dev_arr[dev_idx].ndev->flags & IFF_UP)) {
5502 ("Please bring up network interfaces for %s adapter!\n",
5503 bpctl_dev_arr[dev_idx].name);
5504 bpctl_cmd.status = -1;
5506 /* preempt_enable(); */
5507 /* rcu_read_unlock(); */
5508 spin_unlock_irqrestore(&bpvm_lock, flags);
5515 if ((dev_idx < 0) || (dev_idx > device_num)
5516 || (bpctl_dev_arr[dev_idx].pdev == NULL)) {
5517 bpctl_cmd.status = -1;
5521 pbpctl_dev = &bpctl_dev_arr[dev_idx];
5523 switch (ioctl_num) {
5524 case IOCTL_TX_MSG(SET_BYPASS_PWOFF):
5526 set_bypass_pwoff_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5529 case IOCTL_TX_MSG(GET_BYPASS_PWOFF):
5530 bpctl_cmd.status = get_bypass_pwoff_fn(pbpctl_dev);
5533 case IOCTL_TX_MSG(SET_BYPASS_PWUP):
5535 set_bypass_pwup_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5538 case IOCTL_TX_MSG(GET_BYPASS_PWUP):
5539 bpctl_cmd.status = get_bypass_pwup_fn(pbpctl_dev);
5542 case IOCTL_TX_MSG(SET_BYPASS_WD):
5544 set_bypass_wd_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5547 case IOCTL_TX_MSG(GET_BYPASS_WD):
5549 get_bypass_wd_fn(pbpctl_dev, (int *)&(bpctl_cmd.data[0]));
5552 case IOCTL_TX_MSG(GET_WD_EXPIRE_TIME):
5554 get_wd_expire_time_fn(pbpctl_dev,
5555 (int *)&(bpctl_cmd.data[0]));
5558 case IOCTL_TX_MSG(RESET_BYPASS_WD_TIMER):
5559 bpctl_cmd.status = reset_bypass_wd_timer_fn(pbpctl_dev);
5562 case IOCTL_TX_MSG(GET_WD_SET_CAPS):
5563 bpctl_cmd.status = get_wd_set_caps_fn(pbpctl_dev);
5566 case IOCTL_TX_MSG(SET_STD_NIC):
5568 set_std_nic_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5571 case IOCTL_TX_MSG(GET_STD_NIC):
5572 bpctl_cmd.status = get_std_nic_fn(pbpctl_dev);
5575 case IOCTL_TX_MSG(SET_TAP):
5577 set_tap_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5580 case IOCTL_TX_MSG(GET_TAP):
5581 bpctl_cmd.status = get_tap_fn(pbpctl_dev);
5584 case IOCTL_TX_MSG(GET_TAP_CHANGE):
5585 bpctl_cmd.status = get_tap_change_fn(pbpctl_dev);
5588 case IOCTL_TX_MSG(SET_DIS_TAP):
5590 set_dis_tap_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5593 case IOCTL_TX_MSG(GET_DIS_TAP):
5594 bpctl_cmd.status = get_dis_tap_fn(pbpctl_dev);
5597 case IOCTL_TX_MSG(SET_TAP_PWUP):
5599 set_tap_pwup_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5602 case IOCTL_TX_MSG(GET_TAP_PWUP):
5603 bpctl_cmd.status = get_tap_pwup_fn(pbpctl_dev);
5606 case IOCTL_TX_MSG(SET_WD_EXP_MODE):
5608 set_wd_exp_mode_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5611 case IOCTL_TX_MSG(GET_WD_EXP_MODE):
5612 bpctl_cmd.status = get_wd_exp_mode_fn(pbpctl_dev);
5615 case IOCTL_TX_MSG(GET_DIS_BYPASS):
5616 bpctl_cmd.status = get_dis_bypass_fn(pbpctl_dev);
5619 case IOCTL_TX_MSG(SET_DIS_BYPASS):
5621 set_dis_bypass_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5624 case IOCTL_TX_MSG(GET_BYPASS_CHANGE):
5625 bpctl_cmd.status = get_bypass_change_fn(pbpctl_dev);
5628 case IOCTL_TX_MSG(GET_BYPASS):
5629 bpctl_cmd.status = get_bypass_fn(pbpctl_dev);
5632 case IOCTL_TX_MSG(SET_BYPASS):
5634 set_bypass_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5637 case IOCTL_TX_MSG(GET_BYPASS_CAPS):
5638 bpctl_cmd.status = get_bypass_caps_fn(pbpctl_dev);
5639 /*preempt_enable(); */
5640 /*rcu_read_unlock();*/
5641 spin_unlock_irqrestore(&bpvm_lock, flags);
5643 (argp, (void *)&bpctl_cmd, sizeof(struct bpctl_cmd))) {
5644 /*unlock_bpctl(); */
5645 /*preempt_enable(); */
5651 case IOCTL_TX_MSG(GET_BYPASS_SLAVE):
5653 get_bypass_slave_fn(pbpctl_dev, &pbpctl_dev_out);
5654 if (bpctl_cmd.status == 1) {
5655 bpctl_cmd.out_param[4] = pbpctl_dev_out->bus;
5656 bpctl_cmd.out_param[5] = pbpctl_dev_out->slot;
5657 bpctl_cmd.out_param[6] = pbpctl_dev_out->func;
5658 bpctl_cmd.out_param[7] = pbpctl_dev_out->ifindex;
5662 case IOCTL_TX_MSG(IS_BYPASS):
5663 bpctl_cmd.status = is_bypass(pbpctl_dev);
5665 case IOCTL_TX_MSG(SET_TX):
5666 bpctl_cmd.status = set_tx_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5668 case IOCTL_TX_MSG(GET_TX):
5669 bpctl_cmd.status = get_tx_fn(pbpctl_dev);
5671 case IOCTL_TX_MSG(SET_WD_AUTORESET):
5673 set_wd_autoreset_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5676 case IOCTL_TX_MSG(GET_WD_AUTORESET):
5678 bpctl_cmd.status = get_wd_autoreset_fn(pbpctl_dev);
5680 case IOCTL_TX_MSG(SET_DISC):
5682 set_disc_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5684 case IOCTL_TX_MSG(GET_DISC):
5685 bpctl_cmd.status = get_disc_fn(pbpctl_dev);
5687 case IOCTL_TX_MSG(GET_DISC_CHANGE):
5688 bpctl_cmd.status = get_disc_change_fn(pbpctl_dev);
5690 case IOCTL_TX_MSG(SET_DIS_DISC):
5692 set_dis_disc_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5694 case IOCTL_TX_MSG(GET_DIS_DISC):
5695 bpctl_cmd.status = get_dis_disc_fn(pbpctl_dev);
5697 case IOCTL_TX_MSG(SET_DISC_PWUP):
5699 set_disc_pwup_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5701 case IOCTL_TX_MSG(GET_DISC_PWUP):
5702 bpctl_cmd.status = get_disc_pwup_fn(pbpctl_dev);
5705 case IOCTL_TX_MSG(GET_BYPASS_INFO):
5708 get_bypass_info_fn(pbpctl_dev, (char *)&bpctl_cmd.data,
5709 (char *)&bpctl_cmd.out_param[4]);
5712 case IOCTL_TX_MSG(SET_TPL):
5714 set_tpl_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5717 case IOCTL_TX_MSG(GET_TPL):
5718 bpctl_cmd.status = get_tpl_fn(pbpctl_dev);
5720 case IOCTL_TX_MSG(SET_BP_WAIT_AT_PWUP):
5722 set_bp_wait_at_pwup_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5725 case IOCTL_TX_MSG(GET_BP_WAIT_AT_PWUP):
5726 bpctl_cmd.status = get_bp_wait_at_pwup_fn(pbpctl_dev);
5728 case IOCTL_TX_MSG(SET_BP_HW_RESET):
5730 set_bp_hw_reset_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5733 case IOCTL_TX_MSG(GET_BP_HW_RESET):
5734 bpctl_cmd.status = get_bp_hw_reset_fn(pbpctl_dev);
5737 case IOCTL_TX_MSG(SET_BP_SELF_TEST):
5739 set_bp_self_test_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5742 case IOCTL_TX_MSG(GET_BP_SELF_TEST):
5743 bpctl_cmd.status = get_bp_self_test_fn(pbpctl_dev);
5748 case IOCTL_TX_MSG(SET_DISC_PORT):
5750 set_disc_port_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5753 case IOCTL_TX_MSG(GET_DISC_PORT):
5754 bpctl_cmd.status = get_disc_port_fn(pbpctl_dev);
5757 case IOCTL_TX_MSG(SET_DISC_PORT_PWUP):
5759 set_disc_port_pwup_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5762 case IOCTL_TX_MSG(GET_DISC_PORT_PWUP):
5763 bpctl_cmd.status = get_disc_port_pwup_fn(pbpctl_dev);
5766 case IOCTL_TX_MSG(SET_BP_FORCE_LINK):
5768 set_bp_force_link_fn(dev_idx, bpctl_cmd.in_param[2]);
5771 case IOCTL_TX_MSG(GET_BP_FORCE_LINK):
5772 bpctl_cmd.status = get_bp_force_link_fn(dev_idx);
5776 /* unlock_bpctl(); */
5779 /* preempt_enable(); */
5780 /* rcu_read_unlock();*/
5781 spin_unlock_irqrestore(&bpvm_lock, flags);
5784 /* unlock_bpctl(); */
5785 /* preempt_enable(); */
5787 /* rcu_read_unlock(); */
5788 spin_unlock_irqrestore(&bpvm_lock, flags);
5789 if (copy_to_user(argp, (void *)&bpctl_cmd, sizeof(struct bpctl_cmd)))
5793 /* unlock_kernel(); */
5794 /* spin_unlock_irqrestore(&bpvm_lock, flags); */
5796 /* unlock_kernel(); */
5800 static const struct file_operations Fops = {
5801 .owner = THIS_MODULE,
5802 .unlocked_ioctl = device_ioctl,
5806 #define PCI_DEVICE(vend, dev) \
5807 .vendor = (vend), .device = (dev), \
5808 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
5811 #define SILICOM_E1000BP_ETHERNET_DEVICE(device_id) {\
5812 PCI_DEVICE(SILICOM_VID, device_id)}
5975 unsigned int vendor;
5976 unsigned int device;
5977 unsigned int subvendor;
5978 unsigned int subdevice;
5987 {"Silicom Bypass PXG2BPFI-SD series adapter"},
5988 {"Silicom Bypass PXG2BPFIL-SD series adapter"},
5989 {"Silicom Bypass PXG2BPFILX-SD series adapter"},
5990 {"Silicom Bypass PXG2BPFILLX-SD series adapter"},
5991 {"Silicom Bypass PXG2BPI-SD series adapter"},
5992 {"Silicom Bypass PXG2BPIG-SD series adapter"},
5993 {"Silicom Bypass PXG2TBFI-SD series adapter"},
5994 {"Silicom Bypass PXG4BPI-SD series adapter"},
5995 {"Silicom Bypass PXG4BPFI-SD series adapter"},
5996 {"Silicom Bypass PEG4BPI-SD series adapter"},
5997 {"Silicom Bypass PEG2BPI-SD series adapter"},
5998 {"Silicom Bypass PEG4BPIN-SD series adapter"},
5999 {"Silicom Bypass PEG2BPFI-SD series adapter"},
6000 {"Silicom Bypass PEG2BPFI-LX-SD series adapter"},
6001 {"Silicom Bypass PMCX2BPFI-SD series adapter"},
6002 {"Silicom Bypass PMCX2BPFI-N series adapter"},
6003 {"Intel Bypass PEG2BPII series adapter"},
6004 {"Intel Bypass PEG2BPFII series adapter"},
6005 {"Silicom Bypass PXG4BPFILX-SD series adapter"},
6006 {"Silicom Bypass PMCX2BPI-N series adapter"},
6007 {"Silicom Bypass PMCX4BPI-N series adapter"},
6008 {"Silicom Bypass PXG2BISC1-SD series adapter"},
6009 {"Silicom Bypass PEG2TBFI-SD series adapter"},
6010 {"Silicom Bypass PXG2TBI-SD series adapter"},
6011 {"Silicom Bypass PXG4BPFID-SD series adapter"},
6012 {"Silicom Bypass PEG4BPFI-SD series adapter"},
6013 {"Silicom Bypass PEG4BPIPT-SD series adapter"},
6014 {"Silicom Bypass PXG6BPI-SD series adapter"},
6015 {"Silicom Bypass PEG4BPIL-SD series adapter"},
6016 {"Silicom Bypass PMCX2BPI-N2 series adapter"},
6017 {"Silicom Bypass PMCX4BPI-N2 series adapter"},
6018 {"Silicom Bypass PMCX2BPI-SD series adapter"},
6019 {"Silicom Bypass PEG2BPFID-SD series adapter"},
6020 {"Silicom Bypass PEG2BPFIDLX-SD series adapter"},
6021 {"Silicom Bypass PMCX4BPI-SD series adapter"},
6022 {"Silicom Bypass MEG2BPFILN-SD series adapter"},
6023 {"Silicom Bypass MEG2BPFINX-SD series adapter"},
6024 {"Silicom Bypass PEG4BPFILX-SD series adapter"},
6025 {"Silicom Bypass PE10G2BPISR-SD series adapter"},
6026 {"Silicom Bypass PE10G2BPILR-SD series adapter"},
6027 {"Silicom Bypass MHIO8AD-SD series adapter"},
6028 {"Silicom Bypass PE10G2BPICX4-SD series adapter"},
6029 {"Silicom Bypass PEG2BPI5-SD series adapter"},
6030 {"Silicom Bypass PEG6BPI5-SD series adapter"},
6031 {"Silicom Bypass PEG4BPFI5-SD series adapter"},
6032 {"Silicom Bypass PEG4BPFI5LX-SD series adapter"},
6033 {"Silicom Bypass MEG2BPFILXLN-SD series adapter"},
6034 {"Silicom Bypass PEG2BPIX1-SD series adapter"},
6035 {"Silicom Bypass MEG2BPFILXNX-SD series adapter"},
6036 {"Silicom Bypass XE10G2BPIT-SD series adapter"},
6037 {"Silicom Bypass XE10G2BPICX4-SD series adapter"},
6038 {"Silicom Bypass XE10G2BPISR-SD series adapter"},
6039 {"Silicom Bypass XE10G2BPILR-SD series adapter"},
6040 {"Intel Bypass PEG2BPFII0 series adapter"},
6041 {"Silicom Bypass XE10G2BPIXR series adapter"},
6042 {"Silicom Bypass PE10G2DBISR series adapter"},
6043 {"Silicom Bypass PEG2BI5SC6 series adapter"},
6044 {"Silicom Bypass PEG6BPI5FC series adapter"},
6046 {"Silicom Bypass PE10G2BPTCX4 series adapter"},
6047 {"Silicom Bypass PE10G2BPTSR series adapter"},
6048 {"Silicom Bypass PE10G2BPTLR series adapter"},
6049 {"Silicom Bypass PE10G2BPTT series adapter"},
6050 {"Silicom Bypass PEG4BPI6 series adapter"},
6051 {"Silicom Bypass PEG4BPFI6 series adapter"},
6052 {"Silicom Bypass PEG4BPFI6LX series adapter"},
6053 {"Silicom Bypass PEG4BPFI6ZX series adapter"},
6054 {"Silicom Bypass PEG2BPI6 series adapter"},
6055 {"Silicom Bypass PEG2BPFI6 series adapter"},
6056 {"Silicom Bypass PEG2BPFI6LX series adapter"},
6057 {"Silicom Bypass PEG2BPFI6ZX series adapter"},
6058 {"Silicom Bypass PEG2BPFI6FLXM series adapter"},
6059 {"Silicom Bypass PEG4BPI6FC series adapter"},
6060 {"Silicom Bypass PEG4BPFI6FC series adapter"},
6061 {"Silicom Bypass PEG4BPFI6FCLX series adapter"},
6062 {"Silicom Bypass PEG4BPFI6FCZX series adapter"},
6063 {"Silicom Bypass PEG6BPI6 series adapter"},
6064 {"Silicom Bypass PEG2BPI6SC6 series adapter"},
6065 {"Silicom Bypass MEG2BPI6 series adapter"},
6066 {"Silicom Bypass XEG2BPI6 series adapter"},
6067 {"Silicom Bypass MEG4BPI6 series adapter"},
6068 {"Silicom Bypass PEG2BPFI5-SD series adapter"},
6069 {"Silicom Bypass PEG2BPFI5LX-SD series adapter"},
6070 {"Silicom Bypass PXEG4BPFI-SD series adapter"},
6071 {"Silicom Bypass MxEG2BPI6 series adapter"},
6072 {"Silicom Bypass MxEG2BPFI6 series adapter"},
6073 {"Silicom Bypass MxEG2BPFI6LX series adapter"},
6074 {"Silicom Bypass MxEG2BPFI6ZX series adapter"},
6075 {"Silicom Bypass MxEG4BPI6 series adapter"},
6076 {"Silicom Bypass MxEG4BPFI6 series adapter"},
6077 {"Silicom Bypass MxEG4BPFI6LX series adapter"},
6078 {"Silicom Bypass MxEG4BPFI6ZX series adapter"},
6079 {"Silicom Bypass MxEG6BPI6 series adapter"},
6080 {"Silicom Bypass MxE2G4BPi80 series adapter"},
6081 {"Silicom Bypass MxE2G4BPFi80 series adapter"},
6082 {"Silicom Bypass MxE2G4BPFi80LX series adapter"},
6083 {"Silicom Bypass MxE2G4BPFi80ZX series adapter"},
6085 {"Silicom Bypass PE210G2SPI9 series adapter"},
6087 {"Silicom Bypass MxE210G2BPI9CX4 series adapter"},
6088 {"Silicom Bypass MxE210G2BPI9SR series adapter"},
6089 {"Silicom Bypass MxE210G2BPI9LR series adapter"},
6090 {"Silicom Bypass MxE210G2BPI9T series adapter"},
6092 {"Silicom Bypass PE210G2BPI9CX4 series adapter"},
6093 {"Silicom Bypass PE210G2BPI9SR series adapter"},
6094 {"Silicom Bypass PE210G2BPI9LR series adapter"},
6095 {"Silicom Bypass PE210G2BPI9T series adapter"},
6097 {"Silicom Bypass M2EG2BPFI6 series adapter"},
6098 {"Silicom Bypass M2EG2BPFI6LX series adapter"},
6099 {"Silicom Bypass M2EG2BPFI6ZX series adapter"},
6100 {"Silicom Bypass M2EG4BPI6 series adapter"},
6101 {"Silicom Bypass M2EG4BPFI6 series adapter"},
6102 {"Silicom Bypass M2EG4BPFI6LX series adapter"},
6103 {"Silicom Bypass M2EG4BPFI6ZX series adapter"},
6104 {"Silicom Bypass M2EG6BPI6 series adapter"},
6106 {"Silicom Bypass PEG2DBI6 series adapter"},
6107 {"Silicom Bypass PEG2DBFI6 series adapter"},
6108 {"Silicom Bypass PEG2DBFI6LX series adapter"},
6109 {"Silicom Bypass PEG2DBFI6ZX series adapter"},
6111 {"Silicom Bypass PE2G4BPi80 series adapter"},
6112 {"Silicom Bypass PE2G4BPFi80 series adapter"},
6113 {"Silicom Bypass PE2G4BPFi80LX series adapter"},
6114 {"Silicom Bypass PE2G4BPFi80ZX series adapter"},
6116 {"Silicom Bypass PE2G4BPi80L series adapter"},
6117 {"Silicom Bypass MxE2G8BPi80A series adapter"},
6119 {"Silicom Bypass PE2G2BPi35 series adapter"},
6120 {"Silicom Bypass PAC1200BPi35 series adapter"},
6121 {"Silicom Bypass PE2G2BPFi35 series adapter"},
6122 {"Silicom Bypass PE2G2BPFi35LX series adapter"},
6123 {"Silicom Bypass PE2G2BPFi35ZX series adapter"},
6125 {"Silicom Bypass PE2G4BPi35 series adapter"},
6126 {"Silicom Bypass PE2G4BPi35L series adapter"},
6127 {"Silicom Bypass PE2G4BPFi35 series adapter"},
6128 {"Silicom Bypass PE2G4BPFi35LX series adapter"},
6129 {"Silicom Bypass PE2G4BPFi35ZX series adapter"},
6131 {"Silicom Bypass PE2G6BPi35 series adapter"},
6132 {"Silicom Bypass PE2G6BPi35CX series adapter"},
6134 {"Silicom Bypass PE2G2BPi80 series adapter"},
6135 {"Silicom Bypass PE2G2BPFi80 series adapter"},
6136 {"Silicom Bypass PE2G2BPFi80LX series adapter"},
6137 {"Silicom Bypass PE2G2BPFi80ZX series adapter"},
6139 {"Silicom Bypass M2E10G2BPI9CX4 series adapter"},
6140 {"Silicom Bypass M2E10G2BPI9SR series adapter"},
6141 {"Silicom Bypass M2E10G2BPI9LR series adapter"},
6142 {"Silicom Bypass M2E10G2BPI9T series adapter"},
6143 {"Silicom Bypass MxE2G8BPi80 series adapter"},
6144 {"Silicom Bypass PE210G2DBi9SR series adapter"},
6145 {"Silicom Bypass PE210G2DBi9SRRB series adapter"},
6146 {"Silicom Bypass PE210G2DBi9LR series adapter"},
6147 {"Silicom Bypass PE210G2DBi9LRRB series adapter"},
6148 {"Silicom Bypass PE310G4DBi9-SR series adapter"},
6149 {"Silicom Bypass PE310G4BPi9T series adapter"},
6150 {"Silicom Bypass PE310G4BPi9SR series adapter"},
6151 {"Silicom Bypass PE310G4BPi9LR series adapter"},
6152 {"Silicom Bypass PE210G2BPi40T series adapter"},
6156 static struct bpmod_info tx_ctl_pci_tbl[] = {
6157 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG2BPFI_SSID, PXG2BPFI,
6159 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG2BPFIL_SSID, PXG2BPFIL,
6161 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG2BPFILX_SSID, PXG2BPFILX,
6163 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG2BPFILLX_SSID, PXG2BPFILLX,
6165 {0x8086, 0x1010, SILICOM_SVID, SILICOM_PXGBPI_SSID, PXGBPI,
6167 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PXGBPIG_SSID, PXGBPIG,
6169 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG2TBFI_SSID, PXG2TBFI,
6171 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PXG4BPI_SSID, PXG4BPI,
6173 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG4BPFI_SSID, PXG4BPFI,
6175 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG4BPFILX_SSID, PXG4BPFILX,
6177 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PEG4BPI_SSID, PEG4BPI,
6179 {0x8086, 0x105e, SILICOM_SVID, SILICOM_PEG2BPI_SSID, PEG2BPI,
6181 {0x8086, 0x105e, SILICOM_SVID, SILICOM_PEG4BPIN_SSID, PEG4BPIN,
6183 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG2BPFI_SSID, PEG2BPFI,
6185 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG2BPFILX_SSID, PEG2BPFILX,
6187 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PMCXG2BPFI_SSID, PMCXG2BPFI,
6189 {0x8086, 0x107a, NOKIA_PMCXG2BPFIN_SVID, NOKIA_PMCXG2BPFIN_SSID,
6190 PMCXG2BPFIN, "PMCX2BPFI-N"},
6191 {0x8086, INTEL_PEG4BPII_PID, 0x8086, INTEL_PEG4BPII_SSID, PEG4BPII,
6193 {0x8086, INTEL_PEG4BPIIO_PID, 0x8086, INTEL_PEG4BPIIO_SSID, PEG4BPIIO,
6195 {0x8086, INTEL_PEG4BPFII_PID, 0x8086, INTEL_PEG4BPFII_SSID, PEG4BPFII,
6197 {0x8086, 0x1079, NOKIA_PMCXG2BPFIN_SVID, NOKIA_PMCXG2BPIN_SSID,
6198 PMCXG2BPIN, "PMCX2BPI-N"},
6199 {0x8086, 0x1079, NOKIA_PMCXG2BPFIN_SVID, NOKIA_PMCXG4BPIN_SSID,
6200 PMCXG4BPIN, "PMCX4BPI-N"},
6201 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PXG2BISC1_SSID, PXG2BISC1,
6203 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG2TBFI_SSID, PEG2TBFI,
6205 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PXG2TBI_SSID, PXG2TBI,
6207 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG4BPFID_SSID, PXG4BPFID,
6209 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG4BPFI_SSID, PEG4BPFI,
6211 {0x8086, 0x105e, SILICOM_SVID, SILICOM_PEG4BPIPT_SSID, PEG4BPIPT,
6213 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PXG6BPI_SSID, PXG6BPI,
6215 {0x8086, 0x10a7, SILICOM_SVID /*PCI_ANY_ID */ ,
6216 SILICOM_PEG4BPIL_SSID /*PCI_ANY_ID */ , PEG4BPIL, "PEG4BPIL-SD"},
6217 {0x8086, 0x1079, NOKIA_PMCXG2BPFIN_SVID, NOKIA_PMCXG2BPIN2_SSID,
6218 PMCXG2BPIN2, "PMCX2BPI-N2"},
6219 {0x8086, 0x1079, NOKIA_PMCXG2BPFIN_SVID, NOKIA_PMCXG4BPIN2_SSID,
6220 PMCXG4BPIN2, "PMCX4BPI-N2"},
6221 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PMCX2BPI_SSID, PMCX2BPI,
6223 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PMCX4BPI_SSID, PMCX4BPI,
6225 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG2BPFID_SSID, PEG2BPFID,
6227 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG2BPFIDLX_SSID, PEG2BPFIDLX,
6229 {0x8086, 0x105f, SILICOM_SVID, SILICOM_MEG2BPFILN_SSID, MEG2BPFILN,
6231 {0x8086, 0x105f, SILICOM_SVID, SILICOM_MEG2BPFINX_SSID, MEG2BPFINX,
6233 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG4BPFILX_SSID, PEG4BPFILX,
6235 {0x8086, PCI_ANY_ID, SILICOM_SVID, SILICOM_PE10G2BPISR_SSID,
6236 PE10G2BPISR, "PE10G2BPISR"},
6237 {0x8086, PCI_ANY_ID, SILICOM_SVID, SILICOM_PE10G2BPILR_SSID,
6238 PE10G2BPILR, "PE10G2BPILR"},
6239 {0x8086, 0x10a9, SILICOM_SVID, SILICOM_MHIO8AD_SSID, MHIO8AD,
6241 {0x8086, PCI_ANY_ID, SILICOM_SVID, SILICOM_PE10G2BPICX4_SSID,
6242 PE10G2BPISR, "PE10G2BPICX4"},
6243 {0x8086, 0x10a7, SILICOM_SVID /*PCI_ANY_ID */ ,
6244 SILICOM_PEG2BPI5_SSID /*PCI_ANY_ID */ , PEG2BPI5, "PEG2BPI5-SD"},
6245 {0x8086, 0x10a7, SILICOM_SVID /*PCI_ANY_ID */ ,
6246 SILICOM_PEG6BPI_SSID /*PCI_ANY_ID */ , PEG6BPI, "PEG6BPI5"},
6247 {0x8086, 0x10a9, SILICOM_SVID /*PCI_ANY_ID */ , SILICOM_PEG4BPFI5_SSID,
6248 PEG4BPFI5, "PEG4BPFI5"},
6249 {0x8086, 0x10a9, SILICOM_SVID /*PCI_ANY_ID */ ,
6250 SILICOM_PEG4BPFI5LX_SSID, PEG4BPFI5LX, "PEG4BPFI5LX"},
6251 {0x8086, 0x105f, SILICOM_SVID, SILICOM_MEG2BPFILXLN_SSID, MEG2BPFILXLN,
6253 {0x8086, 0x105e, SILICOM_SVID, SILICOM_PEG2BPIX1_SSID, PEG2BPIX1,
6255 {0x8086, 0x105f, SILICOM_SVID, SILICOM_MEG2BPFILXNX_SSID, MEG2BPFILXNX,
6257 {0x8086, PCI_ANY_ID, SILICOM_SVID, SILICOM_XE10G2BPIT_SSID, XE10G2BPIT,
6259 {0x8086, PCI_ANY_ID, SILICOM_SVID, SILICOM_XE10G2BPICX4_SSID,
6260 XE10G2BPICX4, "XE10G2BPICX4"},
6261 {0x8086, 0x10C6, SILICOM_SVID, SILICOM_XE10G2BPISR_SSID, XE10G2BPISR,
6263 {0x8086, 0x10C6, SILICOM_SVID, SILICOM_XE10G2BPILR_SSID, XE10G2BPILR,
6265 {0x8086, 0x10C6, NOKIA_XE10G2BPIXR_SVID, NOKIA_XE10G2BPIXR_SSID,
6266 XE10G2BPIXR, "XE10G2BPIXR"},
6267 {0x8086, 0x10C6, SILICOM_SVID, SILICOM_PE10GDBISR_SSID, PE10GDBISR,
6269 {0x8086, 0x10C6, SILICOM_SVID, SILICOM_PE10GDBILR_SSID, PE10GDBILR,
6271 {0x8086, 0x10a7, SILICOM_SVID /*PCI_ANY_ID */ ,
6272 SILICOM_PEG2BISC6_SSID /*PCI_ANY_ID */ , PEG2BISC6, "PEG2BI5SC6"},
6273 {0x8086, 0x10a7, SILICOM_SVID /*PCI_ANY_ID */ ,
6274 SILICOM_PEG6BPIFC_SSID /*PCI_ANY_ID */ , PEG6BPIFC, "PEG6BPI5FC"},
6276 {BROADCOM_VID, BROADCOM_PE10G2_PID, SILICOM_SVID,
6277 SILICOM_PE10G2BPTCX4_SSID, PE10G2BPTCX4, "PE10G2BPTCX4"},
6278 {BROADCOM_VID, BROADCOM_PE10G2_PID, SILICOM_SVID,
6279 SILICOM_PE10G2BPTSR_SSID, PE10G2BPTSR, "PE10G2BPTSR"},
6280 {BROADCOM_VID, BROADCOM_PE10G2_PID, SILICOM_SVID,
6281 SILICOM_PE10G2BPTLR_SSID, PE10G2BPTLR, "PE10G2BPTLR"},
6282 {BROADCOM_VID, BROADCOM_PE10G2_PID, SILICOM_SVID,
6283 SILICOM_PE10G2BPTT_SSID, PE10G2BPTT, "PE10G2BPTT"},
6285 /* {BROADCOM_VID, BROADCOM_PE10G2_PID, PCI_ANY_ID, PCI_ANY_ID, PE10G2BPTCX4, "PE10G2BPTCX4"}, */
6287 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6288 SILICOM_PEG4BPI6_SSID /*PCI_ANY_ID */ , PEG4BPI6, "PEG4BPI6"},
6289 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6290 SILICOM_PEG4BPFI6_SSID /*PCI_ANY_ID */ , PEG4BPFI6, "PEG4BPFI6"},
6291 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6292 SILICOM_PEG4BPFI6LX_SSID /*PCI_ANY_ID */ , PEG4BPFI6LX, "PEG4BPFI6LX"},
6293 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6294 SILICOM_PEG4BPFI6ZX_SSID /*PCI_ANY_ID */ , PEG4BPFI6ZX, "PEG4BPFI6ZX"},
6295 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6296 SILICOM_PEG2BPI6_SSID /*PCI_ANY_ID */ , PEG2BPI6, "PEG2BPI6"},
6297 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6298 SILICOM_PEG2BPFI6_SSID /*PCI_ANY_ID */ , PEG2BPFI6, "PEG2BPFI6"},
6299 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6300 SILICOM_PEG2BPFI6LX_SSID /*PCI_ANY_ID */ , PEG2BPFI6LX, "PEG2BPFI6LX"},
6301 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6302 SILICOM_PEG2BPFI6ZX_SSID /*PCI_ANY_ID */ , PEG2BPFI6ZX, "PEG2BPFI6ZX"},
6303 {0x8086, 0x10e7, SILICOM_SVID /*PCI_ANY_ID */ ,
6304 SILICOM_PEG2BPFI6FLXM_SSID /*PCI_ANY_ID */ , PEG2BPFI6FLXM,
6306 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6307 SILICOM_PEG4BPI6FC_SSID /*PCI_ANY_ID */ , PEG4BPI6FC, "PEG4BPI6FC"},
6308 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6309 SILICOM_PEG4BPFI6FC_SSID /*PCI_ANY_ID */ , PEG4BPFI6FC, "PEG4BPFI6FC"},
6310 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6311 SILICOM_PEG4BPFI6FCLX_SSID /*PCI_ANY_ID */ , PEG4BPFI6FCLX,
6313 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6314 SILICOM_PEG4BPFI6FCZX_SSID /*PCI_ANY_ID */ , PEG4BPFI6FCZX,
6316 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6317 SILICOM_PEG6BPI6_SSID /*PCI_ANY_ID */ , PEG6BPI6, "PEG6BPI6"},
6318 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6319 SILICOM_PEG2BPI6SC6_SSID /*PCI_ANY_ID */ , PEG2BPI6SC6,
6321 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6322 SILICOM_MEG2BPI6_SSID /*PCI_ANY_ID */ , MEG2BPI6, "MEG2BPI6"},
6323 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6324 SILICOM_XEG2BPI6_SSID /*PCI_ANY_ID */ , XEG2BPI6, "XEG2BPI6"},
6325 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6326 SILICOM_MEG4BPI6_SSID /*PCI_ANY_ID */ , MEG4BPI6, "MEG4BPI6"},
6328 {0x8086, 0x10a9, SILICOM_SVID /*PCI_ANY_ID */ , SILICOM_PEG2BPFI5_SSID,
6329 PEG2BPFI5, "PEG2BPFI5"},
6330 {0x8086, 0x10a9, SILICOM_SVID /*PCI_ANY_ID */ ,
6331 SILICOM_PEG2BPFI5LX_SSID, PEG2BPFI5LX, "PEG2BPFI5LX"},
6333 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PXEG4BPFI_SSID, PXEG4BPFI,
6336 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6337 SILICOM_M1EG2BPI6_SSID /*PCI_ANY_ID */ , M1EG2BPI6, "MxEG2BPI6"},
6339 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6340 SILICOM_M1EG2BPFI6_SSID /*PCI_ANY_ID */ , M1EG2BPFI6, "MxEG2BPFI6"},
6341 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6342 SILICOM_M1EG2BPFI6LX_SSID /*PCI_ANY_ID */ , M1EG2BPFI6LX,
6344 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6345 SILICOM_M1EG2BPFI6ZX_SSID /*PCI_ANY_ID */ , M1EG2BPFI6ZX,
6348 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6349 SILICOM_M1EG4BPI6_SSID /*PCI_ANY_ID */ , M1EG4BPI6, "MxEG4BPI6"},
6351 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6352 SILICOM_M1EG4BPFI6_SSID /*PCI_ANY_ID */ , M1EG4BPFI6, "MxEG4BPFI6"},
6353 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6354 SILICOM_M1EG4BPFI6LX_SSID /*PCI_ANY_ID */ , M1EG4BPFI6LX,
6356 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6357 SILICOM_M1EG4BPFI6ZX_SSID /*PCI_ANY_ID */ , M1EG4BPFI6ZX,
6360 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6361 SILICOM_M1EG6BPI6_SSID /*PCI_ANY_ID */ , M1EG6BPI6, "MxEG6BPI6"},
6363 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6364 SILICOM_M1E2G4BPi80_SSID /*PCI_ANY_ID */ , M1E2G4BPi80, "MxE2G4BPi80"},
6365 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6366 SILICOM_M1E2G4BPFi80_SSID /*PCI_ANY_ID */ , M1E2G4BPFi80,
6368 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6369 SILICOM_M1E2G4BPFi80LX_SSID /*PCI_ANY_ID */ , M1E2G4BPFi80LX,
6371 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6372 SILICOM_M1E2G4BPFi80ZX_SSID /*PCI_ANY_ID */ , M1E2G4BPFi80ZX,
6375 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6376 SILICOM_M2EG2BPFI6_SSID /*PCI_ANY_ID */ , M2EG2BPFI6, "M2EG2BPFI6"},
6377 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6378 SILICOM_M2EG2BPFI6LX_SSID /*PCI_ANY_ID */ , M2EG2BPFI6LX,
6380 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6381 SILICOM_M2EG2BPFI6ZX_SSID /*PCI_ANY_ID */ , M2EG2BPFI6ZX,
6384 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6385 SILICOM_M2EG4BPI6_SSID /*PCI_ANY_ID */ , M2EG4BPI6, "M2EG4BPI6"},
6387 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6388 SILICOM_M2EG4BPFI6_SSID /*PCI_ANY_ID */ , M2EG4BPFI6, "M2EG4BPFI6"},
6389 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6390 SILICOM_M2EG4BPFI6LX_SSID /*PCI_ANY_ID */ , M2EG4BPFI6LX,
6392 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6393 SILICOM_M2EG4BPFI6ZX_SSID /*PCI_ANY_ID */ , M2EG4BPFI6ZX,
6396 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6397 SILICOM_M2EG6BPI6_SSID /*PCI_ANY_ID */ , M2EG6BPI6, "M2EG6BPI6"},
6399 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6400 SILICOM_PEG2DBI6_SSID /*PCI_ANY_ID */ , PEG2DBI6, "PEG2DBI6"},
6401 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6402 SILICOM_PEG2DBFI6_SSID /*PCI_ANY_ID */ , PEG2DBFI6, "PEG2DBFI6"},
6403 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6404 SILICOM_PEG2DBFI6LX_SSID /*PCI_ANY_ID */ , PEG2DBFI6LX, "PEG2DBFI6LX"},
6405 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6406 SILICOM_PEG2DBFI6ZX_SSID /*PCI_ANY_ID */ , PEG2DBFI6ZX, "PEG2DBFI6ZX"},
6408 {0x8086, 0x10F9, SILICOM_SVID /*PCI_ANY_ID */ ,
6409 SILICOM_PE210G2DBi9SR_SSID, PE210G2DBi9SR, "PE210G2DBi9SR"},
6410 {0x8086, 0x10F9, SILICOM_SVID /*PCI_ANY_ID */ ,
6411 SILICOM_PE210G2DBi9LR_SSID, PE210G2DBi9LR, "PE210G2DBi9LR"},
6412 {0x8086, 0x10F9, SILICOM_SVID /*PCI_ANY_ID */ ,
6413 SILICOM_PE310G4DBi940SR_SSID, PE310G4DBi940SR, "PE310G4DBi9SR"},
6415 {0x8086, 0x10Fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6416 SILICOM_PE310G4BPi9T_SSID, PE310G4BPi9T, "PE310G4BPi9T"},
6417 {0x8086, 0x10Fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6418 SILICOM_PE310G4BPi9SR_SSID, PE310G4BPi9SR, "PE310G4BPi9SR"},
6419 {0x8086, 0x10Fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6420 SILICOM_PE310G4BPi9LR_SSID, PE310G4BPi9LR, "PE310G4BPi9LR"},
6422 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6423 SILICOM_PE2G4BPi80_SSID /*PCI_ANY_ID */ , PE2G4BPi80, "PE2G4BPi80"},
6424 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6425 SILICOM_PE2G4BPFi80_SSID /*PCI_ANY_ID */ , PE2G4BPFi80, "PE2G4BPFi80"},
6426 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6427 SILICOM_PE2G4BPFi80LX_SSID /*PCI_ANY_ID */ , PE2G4BPFi80LX,
6429 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6430 SILICOM_PE2G4BPFi80ZX_SSID /*PCI_ANY_ID */ , PE2G4BPFi80ZX,
6433 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6434 SILICOM_PE2G4BPi80L_SSID /*PCI_ANY_ID */ , PE2G4BPi80L, "PE2G4BPi80L"},
6436 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6437 SILICOM_M6E2G8BPi80A_SSID /*PCI_ANY_ID */ , M6E2G8BPi80A,
6440 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6441 SILICOM_PE2G2BPi35_SSID /*PCI_ANY_ID */ , PE2G2BPi35, "PE2G2BPi35"},
6442 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6443 SILICOM_PAC1200BPi35_SSID /*PCI_ANY_ID */ , PAC1200BPi35,
6446 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6447 SILICOM_PE2G2BPFi35_SSID /*PCI_ANY_ID */ , PE2G2BPFi35, "PE2G2BPFi35"},
6448 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6449 SILICOM_PE2G2BPFi35LX_SSID /*PCI_ANY_ID */ , PE2G2BPFi35LX,
6451 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6452 SILICOM_PE2G2BPFi35ZX_SSID /*PCI_ANY_ID */ , PE2G2BPFi35ZX,
6455 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6456 SILICOM_PE2G4BPi35_SSID /*PCI_ANY_ID */ , PE2G4BPi35, "PE2G4BPi35"},
6458 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6459 SILICOM_PE2G4BPi35L_SSID /*PCI_ANY_ID */ , PE2G4BPi35L, "PE2G4BPi35L"},
6461 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6462 SILICOM_PE2G4BPFi35_SSID /*PCI_ANY_ID */ , PE2G4BPFi35, "PE2G4BPFi35"},
6463 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6464 SILICOM_PE2G4BPFi35LX_SSID /*PCI_ANY_ID */ , PE2G4BPFi35LX,
6466 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6467 SILICOM_PE2G4BPFi35ZX_SSID /*PCI_ANY_ID */ , PE2G4BPFi35ZX,
6470 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6471 SILICOM_PE2G6BPi35_SSID /*PCI_ANY_ID */ , PE2G6BPi35, "PE2G6BPi35"},
6474 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa0, PE2G6BPi35CX,
6476 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa1, PE2G6BPi35CX,
6478 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa2, PE2G6BPi35CX,
6480 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa3, PE2G6BPi35CX,
6482 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa4, PE2G6BPi35CX,
6484 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa5, PE2G6BPi35CX,
6486 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa6, PE2G6BPi35CX,
6488 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa7, PE2G6BPi35CX,
6490 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa8, PE2G6BPi35CX,
6492 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa9, PE2G6BPi35CX,
6494 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaaa, PE2G6BPi35CX,
6496 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaab, PE2G6BPi35CX,
6498 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaac, PE2G6BPi35CX,
6500 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaad, PE2G6BPi35CX,
6502 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaae, PE2G6BPi35CX,
6504 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaaf, PE2G6BPi35CX,
6506 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab0, PE2G6BPi35CX,
6508 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab1, PE2G6BPi35CX,
6510 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab2, PE2G6BPi35CX,
6512 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab3, PE2G6BPi35CX,
6514 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab4, PE2G6BPi35CX,
6516 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab5, PE2G6BPi35CX,
6518 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab6, PE2G6BPi35CX,
6520 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab7, PE2G6BPi35CX,
6522 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab8, PE2G6BPi35CX,
6524 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab9, PE2G6BPi35CX,
6526 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaba, PE2G6BPi35CX,
6528 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xabb, PE2G6BPi35CX,
6530 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xabc, PE2G6BPi35CX,
6532 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xabd, PE2G6BPi35CX,
6534 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xabe, PE2G6BPi35CX,
6536 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xabf, PE2G6BPi35CX,
6539 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6540 SILICOM_PE2G2BPi80_SSID /*PCI_ANY_ID */ , PE2G2BPi80, "PE2G2BPi80"},
6541 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6542 SILICOM_PE2G2BPFi80_SSID /*PCI_ANY_ID */ , PE2G2BPFi80, "PE2G2BPFi80"},
6543 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6544 SILICOM_PE2G2BPFi80LX_SSID /*PCI_ANY_ID */ , PE2G2BPFi80LX,
6546 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6547 SILICOM_PE2G2BPFi80ZX_SSID /*PCI_ANY_ID */ , PE2G2BPFi80ZX,
6550 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6551 SILICOM_MEG2BPI6_SSID /*PCI_ANY_ID */ , MEG2BPI6, "MEG2BPI6"},
6552 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6553 SILICOM_XEG2BPI6_SSID /*PCI_ANY_ID */ , XEG2BPI6, "XEG2BPI6"},
6556 {0x8086, 0x10fb, 0x8086, INTEL_PE210G2SPI9_SSID, PE210G2SPI9,
6559 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6560 SILICOM_M1E10G2BPI9CX4_SSID /*PCI_ANY_ID */ , M1E10G2BPI9CX4,
6562 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6563 SILICOM_M1E10G2BPI9SR_SSID /*PCI_ANY_ID */ , M1E10G2BPI9SR,
6565 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6566 SILICOM_M1E10G2BPI9LR_SSID /*PCI_ANY_ID */ , M1E10G2BPI9LR,
6568 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6569 SILICOM_M1E10G2BPI9T_SSID /*PCI_ANY_ID */ , M1E10G2BPI9T,
6572 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6573 SILICOM_M2E10G2BPI9CX4_SSID /*PCI_ANY_ID */ , M2E10G2BPI9CX4,
6575 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6576 SILICOM_M2E10G2BPI9SR_SSID /*PCI_ANY_ID */ , M2E10G2BPI9SR,
6578 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6579 SILICOM_M2E10G2BPI9LR_SSID /*PCI_ANY_ID */ , M2E10G2BPI9LR,
6581 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6582 SILICOM_M2E10G2BPI9T_SSID /*PCI_ANY_ID */ , M2E10G2BPI9T,
6585 {0x8086, 0x10fb, SILICOM_SVID, SILICOM_PE210G2BPI9CX4_SSID,
6586 PE210G2BPI9CX4, "PE210G2BPI9CX4"},
6587 {0x8086, 0x10fb, SILICOM_SVID, SILICOM_PE210G2BPI9SR_SSID,
6588 PE210G2BPI9SR, "PE210G2BPI9SR"},
6589 {0x8086, 0x10fb, SILICOM_SVID, SILICOM_PE210G2BPI9LR_SSID,
6590 PE210G2BPI9LR, "PE210G2BPI9LR"},
6591 {0x8086, 0x10fb, SILICOM_SVID, SILICOM_PE210G2BPI9T_SSID, PE210G2BPI9T,
6595 {0x1374, 0x2c, SILICOM_SVID, SILICOM_PXG4BPI_SSID, PXG4BPI,
6598 {0x1374, 0x2d, SILICOM_SVID, SILICOM_PXG4BPFI_SSID, PXG4BPFI,
6601 {0x1374, 0x3f, SILICOM_SVID, SILICOM_PXG2TBI_SSID, PXG2TBI,
6604 {0x1374, 0x3d, SILICOM_SVID, SILICOM_PXG2BISC1_SSID, PXG2BISC1,
6607 {0x1374, 0x40, SILICOM_SVID, SILICOM_PEG4BPFI_SSID, PEG4BPFI,
6611 {0x1374, 0x28, SILICOM_SVID, 0x28, PXGBPI, "PXG2BPI-SD"},
6614 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6615 SILICOM_M6E2G8BPi80_SSID /*PCI_ANY_ID */ , M6E2G8BPi80, "MxE2G8BPi80"},
6616 {0x8086, 0x1528, SILICOM_SVID /*PCI_ANY_ID */ ,
6617 SILICOM_PE210G2BPi40_SSID /*PCI_ANY_ID */ , PE210G2BPi40,
6620 /* required last entry */
6624 static void find_fw(struct bpctl_dev *dev)
6626 unsigned long mmio_start, mmio_len;
6627 struct pci_dev *pdev1 = dev->pdev;
6629 if ((OLD_IF_SERIES(dev->subdevice)) ||
6630 (INTEL_IF_SERIES(dev->subdevice)))
6631 dev->bp_fw_ver = 0xff;
6633 dev->bp_fw_ver = bypass_fw_ver(dev);
6635 if (dev->bp_10gb == 1 && dev->bp_fw_ver == 0xff) {
6638 iounmap((void *)dev->mem_map);
6639 mmio_start = pci_resource_start(pdev1, 0);
6640 mmio_len = pci_resource_len(pdev1, 0);
6642 dev->mem_map = (unsigned long)
6643 ioremap(mmio_start, mmio_len);
6645 dev->bp_fw_ver = bypass_fw_ver(dev);
6646 if (dev->bp_fw_ver == 0xa8)
6650 /* dev->bp_fw_ver=0xa8; */
6651 printk("firmware version: 0x%x\n", dev->bp_fw_ver);
6654 static int init_one(struct bpctl_dev *dev, struct bpmod_info *info, struct pci_dev *pdev1)
6656 unsigned long mmio_start, mmio_len;
6659 mmio_start = pci_resource_start(pdev1, 0);
6660 mmio_len = pci_resource_len(pdev1, 0);
6662 dev->desc = dev_desc[info->index].name;
6663 dev->name = info->bp_name;
6664 dev->device = info->device;
6665 dev->vendor = info->vendor;
6666 dev->subdevice = info->subdevice;
6667 dev->subvendor = info->subvendor;
6668 dev->func = PCI_FUNC(pdev1->devfn);
6669 dev->slot = PCI_SLOT(pdev1->devfn);
6670 dev->bus = pdev1->bus->number;
6671 dev->mem_map = (unsigned long)ioremap(mmio_start, mmio_len);
6673 spin_lock_init(&dev->bypass_wr_lock);
6675 if (BP10G9_IF_SERIES(dev->subdevice))
6677 if (BP10G_IF_SERIES(dev->subdevice))
6679 if (PEG540_IF_SERIES(dev->subdevice))
6681 if (PEGF5_IF_SERIES(dev->subdevice))
6683 if (PEG80_IF_SERIES(dev->subdevice))
6685 if (PEGF80_IF_SERIES(dev->subdevice))
6687 if ((dev->subdevice & 0xa00) == 0xa00)
6689 if (BP10GB_IF_SERIES(dev->subdevice)) {
6690 if (dev->ifindex == 0) {
6691 unregister_chrdev(major_num, DEVICE_NAME);
6692 printk("Please load network driver for %s adapter!\n",
6697 if (dev->ndev && !(dev->ndev->flags & IFF_UP)) {
6698 unregister_chrdev(major_num, DEVICE_NAME);
6699 printk("Please bring up network interfaces for %s adapter!\n",
6706 if (!dev->bp_10g9) {
6707 if (is_bypass_fn(dev)) {
6708 printk(KERN_INFO "%s found, ",
6712 dev->wdt_status = WDT_STATUS_UNKNOWN;
6713 dev->reset_time = 0;
6714 atomic_set(&dev->wdt_busy, 0);
6715 dev->bp_status_un = 1;
6717 bypass_caps_init(dev);
6719 init_bypass_wd_auto(dev);
6720 init_bypass_tpl_auto(dev);
6721 if (NOKIA_SERIES(dev->subdevice))
6725 dev->bp_tx_data = kzalloc(BPTEST_DATA_LEN, GFP_KERNEL);
6726 if (dev->bp_tx_data) {
6727 memset(dev->bp_tx_data, 0xff, 6);
6728 memset(dev->bp_tx_data + 6, 0x0, 1);
6729 memset(dev->bp_tx_data + 7, 0xaa, 5);
6730 *(__be16 *)(dev->bp_tx_data + 12) = htons(ETH_P_BPTEST);
6732 printk("bp_ctl: Memory allocation error!\n");
6738 * Initialize the module - Register the character device
6741 static int __init bypass_init_module(void)
6743 int ret_val, idx, idx_dev = 0;
6744 struct pci_dev *pdev1 = NULL;
6745 struct bpctl_dev *dev;
6747 printk(BP_MOD_DESCR " v" BP_MOD_VER "\n");
6748 ret_val = register_chrdev(major_num, DEVICE_NAME, &Fops);
6750 printk("%s failed with %d\n", DEVICE_NAME, ret_val);
6753 major_num = ret_val; /* dynamic */
6754 for (idx = 0; tx_ctl_pci_tbl[idx].vendor; idx++) {
6755 while ((pdev1 = pci_get_subsys(tx_ctl_pci_tbl[idx].vendor,
6756 tx_ctl_pci_tbl[idx].device,
6757 tx_ctl_pci_tbl[idx].subvendor,
6758 tx_ctl_pci_tbl[idx].subdevice,
6765 printk("No such device\n");
6766 unregister_chrdev(major_num, DEVICE_NAME);
6770 bpctl_dev_arr = kmalloc((device_num) * sizeof(struct bpctl_dev), GFP_KERNEL);
6772 if (!bpctl_dev_arr) {
6773 printk("Allocation error\n");
6774 unregister_chrdev(major_num, DEVICE_NAME);
6777 memset(bpctl_dev_arr, 0, ((device_num) * sizeof(struct bpctl_dev)));
6780 dev = bpctl_dev_arr;
6781 for (idx = 0; tx_ctl_pci_tbl[idx].vendor; idx++) {
6782 while ((pdev1 = pci_get_subsys(tx_ctl_pci_tbl[idx].vendor,
6783 tx_ctl_pci_tbl[idx].device,
6784 tx_ctl_pci_tbl[idx].subvendor,
6785 tx_ctl_pci_tbl[idx].subdevice,
6787 if (init_one(dev, &tx_ctl_pci_tbl[idx], pdev1) < 0)
6794 sema_init(&bpctl_sema, 1);
6795 spin_lock_init(&bpvm_lock);
6798 struct bpctl_dev *pbpctl_dev_c = NULL;
6799 for (idx_dev = 0, dev = bpctl_dev_arr;
6800 idx_dev < device_num && dev->pdev;
6803 pbpctl_dev_c = get_status_port_fn(dev);
6804 if (is_bypass_fn(dev)) {
6805 printk(KERN_INFO "%s found, ",
6807 dev->bp_fw_ver = bypass_fw_ver(dev);
6808 printk("firmware version: 0x%x\n",
6811 dev->wdt_status = WDT_STATUS_UNKNOWN;
6812 dev->reset_time = 0;
6813 atomic_set(&dev->wdt_busy, 0);
6814 dev->bp_status_un = 1;
6816 bypass_caps_init(dev);
6818 init_bypass_wd_auto(dev);
6819 init_bypass_tpl_auto(dev);
6826 register_netdevice_notifier(&bp_notifier_block);
6827 #ifdef BP_PROC_SUPPORT
6830 /* unsigned long flags; */
6831 /* rcu_read_lock(); */
6833 for (i = 0; i < device_num; i++) {
6834 if (bpctl_dev_arr[i].ifindex) {
6835 /* spin_lock_irqsave(&bpvm_lock, flags); */
6836 bypass_proc_remove_dev_sd(&bpctl_dev_arr[i]);
6837 bypass_proc_create_dev_sd(&bpctl_dev_arr[i]);
6838 /* spin_unlock_irqrestore(&bpvm_lock, flags); */
6842 /* rcu_read_unlock(); */
6850 * Cleanup - unregister the appropriate file from /proc
6852 static void __exit bypass_cleanup_module(void)
6855 unregister_netdevice_notifier(&bp_notifier_block);
6857 for (i = 0; i < device_num; i++) {
6858 /* unsigned long flags; */
6859 #ifdef BP_PROC_SUPPORT
6860 /* spin_lock_irqsave(&bpvm_lock, flags);
6862 bypass_proc_remove_dev_sd(&bpctl_dev_arr[i]);
6863 /* spin_unlock_irqrestore(&bpvm_lock, flags);
6864 rcu_read_unlock(); */
6866 remove_bypass_wd_auto(&bpctl_dev_arr[i]);
6867 bpctl_dev_arr[i].reset_time = 0;
6869 remove_bypass_tpl_auto(&bpctl_dev_arr[i]);
6872 /* unmap all devices */
6873 for (i = 0; i < device_num; i++) {
6875 kfree(bpctl_dev_arr[i].bp_tx_data);
6877 iounmap((void *)(bpctl_dev_arr[i].mem_map));
6880 /* free all devices space */
6881 kfree(bpctl_dev_arr);
6884 * Unregister the device
6886 unregister_chrdev(major_num, DEVICE_NAME);
6889 module_init(bypass_init_module);
6890 module_exit(bypass_cleanup_module);
6892 int is_bypass_sd(int ifindex)
6894 return is_bypass(get_dev_idx_p(ifindex));
6896 EXPORT_SYMBOL(is_bypass_sd);
6898 int set_bypass_sd(int ifindex, int bypass_mode)
6901 return set_bypass_fn(get_dev_idx_p(ifindex), bypass_mode);
6903 EXPORT_SYMBOL(set_bypass_sd);
6905 int get_bypass_sd(int ifindex)
6908 return get_bypass_fn(get_dev_idx_p(ifindex));
6910 EXPORT_SYMBOL(get_bypass_sd);
6912 int get_bypass_change_sd(int ifindex)
6915 return get_bypass_change_fn(get_dev_idx_p(ifindex));
6917 EXPORT_SYMBOL(get_bypass_change_sd);
6919 int set_dis_bypass_sd(int ifindex, int dis_param)
6921 return set_dis_bypass_fn(get_dev_idx_p(ifindex), dis_param);
6923 EXPORT_SYMBOL(set_dis_bypass_sd);
6925 int get_dis_bypass_sd(int ifindex)
6928 return get_dis_bypass_fn(get_dev_idx_p(ifindex));
6930 EXPORT_SYMBOL(get_dis_bypass_sd);
6932 int set_bypass_pwoff_sd(int ifindex, int bypass_mode)
6934 return set_bypass_pwoff_fn(get_dev_idx_p(ifindex), bypass_mode);
6937 EXPORT_SYMBOL(set_bypass_pwoff_sd);
6939 int get_bypass_pwoff_sd(int ifindex)
6941 return get_bypass_pwoff_fn(get_dev_idx_p(ifindex));
6944 EXPORT_SYMBOL(get_bypass_pwoff_sd);
6946 int set_bypass_pwup_sd(int ifindex, int bypass_mode)
6948 return set_bypass_pwup_fn(get_dev_idx_p(ifindex), bypass_mode);
6951 EXPORT_SYMBOL(set_bypass_pwup_sd);
6953 int get_bypass_pwup_sd(int ifindex)
6955 return get_bypass_pwup_fn(get_dev_idx_p(ifindex));
6958 EXPORT_SYMBOL(get_bypass_pwup_sd);
6960 int set_bypass_wd_sd(int if_index, int ms_timeout, int *ms_timeout_set)
6962 if ((is_bypass(get_dev_idx_p(if_index))) <= 0)
6964 *ms_timeout_set = set_bypass_wd_fn(get_dev_idx_p(if_index), ms_timeout);
6967 EXPORT_SYMBOL(set_bypass_wd_sd);
6969 int get_bypass_wd_sd(int ifindex, int *timeout)
6971 return get_bypass_wd_fn(get_dev_idx_p(ifindex), timeout);
6974 EXPORT_SYMBOL(get_bypass_wd_sd);
6976 int get_wd_expire_time_sd(int ifindex, int *time_left)
6978 return get_wd_expire_time_fn(get_dev_idx_p(ifindex), time_left);
6980 EXPORT_SYMBOL(get_wd_expire_time_sd);
6982 int reset_bypass_wd_timer_sd(int ifindex)
6984 return reset_bypass_wd_timer_fn(get_dev_idx_p(ifindex));
6987 EXPORT_SYMBOL(reset_bypass_wd_timer_sd);
6989 int get_wd_set_caps_sd(int ifindex)
6991 return get_wd_set_caps_fn(get_dev_idx_p(ifindex));
6994 EXPORT_SYMBOL(get_wd_set_caps_sd);
6996 int set_std_nic_sd(int ifindex, int nic_mode)
6998 return set_std_nic_fn(get_dev_idx_p(ifindex), nic_mode);
7001 EXPORT_SYMBOL(set_std_nic_sd);
7003 int get_std_nic_sd(int ifindex)
7005 return get_std_nic_fn(get_dev_idx_p(ifindex));
7008 EXPORT_SYMBOL(get_std_nic_sd);
7010 int set_tap_sd(int ifindex, int tap_mode)
7012 return set_tap_fn(get_dev_idx_p(ifindex), tap_mode);
7015 EXPORT_SYMBOL(set_tap_sd);
7017 int get_tap_sd(int ifindex)
7019 return get_tap_fn(get_dev_idx_p(ifindex));
7022 EXPORT_SYMBOL(get_tap_sd);
7024 int set_tap_pwup_sd(int ifindex, int tap_mode)
7026 return set_tap_pwup_fn(get_dev_idx_p(ifindex), tap_mode);
7029 EXPORT_SYMBOL(set_tap_pwup_sd);
7031 int get_tap_pwup_sd(int ifindex)
7033 return get_tap_pwup_fn(get_dev_idx_p(ifindex));
7036 EXPORT_SYMBOL(get_tap_pwup_sd);
7038 int get_tap_change_sd(int ifindex)
7040 return get_tap_change_fn(get_dev_idx_p(ifindex));
7043 EXPORT_SYMBOL(get_tap_change_sd);
7045 int set_dis_tap_sd(int ifindex, int dis_param)
7047 return set_dis_tap_fn(get_dev_idx_p(ifindex), dis_param);
7050 EXPORT_SYMBOL(set_dis_tap_sd);
7052 int get_dis_tap_sd(int ifindex)
7054 return get_dis_tap_fn(get_dev_idx_p(ifindex));
7057 EXPORT_SYMBOL(get_dis_tap_sd);
7059 int set_bp_disc_sd(int ifindex, int disc_mode)
7061 return set_disc_fn(get_dev_idx_p(ifindex), disc_mode);
7064 EXPORT_SYMBOL(set_bp_disc_sd);
7066 int get_bp_disc_sd(int ifindex)
7068 return get_disc_fn(get_dev_idx_p(ifindex));
7071 EXPORT_SYMBOL(get_bp_disc_sd);
7073 int set_bp_disc_pwup_sd(int ifindex, int disc_mode)
7075 return set_disc_pwup_fn(get_dev_idx_p(ifindex), disc_mode);
7078 EXPORT_SYMBOL(set_bp_disc_pwup_sd);
7080 int get_bp_disc_pwup_sd(int ifindex)
7082 return get_disc_pwup_fn(get_dev_idx_p(ifindex));
7085 EXPORT_SYMBOL(get_bp_disc_pwup_sd);
7087 int get_bp_disc_change_sd(int ifindex)
7089 return get_disc_change_fn(get_dev_idx_p(ifindex));
7092 EXPORT_SYMBOL(get_bp_disc_change_sd);
7094 int set_bp_dis_disc_sd(int ifindex, int dis_param)
7096 return set_dis_disc_fn(get_dev_idx_p(ifindex), dis_param);
7099 EXPORT_SYMBOL(set_bp_dis_disc_sd);
7101 int get_bp_dis_disc_sd(int ifindex)
7103 return get_dis_disc_fn(get_dev_idx_p(ifindex));
7106 EXPORT_SYMBOL(get_bp_dis_disc_sd);
7108 int get_wd_exp_mode_sd(int ifindex)
7110 return get_wd_exp_mode_fn(get_dev_idx_p(ifindex));
7112 EXPORT_SYMBOL(get_wd_exp_mode_sd);
7114 int set_wd_exp_mode_sd(int ifindex, int param)
7116 return set_wd_exp_mode_fn(get_dev_idx_p(ifindex), param);
7119 EXPORT_SYMBOL(set_wd_exp_mode_sd);
7121 int reset_cont_sd(int ifindex)
7123 return reset_cont_fn(get_dev_idx_p(ifindex));
7127 int set_tx_sd(int ifindex, int tx_state)
7129 return set_tx_fn(get_dev_idx_p(ifindex), tx_state);
7132 EXPORT_SYMBOL(set_tx_sd);
7134 int set_tpl_sd(int ifindex, int tpl_state)
7136 return set_tpl_fn(get_dev_idx_p(ifindex), tpl_state);
7139 EXPORT_SYMBOL(set_tpl_sd);
7141 int set_bp_hw_reset_sd(int ifindex, int status)
7143 return set_bp_hw_reset_fn(get_dev_idx_p(ifindex), status);
7146 EXPORT_SYMBOL(set_bp_hw_reset_sd);
7148 int set_wd_autoreset_sd(int ifindex, int param)
7150 return set_wd_autoreset_fn(get_dev_idx_p(ifindex), param);
7153 EXPORT_SYMBOL(set_wd_autoreset_sd);
7155 int get_wd_autoreset_sd(int ifindex)
7157 return get_wd_autoreset_fn(get_dev_idx_p(ifindex));
7160 EXPORT_SYMBOL(get_wd_autoreset_sd);
7162 int get_bypass_caps_sd(int ifindex)
7164 return get_bypass_caps_fn(get_dev_idx_p(ifindex));
7166 EXPORT_SYMBOL(get_bypass_caps_sd);
7168 int get_bypass_slave_sd(int ifindex)
7170 struct bpctl_dev *pbpctl_dev_out;
7171 int ret = get_bypass_slave_fn(get_dev_idx_p(ifindex), &pbpctl_dev_out);
7173 return pbpctl_dev_out->ifindex;
7177 EXPORT_SYMBOL(get_bypass_slave_sd);
7179 int get_tx_sd(int ifindex)
7181 return get_tx_fn(get_dev_idx_p(ifindex));
7184 EXPORT_SYMBOL(get_tx_sd);
7186 int get_tpl_sd(int ifindex)
7188 return get_tpl_fn(get_dev_idx_p(ifindex));
7191 EXPORT_SYMBOL(get_tpl_sd);
7193 int get_bp_hw_reset_sd(int ifindex)
7195 return get_bp_hw_reset_fn(get_dev_idx_p(ifindex));
7198 EXPORT_SYMBOL(get_bp_hw_reset_sd);
7200 int get_bypass_info_sd(int ifindex, struct bp_info *bp_info)
7202 return get_bypass_info_fn(get_dev_idx_p(ifindex), bp_info->prod_name, &bp_info->fw_ver);
7204 EXPORT_SYMBOL(get_bypass_info_sd);
7206 int bp_if_scan_sd(void)
7211 EXPORT_SYMBOL(bp_if_scan_sd);
7213 #define BP_PROC_DIR "bypass"
7215 static struct proc_dir_entry *bp_procfs_dir;
7217 int bp_proc_create(void)
7219 bp_procfs_dir = proc_mkdir(BP_PROC_DIR, init_net.proc_net);
7220 if (bp_procfs_dir == (struct proc_dir_entry *)0) {
7222 "Could not create procfs nicinfo directory %s\n",
7229 static int procfs_add(char *proc_name, const struct file_operations *fops,
7230 struct bpctl_dev *dev)
7232 struct bypass_pfs_sd *pfs = &dev->bypass_pfs_set;
7233 if (!proc_create_data(proc_name, 0644, pfs->bypass_entry, fops, dev))
7238 #define RO_FOPS(name) \
7239 static int name##_open(struct inode *inode, struct file *file) \
7241 return single_open(file, show_##name, PDE_DATA(inode));\
7243 static const struct file_operations name##_ops = { \
7244 .open = name##_open, \
7246 .llseek = seq_lseek, \
7247 .release = single_release, \
7250 #define RW_FOPS(name) \
7251 static int name##_open(struct inode *inode, struct file *file) \
7253 return single_open(file, show_##name, PDE_DATA(inode));\
7255 static const struct file_operations name##_ops = { \
7256 .open = name##_open, \
7258 .write = name##_write, \
7259 .llseek = seq_lseek, \
7260 .release = single_release, \
7263 static int show_bypass_info(struct seq_file *m, void *v)
7265 struct bpctl_dev *dev = m->private;
7267 seq_printf(m, "Name\t\t\t%s\n", dev->name);
7268 seq_printf(m, "Firmware version\t0x%x\n", dev->bp_fw_ver);
7271 RO_FOPS(bypass_info)
7273 static int show_bypass_slave(struct seq_file *m, void *v)
7275 struct bpctl_dev *dev = m->private;
7276 struct bpctl_dev *slave = get_status_port_fn(dev);
7280 seq_puts(m, "fail\n");
7281 else if (slave->ndev)
7282 seq_printf(m, "%s\n", slave->ndev->name);
7285 RO_FOPS(bypass_slave)
7287 static int show_bypass_caps(struct seq_file *m, void *v)
7289 struct bpctl_dev *dev = m->private;
7290 int ret = get_bypass_caps_fn(dev);
7291 if (ret == BP_NOT_CAP)
7292 seq_puts(m, "-1\n");
7294 seq_printf(m, "0x%x\n", ret);
7297 RO_FOPS(bypass_caps)
7299 static int show_wd_set_caps(struct seq_file *m, void *v)
7301 struct bpctl_dev *dev = m->private;
7302 int ret = get_wd_set_caps_fn(dev);
7303 if (ret == BP_NOT_CAP)
7304 seq_puts(m, "-1\n");
7306 seq_printf(m, "0x%x\n", ret);
7309 RO_FOPS(wd_set_caps)
7311 static int user_on_off(const void __user *buffer, size_t count)
7317 if (count > (sizeof(kbuf) - 1))
7320 if (copy_from_user(&kbuf, buffer, count))
7324 length = strlen(kbuf);
7325 if (kbuf[length - 1] == '\n')
7326 kbuf[--length] = '\0';
7328 if (strcmp(kbuf, "on") == 0)
7330 if (strcmp(kbuf, "off") == 0)
7335 static ssize_t bypass_write(struct file *file, const char __user *buffer,
7336 size_t count, loff_t *pos)
7338 int bypass_param = user_on_off(buffer, count);
7339 if (bypass_param < 0)
7342 set_bypass_fn(PDE_DATA(file_inode(file)), bypass_param);
7345 static int show_bypass(struct seq_file *m, void *v)
7347 struct bpctl_dev *dev = m->private;
7348 int ret = get_bypass_fn(dev);
7349 if (ret == BP_NOT_CAP)
7350 seq_puts(m, "fail\n");
7352 seq_puts(m, "on\n");
7354 seq_puts(m, "off\n");
7359 static ssize_t tap_write(struct file *file, const char __user *buffer,
7360 size_t count, loff_t *pos)
7362 int tap_param = user_on_off(buffer, count);
7366 set_tap_fn(PDE_DATA(file_inode(file)), tap_param);
7369 static int show_tap(struct seq_file *m, void *v)
7371 struct bpctl_dev *dev = m->private;
7372 int ret = get_tap_fn(dev);
7373 if (ret == BP_NOT_CAP)
7374 seq_puts(m, "fail\n");
7376 seq_puts(m, "on\n");
7378 seq_puts(m, "off\n");
7383 static ssize_t disc_write(struct file *file, const char __user *buffer,
7384 size_t count, loff_t *pos)
7386 int tap_param = user_on_off(buffer, count);
7390 set_disc_fn(PDE_DATA(file_inode(file)), tap_param);
7393 static int show_disc(struct seq_file *m, void *v)
7395 struct bpctl_dev *dev = m->private;
7396 int ret = get_disc_fn(dev);
7397 if (ret == BP_NOT_CAP)
7398 seq_puts(m, "fail\n");
7400 seq_puts(m, "on\n");
7402 seq_puts(m, "off\n");
7407 static int show_bypass_change(struct seq_file *m, void *v)
7409 struct bpctl_dev *dev = m->private;
7410 int ret = get_bypass_change_fn(dev);
7412 seq_puts(m, "on\n");
7414 seq_puts(m, "off\n");
7416 seq_puts(m, "fail\n");
7419 RO_FOPS(bypass_change)
7421 static int show_tap_change(struct seq_file *m, void *v)
7423 struct bpctl_dev *dev = m->private;
7424 int ret = get_tap_change_fn(dev);
7426 seq_puts(m, "on\n");
7428 seq_puts(m, "off\n");
7430 seq_puts(m, "fail\n");
7435 static int show_disc_change(struct seq_file *m, void *v)
7437 struct bpctl_dev *dev = m->private;
7438 int ret = get_disc_change_fn(dev);
7440 seq_puts(m, "on\n");
7442 seq_puts(m, "off\n");
7444 seq_puts(m, "fail\n");
7447 RO_FOPS(disc_change)
7449 static ssize_t bypass_wd_write(struct file *file, const char __user *buffer,
7450 size_t count, loff_t *pos)
7452 struct bpctl_dev *dev = PDE_DATA(file_inode(file));
7454 int ret = kstrtoint_from_user(buffer, count, 10, &timeout);
7457 set_bypass_wd_fn(dev, timeout);
7460 static int show_bypass_wd(struct seq_file *m, void *v)
7462 struct bpctl_dev *dev = m->private;
7463 int ret = 0, timeout = 0;
7465 ret = get_bypass_wd_fn(dev, &timeout);
7466 if (ret == BP_NOT_CAP)
7467 seq_puts(m, "fail\n");
7468 else if (timeout == -1)
7469 seq_puts(m, "unknown\n");
7470 else if (timeout == 0)
7471 seq_puts(m, "disable\n");
7473 seq_printf(m, "%d\n", timeout);
7478 static int show_wd_expire_time(struct seq_file *m, void *v)
7480 struct bpctl_dev *dev = m->private;
7481 int ret = 0, timeout = 0;
7482 ret = get_wd_expire_time_fn(dev, &timeout);
7483 if (ret == BP_NOT_CAP)
7484 seq_puts(m, "fail\n");
7485 else if (timeout == -1)
7486 seq_puts(m, "expire\n");
7487 else if (timeout == 0)
7488 seq_puts(m, "disable\n");
7490 seq_printf(m, "%d\n", timeout);
7493 RO_FOPS(wd_expire_time)
7495 static ssize_t tpl_write(struct file *file, const char __user *buffer,
7496 size_t count, loff_t *pos)
7498 struct bpctl_dev *dev = PDE_DATA(file_inode(file));
7499 int tpl_param = user_on_off(buffer, count);
7503 set_tpl_fn(dev, tpl_param);
7506 static int show_tpl(struct seq_file *m, void *v)
7508 struct bpctl_dev *dev = m->private;
7509 int ret = get_tpl_fn(dev);
7510 if (ret == BP_NOT_CAP)
7511 seq_puts(m, "fail\n");
7513 seq_puts(m, "on\n");
7515 seq_puts(m, "off\n");
7521 static ssize_t wait_at_pwup_write(struct file *file, const char __user *buffer,
7522 size_t count, loff_t *pos)
7524 struct bpctl_dev *dev = PDE_DATA(file_inode(file));
7525 int tpl_param = user_on_off(buffer, count);
7529 set_bp_wait_at_pwup_fn(dev, tpl_param);
7532 static int show_wait_at_pwup(struct seq_file *m, void *v)
7534 struct bpctl_dev *dev = m->private;
7535 int ret = get_bp_wait_at_pwup_fn(dev);
7536 if (ret == BP_NOT_CAP)
7537 seq_puts(m, "fail\n");
7539 seq_puts(m, "on\n");
7541 seq_puts(m, "off\n");
7544 RW_FOPS(wait_at_pwup)
7546 static ssize_t hw_reset_write(struct file *file, const char __user *buffer,
7547 size_t count, loff_t *pos)
7549 struct bpctl_dev *dev = PDE_DATA(file_inode(file));
7550 int tpl_param = user_on_off(buffer, count);
7554 set_bp_hw_reset_fn(dev, tpl_param);
7557 static int show_hw_reset(struct seq_file *m, void *v)
7559 struct bpctl_dev *dev = m->private;
7560 int ret = get_bp_hw_reset_fn(dev);
7561 if (ret == BP_NOT_CAP)
7562 seq_puts(m, "fail\n");
7564 seq_puts(m, "on\n");
7566 seq_puts(m, "off\n");
7571 #endif /*PMC_WAIT_FLAG */
7573 static int show_reset_bypass_wd(struct seq_file *m, void *v)
7575 struct bpctl_dev *dev = m->private;
7576 int ret = reset_bypass_wd_timer_fn(dev);
7577 if (ret == BP_NOT_CAP)
7578 seq_puts(m, "fail\n");
7580 seq_puts(m, "disable\n");
7582 seq_puts(m, "success\n");
7585 RO_FOPS(reset_bypass_wd)
7587 static ssize_t dis_bypass_write(struct file *file, const char __user *buffer,
7588 size_t count, loff_t *pos)
7590 int bypass_param = user_on_off(buffer, count);
7591 if (bypass_param < 0)
7594 set_dis_bypass_fn(PDE_DATA(file_inode(file)), bypass_param);
7597 static int show_dis_bypass(struct seq_file *m, void *v)
7599 struct bpctl_dev *dev = m->private;
7600 int ret = get_dis_bypass_fn(dev);
7601 if (ret == BP_NOT_CAP)
7602 seq_puts(m, "fail\n");
7604 seq_puts(m, "off\n");
7606 seq_puts(m, "on\n");
7611 static ssize_t dis_tap_write(struct file *file, const char __user *buffer,
7612 size_t count, loff_t *pos)
7614 int tap_param = user_on_off(buffer, count);
7618 set_dis_tap_fn(PDE_DATA(file_inode(file)), tap_param);
7621 static int show_dis_tap(struct seq_file *m, void *v)
7623 struct bpctl_dev *dev = m->private;
7624 int ret = get_dis_tap_fn(dev);
7625 if (ret == BP_NOT_CAP)
7626 seq_puts(m, "fail\n");
7628 seq_puts(m, "off\n");
7630 seq_puts(m, "on\n");
7635 static ssize_t dis_disc_write(struct file *file, const char __user *buffer,
7636 size_t count, loff_t *pos)
7638 int tap_param = user_on_off(buffer, count);
7642 set_dis_disc_fn(PDE_DATA(file_inode(file)), tap_param);
7645 static int show_dis_disc(struct seq_file *m, void *v)
7647 struct bpctl_dev *dev = m->private;
7648 int ret = get_dis_disc_fn(dev);
7649 if (ret == BP_NOT_CAP)
7650 seq_puts(m, "fail\n");
7652 seq_puts(m, "off\n");
7654 seq_puts(m, "on\n");
7659 static ssize_t bypass_pwup_write(struct file *file, const char __user *buffer,
7660 size_t count, loff_t *pos)
7662 int bypass_param = user_on_off(buffer, count);
7663 if (bypass_param < 0)
7666 set_bypass_pwup_fn(PDE_DATA(file_inode(file)), bypass_param);
7669 static int show_bypass_pwup(struct seq_file *m, void *v)
7671 struct bpctl_dev *dev = m->private;
7672 int ret = get_bypass_pwup_fn(dev);
7673 if (ret == BP_NOT_CAP)
7674 seq_puts(m, "fail\n");
7676 seq_puts(m, "off\n");
7678 seq_puts(m, "on\n");
7681 RW_FOPS(bypass_pwup)
7683 static ssize_t bypass_pwoff_write(struct file *file, const char __user *buffer,
7684 size_t count, loff_t *pos)
7686 int bypass_param = user_on_off(buffer, count);
7687 if (bypass_param < 0)
7690 set_bypass_pwoff_fn(PDE_DATA(file_inode(file)), bypass_param);
7693 static int show_bypass_pwoff(struct seq_file *m, void *v)
7695 struct bpctl_dev *dev = m->private;
7696 int ret = get_bypass_pwoff_fn(dev);
7697 if (ret == BP_NOT_CAP)
7698 seq_puts(m, "fail\n");
7700 seq_puts(m, "off\n");
7702 seq_puts(m, "on\n");
7705 RW_FOPS(bypass_pwoff)
7707 static ssize_t tap_pwup_write(struct file *file, const char __user *buffer,
7708 size_t count, loff_t *pos)
7710 int tap_param = user_on_off(buffer, count);
7714 set_tap_pwup_fn(PDE_DATA(file_inode(file)), tap_param);
7717 static int show_tap_pwup(struct seq_file *m, void *v)
7719 struct bpctl_dev *dev = m->private;
7720 int ret = get_tap_pwup_fn(dev);
7721 if (ret == BP_NOT_CAP)
7722 seq_puts(m, "fail\n");
7724 seq_puts(m, "off\n");
7726 seq_puts(m, "on\n");
7731 static ssize_t disc_pwup_write(struct file *file, const char __user *buffer,
7732 size_t count, loff_t *pos)
7734 int tap_param = user_on_off(buffer, count);
7738 set_disc_pwup_fn(PDE_DATA(file_inode(file)), tap_param);
7741 static int show_disc_pwup(struct seq_file *m, void *v)
7743 struct bpctl_dev *dev = m->private;
7744 int ret = get_disc_pwup_fn(dev);
7745 if (ret == BP_NOT_CAP)
7746 seq_puts(m, "fail\n");
7748 seq_puts(m, "off\n");
7750 seq_puts(m, "on\n");
7755 static ssize_t std_nic_write(struct file *file, const char __user *buffer,
7756 size_t count, loff_t *pos)
7758 int bypass_param = user_on_off(buffer, count);
7759 if (bypass_param < 0)
7762 set_std_nic_fn(PDE_DATA(file_inode(file)), bypass_param);
7765 static int show_std_nic(struct seq_file *m, void *v)
7767 struct bpctl_dev *dev = m->private;
7768 int ret = get_std_nic_fn(dev);
7769 if (ret == BP_NOT_CAP)
7770 seq_puts(m, "fail\n");
7772 seq_puts(m, "off\n");
7774 seq_puts(m, "on\n");
7779 static ssize_t wd_exp_mode_write(struct file *file, const char __user *buffer,
7780 size_t count, loff_t *pos)
7783 int bypass_param = 0, length = 0;
7785 if (count > (sizeof(kbuf) - 1))
7788 if (copy_from_user(&kbuf, buffer, count))
7792 length = strlen(kbuf);
7793 if (kbuf[length - 1] == '\n')
7794 kbuf[--length] = '\0';
7796 if (strcmp(kbuf, "tap") == 0)
7798 else if (strcmp(kbuf, "bypass") == 0)
7800 else if (strcmp(kbuf, "disc") == 0)
7803 set_wd_exp_mode_fn(PDE_DATA(file_inode(file)), bypass_param);
7807 static int show_wd_exp_mode(struct seq_file *m, void *v)
7809 struct bpctl_dev *dev = m->private;
7810 int ret = get_wd_exp_mode_fn(dev);
7812 seq_puts(m, "tap\n");
7814 seq_puts(m, "bypass\n");
7816 seq_puts(m, "disc\n");
7818 seq_puts(m, "fail\n");
7821 RW_FOPS(wd_exp_mode)
7823 static ssize_t wd_autoreset_write(struct file *file, const char __user *buffer,
7824 size_t count, loff_t *pos)
7827 int ret = kstrtoint_from_user(buffer, count, 10, &timeout);
7830 set_wd_autoreset_fn(PDE_DATA(file_inode(file)), timeout);
7833 static int show_wd_autoreset(struct seq_file *m, void *v)
7835 struct bpctl_dev *dev = m->private;
7836 int ret = get_wd_autoreset_fn(dev);
7838 seq_printf(m, "%d\n", ret);
7840 seq_puts(m, "fail\n");
7843 RW_FOPS(wd_autoreset)
7845 int bypass_proc_create_dev_sd(struct bpctl_dev *pbp_device_block)
7847 struct bypass_pfs_sd *current_pfs = &(pbp_device_block->bypass_pfs_set);
7848 static struct proc_dir_entry *procfs_dir;
7851 if (!pbp_device_block->ndev)
7853 sprintf(current_pfs->dir_name, "bypass_%s",
7854 pbp_device_block->ndev->name);
7859 /* create device proc dir */
7860 procfs_dir = proc_mkdir(current_pfs->dir_name, bp_procfs_dir);
7862 printk(KERN_DEBUG "Could not create procfs directory %s\n",
7863 current_pfs->dir_name);
7866 current_pfs->bypass_entry = procfs_dir;
7868 #define ENTRY(x) (ret |= procfs_add(#x, &x##_ops, pbp_device_block))
7871 if (pbp_device_block->bp_caps & SW_CTL_CAP) {
7872 /* Create set param proc's */
7873 ENTRY(bypass_slave);
7877 ENTRY(wd_expire_time);
7878 ENTRY(reset_bypass_wd);
7880 if (pbp_device_block->bp_caps & BP_CAP) {
7884 ENTRY(bypass_pwoff);
7885 ENTRY(bypass_change);
7887 if (pbp_device_block->bp_caps & TAP_CAP) {
7893 if (pbp_device_block->bp_caps & DISC_CAP) {
7901 ENTRY(wd_autoreset);
7904 ENTRY(wait_at_pwup);
7910 printk(KERN_DEBUG "Create proc entry failed\n");
7915 int bypass_proc_remove_dev_sd(struct bpctl_dev *pbp_device_block)
7918 struct bypass_pfs_sd *current_pfs = &pbp_device_block->bypass_pfs_set;
7919 remove_proc_subtree(current_pfs->dir_name, bp_procfs_dir);
7920 current_pfs->bypass_entry = NULL;