2 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
22 * Purpose: Implement functions to access baseband
29 * BBuGetFrameTime - Calculate data frame transmitting time
30 * BBvCaculateParameter - Caculate PhyLength, PhyService and Phy Signal parameter for baseband Tx
31 * BBbReadEmbedded - Embedded read baseband register via MAC
32 * BBbWriteEmbedded - Embedded write baseband register via MAC
33 * BBbIsRegBitsOn - Test if baseband register bits on
34 * BBbIsRegBitsOff - Test if baseband register bits off
35 * BBbVT3253Init - VIA VT3253 baseband chip init code
36 * BBvReadAllRegs - Read All Baseband Registers
37 * BBvLoopbackOn - Turn on BaseBand Loopback mode
38 * BBvLoopbackOff - Turn off BaseBand Loopback mode
41 * 06-10-2003 Bryan YC Fan: Re-write codes to support VT3253 spec.
42 * 08-07-2003 Bryan YC Fan: Add MAXIM2827/2825 and RFMD2959 support.
43 * 08-26-2003 Kyle Hsu : Modify BBuGetFrameTime() and BBvCalculateParameter().
44 * cancel the setting of MAC_REG_SOFTPWRCTL on BBbVT3253Init().
46 * 09-01-2003 Bryan YC Fan: RF & BB tables updated.
47 * Modified BBvLoopbackOn & BBvLoopbackOff().
59 /*--------------------- Static Definitions -------------------------*/
60 //static int msglevel =MSG_LEVEL_DEBUG;
61 static int msglevel = MSG_LEVEL_INFO;
63 /*--------------------- Static Classes ----------------------------*/
65 /*--------------------- Static Variables --------------------------*/
67 /*--------------------- Static Functions --------------------------*/
69 /*--------------------- Export Variables --------------------------*/
71 /*--------------------- Static Definitions -------------------------*/
73 /*--------------------- Static Classes ----------------------------*/
75 /*--------------------- Static Variables --------------------------*/
77 #define CB_VT3253_INIT_FOR_RFMD 446
78 unsigned char byVT3253InitTab_RFMD[CB_VT3253_INIT_FOR_RFMD][2] = {
527 #define CB_VT3253B0_INIT_FOR_RFMD 256
528 unsigned char byVT3253B0_RFMD[CB_VT3253B0_INIT_FOR_RFMD][2] = {
787 #define CB_VT3253B0_AGC_FOR_RFMD2959 195
789 unsigned char byVT3253B0_AGC4_RFMD2959[CB_VT3253B0_AGC_FOR_RFMD2959][2] = {
987 #define CB_VT3253B0_INIT_FOR_AIROHA2230 256
989 unsigned char byVT3253B0_AIROHA2230[CB_VT3253B0_INIT_FOR_AIROHA2230][2] = {
1099 {0x6c, 0x00}, //RobertYu:20050125, request by JJSue
1249 #define CB_VT3253B0_INIT_FOR_UW2451 256
1251 unsigned char byVT3253B0_UW2451[CB_VT3253B0_INIT_FOR_UW2451][2] = {
1361 {0x6c, 0x00}, //RobertYu:20050125, request by JJSue
1511 #define CB_VT3253B0_AGC 193
1513 unsigned char byVT3253B0_AGC[CB_VT3253B0_AGC][2] = {
1709 const unsigned short awcFrameTime[MAX_RATE] =
1710 {10, 20, 55, 110, 24, 36, 48, 72, 96, 144, 192, 216};
1712 /*--------------------- Static Functions --------------------------*/
1716 s_ulGetRatio(PSDevice pDevice);
1730 if (pDevice->dwRxAntennaSel == 0) {
1731 pDevice->dwRxAntennaSel = 1;
1732 if (pDevice->bTxRxAntInv == true)
1733 BBvSetRxAntennaMode(pDevice->PortOffset, ANT_A);
1735 BBvSetRxAntennaMode(pDevice->PortOffset, ANT_B);
1737 pDevice->dwRxAntennaSel = 0;
1738 if (pDevice->bTxRxAntInv == true)
1739 BBvSetRxAntennaMode(pDevice->PortOffset, ANT_B);
1741 BBvSetRxAntennaMode(pDevice->PortOffset, ANT_A);
1743 if (pDevice->dwTxAntennaSel == 0) {
1744 pDevice->dwTxAntennaSel = 1;
1745 BBvSetTxAntennaMode(pDevice->PortOffset, ANT_B);
1747 pDevice->dwTxAntennaSel = 0;
1748 BBvSetTxAntennaMode(pDevice->PortOffset, ANT_A);
1752 /*--------------------- Export Variables --------------------------*/
1754 * Description: Calculate data frame transmitting time
1758 * byPreambleType - Preamble Type
1759 * byPktType - PK_TYPE_11A, PK_TYPE_11B, PK_TYPE_11GB, PK_TYPE_11GA
1760 * cbFrameLength - Baseband Type
1764 * Return Value: FrameTime
1769 unsigned char byPreambleType,
1770 unsigned char byPktType,
1771 unsigned int cbFrameLength,
1772 unsigned short wRate
1775 unsigned int uFrameTime;
1776 unsigned int uPreamble;
1778 unsigned int uRateIdx = (unsigned int) wRate;
1779 unsigned int uRate = 0;
1781 if (uRateIdx > RATE_54M) {
1786 uRate = (unsigned int)awcFrameTime[uRateIdx];
1788 if (uRateIdx <= 3) { //CCK mode
1790 if (byPreambleType == 1) {//Short
1795 uFrameTime = (cbFrameLength * 80) / uRate; //?????
1796 uTmp = (uFrameTime * uRate) / 80;
1797 if (cbFrameLength != uTmp) {
1801 return uPreamble + uFrameTime;
1803 uFrameTime = (cbFrameLength * 8 + 22) / uRate; //????????
1804 uTmp = ((uFrameTime * uRate) - 22) / 8;
1805 if (cbFrameLength != uTmp) {
1808 uFrameTime = uFrameTime * 4; //???????
1809 if (byPktType != PK_TYPE_11A) {
1810 uFrameTime += 6; //??????
1812 return 20 + uFrameTime; //??????
1817 * Description: Calculate Length, Service, and Signal fields of Phy for Tx
1821 * pDevice - Device Structure
1822 * cbFrameLength - Tx Frame Length
1825 * pwPhyLen - pointer to Phy Length field
1826 * pbyPhySrv - pointer to Phy Service field
1827 * pbyPhySgn - pointer to Phy Signal field
1829 * Return Value: none
1833 BBvCalculateParameter(
1835 unsigned int cbFrameLength,
1836 unsigned short wRate,
1837 unsigned char byPacketType,
1838 unsigned short *pwPhyLen,
1839 unsigned char *pbyPhySrv,
1840 unsigned char *pbyPhySgn
1843 unsigned int cbBitCount;
1844 unsigned int cbUsCount = 0;
1847 unsigned char byPreambleType = pDevice->byPreambleType;
1848 bool bCCK = pDevice->bCCK;
1850 cbBitCount = cbFrameLength * 8;
1855 cbUsCount = cbBitCount;
1860 cbUsCount = cbBitCount / 2;
1861 if (byPreambleType == 1)
1863 else // long preamble
1870 cbUsCount = (cbBitCount * 10) / 55;
1871 cbTmp = (cbUsCount * 55) / 10;
1872 if (cbTmp != cbBitCount)
1874 if (byPreambleType == 1)
1876 else // long preamble
1884 cbUsCount = cbBitCount / 11;
1885 cbTmp = cbUsCount * 11;
1886 if (cbTmp != cbBitCount) {
1888 if ((cbBitCount - cbTmp) <= 3)
1891 if (byPreambleType == 1)
1893 else // long preamble
1898 if (byPacketType == PK_TYPE_11A) {//11a, 5GHZ
1899 *pbyPhySgn = 0x9B; //1001 1011
1900 } else {//11g, 2.4GHZ
1901 *pbyPhySgn = 0x8B; //1000 1011
1906 if (byPacketType == PK_TYPE_11A) {//11a, 5GHZ
1907 *pbyPhySgn = 0x9F; //1001 1111
1908 } else {//11g, 2.4GHZ
1909 *pbyPhySgn = 0x8F; //1000 1111
1914 if (byPacketType == PK_TYPE_11A) {//11a, 5GHZ
1915 *pbyPhySgn = 0x9A; //1001 1010
1916 } else {//11g, 2.4GHZ
1917 *pbyPhySgn = 0x8A; //1000 1010
1922 if (byPacketType == PK_TYPE_11A) {//11a, 5GHZ
1923 *pbyPhySgn = 0x9E; //1001 1110
1924 } else {//11g, 2.4GHZ
1925 *pbyPhySgn = 0x8E; //1000 1110
1930 if (byPacketType == PK_TYPE_11A) {//11a, 5GHZ
1931 *pbyPhySgn = 0x99; //1001 1001
1932 } else {//11g, 2.4GHZ
1933 *pbyPhySgn = 0x89; //1000 1001
1938 if (byPacketType == PK_TYPE_11A) {//11a, 5GHZ
1939 *pbyPhySgn = 0x9D; //1001 1101
1940 } else {//11g, 2.4GHZ
1941 *pbyPhySgn = 0x8D; //1000 1101
1946 if (byPacketType == PK_TYPE_11A) {//11a, 5GHZ
1947 *pbyPhySgn = 0x98; //1001 1000
1948 } else {//11g, 2.4GHZ
1949 *pbyPhySgn = 0x88; //1000 1000
1954 if (byPacketType == PK_TYPE_11A) {//11a, 5GHZ
1955 *pbyPhySgn = 0x9C; //1001 1100
1956 } else {//11g, 2.4GHZ
1957 *pbyPhySgn = 0x8C; //1000 1100
1962 if (byPacketType == PK_TYPE_11A) {//11a, 5GHZ
1963 *pbyPhySgn = 0x9C; //1001 1100
1964 } else {//11g, 2.4GHZ
1965 *pbyPhySgn = 0x8C; //1000 1100
1970 if (byPacketType == PK_TYPE_11B) {
1973 *pbyPhySrv = *pbyPhySrv | 0x80;
1974 *pwPhyLen = (unsigned short)cbUsCount;
1977 *pwPhyLen = (unsigned short)cbFrameLength;
1982 * Description: Read a byte from BASEBAND, by embedded programming
1986 * dwIoBase - I/O base address
1987 * byBBAddr - address of register in Baseband
1989 * pbyData - data read
1991 * Return Value: true if succeeded; false if failed.
1994 bool BBbReadEmbedded(unsigned long dwIoBase, unsigned char byBBAddr, unsigned char *pbyData)
1997 unsigned char byValue;
2000 VNSvOutPortB(dwIoBase + MAC_REG_BBREGADR, byBBAddr);
2003 MACvRegBitsOn(dwIoBase, MAC_REG_BBREGCTL, BBREGCTL_REGR);
2004 // W_MAX_TIMEOUT is the timeout period
2005 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
2006 VNSvInPortB(dwIoBase + MAC_REG_BBREGCTL, &byValue);
2007 if (byValue & BBREGCTL_DONE)
2012 VNSvInPortB(dwIoBase + MAC_REG_BBREGDATA, pbyData);
2014 if (ww == W_MAX_TIMEOUT) {
2016 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO " DBG_PORT80(0x30)\n");
2023 * Description: Write a Byte to BASEBAND, by embedded programming
2027 * dwIoBase - I/O base address
2028 * byBBAddr - address of register in Baseband
2029 * byData - data to write
2033 * Return Value: true if succeeded; false if failed.
2036 bool BBbWriteEmbedded(unsigned long dwIoBase, unsigned char byBBAddr, unsigned char byData)
2039 unsigned char byValue;
2042 VNSvOutPortB(dwIoBase + MAC_REG_BBREGADR, byBBAddr);
2044 VNSvOutPortB(dwIoBase + MAC_REG_BBREGDATA, byData);
2046 // turn on BBREGCTL_REGW
2047 MACvRegBitsOn(dwIoBase, MAC_REG_BBREGCTL, BBREGCTL_REGW);
2048 // W_MAX_TIMEOUT is the timeout period
2049 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
2050 VNSvInPortB(dwIoBase + MAC_REG_BBREGCTL, &byValue);
2051 if (byValue & BBREGCTL_DONE)
2055 if (ww == W_MAX_TIMEOUT) {
2057 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO " DBG_PORT80(0x31)\n");
2064 * Description: Test if all bits are set for the Baseband register
2068 * dwIoBase - I/O base address
2069 * byBBAddr - address of register in Baseband
2070 * byTestBits - TestBits
2074 * Return Value: true if all TestBits are set; false otherwise.
2077 bool BBbIsRegBitsOn(unsigned long dwIoBase, unsigned char byBBAddr, unsigned char byTestBits)
2079 unsigned char byOrgData;
2081 BBbReadEmbedded(dwIoBase, byBBAddr, &byOrgData);
2082 return (byOrgData & byTestBits) == byTestBits;
2086 * Description: Test if all bits are clear for the Baseband register
2090 * dwIoBase - I/O base address
2091 * byBBAddr - address of register in Baseband
2092 * byTestBits - TestBits
2096 * Return Value: true if all TestBits are clear; false otherwise.
2099 bool BBbIsRegBitsOff(unsigned long dwIoBase, unsigned char byBBAddr, unsigned char byTestBits)
2101 unsigned char byOrgData;
2103 BBbReadEmbedded(dwIoBase, byBBAddr, &byOrgData);
2104 return (byOrgData & byTestBits) == 0;
2108 * Description: VIA VT3253 Baseband chip init function
2112 * dwIoBase - I/O base address
2113 * byRevId - Revision ID
2114 * byRFType - RF type
2118 * Return Value: true if succeeded; false if failed.
2122 bool BBbVT3253Init(PSDevice pDevice)
2124 bool bResult = true;
2126 unsigned long dwIoBase = pDevice->PortOffset;
2127 unsigned char byRFType = pDevice->byRFType;
2128 unsigned char byLocalID = pDevice->byLocalID;
2130 if (byRFType == RF_RFMD2959) {
2131 if (byLocalID <= REV_ID_VT3253_A1) {
2132 for (ii = 0; ii < CB_VT3253_INIT_FOR_RFMD; ii++) {
2133 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253InitTab_RFMD[ii][0], byVT3253InitTab_RFMD[ii][1]);
2136 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_RFMD; ii++) {
2137 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_RFMD[ii][0], byVT3253B0_RFMD[ii][1]);
2139 for (ii = 0; ii < CB_VT3253B0_AGC_FOR_RFMD2959; ii++) {
2140 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_AGC4_RFMD2959[ii][0], byVT3253B0_AGC4_RFMD2959[ii][1]);
2142 VNSvOutPortD(dwIoBase + MAC_REG_ITRTMSET, 0x23);
2143 MACvRegBitsOn(dwIoBase, MAC_REG_PAPEDELAY, BIT0);
2145 pDevice->abyBBVGA[0] = 0x18;
2146 pDevice->abyBBVGA[1] = 0x0A;
2147 pDevice->abyBBVGA[2] = 0x0;
2148 pDevice->abyBBVGA[3] = 0x0;
2149 pDevice->ldBmThreshold[0] = -70;
2150 pDevice->ldBmThreshold[1] = -50;
2151 pDevice->ldBmThreshold[2] = 0;
2152 pDevice->ldBmThreshold[3] = 0;
2153 } else if ((byRFType == RF_AIROHA) || (byRFType == RF_AL2230S)) {
2154 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_AIROHA2230; ii++) {
2155 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_AIROHA2230[ii][0], byVT3253B0_AIROHA2230[ii][1]);
2157 for (ii = 0; ii < CB_VT3253B0_AGC; ii++) {
2158 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]);
2160 pDevice->abyBBVGA[0] = 0x1C;
2161 pDevice->abyBBVGA[1] = 0x10;
2162 pDevice->abyBBVGA[2] = 0x0;
2163 pDevice->abyBBVGA[3] = 0x0;
2164 pDevice->ldBmThreshold[0] = -70;
2165 pDevice->ldBmThreshold[1] = -48;
2166 pDevice->ldBmThreshold[2] = 0;
2167 pDevice->ldBmThreshold[3] = 0;
2168 } else if (byRFType == RF_UW2451) {
2169 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_UW2451; ii++) {
2170 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_UW2451[ii][0], byVT3253B0_UW2451[ii][1]);
2172 for (ii = 0; ii < CB_VT3253B0_AGC; ii++) {
2173 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]);
2175 VNSvOutPortB(dwIoBase + MAC_REG_ITRTMSET, 0x23);
2176 MACvRegBitsOn(dwIoBase, MAC_REG_PAPEDELAY, BIT0);
2178 pDevice->abyBBVGA[0] = 0x14;
2179 pDevice->abyBBVGA[1] = 0x0A;
2180 pDevice->abyBBVGA[2] = 0x0;
2181 pDevice->abyBBVGA[3] = 0x0;
2182 pDevice->ldBmThreshold[0] = -60;
2183 pDevice->ldBmThreshold[1] = -50;
2184 pDevice->ldBmThreshold[2] = 0;
2185 pDevice->ldBmThreshold[3] = 0;
2186 } else if (byRFType == RF_UW2452) {
2187 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_UW2451; ii++) {
2188 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_UW2451[ii][0], byVT3253B0_UW2451[ii][1]);
2190 // Init ANT B select,TX Config CR09 = 0x61->0x45, 0x45->0x41(VC1/VC2 define, make the ANT_A, ANT_B inverted)
2191 //bResult &= BBbWriteEmbedded(dwIoBase,0x09,0x41);
2192 // Init ANT B select,RX Config CR10 = 0x28->0x2A, 0x2A->0x28(VC1/VC2 define, make the ANT_A, ANT_B inverted)
2193 //bResult &= BBbWriteEmbedded(dwIoBase,0x0a,0x28);
2194 // Select VC1/VC2, CR215 = 0x02->0x06
2195 bResult &= BBbWriteEmbedded(dwIoBase, 0xd7, 0x06);
2197 //{{RobertYu:20050125, request by Jack
2198 bResult &= BBbWriteEmbedded(dwIoBase, 0x90, 0x20);
2199 bResult &= BBbWriteEmbedded(dwIoBase, 0x97, 0xeb);
2202 //{{RobertYu:20050221, request by Jack
2203 bResult &= BBbWriteEmbedded(dwIoBase, 0xa6, 0x00);
2204 bResult &= BBbWriteEmbedded(dwIoBase, 0xa8, 0x30);
2206 bResult &= BBbWriteEmbedded(dwIoBase, 0xb0, 0x58);
2208 for (ii = 0; ii < CB_VT3253B0_AGC; ii++) {
2209 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]);
2211 //VNSvOutPortB(dwIoBase + MAC_REG_ITRTMSET, 0x23); // RobertYu: 20050104, 20050131 disable PA_Delay
2212 //MACvRegBitsOn(dwIoBase, MAC_REG_PAPEDELAY, BIT0); // RobertYu: 20050104, 20050131 disable PA_Delay
2214 pDevice->abyBBVGA[0] = 0x14;
2215 pDevice->abyBBVGA[1] = 0x0A;
2216 pDevice->abyBBVGA[2] = 0x0;
2217 pDevice->abyBBVGA[3] = 0x0;
2218 pDevice->ldBmThreshold[0] = -60;
2219 pDevice->ldBmThreshold[1] = -50;
2220 pDevice->ldBmThreshold[2] = 0;
2221 pDevice->ldBmThreshold[3] = 0;
2224 } else if (byRFType == RF_VT3226) {
2225 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_AIROHA2230; ii++) {
2226 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_AIROHA2230[ii][0], byVT3253B0_AIROHA2230[ii][1]);
2228 for (ii = 0; ii < CB_VT3253B0_AGC; ii++) {
2229 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]);
2231 pDevice->abyBBVGA[0] = 0x1C;
2232 pDevice->abyBBVGA[1] = 0x10;
2233 pDevice->abyBBVGA[2] = 0x0;
2234 pDevice->abyBBVGA[3] = 0x0;
2235 pDevice->ldBmThreshold[0] = -70;
2236 pDevice->ldBmThreshold[1] = -48;
2237 pDevice->ldBmThreshold[2] = 0;
2238 pDevice->ldBmThreshold[3] = 0;
2239 // Fix VT3226 DFC system timing issue
2240 MACvSetRFLE_LatchBase(dwIoBase);
2241 //{{ RobertYu: 20050104
2242 } else if (byRFType == RF_AIROHA7230) {
2243 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_AIROHA2230; ii++) {
2244 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_AIROHA2230[ii][0], byVT3253B0_AIROHA2230[ii][1]);
2247 //{{ RobertYu:20050223, request by JerryChung
2248 // Init ANT B select,TX Config CR09 = 0x61->0x45, 0x45->0x41(VC1/VC2 define, make the ANT_A, ANT_B inverted)
2249 //bResult &= BBbWriteEmbedded(dwIoBase,0x09,0x41);
2250 // Init ANT B select,RX Config CR10 = 0x28->0x2A, 0x2A->0x28(VC1/VC2 define, make the ANT_A, ANT_B inverted)
2251 //bResult &= BBbWriteEmbedded(dwIoBase,0x0a,0x28);
2252 // Select VC1/VC2, CR215 = 0x02->0x06
2253 bResult &= BBbWriteEmbedded(dwIoBase, 0xd7, 0x06);
2256 for (ii = 0; ii < CB_VT3253B0_AGC; ii++) {
2257 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]);
2259 pDevice->abyBBVGA[0] = 0x1C;
2260 pDevice->abyBBVGA[1] = 0x10;
2261 pDevice->abyBBVGA[2] = 0x0;
2262 pDevice->abyBBVGA[3] = 0x0;
2263 pDevice->ldBmThreshold[0] = -70;
2264 pDevice->ldBmThreshold[1] = -48;
2265 pDevice->ldBmThreshold[2] = 0;
2266 pDevice->ldBmThreshold[3] = 0;
2270 pDevice->bUpdateBBVGA = false;
2271 pDevice->abyBBVGA[0] = 0x1C;
2274 if (byLocalID > REV_ID_VT3253_A1) {
2275 BBbWriteEmbedded(dwIoBase, 0x04, 0x7F);
2276 BBbWriteEmbedded(dwIoBase, 0x0D, 0x01);
2283 * Description: Read All Baseband Registers
2287 * dwIoBase - I/O base address
2288 * pbyBBRegs - Point to struct that stores Baseband Registers
2292 * Return Value: none
2295 void BBvReadAllRegs(unsigned long dwIoBase, unsigned char *pbyBBRegs)
2298 unsigned char byBase = 1;
2299 for (ii = 0; ii < BB_MAX_CONTEXT_SIZE; ii++) {
2300 BBbReadEmbedded(dwIoBase, (unsigned char)(ii*byBase), pbyBBRegs);
2301 pbyBBRegs += byBase;
2306 * Description: Turn on BaseBand Loopback mode
2310 * dwIoBase - I/O base address
2311 * bCCK - If CCK is set
2315 * Return Value: none
2319 void BBvLoopbackOn(PSDevice pDevice)
2321 unsigned char byData;
2322 unsigned long dwIoBase = pDevice->PortOffset;
2325 BBbReadEmbedded(dwIoBase, 0xC9, &pDevice->byBBCRc9);//CR201
2326 BBbWriteEmbedded(dwIoBase, 0xC9, 0);
2327 BBbReadEmbedded(dwIoBase, 0x4D, &pDevice->byBBCR4d);//CR77
2328 BBbWriteEmbedded(dwIoBase, 0x4D, 0x90);
2330 //CR 88 = 0x02(CCK), 0x03(OFDM)
2331 BBbReadEmbedded(dwIoBase, 0x88, &pDevice->byBBCR88);//CR136
2333 if (pDevice->uConnectionRate <= RATE_11M) { //CCK
2334 // Enable internal digital loopback: CR33 |= 0000 0001
2335 BBbReadEmbedded(dwIoBase, 0x21, &byData);//CR33
2336 BBbWriteEmbedded(dwIoBase, 0x21, (unsigned char)(byData | 0x01));//CR33
2338 BBbWriteEmbedded(dwIoBase, 0x9A, 0); //CR154
2340 BBbWriteEmbedded(dwIoBase, 0x88, 0x02);//CR239
2342 // Enable internal digital loopback:CR154 |= 0000 0001
2343 BBbReadEmbedded(dwIoBase, 0x9A, &byData);//CR154
2344 BBbWriteEmbedded(dwIoBase, 0x9A, (unsigned char)(byData | 0x01));//CR154
2346 BBbWriteEmbedded(dwIoBase, 0x21, 0); //CR33
2348 BBbWriteEmbedded(dwIoBase, 0x88, 0x03);//CR239
2352 BBbWriteEmbedded(dwIoBase, 0x0E, 0);//CR14
2355 BBbReadEmbedded(pDevice->PortOffset, 0x09, &pDevice->byBBCR09);
2356 BBbWriteEmbedded(pDevice->PortOffset, 0x09, (unsigned char)(pDevice->byBBCR09 & 0xDE));
2360 * Description: Turn off BaseBand Loopback mode
2364 * pDevice - Device Structure
2369 * Return Value: none
2372 void BBvLoopbackOff(PSDevice pDevice)
2374 unsigned char byData;
2375 unsigned long dwIoBase = pDevice->PortOffset;
2377 BBbWriteEmbedded(dwIoBase, 0xC9, pDevice->byBBCRc9);//CR201
2378 BBbWriteEmbedded(dwIoBase, 0x88, pDevice->byBBCR88);//CR136
2379 BBbWriteEmbedded(dwIoBase, 0x09, pDevice->byBBCR09);//CR136
2380 BBbWriteEmbedded(dwIoBase, 0x4D, pDevice->byBBCR4d);//CR77
2382 if (pDevice->uConnectionRate <= RATE_11M) { // CCK
2383 // Set the CR33 Bit2 to disable internal Loopback.
2384 BBbReadEmbedded(dwIoBase, 0x21, &byData);//CR33
2385 BBbWriteEmbedded(dwIoBase, 0x21, (unsigned char)(byData & 0xFE));//CR33
2387 BBbReadEmbedded(dwIoBase, 0x9A, &byData);//CR154
2388 BBbWriteEmbedded(dwIoBase, 0x9A, (unsigned char)(byData & 0xFE));//CR154
2390 BBbReadEmbedded(dwIoBase, 0x0E, &byData);//CR14
2391 BBbWriteEmbedded(dwIoBase, 0x0E, (unsigned char)(byData | 0x80));//CR14
2395 * Description: Set ShortSlotTime mode
2399 * pDevice - Device Structure
2403 * Return Value: none
2407 BBvSetShortSlotTime(PSDevice pDevice)
2409 unsigned char byBBRxConf = 0;
2410 unsigned char byBBVGA = 0;
2412 BBbReadEmbedded(pDevice->PortOffset, 0x0A, &byBBRxConf);//CR10
2414 if (pDevice->bShortSlotTime) {
2415 byBBRxConf &= 0xDF;//1101 1111
2417 byBBRxConf |= 0x20;//0010 0000
2420 // patch for 3253B0 Baseband with Cardbus module
2421 BBbReadEmbedded(pDevice->PortOffset, 0xE7, &byBBVGA);
2422 if (byBBVGA == pDevice->abyBBVGA[0]) {
2423 byBBRxConf |= 0x20;//0010 0000
2426 BBbWriteEmbedded(pDevice->PortOffset, 0x0A, byBBRxConf);//CR10
2429 void BBvSetVGAGainOffset(PSDevice pDevice, unsigned char byData)
2431 unsigned char byBBRxConf = 0;
2433 BBbWriteEmbedded(pDevice->PortOffset, 0xE7, byData);
2435 BBbReadEmbedded(pDevice->PortOffset, 0x0A, &byBBRxConf);//CR10
2436 // patch for 3253B0 Baseband with Cardbus module
2437 if (byData == pDevice->abyBBVGA[0]) {
2438 byBBRxConf |= 0x20;//0010 0000
2439 } else if (pDevice->bShortSlotTime) {
2440 byBBRxConf &= 0xDF;//1101 1111
2442 byBBRxConf |= 0x20;//0010 0000
2444 pDevice->byBBVGACurrent = byData;
2445 BBbWriteEmbedded(pDevice->PortOffset, 0x0A, byBBRxConf);//CR10
2449 * Description: Baseband SoftwareReset
2453 * dwIoBase - I/O base address
2457 * Return Value: none
2461 BBvSoftwareReset(unsigned long dwIoBase)
2463 BBbWriteEmbedded(dwIoBase, 0x50, 0x40);
2464 BBbWriteEmbedded(dwIoBase, 0x50, 0);
2465 BBbWriteEmbedded(dwIoBase, 0x9C, 0x01);
2466 BBbWriteEmbedded(dwIoBase, 0x9C, 0);
2470 * Description: Baseband Power Save Mode ON
2474 * dwIoBase - I/O base address
2478 * Return Value: none
2482 BBvPowerSaveModeON(unsigned long dwIoBase)
2484 unsigned char byOrgData;
2486 BBbReadEmbedded(dwIoBase, 0x0D, &byOrgData);
2488 BBbWriteEmbedded(dwIoBase, 0x0D, byOrgData);
2492 * Description: Baseband Power Save Mode OFF
2496 * dwIoBase - I/O base address
2500 * Return Value: none
2504 BBvPowerSaveModeOFF(unsigned long dwIoBase)
2506 unsigned char byOrgData;
2508 BBbReadEmbedded(dwIoBase, 0x0D, &byOrgData);
2509 byOrgData &= ~(BIT0);
2510 BBbWriteEmbedded(dwIoBase, 0x0D, byOrgData);
2514 * Description: Set Tx Antenna mode
2518 * pDevice - Device Structure
2519 * byAntennaMode - Antenna Mode
2523 * Return Value: none
2528 BBvSetTxAntennaMode(unsigned long dwIoBase, unsigned char byAntennaMode)
2530 unsigned char byBBTxConf;
2532 BBbReadEmbedded(dwIoBase, 0x09, &byBBTxConf);//CR09
2533 if (byAntennaMode == ANT_DIVERSITY) {
2534 // bit 1 is diversity
2536 } else if (byAntennaMode == ANT_A) {
2538 byBBTxConf &= 0xF9; // 1111 1001
2539 } else if (byAntennaMode == ANT_B) {
2540 byBBTxConf &= 0xFD; // 1111 1101
2543 BBbWriteEmbedded(dwIoBase, 0x09, byBBTxConf);//CR09
2547 * Description: Set Rx Antenna mode
2551 * pDevice - Device Structure
2552 * byAntennaMode - Antenna Mode
2556 * Return Value: none
2561 BBvSetRxAntennaMode(unsigned long dwIoBase, unsigned char byAntennaMode)
2563 unsigned char byBBRxConf;
2565 BBbReadEmbedded(dwIoBase, 0x0A, &byBBRxConf);//CR10
2566 if (byAntennaMode == ANT_DIVERSITY) {
2569 } else if (byAntennaMode == ANT_A) {
2570 byBBRxConf &= 0xFC; // 1111 1100
2571 } else if (byAntennaMode == ANT_B) {
2572 byBBRxConf &= 0xFE; // 1111 1110
2575 BBbWriteEmbedded(dwIoBase, 0x0A, byBBRxConf);//CR10
2579 * Description: BBvSetDeepSleep
2583 * pDevice - Device Structure
2587 * Return Value: none
2591 BBvSetDeepSleep(unsigned long dwIoBase, unsigned char byLocalID)
2593 BBbWriteEmbedded(dwIoBase, 0x0C, 0x17);//CR12
2594 BBbWriteEmbedded(dwIoBase, 0x0D, 0xB9);//CR13
2598 BBvExitDeepSleep(unsigned long dwIoBase, unsigned char byLocalID)
2600 BBbWriteEmbedded(dwIoBase, 0x0C, 0x00);//CR12
2601 BBbWriteEmbedded(dwIoBase, 0x0D, 0x01);//CR13
2606 s_ulGetRatio(PSDevice pDevice)
2608 unsigned long ulRatio = 0;
2609 unsigned long ulMaxPacket;
2610 unsigned long ulPacketNum;
2612 //This is a thousand-ratio
2613 ulMaxPacket = pDevice->uNumSQ3[RATE_54M];
2614 if (pDevice->uNumSQ3[RATE_54M] != 0) {
2615 ulPacketNum = pDevice->uNumSQ3[RATE_54M];
2616 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2617 //ulRatio = (pDevice->uNumSQ3[RATE_54M] * 1000 / pDevice->uDiversityCnt);
2618 ulRatio += TOP_RATE_54M;
2620 if (pDevice->uNumSQ3[RATE_48M] > ulMaxPacket) {
2621 ulPacketNum = pDevice->uNumSQ3[RATE_54M] + pDevice->uNumSQ3[RATE_48M];
2622 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2623 //ulRatio = (pDevice->uNumSQ3[RATE_48M] * 1000 / pDevice->uDiversityCnt);
2624 ulRatio += TOP_RATE_48M;
2625 ulMaxPacket = pDevice->uNumSQ3[RATE_48M];
2627 if (pDevice->uNumSQ3[RATE_36M] > ulMaxPacket) {
2628 ulPacketNum = pDevice->uNumSQ3[RATE_54M] + pDevice->uNumSQ3[RATE_48M] +
2629 pDevice->uNumSQ3[RATE_36M];
2630 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2631 //ulRatio = (pDevice->uNumSQ3[RATE_36M] * 1000 / pDevice->uDiversityCnt);
2632 ulRatio += TOP_RATE_36M;
2633 ulMaxPacket = pDevice->uNumSQ3[RATE_36M];
2635 if (pDevice->uNumSQ3[RATE_24M] > ulMaxPacket) {
2636 ulPacketNum = pDevice->uNumSQ3[RATE_54M] + pDevice->uNumSQ3[RATE_48M] +
2637 pDevice->uNumSQ3[RATE_36M] + pDevice->uNumSQ3[RATE_24M];
2638 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2639 //ulRatio = (pDevice->uNumSQ3[RATE_24M] * 1000 / pDevice->uDiversityCnt);
2640 ulRatio += TOP_RATE_24M;
2641 ulMaxPacket = pDevice->uNumSQ3[RATE_24M];
2643 if (pDevice->uNumSQ3[RATE_18M] > ulMaxPacket) {
2644 ulPacketNum = pDevice->uNumSQ3[RATE_54M] + pDevice->uNumSQ3[RATE_48M] +
2645 pDevice->uNumSQ3[RATE_36M] + pDevice->uNumSQ3[RATE_24M] +
2646 pDevice->uNumSQ3[RATE_18M];
2647 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2648 //ulRatio = (pDevice->uNumSQ3[RATE_18M] * 1000 / pDevice->uDiversityCnt);
2649 ulRatio += TOP_RATE_18M;
2650 ulMaxPacket = pDevice->uNumSQ3[RATE_18M];
2652 if (pDevice->uNumSQ3[RATE_12M] > ulMaxPacket) {
2653 ulPacketNum = pDevice->uNumSQ3[RATE_54M] + pDevice->uNumSQ3[RATE_48M] +
2654 pDevice->uNumSQ3[RATE_36M] + pDevice->uNumSQ3[RATE_24M] +
2655 pDevice->uNumSQ3[RATE_18M] + pDevice->uNumSQ3[RATE_12M];
2656 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2657 //ulRatio = (pDevice->uNumSQ3[RATE_12M] * 1000 / pDevice->uDiversityCnt);
2658 ulRatio += TOP_RATE_12M;
2659 ulMaxPacket = pDevice->uNumSQ3[RATE_12M];
2661 if (pDevice->uNumSQ3[RATE_11M] > ulMaxPacket) {
2662 ulPacketNum = pDevice->uDiversityCnt - pDevice->uNumSQ3[RATE_1M] -
2663 pDevice->uNumSQ3[RATE_2M] - pDevice->uNumSQ3[RATE_5M] -
2664 pDevice->uNumSQ3[RATE_6M] - pDevice->uNumSQ3[RATE_9M];
2665 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2666 //ulRatio = (pDevice->uNumSQ3[RATE_11M] * 1000 / pDevice->uDiversityCnt);
2667 ulRatio += TOP_RATE_11M;
2668 ulMaxPacket = pDevice->uNumSQ3[RATE_11M];
2670 if (pDevice->uNumSQ3[RATE_9M] > ulMaxPacket) {
2671 ulPacketNum = pDevice->uDiversityCnt - pDevice->uNumSQ3[RATE_1M] -
2672 pDevice->uNumSQ3[RATE_2M] - pDevice->uNumSQ3[RATE_5M] -
2673 pDevice->uNumSQ3[RATE_6M];
2674 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2675 //ulRatio = (pDevice->uNumSQ3[RATE_9M] * 1000 / pDevice->uDiversityCnt);
2676 ulRatio += TOP_RATE_9M;
2677 ulMaxPacket = pDevice->uNumSQ3[RATE_9M];
2679 if (pDevice->uNumSQ3[RATE_6M] > ulMaxPacket) {
2680 ulPacketNum = pDevice->uDiversityCnt - pDevice->uNumSQ3[RATE_1M] -
2681 pDevice->uNumSQ3[RATE_2M] - pDevice->uNumSQ3[RATE_5M];
2682 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2683 //ulRatio = (pDevice->uNumSQ3[RATE_6M] * 1000 / pDevice->uDiversityCnt);
2684 ulRatio += TOP_RATE_6M;
2685 ulMaxPacket = pDevice->uNumSQ3[RATE_6M];
2687 if (pDevice->uNumSQ3[RATE_5M] > ulMaxPacket) {
2688 ulPacketNum = pDevice->uDiversityCnt - pDevice->uNumSQ3[RATE_1M] -
2689 pDevice->uNumSQ3[RATE_2M];
2690 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2691 //ulRatio = (pDevice->uNumSQ3[RATE_5M] * 1000 / pDevice->uDiversityCnt);
2692 ulRatio += TOP_RATE_55M;
2693 ulMaxPacket = pDevice->uNumSQ3[RATE_5M];
2695 if (pDevice->uNumSQ3[RATE_2M] > ulMaxPacket) {
2696 ulPacketNum = pDevice->uDiversityCnt - pDevice->uNumSQ3[RATE_1M];
2697 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2698 //ulRatio = (pDevice->uNumSQ3[RATE_2M] * 1000 / pDevice->uDiversityCnt);
2699 ulRatio += TOP_RATE_2M;
2700 ulMaxPacket = pDevice->uNumSQ3[RATE_2M];
2702 if (pDevice->uNumSQ3[RATE_1M] > ulMaxPacket) {
2703 ulPacketNum = pDevice->uDiversityCnt;
2704 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2705 //ulRatio = (pDevice->uNumSQ3[RATE_1M] * 1000 / pDevice->uDiversityCnt);
2706 ulRatio += TOP_RATE_1M;
2713 BBvClearAntDivSQ3Value(PSDevice pDevice)
2717 pDevice->uDiversityCnt = 0;
2718 for (ii = 0; ii < MAX_RATE; ii++) {
2719 pDevice->uNumSQ3[ii] = 0;
2724 * Description: Antenna Diversity
2728 * pDevice - Device Structure
2729 * byRSR - RSR from received packet
2730 * bySQ3 - SQ3 value from received packet
2734 * Return Value: none
2739 BBvAntennaDiversity(PSDevice pDevice, unsigned char byRxRate, unsigned char bySQ3)
2741 if ((byRxRate >= MAX_RATE) || (pDevice->wAntDiversityMaxRate >= MAX_RATE)) {
2744 pDevice->uDiversityCnt++;
2745 // DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "pDevice->uDiversityCnt = %d\n", (int)pDevice->uDiversityCnt);
2747 pDevice->uNumSQ3[byRxRate]++;
2749 if (pDevice->byAntennaState == 0) {
2750 if (pDevice->uDiversityCnt > pDevice->ulDiversityNValue) {
2751 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "ulDiversityNValue=[%d],54M-[%d]\n",
2752 (int)pDevice->ulDiversityNValue, (int)pDevice->uNumSQ3[(int)pDevice->wAntDiversityMaxRate]);
2754 if (pDevice->uNumSQ3[pDevice->wAntDiversityMaxRate] < pDevice->uDiversityCnt/2) {
2755 pDevice->ulRatio_State0 = s_ulGetRatio(pDevice);
2756 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "SQ3_State0, rate = [%08x]\n", (int)pDevice->ulRatio_State0);
2758 if (pDevice->byTMax == 0)
2760 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "1.[%08x], uNumSQ3[%d]=%d, %d\n",
2761 (int)pDevice->ulRatio_State0, (int)pDevice->wAntDiversityMaxRate,
2762 (int)pDevice->uNumSQ3[(int)pDevice->wAntDiversityMaxRate], (int)pDevice->uDiversityCnt);
2764 s_vChangeAntenna(pDevice);
2765 pDevice->byAntennaState = 1;
2766 del_timer(&pDevice->TimerSQ3Tmax3);
2767 del_timer(&pDevice->TimerSQ3Tmax2);
2768 pDevice->TimerSQ3Tmax1.expires = RUN_AT(pDevice->byTMax * HZ);
2769 add_timer(&pDevice->TimerSQ3Tmax1);
2772 pDevice->TimerSQ3Tmax3.expires = RUN_AT(pDevice->byTMax3 * HZ);
2773 add_timer(&pDevice->TimerSQ3Tmax3);
2775 BBvClearAntDivSQ3Value(pDevice);
2778 } else { //byAntennaState == 1
2780 if (pDevice->uDiversityCnt > pDevice->ulDiversityMValue) {
2781 del_timer(&pDevice->TimerSQ3Tmax1);
2783 pDevice->ulRatio_State1 = s_ulGetRatio(pDevice);
2784 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "RX:SQ3_State1, rate0 = %08x,rate1 = %08x\n",
2785 (int)pDevice->ulRatio_State0, (int)pDevice->ulRatio_State1);
2787 if (pDevice->ulRatio_State1 < pDevice->ulRatio_State0) {
2788 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "2.[%08x][%08x], uNumSQ3[%d]=%d, %d\n",
2789 (int)pDevice->ulRatio_State0, (int)pDevice->ulRatio_State1,
2790 (int)pDevice->wAntDiversityMaxRate,
2791 (int)pDevice->uNumSQ3[(int)pDevice->wAntDiversityMaxRate], (int)pDevice->uDiversityCnt);
2793 s_vChangeAntenna(pDevice);
2794 pDevice->TimerSQ3Tmax3.expires = RUN_AT(pDevice->byTMax3 * HZ);
2795 pDevice->TimerSQ3Tmax2.expires = RUN_AT(pDevice->byTMax2 * HZ);
2796 add_timer(&pDevice->TimerSQ3Tmax3);
2797 add_timer(&pDevice->TimerSQ3Tmax2);
2799 pDevice->byAntennaState = 0;
2800 BBvClearAntDivSQ3Value(pDevice);
2808 * Timer for SQ3 antenna diversity
2815 * Return Value: none
2821 void *hDeviceContext
2824 PSDevice pDevice = (PSDevice)hDeviceContext;
2826 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "TimerSQ3CallBack...");
2827 spin_lock_irq(&pDevice->lock);
2829 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "3.[%08x][%08x], %d\n", (int)pDevice->ulRatio_State0, (int)pDevice->ulRatio_State1, (int)pDevice->uDiversityCnt);
2831 s_vChangeAntenna(pDevice);
2832 pDevice->byAntennaState = 0;
2833 BBvClearAntDivSQ3Value(pDevice);
2835 pDevice->TimerSQ3Tmax3.expires = RUN_AT(pDevice->byTMax3 * HZ);
2836 pDevice->TimerSQ3Tmax2.expires = RUN_AT(pDevice->byTMax2 * HZ);
2837 add_timer(&pDevice->TimerSQ3Tmax3);
2838 add_timer(&pDevice->TimerSQ3Tmax2);
2840 spin_unlock_irq(&pDevice->lock);
2847 * Timer for SQ3 antenna diversity
2852 * hDeviceContext - Pointer to the adapter
2858 * Return Value: none
2863 TimerState1CallBack(
2864 void *hDeviceContext
2867 PSDevice pDevice = (PSDevice)hDeviceContext;
2869 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "TimerState1CallBack...");
2871 spin_lock_irq(&pDevice->lock);
2872 if (pDevice->uDiversityCnt < pDevice->ulDiversityMValue/100) {
2873 s_vChangeAntenna(pDevice);
2874 pDevice->TimerSQ3Tmax3.expires = RUN_AT(pDevice->byTMax3 * HZ);
2875 pDevice->TimerSQ3Tmax2.expires = RUN_AT(pDevice->byTMax2 * HZ);
2876 add_timer(&pDevice->TimerSQ3Tmax3);
2877 add_timer(&pDevice->TimerSQ3Tmax2);
2879 pDevice->ulRatio_State1 = s_ulGetRatio(pDevice);
2880 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "SQ3_State1, rate0 = %08x,rate1 = %08x\n",
2881 (int)pDevice->ulRatio_State0, (int)pDevice->ulRatio_State1);
2883 if (pDevice->ulRatio_State1 < pDevice->ulRatio_State0) {
2884 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "2.[%08x][%08x], uNumSQ3[%d]=%d, %d\n",
2885 (int)pDevice->ulRatio_State0, (int)pDevice->ulRatio_State1,
2886 (int)pDevice->wAntDiversityMaxRate,
2887 (int)pDevice->uNumSQ3[(int)pDevice->wAntDiversityMaxRate], (int)pDevice->uDiversityCnt);
2889 s_vChangeAntenna(pDevice);
2891 pDevice->TimerSQ3Tmax3.expires = RUN_AT(pDevice->byTMax3 * HZ);
2892 pDevice->TimerSQ3Tmax2.expires = RUN_AT(pDevice->byTMax2 * HZ);
2893 add_timer(&pDevice->TimerSQ3Tmax3);
2894 add_timer(&pDevice->TimerSQ3Tmax2);
2897 pDevice->byAntennaState = 0;
2898 BBvClearAntDivSQ3Value(pDevice);
2899 spin_unlock_irq(&pDevice->lock);