2 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
22 * Purpose: MAC routines
29 * 07-01-2003 Bryan YC Fan: Re-write codes to support VT3253 spec.
30 * 08-25-2003 Kyle Hsu: Porting MAC functions from sim53.
31 * 09-03-2003 Bryan YC Fan: Add MACvDisableProtectMD & MACvEnableProtectMD
40 /*--------------------- Export Definitions -------------------------*/
42 // Registers in the MAC
44 #define MAC_MAX_CONTEXT_SIZE_PAGE0 256
45 #define MAC_MAX_CONTEXT_SIZE_PAGE1 128
47 // Registers not related to 802.11b
48 #define MAC_REG_BCFG0 0x00
49 #define MAC_REG_BCFG1 0x01
50 #define MAC_REG_FCR0 0x02
51 #define MAC_REG_FCR1 0x03
52 #define MAC_REG_BISTCMD 0x04
53 #define MAC_REG_BISTSR0 0x05
54 #define MAC_REG_BISTSR1 0x06
55 #define MAC_REG_BISTSR2 0x07
56 #define MAC_REG_I2MCSR 0x08
57 #define MAC_REG_I2MTGID 0x09
58 #define MAC_REG_I2MTGAD 0x0A
59 #define MAC_REG_I2MCFG 0x0B
60 #define MAC_REG_I2MDIPT 0x0C
61 #define MAC_REG_I2MDOPT 0x0E
62 #define MAC_REG_PMC0 0x10
63 #define MAC_REG_PMC1 0x11
64 #define MAC_REG_STICKHW 0x12
65 #define MAC_REG_LOCALID 0x14
66 #define MAC_REG_TESTCFG 0x15
67 #define MAC_REG_JUMPER0 0x16
68 #define MAC_REG_JUMPER1 0x17
69 #define MAC_REG_TMCTL0 0x18
70 #define MAC_REG_TMCTL1 0x19
71 #define MAC_REG_TMDATA0 0x1C
72 // MAC Parameter related
73 #define MAC_REG_LRT 0x20 //
74 #define MAC_REG_SRT 0x21 //
75 #define MAC_REG_SIFS 0x22 //
76 #define MAC_REG_DIFS 0x23 //
77 #define MAC_REG_EIFS 0x24 //
78 #define MAC_REG_SLOT 0x25 //
79 #define MAC_REG_BI 0x26 //
80 #define MAC_REG_CWMAXMIN0 0x28 //
81 #define MAC_REG_LINKOFFTOTM 0x2A
82 #define MAC_REG_SWTMOT 0x2B
83 #define MAC_REG_MIBCNTR 0x2C
84 #define MAC_REG_RTSOKCNT 0x2C
85 #define MAC_REG_RTSFAILCNT 0x2D
86 #define MAC_REG_ACKFAILCNT 0x2E
87 #define MAC_REG_FCSERRCNT 0x2F
89 #define MAC_REG_TSFCNTR 0x30 //
90 #define MAC_REG_NEXTTBTT 0x38 //
91 #define MAC_REG_TSFOFST 0x40 //
92 #define MAC_REG_TFTCTL 0x48 //
93 // WMAC Control/Status Related
94 #define MAC_REG_ENCFG 0x4C //
95 #define MAC_REG_PAGE1SEL 0x4F //
96 #define MAC_REG_CFG 0x50 //
97 #define MAC_REG_TEST 0x52 //
98 #define MAC_REG_HOSTCR 0x54 //
99 #define MAC_REG_MACCR 0x55 //
100 #define MAC_REG_RCR 0x56 //
101 #define MAC_REG_TCR 0x57 //
102 #define MAC_REG_IMR 0x58 //
103 #define MAC_REG_ISR 0x5C
104 // Power Saving Related
105 #define MAC_REG_PSCFG 0x60 //
106 #define MAC_REG_PSCTL 0x61 //
107 #define MAC_REG_PSPWRSIG 0x62 //
108 #define MAC_REG_BBCR13 0x63
109 #define MAC_REG_AIDATIM 0x64
110 #define MAC_REG_PWBT 0x66
111 #define MAC_REG_WAKEOKTMR 0x68
112 #define MAC_REG_CALTMR 0x69
113 #define MAC_REG_SYNSPACCNT 0x6A
114 #define MAC_REG_WAKSYNOPT 0x6B
115 // Baseband/IF Control Group
116 #define MAC_REG_BBREGCTL 0x6C //
117 #define MAC_REG_CHANNEL 0x6D
118 #define MAC_REG_BBREGADR 0x6E
119 #define MAC_REG_BBREGDATA 0x6F
120 #define MAC_REG_IFREGCTL 0x70 //
121 #define MAC_REG_IFDATA 0x71 //
122 #define MAC_REG_ITRTMSET 0x74 //
123 #define MAC_REG_PAPEDELAY 0x77
124 #define MAC_REG_SOFTPWRCTL 0x78 //
125 #define MAC_REG_GPIOCTL0 0x7A //
126 #define MAC_REG_GPIOCTL1 0x7B //
128 // MAC DMA Related Group
129 #define MAC_REG_TXDMACTL0 0x7C //
130 #define MAC_REG_TXDMAPTR0 0x80 //
131 #define MAC_REG_AC0DMACTL 0x84 //
132 #define MAC_REG_AC0DMAPTR 0x88 //
133 #define MAC_REG_BCNDMACTL 0x8C //
134 #define MAC_REG_BCNDMAPTR 0x90 //
135 #define MAC_REG_RXDMACTL0 0x94 //
136 #define MAC_REG_RXDMAPTR0 0x98 //
137 #define MAC_REG_RXDMACTL1 0x9C //
138 #define MAC_REG_RXDMAPTR1 0xA0 //
139 #define MAC_REG_SYNCDMACTL 0xA4 //
140 #define MAC_REG_SYNCDMAPTR 0xA8
141 #define MAC_REG_ATIMDMACTL 0xAC
142 #define MAC_REG_ATIMDMAPTR 0xB0
143 // MiscFF PIO related
144 #define MAC_REG_MISCFFNDEX 0xB4
145 #define MAC_REG_MISCFFCTL 0xB6
146 #define MAC_REG_MISCFFDATA 0xB8
148 #define MAC_REG_TMDATA1 0xBC
150 #define MAC_REG_WAKEUPEN0 0xC0
151 #define MAC_REG_WAKEUPEN1 0xC1
152 #define MAC_REG_WAKEUPSR0 0xC2
153 #define MAC_REG_WAKEUPSR1 0xC3
154 #define MAC_REG_WAKE128_0 0xC4
155 #define MAC_REG_WAKE128_1 0xD4
156 #define MAC_REG_WAKE128_2 0xE4
157 #define MAC_REG_WAKE128_3 0xF4
159 /////////////// Page 1 ///////////////////
160 #define MAC_REG_CRC_128_0 0x04
161 #define MAC_REG_CRC_128_1 0x06
162 #define MAC_REG_CRC_128_2 0x08
163 #define MAC_REG_CRC_128_3 0x0A
164 // MAC Configuration Group
165 #define MAC_REG_PAR0 0x0C
166 #define MAC_REG_PAR4 0x10
167 #define MAC_REG_BSSID0 0x14
168 #define MAC_REG_BSSID4 0x18
169 #define MAC_REG_MAR0 0x1C
170 #define MAC_REG_MAR4 0x20
171 // MAC RSPPKT INFO Group
172 #define MAC_REG_RSPINF_B_1 0x24
173 #define MAC_REG_RSPINF_B_2 0x28
174 #define MAC_REG_RSPINF_B_5 0x2C
175 #define MAC_REG_RSPINF_B_11 0x30
176 #define MAC_REG_RSPINF_A_6 0x34
177 #define MAC_REG_RSPINF_A_9 0x36
178 #define MAC_REG_RSPINF_A_12 0x38
179 #define MAC_REG_RSPINF_A_18 0x3A
180 #define MAC_REG_RSPINF_A_24 0x3C
181 #define MAC_REG_RSPINF_A_36 0x3E
182 #define MAC_REG_RSPINF_A_48 0x40
183 #define MAC_REG_RSPINF_A_54 0x42
184 #define MAC_REG_RSPINF_A_72 0x44
187 #define MAC_REG_QUIETINIT 0x60
188 #define MAC_REG_QUIETGAP 0x62
189 #define MAC_REG_QUIETDUR 0x64
190 #define MAC_REG_MSRCTL 0x66
191 #define MAC_REG_MSRBBSTS 0x67
192 #define MAC_REG_MSRSTART 0x68
193 #define MAC_REG_MSRDURATION 0x70
194 #define MAC_REG_CCAFRACTION 0x72
195 #define MAC_REG_PWRCCK 0x73
196 #define MAC_REG_PWROFDM 0x7C
199 // Bits in the BCFG0 register
201 #define BCFG0_PERROFF 0x40
202 #define BCFG0_MRDMDIS 0x20
203 #define BCFG0_MRDLDIS 0x10
204 #define BCFG0_MWMEN 0x08
205 #define BCFG0_VSERREN 0x02
206 #define BCFG0_LATMEN 0x01
209 // Bits in the BCFG1 register
211 #define BCFG1_CFUNOPT 0x80
212 #define BCFG1_CREQOPT 0x40
213 #define BCFG1_DMA8 0x10
214 #define BCFG1_ARBITOPT 0x08
215 #define BCFG1_PCIMEN 0x04
216 #define BCFG1_MIOEN 0x02
217 #define BCFG1_CISDLYEN 0x01
219 // Bits in RAMBIST registers
220 #define BISTCMD_TSTPAT5 0x00 //
221 #define BISTCMD_TSTPATA 0x80 //
222 #define BISTCMD_TSTERR 0x20 //
223 #define BISTCMD_TSTPATF 0x18 //
224 #define BISTCMD_TSTPAT0 0x10 //
225 #define BISTCMD_TSTMODE 0x04 //
226 #define BISTCMD_TSTITTX 0x03 //
227 #define BISTCMD_TSTATRX 0x02 //
228 #define BISTCMD_TSTATTX 0x01 //
229 #define BISTCMD_TSTRX 0x00 //
230 #define BISTSR0_BISTGO 0x01 //
231 #define BISTSR1_TSTSR 0x01 //
232 #define BISTSR2_CMDPRTEN 0x02 //
233 #define BISTSR2_RAMTSTEN 0x01 //
236 // Bits in the I2MCFG EEPROM register
238 #define I2MCFG_BOUNDCTL 0x80
239 #define I2MCFG_WAITCTL 0x20
240 #define I2MCFG_SCLOECTL 0x10
241 #define I2MCFG_WBUSYCTL 0x08
242 #define I2MCFG_NORETRY 0x04
243 #define I2MCFG_I2MLDSEQ 0x02
244 #define I2MCFG_I2CMFAST 0x01
247 // Bits in the I2MCSR EEPROM register
249 #define I2MCSR_EEMW 0x80
250 #define I2MCSR_EEMR 0x40
251 #define I2MCSR_AUTOLD 0x08
252 #define I2MCSR_NACK 0x02
253 #define I2MCSR_DONE 0x01
256 // Bits in the PMC1 register
259 #define PCISTIKY 0x40
263 // Bits in the STICKYHW register
265 #define STICKHW_DS1_SHADOW 0x02
266 #define STICKHW_DS0_SHADOW 0x01
269 // Bits in the TMCTL register
271 #define TMCTL_TSUSP 0x04
272 #define TMCTL_TMD 0x02
273 #define TMCTL_TE 0x01
276 // Bits in the TFTCTL register
278 #define TFTCTL_HWUTSF 0x80 //
279 #define TFTCTL_TBTTSYNC 0x40
280 #define TFTCTL_HWUTSFEN 0x20
281 #define TFTCTL_TSFCNTRRD 0x10 //
282 #define TFTCTL_TBTTSYNCEN 0x08 //
283 #define TFTCTL_TSFSYNCEN 0x04 //
284 #define TFTCTL_TSFCNTRST 0x02 //
285 #define TFTCTL_TSFCNTREN 0x01 //
288 // Bits in the EnhanceCFG register
290 #define EnCFG_BarkerPream 0x00020000
291 #define EnCFG_NXTBTTCFPSTR 0x00010000
292 #define EnCFG_BcnSusClr 0x00000200
293 #define EnCFG_BcnSusInd 0x00000100
294 #define EnCFG_CFP_ProtectEn 0x00000040
295 #define EnCFG_ProtectMd 0x00000020
296 #define EnCFG_HwParCFP 0x00000010
297 #define EnCFG_CFNULRSP 0x00000004
298 #define EnCFG_BBType_MASK 0x00000003
299 #define EnCFG_BBType_g 0x00000002
300 #define EnCFG_BBType_b 0x00000001
301 #define EnCFG_BBType_a 0x00000000
304 // Bits in the Page1Sel register
306 #define PAGE1_SEL 0x01
309 // Bits in the CFG register
311 #define CFG_TKIPOPT 0x80
312 #define CFG_RXDMAOPT 0x40
313 #define CFG_TMOT_SW 0x20
314 #define CFG_TMOT_HWLONG 0x10
315 #define CFG_TMOT_HW 0x00
316 #define CFG_CFPENDOPT 0x08
317 #define CFG_BCNSUSEN 0x04
318 #define CFG_NOTXTIMEOUT 0x02
319 #define CFG_NOBUFOPT 0x01
322 // Bits in the TEST register
324 #define TEST_LBEXT 0x80 //
325 #define TEST_LBINT 0x40 //
326 #define TEST_LBNONE 0x00 //
327 #define TEST_SOFTINT 0x20 //
328 #define TEST_CONTTX 0x10 //
329 #define TEST_TXPE 0x08 //
330 #define TEST_NAVDIS 0x04 //
331 #define TEST_NOCTS 0x02 //
332 #define TEST_NOACK 0x01 //
335 // Bits in the HOSTCR register
337 #define HOSTCR_TXONST 0x80 //
338 #define HOSTCR_RXONST 0x40 //
339 #define HOSTCR_ADHOC 0x20 // Network Type 1 = Ad-hoc
340 #define HOSTCR_AP 0x10 // Port Type 1 = AP
341 #define HOSTCR_TXON 0x08 //0000 1000
342 #define HOSTCR_RXON 0x04 //0000 0100
343 #define HOSTCR_MACEN 0x02 //0000 0010
344 #define HOSTCR_SOFTRST 0x01 //0000 0001
347 // Bits in the MACCR register
349 #define MACCR_SYNCFLUSHOK 0x04 //
350 #define MACCR_SYNCFLUSH 0x02 //
351 #define MACCR_CLRNAV 0x01 //
353 // Bits in the MAC_REG_GPIOCTL0 register
355 #define LED_ACTSET 0x01 //
356 #define LED_RFOFF 0x02 //
357 #define LED_NOCONNECT 0x04 //
359 // Bits in the RCR register
361 #define RCR_SSID 0x80
362 #define RCR_RXALLTYPE 0x40 //
363 #define RCR_UNICAST 0x20 //
364 #define RCR_BROADCAST 0x10 //
365 #define RCR_MULTICAST 0x08 //
366 #define RCR_WPAERR 0x04 //
367 #define RCR_ERRCRC 0x02 //
368 #define RCR_BSSID 0x01 //
371 // Bits in the TCR register
373 #define TCR_SYNCDCFOPT 0x02 //
374 #define TCR_AUTOBCNTX 0x01 // Beacon automatically transmit enable
377 // Bits in the IMR register
379 #define IMR_MEASURESTART 0x80000000 //
380 #define IMR_QUIETSTART 0x20000000 //
381 #define IMR_RADARDETECT 0x10000000 //
382 #define IMR_MEASUREEND 0x08000000 //
383 #define IMR_SOFTTIMER1 0x00200000 //
384 #define IMR_RXDMA1 0x00001000 //0000 0000 0001 0000 0000 0000
385 #define IMR_RXNOBUF 0x00000800 //
386 #define IMR_MIBNEARFULL 0x00000400 //
387 #define IMR_SOFTINT 0x00000200 //
388 #define IMR_FETALERR 0x00000100 //
389 #define IMR_WATCHDOG 0x00000080 //
390 #define IMR_SOFTTIMER 0x00000040 //
391 #define IMR_GPIO 0x00000020 //
392 #define IMR_TBTT 0x00000010 //
393 #define IMR_RXDMA0 0x00000008 //
394 #define IMR_BNTX 0x00000004 //
395 #define IMR_AC0DMA 0x00000002 //
396 #define IMR_TXDMA0 0x00000001 //
399 // Bits in the ISR register
402 #define ISR_MEASURESTART 0x80000000 //
403 #define ISR_QUIETSTART 0x20000000 //
404 #define ISR_RADARDETECT 0x10000000 //
405 #define ISR_MEASUREEND 0x08000000 //
406 #define ISR_SOFTTIMER1 0x00200000 //
407 #define ISR_RXDMA1 0x00001000 //0000 0000 0001 0000 0000 0000
408 #define ISR_RXNOBUF 0x00000800 //0000 0000 0000 1000 0000 0000
409 #define ISR_MIBNEARFULL 0x00000400 //0000 0000 0000 0100 0000 0000
410 #define ISR_SOFTINT 0x00000200 //
411 #define ISR_FETALERR 0x00000100 //
412 #define ISR_WATCHDOG 0x00000080 //
413 #define ISR_SOFTTIMER 0x00000040 //
414 #define ISR_GPIO 0x00000020 //
415 #define ISR_TBTT 0x00000010 //
416 #define ISR_RXDMA0 0x00000008 //
417 #define ISR_BNTX 0x00000004 //
418 #define ISR_AC0DMA 0x00000002 //
419 #define ISR_TXDMA0 0x00000001 //
422 // Bits in the PSCFG register
424 #define PSCFG_PHILIPMD 0x40 //
425 #define PSCFG_WAKECALEN 0x20 //
426 #define PSCFG_WAKETMREN 0x10 //
427 #define PSCFG_BBPSPROG 0x08 //
428 #define PSCFG_WAKESYN 0x04 //
429 #define PSCFG_SLEEPSYN 0x02 //
430 #define PSCFG_AUTOSLEEP 0x01 //
433 // Bits in the PSCTL register
435 #define PSCTL_WAKEDONE 0x20 //
436 #define PSCTL_PS 0x10 //
437 #define PSCTL_GO2DOZE 0x08 //
438 #define PSCTL_LNBCN 0x04 //
439 #define PSCTL_ALBCN 0x02 //
440 #define PSCTL_PSEN 0x01 //
443 // Bits in the PSPWSIG register
445 #define PSSIG_WPE3 0x80 //
446 #define PSSIG_WPE2 0x40 //
447 #define PSSIG_WPE1 0x20 //
448 #define PSSIG_WRADIOPE 0x10 //
449 #define PSSIG_SPE3 0x08 //
450 #define PSSIG_SPE2 0x04 //
451 #define PSSIG_SPE1 0x02 //
452 #define PSSIG_SRADIOPE 0x01 //
455 // Bits in the BBREGCTL register
457 #define BBREGCTL_DONE 0x04 //
458 #define BBREGCTL_REGR 0x02 //
459 #define BBREGCTL_REGW 0x01 //
462 // Bits in the IFREGCTL register
464 #define IFREGCTL_DONE 0x04 //
465 #define IFREGCTL_IFRF 0x02 //
466 #define IFREGCTL_REGW 0x01 //
469 // Bits in the SOFTPWRCTL register
471 #define SOFTPWRCTL_RFLEOPT 0x0800 //
472 #define SOFTPWRCTL_TXPEINV 0x0200 //
473 #define SOFTPWRCTL_SWPECTI 0x0100 //
474 #define SOFTPWRCTL_SWPAPE 0x0020 //
475 #define SOFTPWRCTL_SWCALEN 0x0010 //
476 #define SOFTPWRCTL_SWRADIO_PE 0x0008 //
477 #define SOFTPWRCTL_SWPE2 0x0004 //
478 #define SOFTPWRCTL_SWPE1 0x0002 //
479 #define SOFTPWRCTL_SWPE3 0x0001 //
482 // Bits in the GPIOCTL1 register
484 #define GPIO1_DATA1 0x20 //
485 #define GPIO1_MD1 0x10 //
486 #define GPIO1_DATA0 0x02 //
487 #define GPIO1_MD0 0x01 //
490 // Bits in the DMACTL register
492 #define DMACTL_CLRRUN 0x00080000 //
493 #define DMACTL_RUN 0x00000008 //
494 #define DMACTL_WAKE 0x00000004 //
495 #define DMACTL_DEAD 0x00000002 //
496 #define DMACTL_ACTIVE 0x00000001 //
498 // Bits in the RXDMACTL0 register
500 #define RX_PERPKT 0x00000100 //
501 #define RX_PERPKTCLR 0x01000000 //
503 // Bits in the BCNDMACTL register
505 #define BEACON_READY 0x01 //
507 // Bits in the MISCFFCTL register
509 #define MISCFFCTL_WRITE 0x0001 //
514 #define WAKEUPEN0_DIRPKT 0x10
515 #define WAKEUPEN0_LINKOFF 0x08
516 #define WAKEUPEN0_ATIMEN 0x04
517 #define WAKEUPEN0_TIMEN 0x02
518 #define WAKEUPEN0_MAGICEN 0x01
523 #define WAKEUPEN1_128_3 0x08
524 #define WAKEUPEN1_128_2 0x04
525 #define WAKEUPEN1_128_1 0x02
526 #define WAKEUPEN1_128_0 0x01
531 #define WAKEUPSR0_DIRPKT 0x10
532 #define WAKEUPSR0_LINKOFF 0x08
533 #define WAKEUPSR0_ATIMEN 0x04
534 #define WAKEUPSR0_TIMEN 0x02
535 #define WAKEUPSR0_MAGICEN 0x01
540 #define WAKEUPSR1_128_3 0x08
541 #define WAKEUPSR1_128_2 0x04
542 #define WAKEUPSR1_128_1 0x02
543 #define WAKEUPSR1_128_0 0x01
546 // Bits in the MAC_REG_GPIOCTL register
548 #define GPIO0_MD 0x01 //
549 #define GPIO0_DATA 0x02 //
550 #define GPIO0_INTMD 0x04 //
551 #define GPIO1_MD 0x10 //
552 #define GPIO1_DATA 0x20 //
555 // Bits in the MSRCTL register
557 #define MSRCTL_FINISH 0x80
558 #define MSRCTL_READY 0x40
559 #define MSRCTL_RADARDETECT 0x20
560 #define MSRCTL_EN 0x10
561 #define MSRCTL_QUIETTXCHK 0x08
562 #define MSRCTL_QUIETRPT 0x04
563 #define MSRCTL_QUIETINT 0x02
564 #define MSRCTL_QUIETEN 0x01
566 // Bits in the MSRCTL1 register
568 #define MSRCTL1_TXPWR 0x08
569 #define MSRCTL1_CSAPAREN 0x04
570 #define MSRCTL1_TXPAUSE 0x01
573 #define MAC_LB_EXT 0x02 //
574 #define MAC_LB_INTERNAL 0x01 //
575 #define MAC_LB_NONE 0x00 //
577 #define Default_BI 0x200
580 #define MISCFIFO_KEYETRY0 32
581 #define MISCFIFO_KEYENTRYSIZE 22
582 #define MISCFIFO_SYNINFO_IDX 10
583 #define MISCFIFO_SYNDATA_IDX 11
584 #define MISCFIFO_SYNDATASIZE 21
586 // enabled mask value of irq
587 #define IMR_MASK_VALUE (IMR_SOFTTIMER1 | \
602 // max time out delay time
603 #define W_MAX_TIMEOUT 0xFFF0U //
605 // wait time within loop
606 #define CB_DELAY_LOOP_WAIT 10 // 10ms
611 #define REV_ID_VT3253_A0 0x00
612 #define REV_ID_VT3253_A1 0x01
613 #define REV_ID_VT3253_B0 0x08
614 #define REV_ID_VT3253_B1 0x09
616 /*--------------------- Export Types ------------------------------*/
618 /*--------------------- Export Macros ------------------------------*/
620 #define MACvRegBitsOn(dwIoBase, byRegOfs, byBits) \
622 unsigned char byData; \
623 VNSvInPortB(dwIoBase + byRegOfs, &byData); \
624 VNSvOutPortB(dwIoBase + byRegOfs, byData | (byBits)); \
627 #define MACvWordRegBitsOn(dwIoBase, byRegOfs, wBits) \
629 unsigned short wData; \
630 VNSvInPortW(dwIoBase + byRegOfs, &wData); \
631 VNSvOutPortW(dwIoBase + byRegOfs, wData | (wBits)); \
634 #define MACvDWordRegBitsOn(dwIoBase, byRegOfs, dwBits) \
636 unsigned long dwData; \
637 VNSvInPortD(dwIoBase + byRegOfs, &dwData); \
638 VNSvOutPortD(dwIoBase + byRegOfs, dwData | (dwBits)); \
641 #define MACvRegBitsOnEx(dwIoBase, byRegOfs, byMask, byBits) \
643 unsigned char byData; \
644 VNSvInPortB(dwIoBase + byRegOfs, &byData); \
646 VNSvOutPortB(dwIoBase + byRegOfs, byData | (byBits)); \
649 #define MACvRegBitsOff(dwIoBase, byRegOfs, byBits) \
651 unsigned char byData; \
652 VNSvInPortB(dwIoBase + byRegOfs, &byData); \
653 VNSvOutPortB(dwIoBase + byRegOfs, byData & ~(byBits)); \
656 #define MACvWordRegBitsOff(dwIoBase, byRegOfs, wBits) \
658 unsigned short wData; \
659 VNSvInPortW(dwIoBase + byRegOfs, &wData); \
660 VNSvOutPortW(dwIoBase + byRegOfs, wData & ~(wBits)); \
663 #define MACvDWordRegBitsOff(dwIoBase, byRegOfs, dwBits) \
665 unsigned long dwData; \
666 VNSvInPortD(dwIoBase + byRegOfs, &dwData); \
667 VNSvOutPortD(dwIoBase + byRegOfs, dwData & ~(dwBits)); \
670 #define MACvGetCurrRx0DescAddr(dwIoBase, pdwCurrDescAddr) \
671 VNSvInPortD(dwIoBase + MAC_REG_RXDMAPTR0, \
672 (unsigned long *)pdwCurrDescAddr)
674 #define MACvGetCurrRx1DescAddr(dwIoBase, pdwCurrDescAddr) \
675 VNSvInPortD(dwIoBase + MAC_REG_RXDMAPTR1, \
676 (unsigned long *)pdwCurrDescAddr)
678 #define MACvGetCurrTx0DescAddr(dwIoBase, pdwCurrDescAddr) \
679 VNSvInPortD(dwIoBase + MAC_REG_TXDMAPTR0, \
680 (unsigned long *)pdwCurrDescAddr)
682 #define MACvGetCurrAC0DescAddr(dwIoBase, pdwCurrDescAddr) \
683 VNSvInPortD(dwIoBase + MAC_REG_AC0DMAPTR, \
684 (unsigned long *)pdwCurrDescAddr)
686 #define MACvGetCurrSyncDescAddr(dwIoBase, pdwCurrDescAddr) \
687 VNSvInPortD(dwIoBase + MAC_REG_SYNCDMAPTR, \
688 (unsigned long *)pdwCurrDescAddr)
690 #define MACvGetCurrATIMDescAddr(dwIoBase, pdwCurrDescAddr) \
691 VNSvInPortD(dwIoBase + MAC_REG_ATIMDMAPTR, \
692 (unsigned long *)pdwCurrDescAddr)
694 // set the chip with current BCN tx descriptor address
695 #define MACvSetCurrBCNTxDescAddr(dwIoBase, dwCurrDescAddr) \
696 VNSvOutPortD(dwIoBase + MAC_REG_BCNDMAPTR, \
699 // set the chip with current BCN length
700 #define MACvSetCurrBCNLength(dwIoBase, wCurrBCNLength) \
701 VNSvOutPortW(dwIoBase + MAC_REG_BCNDMACTL+2, \
704 #define MACvReadBSSIDAddress(dwIoBase, pbyEtherAddr) \
706 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \
707 VNSvInPortB(dwIoBase + MAC_REG_BSSID0, \
708 (unsigned char *)pbyEtherAddr); \
709 VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 1, \
711 VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 2, \
713 VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 3, \
715 VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 4, \
717 VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 5, \
719 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \
722 #define MACvWriteBSSIDAddress(dwIoBase, pbyEtherAddr) \
724 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \
725 VNSvOutPortB(dwIoBase + MAC_REG_BSSID0, \
727 VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 1, \
728 *(pbyEtherAddr + 1)); \
729 VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 2, \
730 *(pbyEtherAddr + 2)); \
731 VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 3, \
732 *(pbyEtherAddr + 3)); \
733 VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 4, \
734 *(pbyEtherAddr + 4)); \
735 VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 5, \
736 *(pbyEtherAddr + 5)); \
737 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \
740 #define MACvReadEtherAddress(dwIoBase, pbyEtherAddr) \
742 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \
743 VNSvInPortB(dwIoBase + MAC_REG_PAR0, \
744 (unsigned char *)pbyEtherAddr); \
745 VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 1, \
747 VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 2, \
749 VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 3, \
751 VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 4, \
753 VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 5, \
755 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \
758 #define MACvWriteEtherAddress(dwIoBase, pbyEtherAddr) \
760 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \
761 VNSvOutPortB(dwIoBase + MAC_REG_PAR0, \
763 VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 1, \
764 *(pbyEtherAddr + 1)); \
765 VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 2, \
766 *(pbyEtherAddr + 2)); \
767 VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 3, \
768 *(pbyEtherAddr + 3)); \
769 VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 4, \
770 *(pbyEtherAddr + 4)); \
771 VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 5, \
772 *(pbyEtherAddr + 5)); \
773 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \
776 #define MACvClearISR(dwIoBase) \
777 VNSvOutPortD(dwIoBase + MAC_REG_ISR, IMR_MASK_VALUE)
779 #define MACvStart(dwIoBase) \
780 VNSvOutPortB(dwIoBase + MAC_REG_HOSTCR, \
781 (HOSTCR_MACEN | HOSTCR_RXON | HOSTCR_TXON))
783 #define MACvRx0PerPktMode(dwIoBase) \
784 VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, RX_PERPKT)
786 #define MACvRx0BufferFillMode(dwIoBase) \
787 VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, RX_PERPKTCLR)
789 #define MACvRx1PerPktMode(dwIoBase) \
790 VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, RX_PERPKT)
792 #define MACvRx1BufferFillMode(dwIoBase) \
793 VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, RX_PERPKTCLR)
795 #define MACvRxOn(dwIoBase) \
796 MACvRegBitsOn(dwIoBase, MAC_REG_HOSTCR, HOSTCR_RXON)
798 #define MACvReceive0(dwIoBase) \
800 unsigned long dwData; \
801 VNSvInPortD(dwIoBase + MAC_REG_RXDMACTL0, &dwData); \
802 if (dwData & DMACTL_RUN) \
803 VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, DMACTL_WAKE); \
805 VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, DMACTL_RUN); \
808 #define MACvReceive1(dwIoBase) \
810 unsigned long dwData; \
811 VNSvInPortD(dwIoBase + MAC_REG_RXDMACTL1, &dwData); \
812 if (dwData & DMACTL_RUN) \
813 VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, DMACTL_WAKE); \
815 VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, DMACTL_RUN); \
818 #define MACvTxOn(dwIoBase) \
819 MACvRegBitsOn(dwIoBase, MAC_REG_HOSTCR, HOSTCR_TXON)
821 #define MACvTransmit0(dwIoBase) \
823 unsigned long dwData; \
824 VNSvInPortD(dwIoBase + MAC_REG_TXDMACTL0, &dwData); \
825 if (dwData & DMACTL_RUN) \
826 VNSvOutPortD(dwIoBase + MAC_REG_TXDMACTL0, DMACTL_WAKE); \
828 VNSvOutPortD(dwIoBase + MAC_REG_TXDMACTL0, DMACTL_RUN); \
831 #define MACvTransmitAC0(dwIoBase) \
833 unsigned long dwData; \
834 VNSvInPortD(dwIoBase + MAC_REG_AC0DMACTL, &dwData); \
835 if (dwData & DMACTL_RUN) \
836 VNSvOutPortD(dwIoBase + MAC_REG_AC0DMACTL, DMACTL_WAKE); \
838 VNSvOutPortD(dwIoBase + MAC_REG_AC0DMACTL, DMACTL_RUN); \
841 #define MACvTransmitSYNC(dwIoBase) \
843 unsigned long dwData; \
844 VNSvInPortD(dwIoBase + MAC_REG_SYNCDMACTL, &dwData); \
845 if (dwData & DMACTL_RUN) \
846 VNSvOutPortD(dwIoBase + MAC_REG_SYNCDMACTL, DMACTL_WAKE); \
848 VNSvOutPortD(dwIoBase + MAC_REG_SYNCDMACTL, DMACTL_RUN); \
851 #define MACvTransmitATIM(dwIoBase) \
853 unsigned long dwData; \
854 VNSvInPortD(dwIoBase + MAC_REG_ATIMDMACTL, &dwData); \
855 if (dwData & DMACTL_RUN) \
856 VNSvOutPortD(dwIoBase + MAC_REG_ATIMDMACTL, DMACTL_WAKE); \
858 VNSvOutPortD(dwIoBase + MAC_REG_ATIMDMACTL, DMACTL_RUN); \
861 #define MACvTransmitBCN(dwIoBase) \
862 VNSvOutPortB(dwIoBase + MAC_REG_BCNDMACTL, BEACON_READY)
864 #define MACvClearStckDS(dwIoBase) \
866 unsigned char byOrgValue; \
867 VNSvInPortB(dwIoBase + MAC_REG_STICKHW, &byOrgValue); \
868 byOrgValue = byOrgValue & 0xFC; \
869 VNSvOutPortB(dwIoBase + MAC_REG_STICKHW, byOrgValue); \
872 #define MACvReadISR(dwIoBase, pdwValue) \
873 VNSvInPortD(dwIoBase + MAC_REG_ISR, pdwValue)
875 #define MACvWriteISR(dwIoBase, dwValue) \
876 VNSvOutPortD(dwIoBase + MAC_REG_ISR, dwValue)
878 #define MACvIntEnable(dwIoBase, dwMask) \
879 VNSvOutPortD(dwIoBase + MAC_REG_IMR, dwMask)
881 #define MACvIntDisable(dwIoBase) \
882 VNSvOutPortD(dwIoBase + MAC_REG_IMR, 0)
884 #define MACvSelectPage0(dwIoBase) \
885 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0)
887 #define MACvSelectPage1(dwIoBase) \
888 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1)
890 #define MACvReadMIBCounter(dwIoBase, pdwCounter) \
891 VNSvInPortD(dwIoBase + MAC_REG_MIBCNTR , pdwCounter)
893 #define MACvPwrEvntDisable(dwIoBase) \
894 VNSvOutPortW(dwIoBase + MAC_REG_WAKEUPEN0, 0x0000)
896 #define MACvEnableProtectMD(dwIoBase) \
898 unsigned long dwOrgValue; \
899 VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue); \
900 dwOrgValue = dwOrgValue | EnCFG_ProtectMd; \
901 VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \
904 #define MACvDisableProtectMD(dwIoBase) \
906 unsigned long dwOrgValue; \
907 VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue); \
908 dwOrgValue = dwOrgValue & ~EnCFG_ProtectMd; \
909 VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \
912 #define MACvEnableBarkerPreambleMd(dwIoBase) \
914 unsigned long dwOrgValue; \
915 VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue); \
916 dwOrgValue = dwOrgValue | EnCFG_BarkerPream; \
917 VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \
920 #define MACvDisableBarkerPreambleMd(dwIoBase) \
922 unsigned long dwOrgValue; \
923 VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue); \
924 dwOrgValue = dwOrgValue & ~EnCFG_BarkerPream; \
925 VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \
928 #define MACvSetBBType(dwIoBase, byTyp) \
930 unsigned long dwOrgValue; \
931 VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue); \
932 dwOrgValue = dwOrgValue & ~EnCFG_BBType_MASK; \
933 dwOrgValue = dwOrgValue | (unsigned long)byTyp; \
934 VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \
937 #define MACvReadATIMW(dwIoBase, pwCounter) \
938 VNSvInPortW(dwIoBase + MAC_REG_AIDATIM, pwCounter)
940 #define MACvWriteATIMW(dwIoBase, wCounter) \
941 VNSvOutPortW(dwIoBase + MAC_REG_AIDATIM, wCounter)
943 #define MACvWriteCRC16_128(dwIoBase, byRegOfs, wCRC) \
945 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \
946 VNSvOutPortW(dwIoBase + byRegOfs, wCRC); \
947 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \
950 #define MACvGPIOIn(dwIoBase, pbyValue) \
951 VNSvInPortB(dwIoBase + MAC_REG_GPIOCTL1, pbyValue)
953 #define MACvSetRFLE_LatchBase(dwIoBase) \
954 MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_RFLEOPT)
956 bool MACbIsRegBitsOn(void __iomem *dwIoBase, unsigned char byRegOfs, unsigned char byTestBits);
957 bool MACbIsRegBitsOff(void __iomem *dwIoBase, unsigned char byRegOfs, unsigned char byTestBits);
959 bool MACbIsIntDisable(void __iomem *dwIoBase);
961 void MACvSetShortRetryLimit(void __iomem *dwIoBase, unsigned char byRetryLimit);
963 void MACvSetLongRetryLimit(void __iomem *dwIoBase, unsigned char byRetryLimit);
964 void MACvGetLongRetryLimit(void __iomem *dwIoBase, unsigned char *pbyRetryLimit);
966 void MACvSetLoopbackMode(void __iomem *dwIoBase, unsigned char byLoopbackMode);
968 void MACvSaveContext(void __iomem *dwIoBase, unsigned char *pbyCxtBuf);
969 void MACvRestoreContext(void __iomem *dwIoBase, unsigned char *pbyCxtBuf);
971 bool MACbSoftwareReset(void __iomem *dwIoBase);
972 bool MACbSafeSoftwareReset(void __iomem *dwIoBase);
973 bool MACbSafeRxOff(void __iomem *dwIoBase);
974 bool MACbSafeTxOff(void __iomem *dwIoBase);
975 bool MACbSafeStop(void __iomem *dwIoBase);
976 bool MACbShutdown(void __iomem *dwIoBase);
977 void MACvInitialize(void __iomem *dwIoBase);
978 void MACvSetCurrRx0DescAddr(void __iomem *dwIoBase, unsigned long dwCurrDescAddr);
979 void MACvSetCurrRx1DescAddr(void __iomem *dwIoBase, unsigned long dwCurrDescAddr);
980 void MACvSetCurrTXDescAddr(int iTxType, void __iomem *dwIoBase, unsigned long dwCurrDescAddr);
981 void MACvSetCurrTx0DescAddrEx(void __iomem *dwIoBase, unsigned long dwCurrDescAddr);
982 void MACvSetCurrAC0DescAddrEx(void __iomem *dwIoBase, unsigned long dwCurrDescAddr);
983 void MACvSetCurrSyncDescAddrEx(void __iomem *dwIoBase, unsigned long dwCurrDescAddr);
984 void MACvSetCurrATIMDescAddrEx(void __iomem *dwIoBase, unsigned long dwCurrDescAddr);
985 void MACvTimer0MicroSDelay(void __iomem *dwIoBase, unsigned int uDelay);
986 void MACvOneShotTimer1MicroSec(void __iomem *dwIoBase, unsigned int uDelayTime);
988 void MACvSetMISCFifo(void __iomem *dwIoBase, unsigned short wOffset, unsigned long dwData);
990 bool MACbPSWakeup(void __iomem *dwIoBase);
992 void MACvSetKeyEntry(void __iomem *dwIoBase, unsigned short wKeyCtl, unsigned int uEntryIdx,
993 unsigned int uKeyIdx, unsigned char *pbyAddr, u32 *pdwKey, unsigned char byLocalID);
994 void MACvDisableKeyEntry(void __iomem *dwIoBase, unsigned int uEntryIdx);