1 /* ////////////////////////////////////////////////////////////////////////// */
3 /* Copyright (c) Atmel Corporation. All rights reserved. */
5 /* Module Name: wilc_spi.c */
8 /* //////////////////////////////////////////////////////////////////////////// */
10 #include "wilc_wlan_if.h"
11 #include "wilc_wlan.h"
13 extern unsigned int int_clrd;
16 * #include <linux/kernel.h>
17 * #include <linux/string.h>
21 int (*spi_tx)(uint8_t *, uint32_t);
22 int (*spi_rx)(uint8_t *, uint32_t);
23 int (*spi_trx)(uint8_t *, uint8_t *, uint32_t);
24 int (*spi_max_speed)(void);
25 wilc_debug_func dPrint;
31 static wilc_spi_t g_spi;
33 static int spi_read(uint32_t, uint8_t *, uint32_t);
34 static int spi_write(uint32_t, uint8_t *, uint32_t);
36 /********************************************
40 ********************************************/
42 static const uint8_t crc7_syndrome_table[256] = {
43 0x00, 0x09, 0x12, 0x1b, 0x24, 0x2d, 0x36, 0x3f,
44 0x48, 0x41, 0x5a, 0x53, 0x6c, 0x65, 0x7e, 0x77,
45 0x19, 0x10, 0x0b, 0x02, 0x3d, 0x34, 0x2f, 0x26,
46 0x51, 0x58, 0x43, 0x4a, 0x75, 0x7c, 0x67, 0x6e,
47 0x32, 0x3b, 0x20, 0x29, 0x16, 0x1f, 0x04, 0x0d,
48 0x7a, 0x73, 0x68, 0x61, 0x5e, 0x57, 0x4c, 0x45,
49 0x2b, 0x22, 0x39, 0x30, 0x0f, 0x06, 0x1d, 0x14,
50 0x63, 0x6a, 0x71, 0x78, 0x47, 0x4e, 0x55, 0x5c,
51 0x64, 0x6d, 0x76, 0x7f, 0x40, 0x49, 0x52, 0x5b,
52 0x2c, 0x25, 0x3e, 0x37, 0x08, 0x01, 0x1a, 0x13,
53 0x7d, 0x74, 0x6f, 0x66, 0x59, 0x50, 0x4b, 0x42,
54 0x35, 0x3c, 0x27, 0x2e, 0x11, 0x18, 0x03, 0x0a,
55 0x56, 0x5f, 0x44, 0x4d, 0x72, 0x7b, 0x60, 0x69,
56 0x1e, 0x17, 0x0c, 0x05, 0x3a, 0x33, 0x28, 0x21,
57 0x4f, 0x46, 0x5d, 0x54, 0x6b, 0x62, 0x79, 0x70,
58 0x07, 0x0e, 0x15, 0x1c, 0x23, 0x2a, 0x31, 0x38,
59 0x41, 0x48, 0x53, 0x5a, 0x65, 0x6c, 0x77, 0x7e,
60 0x09, 0x00, 0x1b, 0x12, 0x2d, 0x24, 0x3f, 0x36,
61 0x58, 0x51, 0x4a, 0x43, 0x7c, 0x75, 0x6e, 0x67,
62 0x10, 0x19, 0x02, 0x0b, 0x34, 0x3d, 0x26, 0x2f,
63 0x73, 0x7a, 0x61, 0x68, 0x57, 0x5e, 0x45, 0x4c,
64 0x3b, 0x32, 0x29, 0x20, 0x1f, 0x16, 0x0d, 0x04,
65 0x6a, 0x63, 0x78, 0x71, 0x4e, 0x47, 0x5c, 0x55,
66 0x22, 0x2b, 0x30, 0x39, 0x06, 0x0f, 0x14, 0x1d,
67 0x25, 0x2c, 0x37, 0x3e, 0x01, 0x08, 0x13, 0x1a,
68 0x6d, 0x64, 0x7f, 0x76, 0x49, 0x40, 0x5b, 0x52,
69 0x3c, 0x35, 0x2e, 0x27, 0x18, 0x11, 0x0a, 0x03,
70 0x74, 0x7d, 0x66, 0x6f, 0x50, 0x59, 0x42, 0x4b,
71 0x17, 0x1e, 0x05, 0x0c, 0x33, 0x3a, 0x21, 0x28,
72 0x5f, 0x56, 0x4d, 0x44, 0x7b, 0x72, 0x69, 0x60,
73 0x0e, 0x07, 0x1c, 0x15, 0x2a, 0x23, 0x38, 0x31,
74 0x46, 0x4f, 0x54, 0x5d, 0x62, 0x6b, 0x70, 0x79
77 static uint8_t crc7_byte(uint8_t crc, uint8_t data)
79 return crc7_syndrome_table[(crc << 1) ^ data];
82 static uint8_t crc7(uint8_t crc, const uint8_t *buffer, uint32_t len)
85 crc = crc7_byte(crc, *buffer++);
89 /********************************************
91 * Spi protocol Function
93 ********************************************/
95 #define CMD_DMA_WRITE 0xc1
96 #define CMD_DMA_READ 0xc2
97 #define CMD_INTERNAL_WRITE 0xc3
98 #define CMD_INTERNAL_READ 0xc4
99 #define CMD_TERMINATE 0xc5
100 #define CMD_REPEAT 0xc6
101 #define CMD_DMA_EXT_WRITE 0xc7
102 #define CMD_DMA_EXT_READ 0xc8
103 #define CMD_SINGLE_WRITE 0xc9
104 #define CMD_SINGLE_READ 0xca
105 #define CMD_RESET 0xcf
112 #define DATA_PKT_SZ_256 256
113 #define DATA_PKT_SZ_512 512
114 #define DATA_PKT_SZ_1K 1024
115 #define DATA_PKT_SZ_4K (4 * 1024)
116 #define DATA_PKT_SZ_8K (8 * 1024)
117 #define DATA_PKT_SZ DATA_PKT_SZ_8K
119 static int spi_cmd(uint8_t cmd, uint32_t adr, uint32_t data, uint32_t sz, uint8_t clockless)
127 case CMD_SINGLE_READ: /* single word (4 bytes) read */
128 bc[1] = (uint8_t)(adr >> 16);
129 bc[2] = (uint8_t)(adr >> 8);
130 bc[3] = (uint8_t)adr;
134 case CMD_INTERNAL_READ: /* internal register read */
135 bc[1] = (uint8_t)(adr >> 8);
138 bc[2] = (uint8_t)adr;
143 case CMD_TERMINATE: /* termination */
150 case CMD_REPEAT: /* repeat */
157 case CMD_RESET: /* reset */
164 case CMD_DMA_WRITE: /* dma write */
165 case CMD_DMA_READ: /* dma read */
166 bc[1] = (uint8_t)(adr >> 16);
167 bc[2] = (uint8_t)(adr >> 8);
168 bc[3] = (uint8_t)adr;
169 bc[4] = (uint8_t)(sz >> 8);
170 bc[5] = (uint8_t)(sz);
174 case CMD_DMA_EXT_WRITE: /* dma extended write */
175 case CMD_DMA_EXT_READ: /* dma extended read */
176 bc[1] = (uint8_t)(adr >> 16);
177 bc[2] = (uint8_t)(adr >> 8);
178 bc[3] = (uint8_t)adr;
179 bc[4] = (uint8_t)(sz >> 16);
180 bc[5] = (uint8_t)(sz >> 8);
181 bc[6] = (uint8_t)(sz);
185 case CMD_INTERNAL_WRITE: /* internal register write */
186 bc[1] = (uint8_t)(adr >> 8);
189 bc[2] = (uint8_t)(adr);
190 bc[3] = (uint8_t)(data >> 24);
191 bc[4] = (uint8_t)(data >> 16);
192 bc[5] = (uint8_t)(data >> 8);
193 bc[6] = (uint8_t)(data);
197 case CMD_SINGLE_WRITE: /* single word write */
198 bc[1] = (uint8_t)(adr >> 16);
199 bc[2] = (uint8_t)(adr >> 8);
200 bc[3] = (uint8_t)(adr);
201 bc[4] = (uint8_t)(data >> 24);
202 bc[5] = (uint8_t)(data >> 16);
203 bc[6] = (uint8_t)(data >> 8);
204 bc[7] = (uint8_t)(data);
215 bc[len - 1] = (crc7(0x7f, (const uint8_t *)&bc[0], len - 1)) << 1;
219 if (!g_spi.spi_tx(bc, len)) {
220 PRINT_ER("[wilc spi]: Failed cmd write, bus error...\n");
228 static int spi_cmd_rsp(uint8_t cmd)
234 * Command/Control response
236 if ((cmd == CMD_RESET) ||
237 (cmd == CMD_TERMINATE) ||
238 (cmd == CMD_REPEAT)) {
239 if (!g_spi.spi_rx(&rsp, 1)) {
245 if (!g_spi.spi_rx(&rsp, 1)) {
246 PRINT_ER("[wilc spi]: Failed cmd response read, bus error...\n");
252 PRINT_ER("[wilc spi]: Failed cmd response, cmd (%02x), resp (%02x)\n", cmd, rsp);
260 if (!g_spi.spi_rx(&rsp, 1)) {
261 PRINT_ER("[wilc spi]: Failed cmd state read, bus error...\n");
267 PRINT_ER("[wilc spi]: Failed cmd state response state (%02x)\n", rsp);
276 static int spi_cmd_complete(uint8_t cmd, uint32_t adr, uint8_t *b, uint32_t sz, uint8_t clockless)
278 uint8_t wb[32], rb[32];
287 case CMD_SINGLE_READ: /* single word (4 bytes) read */
288 wb[1] = (uint8_t)(adr >> 16);
289 wb[2] = (uint8_t)(adr >> 8);
290 wb[3] = (uint8_t)adr;
294 case CMD_INTERNAL_READ: /* internal register read */
295 wb[1] = (uint8_t)(adr >> 8);
298 wb[2] = (uint8_t)adr;
303 case CMD_TERMINATE: /* termination */
310 case CMD_REPEAT: /* repeat */
317 case CMD_RESET: /* reset */
324 case CMD_DMA_WRITE: /* dma write */
325 case CMD_DMA_READ: /* dma read */
326 wb[1] = (uint8_t)(adr >> 16);
327 wb[2] = (uint8_t)(adr >> 8);
328 wb[3] = (uint8_t)adr;
329 wb[4] = (uint8_t)(sz >> 8);
330 wb[5] = (uint8_t)(sz);
334 case CMD_DMA_EXT_WRITE: /* dma extended write */
335 case CMD_DMA_EXT_READ: /* dma extended read */
336 wb[1] = (uint8_t)(adr >> 16);
337 wb[2] = (uint8_t)(adr >> 8);
338 wb[3] = (uint8_t)adr;
339 wb[4] = (uint8_t)(sz >> 16);
340 wb[5] = (uint8_t)(sz >> 8);
341 wb[6] = (uint8_t)(sz);
345 case CMD_INTERNAL_WRITE: /* internal register write */
346 wb[1] = (uint8_t)(adr >> 8);
349 wb[2] = (uint8_t)(adr);
357 case CMD_SINGLE_WRITE: /* single word write */
358 wb[1] = (uint8_t)(adr >> 16);
359 wb[2] = (uint8_t)(adr >> 8);
360 wb[3] = (uint8_t)(adr);
373 if (result != N_OK) {
378 wb[len - 1] = (crc7(0x7f, (const uint8_t *)&wb[0], len - 1)) << 1;
382 #define NUM_SKIP_BYTES (1)
383 #define NUM_RSP_BYTES (2)
384 #define NUM_DATA_HDR_BYTES (1)
385 #define NUM_DATA_BYTES (4)
386 #define NUM_CRC_BYTES (2)
387 #define NUM_DUMMY_BYTES (3)
388 if ((cmd == CMD_RESET) ||
389 (cmd == CMD_TERMINATE) ||
390 (cmd == CMD_REPEAT)) {
391 len2 = len + (NUM_SKIP_BYTES + NUM_RSP_BYTES + NUM_DUMMY_BYTES);
392 } else if ((cmd == CMD_INTERNAL_READ) || (cmd == CMD_SINGLE_READ)) {
393 if (!g_spi.crc_off) {
394 len2 = len + (NUM_RSP_BYTES + NUM_DATA_HDR_BYTES + NUM_DATA_BYTES
395 + NUM_CRC_BYTES + NUM_DUMMY_BYTES);
397 len2 = len + (NUM_RSP_BYTES + NUM_DATA_HDR_BYTES + NUM_DATA_BYTES
401 len2 = len + (NUM_RSP_BYTES + NUM_DUMMY_BYTES);
403 #undef NUM_DUMMY_BYTES
405 if (len2 > (sizeof(wb) / sizeof(wb[0]))) {
406 PRINT_ER("[wilc spi]: spi buffer size too small (%d) (%zu)\n",
407 len2, (sizeof(wb) / sizeof(wb[0])));
411 /* zero spi write buffers. */
412 for (wix = len; wix < len2; wix++) {
417 if (!g_spi.spi_trx(wb, rb, len2)) {
418 PRINT_ER("[wilc spi]: Failed cmd write, bus error...\n");
424 * Command/Control response
426 if ((cmd == CMD_RESET) ||
427 (cmd == CMD_TERMINATE) ||
428 (cmd == CMD_REPEAT)) {
429 rix++; /* skip 1 byte */
434 /* if(rsp == cmd) break; */
435 /* } while(&rptr[1] <= &rb[len2]); */
438 PRINT_ER("[wilc spi]: Failed cmd response, cmd (%02x)"
439 ", resp (%02x)\n", cmd, rsp);
449 PRINT_ER("[wilc spi]: Failed cmd state response "
450 "state (%02x)\n", rsp);
455 if ((cmd == CMD_INTERNAL_READ) || (cmd == CMD_SINGLE_READ)
456 || (cmd == CMD_DMA_READ) || (cmd == CMD_DMA_EXT_READ)) {
458 /* uint16_t crc1, crc2; */
461 * Data Respnose header
465 /* ensure there is room in buffer later to read data and crc */
472 if (((rsp >> 4) & 0xf) == 0xf)
477 PRINT_ER("[wilc spi]: Error, data read "
478 "response (%02x)\n", rsp);
483 if ((cmd == CMD_INTERNAL_READ) || (cmd == CMD_SINGLE_READ)) {
487 if ((rix + 3) < len2) {
493 PRINT_ER("[wilc spi]: buffer overrun when reading data.\n");
498 if (!g_spi.crc_off) {
502 if ((rix + 1) < len2) {
506 PRINT_ER("[wilc spi]: buffer overrun when reading crc.\n");
511 } else if ((cmd == CMD_DMA_READ) || (cmd == CMD_DMA_EXT_READ)) {
514 /* some data may be read in response to dummy bytes. */
515 for (ix = 0; (rix < len2) && (ix < sz); ) {
524 if (sz <= (DATA_PKT_SZ - ix))
527 nbytes = DATA_PKT_SZ - ix;
532 if (!g_spi.spi_rx(&b[ix], nbytes)) {
533 PRINT_ER("[wilc spi]: Failed data block read, bus error...\n");
541 if (!g_spi.crc_off) {
542 if (!g_spi.spi_rx(crc, 2)) {
543 PRINT_ER("[wilc spi]: Failed data block crc read, bus error...\n");
554 /* if any data in left unread, then read the rest using normal DMA code.*/
558 if (sz <= DATA_PKT_SZ)
561 nbytes = DATA_PKT_SZ;
564 * read data response only on the next DMA cycles not
565 * the first DMA since data response header is already
566 * handled above for the first DMA.
569 * Data Respnose header
573 if (!g_spi.spi_rx(&rsp, 1)) {
574 PRINT_ER("[wilc spi]: Failed data response read, bus error...\n");
578 if (((rsp >> 4) & 0xf) == 0xf)
582 if (result == N_FAIL)
589 if (!g_spi.spi_rx(&b[ix], nbytes)) {
590 PRINT_ER("[wilc spi]: Failed data block read, bus error...\n");
598 if (!g_spi.crc_off) {
599 if (!g_spi.spi_rx(crc, 2)) {
600 PRINT_ER("[wilc spi]: Failed data block crc read, bus error...\n");
615 static int spi_data_read(uint8_t *b, uint32_t sz)
617 int retry, ix, nbytes;
627 if (sz <= DATA_PKT_SZ)
630 nbytes = DATA_PKT_SZ;
633 * Data Respnose header
637 if (!g_spi.spi_rx(&rsp, 1)) {
638 PRINT_ER("[wilc spi]: Failed data response read, bus error...\n");
642 if (((rsp >> 4) & 0xf) == 0xf)
646 if (result == N_FAIL)
650 PRINT_ER("[wilc spi]: Failed data response read...(%02x)\n", rsp);
658 if (!g_spi.spi_rx(&b[ix], nbytes)) {
659 PRINT_ER("[wilc spi]: Failed data block read, bus error...\n");
667 if (!g_spi.crc_off) {
668 if (!g_spi.spi_rx(crc, 2)) {
669 PRINT_ER("[wilc spi]: Failed data block crc read, bus error...\n");
683 static int spi_data_write(uint8_t *b, uint32_t sz)
687 uint8_t cmd, order, crc[2] = {0};
695 if (sz <= DATA_PKT_SZ)
698 nbytes = DATA_PKT_SZ;
705 if (sz <= DATA_PKT_SZ)
711 if (sz <= DATA_PKT_SZ)
717 if (!g_spi.spi_tx(&cmd, 1)) {
718 PRINT_ER("[wilc spi]: Failed data block cmd write, bus error...\n");
726 if (!g_spi.spi_tx(&b[ix], nbytes)) {
727 PRINT_ER("[wilc spi]: Failed data block write, bus error...\n");
735 if (!g_spi.crc_off) {
736 if (!g_spi.spi_tx(crc, 2)) {
737 PRINT_ER("[wilc spi]: Failed data block crc write, bus error...\n");
744 * No need to wait for response
754 /********************************************
756 * Spi Internal Read/Write Function
758 ********************************************/
760 static int spi_internal_write(uint32_t adr, uint32_t dat)
764 #if defined USE_OLD_SPI_SW
768 result = spi_cmd(CMD_INTERNAL_WRITE, adr, dat, 4, 0);
769 if (result != N_OK) {
770 PRINT_ER("[wilc spi]: Failed internal write cmd...\n");
774 result = spi_cmd_rsp(CMD_INTERNAL_WRITE, 0);
775 if (result != N_OK) {
776 PRINT_ER("[wilc spi]: Failed internal write cmd response...\n");
781 dat = BYTE_SWAP(dat);
783 result = spi_cmd_complete(CMD_INTERNAL_WRITE, adr, (uint8_t *)&dat, 4, 0);
784 if (result != N_OK) {
785 PRINT_ER("[wilc spi]: Failed internal write cmd...\n");
792 static int spi_internal_read(uint32_t adr, uint32_t *data)
796 #if defined USE_OLD_SPI_SW
797 result = spi_cmd(CMD_INTERNAL_READ, adr, 0, 4, 0);
798 if (result != N_OK) {
799 PRINT_ER("[wilc spi]: Failed internal read cmd...\n");
803 result = spi_cmd_rsp(CMD_INTERNAL_READ, 0);
804 if (result != N_OK) {
805 PRINT_ER("[wilc spi]: Failed internal read cmd response...\n");
812 result = spi_data_read((uint8_t *)data, 4);
813 if (result != N_OK) {
814 PRINT_ER("[wilc spi]: Failed internal read data...\n");
818 result = spi_cmd_complete(CMD_INTERNAL_READ, adr, (uint8_t *)data, 4, 0);
819 if (result != N_OK) {
820 PRINT_ER("[wilc spi]: Failed internal read cmd...\n");
827 *data = BYTE_SWAP(*data);
833 /********************************************
837 ********************************************/
839 static int spi_write_reg(uint32_t addr, uint32_t data)
842 uint8_t cmd = CMD_SINGLE_WRITE;
843 uint8_t clockless = 0;
846 #if defined USE_OLD_SPI_SW
848 result = spi_cmd(cmd, addr, data, 4, 0);
849 if (result != N_OK) {
850 PRINT_ER("[wilc spi]: Failed cmd, write reg (%08x)...\n", addr);
854 result = spi_cmd_rsp(cmd, 0);
855 if (result != N_OK) {
856 PRINT_ER("[wilc spi]: Failed cmd response, write reg (%08x)...\n", addr);
864 data = BYTE_SWAP(data);
867 /* Clockless register*/
868 cmd = CMD_INTERNAL_WRITE;
872 result = spi_cmd_complete(cmd, addr, (uint8_t *)&data, 4, clockless);
873 if (result != N_OK) {
874 PRINT_ER("[wilc spi]: Failed cmd, write reg (%08x)...\n", addr);
882 static int spi_write(uint32_t addr, uint8_t *buf, uint32_t size)
885 uint8_t cmd = CMD_DMA_EXT_WRITE;
888 * has to be greated than 4
893 #if defined USE_OLD_SPI_SW
897 result = spi_cmd(cmd, addr, 0, size, 0);
898 if (result != N_OK) {
899 PRINT_ER("[wilc spi]: Failed cmd, write block (%08x)...\n", addr);
903 result = spi_cmd_rsp(cmd, 0);
904 if (result != N_OK) {
905 PRINT_ER("[wilc spi ]: Failed cmd response, write block (%08x)...\n", addr);
909 result = spi_cmd_complete(cmd, addr, NULL, size, 0);
910 if (result != N_OK) {
911 PRINT_ER("[wilc spi]: Failed cmd, write block (%08x)...\n", addr);
919 result = spi_data_write(buf, size);
920 if (result != N_OK) {
921 PRINT_ER("[wilc spi]: Failed block data write...\n");
927 static int spi_read_reg(uint32_t addr, uint32_t *data)
930 uint8_t cmd = CMD_SINGLE_READ;
931 uint8_t clockless = 0;
933 #if defined USE_OLD_SPI_SW
934 result = spi_cmd(cmd, addr, 0, 4, 0);
935 if (result != N_OK) {
936 PRINT_ER("[wilc spi]: Failed cmd, read reg (%08x)...\n", addr);
939 result = spi_cmd_rsp(cmd, 0);
940 if (result != N_OK) {
941 PRINT_ER("[wilc spi]: Failed cmd response, read reg (%08x)...\n", addr);
945 result = spi_data_read((uint8_t *)data, 4);
946 if (result != N_OK) {
947 PRINT_ER("[wilc spi]: Failed data read...\n");
952 /* PRINT_ER("***** read addr %d\n\n", addr); */
953 /* Clockless register*/
954 cmd = CMD_INTERNAL_READ;
958 result = spi_cmd_complete(cmd, addr, (uint8_t *)data, 4, clockless);
959 if (result != N_OK) {
960 PRINT_ER("[wilc spi]: Failed cmd, read reg (%08x)...\n", addr);
967 *data = BYTE_SWAP(*data);
973 static int spi_read(uint32_t addr, uint8_t *buf, uint32_t size)
975 uint8_t cmd = CMD_DMA_EXT_READ;
981 #if defined USE_OLD_SPI_SW
985 result = spi_cmd(cmd, addr, 0, size, 0);
986 if (result != N_OK) {
987 PRINT_ER("[wilc spi]: Failed cmd, read block (%08x)...\n", addr);
991 result = spi_cmd_rsp(cmd, 0);
992 if (result != N_OK) {
993 PRINT_ER("[wilc spi]: Failed cmd response, read block (%08x)...\n", addr);
1000 result = spi_data_read(buf, size);
1001 if (result != N_OK) {
1002 PRINT_ER("[wilc spi]: Failed block data read...\n");
1006 result = spi_cmd_complete(cmd, addr, buf, size, 0);
1007 if (result != N_OK) {
1008 PRINT_ER("[wilc spi]: Failed cmd, read block (%08x)...\n", addr);
1017 /********************************************
1021 ********************************************/
1023 static int spi_clear_int(void)
1026 if (!spi_read_reg(WILC_HOST_RX_CTRL_0, ®)) {
1027 PRINT_ER("[wilc spi]: Failed read reg (%08x)...\n", WILC_HOST_RX_CTRL_0);
1031 spi_write_reg(WILC_HOST_RX_CTRL_0, reg);
1036 static int spi_deinit(void *pv)
1044 static int spi_sync(void)
1050 * interrupt pin mux select
1052 ret = spi_read_reg(WILC_PIN_MUX_0, ®);
1054 PRINT_ER("[wilc spi]: Failed read reg (%08x)...\n", WILC_PIN_MUX_0);
1058 ret = spi_write_reg(WILC_PIN_MUX_0, reg);
1060 PRINT_ER("[wilc spi]: Failed write reg (%08x)...\n", WILC_PIN_MUX_0);
1067 ret = spi_read_reg(WILC_INTR_ENABLE, ®);
1069 PRINT_ER("[wilc spi]: Failed read reg (%08x)...\n", WILC_INTR_ENABLE);
1073 ret = spi_write_reg(WILC_INTR_ENABLE, reg);
1075 PRINT_ER("[wilc spi]: Failed write reg (%08x)...\n", WILC_INTR_ENABLE);
1082 static int spi_init(wilc_wlan_inp_t *inp, wilc_debug_func func)
1091 if (!spi_read_reg(0x1000, &chipid)) {
1092 PRINT_ER("[wilc spi]: Fail cmd read chip id...\n");
1098 memset(&g_spi, 0, sizeof(wilc_spi_t));
1100 g_spi.dPrint = func;
1101 g_spi.os_context = inp->os_context.os_private;
1102 if (inp->io_func.io_init) {
1103 if (!inp->io_func.io_init(g_spi.os_context)) {
1104 PRINT_ER("[wilc spi]: Failed io init bus...\n");
1110 g_spi.spi_tx = inp->io_func.u.spi.spi_tx;
1111 g_spi.spi_rx = inp->io_func.u.spi.spi_rx;
1112 g_spi.spi_trx = inp->io_func.u.spi.spi_trx;
1113 g_spi.spi_max_speed = inp->io_func.u.spi.spi_max_speed;
1116 * configure protocol
1120 /* TODO: We can remove the CRC trials if there is a definite way to reset */
1121 /* the SPI to it's initial value. */
1122 if (!spi_internal_read(WILC_SPI_PROTOCOL_OFFSET, ®)) {
1123 /* Read failed. Try with CRC off. This might happen when module
1124 * is removed but chip isn't reset*/
1126 PRINT_ER("[wilc spi]: Failed internal read protocol with CRC on, retyring with CRC off...\n");
1127 if (!spi_internal_read(WILC_SPI_PROTOCOL_OFFSET, ®)) {
1128 /* Reaad failed with both CRC on and off, something went bad */
1129 PRINT_ER("[wilc spi]: Failed internal read protocol...\n");
1133 if (g_spi.crc_off == 0) {
1134 reg &= ~0xc; /* disable crc checking */
1137 if (!spi_internal_write(WILC_SPI_PROTOCOL_OFFSET, reg)) {
1138 PRINT_ER("[wilc spi %d]: Failed internal write protocol reg...\n", __LINE__);
1146 * make sure can read back chip id correctly
1148 if (!spi_read_reg(0x1000, &chipid)) {
1149 PRINT_ER("[wilc spi]: Fail cmd read chip id...\n");
1152 /* PRINT_ER("[wilc spi]: chipid (%08x)\n", chipid); */
1154 g_spi.has_thrpt_enh = 1;
1161 static void spi_max_bus_speed(void)
1163 g_spi.spi_max_speed();
1166 static void spi_default_bus_speed(void)
1170 static int spi_read_size(uint32_t *size)
1173 if (g_spi.has_thrpt_enh) {
1174 ret = spi_internal_read(0xe840 - WILC_SPI_REG_BASE, size);
1175 *size = *size & IRQ_DMA_WD_CNT_MASK;
1180 ret = spi_read_reg(WILC_VMM_TO_HOST_SIZE, &byte_cnt);
1182 PRINT_ER("[wilc spi]: Failed read WILC_VMM_TO_HOST_SIZE ...\n");
1185 tmp = (byte_cnt >> 2) & IRQ_DMA_WD_CNT_MASK;
1197 static int spi_read_int(uint32_t *int_status)
1200 if (g_spi.has_thrpt_enh) {
1201 ret = spi_internal_read(0xe840 - WILC_SPI_REG_BASE, int_status);
1206 ret = spi_read_reg(WILC_VMM_TO_HOST_SIZE, &byte_cnt);
1208 PRINT_ER("[wilc spi]: Failed read WILC_VMM_TO_HOST_SIZE ...\n");
1211 tmp = (byte_cnt >> 2) & IRQ_DMA_WD_CNT_MASK;
1222 spi_read_reg(0x1a90, &irq_flags);
1223 tmp |= ((irq_flags >> 27) << IRG_FLAGS_OFFSET);
1225 if (g_spi.nint > 5) {
1226 spi_read_reg(0x1a94, &irq_flags);
1227 tmp |= (((irq_flags >> 0) & 0x7) << (IRG_FLAGS_OFFSET + 5));
1231 uint32_t unkmown_mask;
1233 unkmown_mask = ~((1ul << g_spi.nint) - 1);
1235 if ((tmp >> IRG_FLAGS_OFFSET) & unkmown_mask) {
1236 PRINT_ER("[wilc spi]: Unexpected interrupt (2): j=%d, tmp=%x, mask=%x\n", j, tmp, unkmown_mask);
1241 } while (happended);
1252 static int spi_clear_int_ext(uint32_t val)
1256 if (g_spi.has_thrpt_enh) {
1257 ret = spi_internal_write(0xe844 - WILC_SPI_REG_BASE, val);
1260 flags = val & ((1 << MAX_NUM_INT) - 1);
1265 for (i = 0; i < g_spi.nint; i++) {
1266 /* No matter what you write 1 or 0, it will clear interrupt. */
1268 ret = spi_write_reg(0x10c8 + i * 4, 1);
1274 PRINT_ER("[wilc spi]: Failed spi_write_reg, set reg %x ...\n", 0x10c8 + i * 4);
1277 for (i = g_spi.nint; i < MAX_NUM_INT; i++) {
1279 PRINT_ER("[wilc spi]: Unexpected interrupt cleared %d...\n", i);
1288 /* select VMM table 0 */
1289 if ((val & SEL_VMM_TBL0) == SEL_VMM_TBL0)
1290 tbl_ctl |= (1 << 0);
1291 /* select VMM table 1 */
1292 if ((val & SEL_VMM_TBL1) == SEL_VMM_TBL1)
1293 tbl_ctl |= (1 << 1);
1295 ret = spi_write_reg(WILC_VMM_TBL_CTL, tbl_ctl);
1297 PRINT_ER("[wilc spi]: fail write reg vmm_tbl_ctl...\n");
1301 if ((val & EN_VMM) == EN_VMM) {
1303 * enable vmm transfer.
1305 ret = spi_write_reg(WILC_VMM_CORE_CTL, 1);
1307 PRINT_ER("[wilc spi]: fail write reg vmm_core_ctl...\n");
1317 static int spi_sync_ext(int nint /* how mant interrupts to enable. */)
1322 if (nint > MAX_NUM_INT) {
1323 PRINT_ER("[wilc spi]: Too many interupts (%d)...\n", nint);
1330 * interrupt pin mux select
1332 ret = spi_read_reg(WILC_PIN_MUX_0, ®);
1334 PRINT_ER("[wilc spi]: Failed read reg (%08x)...\n", WILC_PIN_MUX_0);
1338 ret = spi_write_reg(WILC_PIN_MUX_0, reg);
1340 PRINT_ER("[wilc spi]: Failed write reg (%08x)...\n", WILC_PIN_MUX_0);
1347 ret = spi_read_reg(WILC_INTR_ENABLE, ®);
1349 PRINT_ER("[wilc spi]: Failed read reg (%08x)...\n", WILC_INTR_ENABLE);
1353 for (i = 0; (i < 5) && (nint > 0); i++, nint--) {
1354 reg |= (1 << (27 + i));
1356 ret = spi_write_reg(WILC_INTR_ENABLE, reg);
1358 PRINT_ER("[wilc spi]: Failed write reg (%08x)...\n", WILC_INTR_ENABLE);
1362 ret = spi_read_reg(WILC_INTR2_ENABLE, ®);
1364 PRINT_ER("[wilc spi]: Failed read reg (%08x)...\n", WILC_INTR2_ENABLE);
1368 for (i = 0; (i < 3) && (nint > 0); i++, nint--) {
1372 ret = spi_read_reg(WILC_INTR2_ENABLE, ®);
1374 PRINT_ER("[wilc spi]: Failed write reg (%08x)...\n", WILC_INTR2_ENABLE);
1381 /********************************************
1383 * Global spi HIF function table
1385 ********************************************/
1386 wilc_hif_func_t hif_spi = {
1402 spi_default_bus_speed,