drivers/staging/xgifb/vb_init.c

   1 #include <linux/types.h>
   2 #include <linux/delay.h> /* udelay */
   3 #include <linux/pci.h>
   4
   5 #include "vgatypes.h"
   6 #include "XGIfb.h"
   7
   8 #include "vb_def.h"
   9 #include "vb_struct.h"
  10 #include "vb_util.h"
  11 #include "vb_setmode.h"
  12 #include "vb_init.h"
  13
  14
  15 #include <linux/io.h>
  16
  17 static const unsigned short XGINew_DDRDRAM_TYPE340[4][5] = {
  18         { 2, 13, 9, 64, 0x45},
  19         { 2, 12, 9, 32, 0x35},
  20         { 2, 12, 8, 16, 0x31},
  21         { 2, 11, 8,  8, 0x21} };
  22
  23 static const unsigned short XGINew_DDRDRAM_TYPE20[12][5] = {
  24         { 2, 14, 11, 128, 0x5D},
  25         { 2, 14, 10, 64, 0x59},
  26         { 2, 13, 11, 64, 0x4D},
  27         { 2, 14,  9, 32, 0x55},
  28         { 2, 13, 10, 32, 0x49},
  29         { 2, 12, 11, 32, 0x3D},
  30         { 2, 14,  8, 16, 0x51},
  31         { 2, 13,  9, 16, 0x45},
  32         { 2, 12, 10, 16, 0x39},
  33         { 2, 13,  8,  8, 0x41},
  34         { 2, 12,  9,  8, 0x35},
  35         { 2, 12,  8,  4, 0x31} };
  36
  37 static unsigned char
  38 XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension,
  39                        struct vb_device_info *pVBInfo)
  40 {
  41         unsigned char data, temp;
  42
  43         if (HwDeviceExtension->jChipType < XG20) {
  44                 if (*pVBInfo->pSoftSetting & SoftDRAMType) {
  45                         data = *pVBInfo->pSoftSetting & 0x07;
  46                         return data;
  47                 } else {
  48                         data = xgifb_reg_get(pVBInfo->P3c4, 0x39) & 0x02;
  49                         if (data == 0)
  50                                 data = (xgifb_reg_get(pVBInfo->P3c4, 0x3A) &
  51                                        0x02) >> 1;
  52                         return data;
  53                 }
  54         } else if (HwDeviceExtension->jChipType == XG27) {
  55                 if (*pVBInfo->pSoftSetting & SoftDRAMType) {
  56                         data = *pVBInfo->pSoftSetting & 0x07;
  57                         return data;
  58                 }
  59                 temp = xgifb_reg_get(pVBInfo->P3c4, 0x3B);
  60                 /* SR3B[7][3]MAA15 MAA11 (Power on Trapping) */
  61                 if ((temp & 0x88) == 0x80)
  62                         data = 0; /* DDR */
  63                 else
  64                         data = 1; /* DDRII */
  65                 return data;
  66         } else if (HwDeviceExtension->jChipType == XG21) {
  67                 /* Independent GPIO control */
  68                 xgifb_reg_and(pVBInfo->P3d4, 0xB4, ~0x02);
  69                 udelay(800);
  70                 xgifb_reg_or(pVBInfo->P3d4, 0x4A, 0x80); /* Enable GPIOH read */
  71                 /* GPIOF 0:DVI 1:DVO */
  72                 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
  73                 /* HOTPLUG_SUPPORT */
  74                 /* for current XG20 & XG21, GPIOH is floating, driver will
  75                  * fix DDR temporarily */
  76                 if (temp & 0x01) /* DVI read GPIOH */
  77                         data = 1; /* DDRII */
  78                 else
  79                         data = 0; /* DDR */
  80                 /* ~HOTPLUG_SUPPORT */
  81                 xgifb_reg_or(pVBInfo->P3d4, 0xB4, 0x02);
  82                 return data;
  83         } else {
  84                 data = xgifb_reg_get(pVBInfo->P3d4, 0x97) & 0x01;
  85
  86                 if (data == 1)
  87                         data++;
  88
  89                 return data;
  90         }
  91 }
  92
  93 static void XGINew_DDR1x_MRS_340(unsigned long P3c4,
  94                                  struct vb_device_info *pVBInfo)
  95 {
  96         xgifb_reg_set(P3c4, 0x18, 0x01);
  97         xgifb_reg_set(P3c4, 0x19, 0x20);
  98         xgifb_reg_set(P3c4, 0x16, 0x00);
  99         xgifb_reg_set(P3c4, 0x16, 0x80);
 100
 101         if (*pVBInfo->pXGINew_DRAMTypeDefinition != 0x0C) { /* Samsung F Die */
 102                 mdelay(3);
 103                 xgifb_reg_set(P3c4, 0x18, 0x00);
 104                 xgifb_reg_set(P3c4, 0x19, 0x20);
 105                 xgifb_reg_set(P3c4, 0x16, 0x00);
 106                 xgifb_reg_set(P3c4, 0x16, 0x80);
 107         }
 108
 109         udelay(60);
 110         xgifb_reg_set(P3c4,
 111                       0x18,
 112                       pVBInfo->SR15[2][pVBInfo->ram_type]); /* SR18 */
 113         xgifb_reg_set(P3c4, 0x19, 0x01);
 114         xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[0]);
 115         xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[1]);
 116         mdelay(1);
 117         xgifb_reg_set(P3c4, 0x1B, 0x03);
 118         udelay(500);
 119         xgifb_reg_set(P3c4,
 120                       0x18,
 121                       pVBInfo->SR15[2][pVBInfo->ram_type]); /* SR18 */
 122         xgifb_reg_set(P3c4, 0x19, 0x00);
 123         xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[2]);
 124         xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[3]);
 125         xgifb_reg_set(P3c4, 0x1B, 0x00);
 126 }
 127
 128 static void XGINew_SetMemoryClock(struct xgi_hw_device_info *HwDeviceExtension,
 129                 struct vb_device_info *pVBInfo)
 130 {
 131
 132         xgifb_reg_set(pVBInfo->P3c4,
 133                       0x28,
 134                       pVBInfo->MCLKData[pVBInfo->ram_type].SR28);
 135         xgifb_reg_set(pVBInfo->P3c4,
 136                       0x29,
 137                       pVBInfo->MCLKData[pVBInfo->ram_type].SR29);
 138         xgifb_reg_set(pVBInfo->P3c4,
 139                       0x2A,
 140                       pVBInfo->MCLKData[pVBInfo->ram_type].SR2A);
 141
 142         xgifb_reg_set(pVBInfo->P3c4,
 143                       0x2E,
 144                       pVBInfo->ECLKData[pVBInfo->ram_type].SR2E);
 145         xgifb_reg_set(pVBInfo->P3c4,
 146                       0x2F,
 147                       pVBInfo->ECLKData[pVBInfo->ram_type].SR2F);
 148         xgifb_reg_set(pVBInfo->P3c4,
 149                       0x30,
 150                       pVBInfo->ECLKData[pVBInfo->ram_type].SR30);
 151
 152         /* [Vicent] 2004/07/07,
 153          * When XG42 ECLK = MCLK = 207MHz, Set SR32 D[1:0] = 10b */
 154         /* [Hsuan] 2004/08/20,
 155          * Modify SR32 value, when MCLK=207MHZ, ELCK=250MHz,
 156          * Set SR32 D[1:0] = 10b */
 157         if (HwDeviceExtension->jChipType == XG42) {
 158                 if ((pVBInfo->MCLKData[pVBInfo->ram_type].SR28 == 0x1C) &&
 159                     (pVBInfo->MCLKData[pVBInfo->ram_type].SR29 == 0x01) &&
 160                     (((pVBInfo->ECLKData[pVBInfo->ram_type].SR2E == 0x1C) &&
 161                       (pVBInfo->ECLKData[pVBInfo->ram_type].SR2F == 0x01)) ||
 162                      ((pVBInfo->ECLKData[pVBInfo->ram_type].SR2E == 0x22) &&
 163                       (pVBInfo->ECLKData[pVBInfo->ram_type].SR2F == 0x01))))
 164                         xgifb_reg_set(pVBInfo->P3c4,
 165                                       0x32,
 166                                       ((unsigned char) xgifb_reg_get(
 167                                           pVBInfo->P3c4, 0x32) & 0xFC) | 0x02);
 168         }
 169 }
 170
 171 static void XGINew_DDRII_Bootup_XG27(
 172                         struct xgi_hw_device_info *HwDeviceExtension,
 173                         unsigned long P3c4, struct vb_device_info *pVBInfo)
 174 {
 175         unsigned long P3d4 = P3c4 + 0x10;
 176         pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
 177         XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
 178
 179         /* Set Double Frequency */
 180         /* xgifb_reg_set(P3d4, 0x97, 0x11); *//* CR97 */
 181         xgifb_reg_set(P3d4, 0x97, *pVBInfo->pXGINew_CR97); /* CR97 */
 182
 183         udelay(200);
 184
 185         xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS2 */
 186         xgifb_reg_set(P3c4, 0x19, 0x80); /* Set SR19 */
 187         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 188         udelay(15);
 189         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 190         udelay(15);
 191
 192         xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS3 */
 193         xgifb_reg_set(P3c4, 0x19, 0xC0); /* Set SR19 */
 194         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 195         udelay(15);
 196         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 197         udelay(15);
 198
 199         xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS1 */
 200         xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
 201         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 202         udelay(30);
 203         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 204         udelay(15);
 205
 206         xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Enable */
 207         xgifb_reg_set(P3c4, 0x19, 0x0A); /* Set SR19 */
 208         xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
 209         udelay(30);
 210         xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
 211         xgifb_reg_set(P3c4, 0x16, 0x80); /* Set SR16 */
 212         /* udelay(15); */
 213
 214         xgifb_reg_set(P3c4, 0x1B, 0x04); /* Set SR1B */
 215         udelay(60);
 216         xgifb_reg_set(P3c4, 0x1B, 0x00); /* Set SR1B */
 217
 218         xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Reset */
 219         xgifb_reg_set(P3c4, 0x19, 0x08); /* Set SR19 */
 220         xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
 221
 222         udelay(30);
 223         xgifb_reg_set(P3c4, 0x16, 0x83); /* Set SR16 */
 224         udelay(15);
 225
 226         xgifb_reg_set(P3c4, 0x18, 0x80); /* Set SR18 */ /* MRS, ODT */
 227         xgifb_reg_set(P3c4, 0x19, 0x46); /* Set SR19 */
 228         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 229         udelay(30);
 230         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 231         udelay(15);
 232
 233         xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS */
 234         xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
 235         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 236         udelay(30);
 237         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 238         udelay(15);
 239
 240         /* Set SR1B refresh control 000:close; 010:open */
 241         xgifb_reg_set(P3c4, 0x1B, 0x04);
 242         udelay(200);
 243
 244 }
 245
 246 static void XGINew_DDR2_MRS_XG20(struct xgi_hw_device_info *HwDeviceExtension,
 247                 unsigned long P3c4, struct vb_device_info *pVBInfo)
 248 {
 249         unsigned long P3d4 = P3c4 + 0x10;
 250
 251         pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
 252         XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
 253
 254         xgifb_reg_set(P3d4, 0x97, 0x11); /* CR97 */
 255
 256         udelay(200);
 257         xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS2 */
 258         xgifb_reg_set(P3c4, 0x19, 0x80);
 259         xgifb_reg_set(P3c4, 0x16, 0x05);
 260         xgifb_reg_set(P3c4, 0x16, 0x85);
 261
 262         xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS3 */
 263         xgifb_reg_set(P3c4, 0x19, 0xC0);
 264         xgifb_reg_set(P3c4, 0x16, 0x05);
 265         xgifb_reg_set(P3c4, 0x16, 0x85);
 266
 267         xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS1 */
 268         xgifb_reg_set(P3c4, 0x19, 0x40);
 269         xgifb_reg_set(P3c4, 0x16, 0x05);
 270         xgifb_reg_set(P3c4, 0x16, 0x85);
 271
 272         /* xgifb_reg_set(P3c4, 0x18, 0x52); */ /* MRS1 */
 273         xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
 274         xgifb_reg_set(P3c4, 0x19, 0x02);
 275         xgifb_reg_set(P3c4, 0x16, 0x05);
 276         xgifb_reg_set(P3c4, 0x16, 0x85);
 277
 278         udelay(15);
 279         xgifb_reg_set(P3c4, 0x1B, 0x04); /* SR1B */
 280         udelay(30);
 281         xgifb_reg_set(P3c4, 0x1B, 0x00); /* SR1B */
 282         udelay(100);
 283
 284         /* xgifb_reg_set(P3c4 ,0x18, 0x52); */ /* MRS2 */
 285         xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
 286         xgifb_reg_set(P3c4, 0x19, 0x00);
 287         xgifb_reg_set(P3c4, 0x16, 0x05);
 288         xgifb_reg_set(P3c4, 0x16, 0x85);
 289
 290         udelay(200);
 291 }
 292
 293 static void XGINew_DDR1x_MRS_XG20(unsigned long P3c4,
 294                                   struct vb_device_info *pVBInfo)
 295 {
 296         xgifb_reg_set(P3c4, 0x18, 0x01);
 297         xgifb_reg_set(P3c4, 0x19, 0x40);
 298         xgifb_reg_set(P3c4, 0x16, 0x00);
 299         xgifb_reg_set(P3c4, 0x16, 0x80);
 300         udelay(60);
 301
 302         xgifb_reg_set(P3c4, 0x18, 0x00);
 303         xgifb_reg_set(P3c4, 0x19, 0x40);
 304         xgifb_reg_set(P3c4, 0x16, 0x00);
 305         xgifb_reg_set(P3c4, 0x16, 0x80);
 306         udelay(60);
 307         xgifb_reg_set(P3c4,
 308                       0x18,
 309                       pVBInfo->SR15[2][pVBInfo->ram_type]); /* SR18 */
 310         /* xgifb_reg_set(P3c4, 0x18, 0x31); */
 311         xgifb_reg_set(P3c4, 0x19, 0x01);
 312         xgifb_reg_set(P3c4, 0x16, 0x03);
 313         xgifb_reg_set(P3c4, 0x16, 0x83);
 314         mdelay(1);
 315         xgifb_reg_set(P3c4, 0x1B, 0x03);
 316         udelay(500);
 317         /* xgifb_reg_set(P3c4, 0x18, 0x31); */
 318         xgifb_reg_set(P3c4,
 319                       0x18,
 320                       pVBInfo->SR15[2][pVBInfo->ram_type]); /* SR18 */
 321         xgifb_reg_set(P3c4, 0x19, 0x00);
 322         xgifb_reg_set(P3c4, 0x16, 0x03);
 323         xgifb_reg_set(P3c4, 0x16, 0x83);
 324         xgifb_reg_set(P3c4, 0x1B, 0x00);
 325 }
 326
 327 static void XGINew_DDR1x_DefaultRegister(
 328                 struct xgi_hw_device_info *HwDeviceExtension,
 329                 unsigned long Port, struct vb_device_info *pVBInfo)
 330 {
 331         unsigned long P3d4 = Port, P3c4 = Port - 0x10;
 332
 333         if (HwDeviceExtension->jChipType >= XG20) {
 334                 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
 335                 xgifb_reg_set(P3d4,
 336                               0x82,
 337                               pVBInfo->CR40[11][pVBInfo->ram_type]); /* CR82 */
 338                 xgifb_reg_set(P3d4,
 339                               0x85,
 340                               pVBInfo->CR40[12][pVBInfo->ram_type]); /* CR85 */
 341                 xgifb_reg_set(P3d4,
 342                               0x86,
 343                               pVBInfo->CR40[13][pVBInfo->ram_type]); /* CR86 */
 344
 345                 xgifb_reg_set(P3d4, 0x98, 0x01);
 346                 xgifb_reg_set(P3d4, 0x9A, 0x02);
 347
 348                 XGINew_DDR1x_MRS_XG20(P3c4, pVBInfo);
 349         } else {
 350                 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
 351
 352                 switch (HwDeviceExtension->jChipType) {
 353                 case XG41:
 354                 case XG42:
 355                         /* CR82 */
 356                         xgifb_reg_set(P3d4,
 357                                       0x82,
 358                                       pVBInfo->CR40[11][pVBInfo->ram_type]);
 359                         /* CR85 */
 360                         xgifb_reg_set(P3d4,
 361                                       0x85,
 362                                       pVBInfo->CR40[12][pVBInfo->ram_type]);
 363                         /* CR86 */
 364                         xgifb_reg_set(P3d4,
 365                                       0x86,
 366                                       pVBInfo->CR40[13][pVBInfo->ram_type]);
 367                         break;
 368                 default:
 369                         xgifb_reg_set(P3d4, 0x82, 0x88);
 370                         xgifb_reg_set(P3d4, 0x86, 0x00);
 371                         /* Insert read command for delay */
 372                         xgifb_reg_get(P3d4, 0x86);
 373                         xgifb_reg_set(P3d4, 0x86, 0x88);
 374                         xgifb_reg_get(P3d4, 0x86);
 375                         xgifb_reg_set(P3d4,
 376                                       0x86,
 377                                       pVBInfo->CR40[13][pVBInfo->ram_type]);
 378                         xgifb_reg_set(P3d4, 0x82, 0x77);
 379                         xgifb_reg_set(P3d4, 0x85, 0x00);
 380
 381                         /* Insert read command for delay */
 382                         xgifb_reg_get(P3d4, 0x85);
 383                         xgifb_reg_set(P3d4, 0x85, 0x88);
 384
 385                         /* Insert read command for delay */
 386                         xgifb_reg_get(P3d4, 0x85);
 387                         /* CR85 */
 388                         xgifb_reg_set(P3d4,
 389                                       0x85,
 390                                       pVBInfo->CR40[12][pVBInfo->ram_type]);
 391                         /* CR82 */
 392                         xgifb_reg_set(P3d4,
 393                                       0x82,
 394                                       pVBInfo->CR40[11][pVBInfo->ram_type]);
 395                         break;
 396                 }
 397
 398                 xgifb_reg_set(P3d4, 0x97, 0x00);
 399                 xgifb_reg_set(P3d4, 0x98, 0x01);
 400                 xgifb_reg_set(P3d4, 0x9A, 0x02);
 401                 XGINew_DDR1x_MRS_340(P3c4, pVBInfo);
 402         }
 403 }
 404
 405 static void XGINew_DDR2_DefaultRegister(
 406                 struct xgi_hw_device_info *HwDeviceExtension,
 407                 unsigned long Port, struct vb_device_info *pVBInfo)
 408 {
 409         unsigned long P3d4 = Port, P3c4 = Port - 0x10;
 410
 411         /* keep following setting sequence, each setting in
 412          * the same reg insert idle */
 413         xgifb_reg_set(P3d4, 0x82, 0x77);
 414         xgifb_reg_set(P3d4, 0x86, 0x00);
 415         xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
 416         xgifb_reg_set(P3d4, 0x86, 0x88);
 417         xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
 418         /* CR86 */
 419         xgifb_reg_set(P3d4, 0x86, pVBInfo->CR40[13][pVBInfo->ram_type]);
 420         xgifb_reg_set(P3d4, 0x82, 0x77);
 421         xgifb_reg_set(P3d4, 0x85, 0x00);
 422         xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
 423         xgifb_reg_set(P3d4, 0x85, 0x88);
 424         xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
 425         xgifb_reg_set(P3d4,
 426                       0x85,
 427                       pVBInfo->CR40[12][pVBInfo->ram_type]); /* CR85 */
 428         if (HwDeviceExtension->jChipType == XG27)
 429                 /* CR82 */
 430                 xgifb_reg_set(P3d4, 0x82, pVBInfo->CR40[11][pVBInfo->ram_type]);
 431         else
 432                 xgifb_reg_set(P3d4, 0x82, 0xA8); /* CR82 */
 433
 434         xgifb_reg_set(P3d4, 0x98, 0x01);
 435         xgifb_reg_set(P3d4, 0x9A, 0x02);
 436         if (HwDeviceExtension->jChipType == XG27)
 437                 XGINew_DDRII_Bootup_XG27(HwDeviceExtension, P3c4, pVBInfo);
 438         else
 439                 XGINew_DDR2_MRS_XG20(HwDeviceExtension, P3c4, pVBInfo);
 440 }
 441
 442 static void XGINew_SetDRAMDefaultRegister340(
 443                 struct xgi_hw_device_info *HwDeviceExtension,
 444                 unsigned long Port, struct vb_device_info *pVBInfo)
 445 {
 446         unsigned char temp, temp1, temp2, temp3, i, j, k;
 447
 448         unsigned long P3d4 = Port, P3c4 = Port - 0x10;
 449
 450         xgifb_reg_set(P3d4, 0x6D, pVBInfo->CR40[8][pVBInfo->ram_type]);
 451         xgifb_reg_set(P3d4, 0x68, pVBInfo->CR40[5][pVBInfo->ram_type]);
 452         xgifb_reg_set(P3d4, 0x69, pVBInfo->CR40[6][pVBInfo->ram_type]);
 453         xgifb_reg_set(P3d4, 0x6A, pVBInfo->CR40[7][pVBInfo->ram_type]);
 454
 455         temp2 = 0;
 456         for (i = 0; i < 4; i++) {
 457                 /* CR6B DQS fine tune delay */
 458                 temp = pVBInfo->CR6B[pVBInfo->ram_type][i];
 459                 for (j = 0; j < 4; j++) {
 460                         temp1 = ((temp >> (2 * j)) & 0x03) << 2;
 461                         temp2 |= temp1;
 462                         xgifb_reg_set(P3d4, 0x6B, temp2);
 463                         /* Insert read command for delay */
 464                         xgifb_reg_get(P3d4, 0x6B);
 465                         temp2 &= 0xF0;
 466                         temp2 += 0x10;
 467                 }
 468         }
 469
 470         temp2 = 0;
 471         for (i = 0; i < 4; i++) {
 472                 /* CR6E DQM fine tune delay */
 473                 temp = pVBInfo->CR6E[pVBInfo->ram_type][i];
 474                 for (j = 0; j < 4; j++) {
 475                         temp1 = ((temp >> (2 * j)) & 0x03) << 2;
 476                         temp2 |= temp1;
 477                         xgifb_reg_set(P3d4, 0x6E, temp2);
 478                         /* Insert read command for delay */
 479                         xgifb_reg_get(P3d4, 0x6E);
 480                         temp2 &= 0xF0;
 481                         temp2 += 0x10;
 482                 }
 483         }
 484
 485         temp3 = 0;
 486         for (k = 0; k < 4; k++) {
 487                 /* CR6E_D[1:0] select channel */
 488                 xgifb_reg_and_or(P3d4, 0x6E, 0xFC, temp3);
 489                 temp2 = 0;
 490                 for (i = 0; i < 8; i++) {
 491                         /* CR6F DQ fine tune delay */
 492                         temp = pVBInfo->CR6F[pVBInfo->ram_type][8 * k + i];
 493                         for (j = 0; j < 4; j++) {
 494                                 temp1 = (temp >> (2 * j)) & 0x03;
 495                                 temp2 |= temp1;
 496                                 xgifb_reg_set(P3d4, 0x6F, temp2);
 497                                 /* Insert read command for delay */
 498                                 xgifb_reg_get(P3d4, 0x6F);
 499                                 temp2 &= 0xF8;
 500                                 temp2 += 0x08;
 501                         }
 502                 }
 503                 temp3 += 0x01;
 504         }
 505
 506         xgifb_reg_set(P3d4,
 507                       0x80,
 508                       pVBInfo->CR40[9][pVBInfo->ram_type]); /* CR80 */
 509         xgifb_reg_set(P3d4,
 510                       0x81,
 511                       pVBInfo->CR40[10][pVBInfo->ram_type]); /* CR81 */
 512
 513         temp2 = 0x80;
 514         /* CR89 terminator type select */
 515         temp = pVBInfo->CR89[pVBInfo->ram_type][0];
 516         for (j = 0; j < 4; j++) {
 517                 temp1 = (temp >> (2 * j)) & 0x03;
 518                 temp2 |= temp1;
 519                 xgifb_reg_set(P3d4, 0x89, temp2);
 520                 xgifb_reg_get(P3d4, 0x89); /* Insert read command for delay */
 521                 temp2 &= 0xF0;
 522                 temp2 += 0x10;
 523         }
 524
 525         temp = pVBInfo->CR89[pVBInfo->ram_type][1];
 526         temp1 = temp & 0x03;
 527         temp2 |= temp1;
 528         xgifb_reg_set(P3d4, 0x89, temp2);
 529
 530         temp = pVBInfo->CR40[3][pVBInfo->ram_type];
 531         temp1 = temp & 0x0F;
 532         temp2 = (temp >> 4) & 0x07;
 533         temp3 = temp & 0x80;
 534         xgifb_reg_set(P3d4, 0x45, temp1); /* CR45 */
 535         xgifb_reg_set(P3d4, 0x99, temp2); /* CR99 */
 536         xgifb_reg_or(P3d4, 0x40, temp3); /* CR40_D[7] */
 537         xgifb_reg_set(P3d4,
 538                       0x41,
 539                       pVBInfo->CR40[0][pVBInfo->ram_type]); /* CR41 */
 540
 541         if (HwDeviceExtension->jChipType == XG27)
 542                 xgifb_reg_set(P3d4, 0x8F, *pVBInfo->pCR8F); /* CR8F */
 543
 544         for (j = 0; j <= 6; j++) /* CR90 - CR96 */
 545                 xgifb_reg_set(P3d4, (0x90 + j),
 546                                 pVBInfo->CR40[14 + j][pVBInfo->ram_type]);
 547
 548         for (j = 0; j <= 2; j++) /* CRC3 - CRC5 */
 549                 xgifb_reg_set(P3d4, (0xC3 + j),
 550                                 pVBInfo->CR40[21 + j][pVBInfo->ram_type]);
 551
 552         for (j = 0; j < 2; j++) /* CR8A - CR8B */
 553                 xgifb_reg_set(P3d4, (0x8A + j),
 554                                 pVBInfo->CR40[1 + j][pVBInfo->ram_type]);
 555
 556         if ((HwDeviceExtension->jChipType == XG41) ||
 557             (HwDeviceExtension->jChipType == XG42))
 558                 xgifb_reg_set(P3d4, 0x8C, 0x87);
 559
 560         xgifb_reg_set(P3d4,
 561                       0x59,
 562                       pVBInfo->CR40[4][pVBInfo->ram_type]); /* CR59 */
 563
 564         xgifb_reg_set(P3d4, 0x83, 0x09); /* CR83 */
 565         xgifb_reg_set(P3d4, 0x87, 0x00); /* CR87 */
 566         xgifb_reg_set(P3d4, 0xCF, *pVBInfo->pCRCF); /* CRCF */
 567         if (pVBInfo->ram_type) {
 568                 /* xgifb_reg_set(P3c4, 0x17, 0xC0); */ /* SR17 DDRII */
 569                 xgifb_reg_set(P3c4, 0x17, 0x80); /* SR17 DDRII */
 570                 if (HwDeviceExtension->jChipType == XG27)
 571                         xgifb_reg_set(P3c4, 0x17, 0x02); /* SR17 DDRII */
 572
 573         } else {
 574                 xgifb_reg_set(P3c4, 0x17, 0x00); /* SR17 DDR */
 575         }
 576         xgifb_reg_set(P3c4, 0x1A, 0x87); /* SR1A */
 577
 578         temp = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
 579         if (temp == 0) {
 580                 XGINew_DDR1x_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
 581         } else {
 582                 xgifb_reg_set(P3d4, 0xB0, 0x80); /* DDRII Dual frequency mode */
 583                 XGINew_DDR2_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
 584         }
 585         xgifb_reg_set(P3c4,
 586                       0x1B,
 587                       pVBInfo->SR15[3][pVBInfo->ram_type]); /* SR1B */
 588 }
 589
 590 static void XGINew_SetDRAMSizingType(int index,
 591                 const unsigned short DRAMTYPE_TABLE[][5],
 592                 struct vb_device_info *pVBInfo)
 593 {
 594         unsigned short data;
 595
 596         data = DRAMTYPE_TABLE[index][4];
 597         xgifb_reg_and_or(pVBInfo->P3c4, 0x13, 0x80, data);
 598         udelay(15);
 599         /* should delay 50 ns */
 600 }
 601
 602 static unsigned short XGINew_SetDRAMSizeReg(int index,
 603                 const unsigned short DRAMTYPE_TABLE[][5],
 604                 struct vb_device_info *pVBInfo)
 605 {
 606         unsigned short data = 0, memsize = 0;
 607         int RankSize;
 608         unsigned char ChannelNo;
 609
 610         RankSize = DRAMTYPE_TABLE[index][3] * pVBInfo->ram_bus / 32;
 611         data = xgifb_reg_get(pVBInfo->P3c4, 0x13);
 612         data &= 0x80;
 613
 614         if (data == 0x80)
 615                 RankSize *= 2;
 616
 617         data = 0;
 618
 619         if (pVBInfo->ram_channel == 3)
 620                 ChannelNo = 4;
 621         else
 622                 ChannelNo = pVBInfo->ram_channel;
 623
 624         if (ChannelNo * RankSize <= 256) {
 625                 while ((RankSize >>= 1) > 0)
 626                         data += 0x10;
 627
 628                 memsize = data >> 4;
 629
 630                 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */
 631                 xgifb_reg_set(pVBInfo->P3c4,
 632                               0x14,
 633                               (xgifb_reg_get(pVBInfo->P3c4, 0x14) & 0x0F) |
 634                                (data & 0xF0));
 635
 636                 /* data |= pVBInfo->ram_channel << 2; */
 637                 /* data |= (pVBInfo->ram_bus / 64) << 1; */
 638                 /* xgifb_reg_set(pVBInfo->P3c4, 0x14, data); */
 639
 640                 /* should delay */
 641                 /* XGINew_SetDRAMModeRegister340(pVBInfo); */
 642         }
 643         return memsize;
 644 }
 645
 646 static unsigned short XGINew_SetDRAMSize20Reg(int index,
 647                 const unsigned short DRAMTYPE_TABLE[][5],
 648                 struct vb_device_info *pVBInfo)
 649 {
 650         unsigned short data = 0, memsize = 0;
 651         int RankSize;
 652         unsigned char ChannelNo;
 653
 654         RankSize = DRAMTYPE_TABLE[index][3] * pVBInfo->ram_bus / 8;
 655         data = xgifb_reg_get(pVBInfo->P3c4, 0x13);
 656         data &= 0x80;
 657
 658         if (data == 0x80)
 659                 RankSize *= 2;
 660
 661         data = 0;
 662
 663         if (pVBInfo->ram_channel == 3)
 664                 ChannelNo = 4;
 665         else
 666                 ChannelNo = pVBInfo->ram_channel;
 667
 668         if (ChannelNo * RankSize <= 256) {
 669                 while ((RankSize >>= 1) > 0)
 670                         data += 0x10;
 671
 672                 memsize = data >> 4;
 673
 674                 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */
 675                 xgifb_reg_set(pVBInfo->P3c4,
 676                               0x14,
 677                               (xgifb_reg_get(pVBInfo->P3c4, 0x14) & 0x0F) |
 678                                 (data & 0xF0));
 679                 udelay(15);
 680
 681                 /* data |= pVBInfo->ram_channel << 2; */
 682                 /* data |= (pVBInfo->ram_bus / 64) << 1; */
 683                 /* xgifb_reg_set(pVBInfo->P3c4, 0x14, data); */
 684
 685                 /* should delay */
 686                 /* XGINew_SetDRAMModeRegister340(pVBInfo); */
 687         }
 688         return memsize;
 689 }
 690
 691 static int XGINew_ReadWriteRest(unsigned short StopAddr,
 692                 unsigned short StartAddr, struct vb_device_info *pVBInfo)
 693 {
 694         int i;
 695         unsigned long Position = 0;
 696         void __iomem *fbaddr = pVBInfo->FBAddr;
 697
 698         writel(Position, fbaddr + Position);
 699
 700         for (i = StartAddr; i <= StopAddr; i++) {
 701                 Position = 1 << i;
 702                 writel(Position, fbaddr + Position);
 703         }
 704
 705         udelay(500); /* [Vicent] 2004/04/16.
 706                         Fix #1759 Memory Size error in Multi-Adapter. */
 707
 708         Position = 0;
 709
 710         if (readl(fbaddr + Position) != Position)
 711                 return 0;
 712
 713         for (i = StartAddr; i <= StopAddr; i++) {
 714                 Position = 1 << i;
 715                 if (readl(fbaddr + Position) != Position)
 716                         return 0;
 717         }
 718         return 1;
 719 }
 720
 721 static unsigned char XGINew_CheckFrequence(struct vb_device_info *pVBInfo)
 722 {
 723         unsigned char data;
 724
 725         data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
 726
 727         if ((data & 0x10) == 0) {
 728                 data = xgifb_reg_get(pVBInfo->P3c4, 0x39);
 729                 data = (data & 0x02) >> 1;
 730                 return data;
 731         } else {
 732                 return data & 0x01;
 733         }
 734 }
 735
 736 static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
 737                 struct vb_device_info *pVBInfo)
 738 {
 739         unsigned char data;
 740
 741         switch (HwDeviceExtension->jChipType) {
 742         case XG20:
 743         case XG21:
 744                 data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
 745                 data = data & 0x01;
 746                 pVBInfo->ram_channel = 1; /* XG20 "JUST" one channel */
 747
 748                 if (data == 0) { /* Single_32_16 */
 749
 750                         if ((HwDeviceExtension->ulVideoMemorySize - 1)
 751                                         > 0x1000000) {
 752
 753                                 pVBInfo->ram_bus = 32; /* 32 bits */
 754                                 /* 22bit + 2 rank + 32bit */
 755                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
 756                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
 757                                 udelay(15);
 758
 759                                 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 760                                         return;
 761
 762                                 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 763                                     0x800000) {
 764                                         /* 22bit + 1 rank + 32bit */
 765                                         xgifb_reg_set(pVBInfo->P3c4,
 766                                                       0x13,
 767                                                       0x31);
 768                                         xgifb_reg_set(pVBInfo->P3c4,
 769                                                       0x14,
 770                                                       0x42);
 771                                         udelay(15);
 772
 773                                         if (XGINew_ReadWriteRest(23,
 774                                                                  23,
 775                                                                  pVBInfo) == 1)
 776                                                 return;
 777                                 }
 778                         }
 779
 780                         if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 781                             0x800000) {
 782                                 pVBInfo->ram_bus = 16; /* 16 bits */
 783                                 /* 22bit + 2 rank + 16bit */
 784                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
 785                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
 786                                 udelay(15);
 787
 788                                 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
 789                                         return;
 790                                 else
 791                                         xgifb_reg_set(pVBInfo->P3c4,
 792                                                       0x13,
 793                                                       0x31);
 794                                 udelay(15);
 795                         }
 796
 797                 } else { /* Dual_16_8 */
 798                         if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 799                             0x800000) {
 800                                 pVBInfo->ram_bus = 16; /* 16 bits */
 801                                 /* (0x31:12x8x2) 22bit + 2 rank */
 802                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
 803                                 /* 0x41:16Mx16 bit*/
 804                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
 805                                 udelay(15);
 806
 807                                 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
 808                                         return;
 809
 810                                 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 811                                     0x400000) {
 812                                         /* (0x31:12x8x2) 22bit + 1 rank */
 813                                         xgifb_reg_set(pVBInfo->P3c4,
 814                                                       0x13,
 815                                                       0x31);
 816                                         /* 0x31:8Mx16 bit*/
 817                                         xgifb_reg_set(pVBInfo->P3c4,
 818                                                       0x14,
 819                                                       0x31);
 820                                         udelay(15);
 821
 822                                         if (XGINew_ReadWriteRest(22,
 823                                                                  22,
 824                                                                  pVBInfo) == 1)
 825                                                 return;
 826                                 }
 827                         }
 828
 829                         if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 830                             0x400000) {
 831                                 pVBInfo->ram_bus = 8; /* 8 bits */
 832                                 /* (0x31:12x8x2) 22bit + 2 rank */
 833                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
 834                                 /* 0x30:8Mx8 bit*/
 835                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
 836                                 udelay(15);
 837
 838                                 if (XGINew_ReadWriteRest(22, 21, pVBInfo) == 1)
 839                                         return;
 840                                 else /* (0x31:12x8x2) 22bit + 1 rank */
 841                                         xgifb_reg_set(pVBInfo->P3c4,
 842                                                       0x13,
 843                                                       0x31);
 844                                 udelay(15);
 845                         }
 846                 }
 847                 break;
 848
 849         case XG27:
 850                 pVBInfo->ram_bus = 16; /* 16 bits */
 851                 pVBInfo->ram_channel = 1; /* Single channel */
 852                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x51); /* 32Mx16 bit*/
 853                 break;
 854         case XG41:
 855                 if (XGINew_CheckFrequence(pVBInfo) == 1) {
 856                         pVBInfo->ram_bus = 32; /* 32 bits */
 857                         pVBInfo->ram_channel = 3; /* Quad Channel */
 858                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 859                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4C);
 860
 861                         if (XGINew_ReadWriteRest(25, 23, pVBInfo) == 1)
 862                                 return;
 863
 864                         pVBInfo->ram_channel = 2; /* Dual channels */
 865                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x48);
 866
 867                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 868                                 return;
 869
 870                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x49);
 871
 872                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 873                                 return;
 874
 875                         pVBInfo->ram_channel = 3;
 876                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 877                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x3C);
 878
 879                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 880                                 return;
 881
 882                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x38);
 883
 884                         if (XGINew_ReadWriteRest(8, 4, pVBInfo) == 1)
 885                                 return;
 886                         else
 887                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x39);
 888                 } else { /* DDR */
 889                         pVBInfo->ram_bus = 64; /* 64 bits */
 890                         pVBInfo->ram_channel = 2; /* Dual channels */
 891                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 892                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x5A);
 893
 894                         if (XGINew_ReadWriteRest(25, 24, pVBInfo) == 1)
 895                                 return;
 896
 897                         pVBInfo->ram_channel = 1; /* Single channels */
 898                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
 899
 900                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 901                                 return;
 902
 903                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x53);
 904
 905                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 906                                 return;
 907
 908                         pVBInfo->ram_channel = 2; /* Dual channels */
 909                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 910                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4A);
 911
 912                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 913                                 return;
 914
 915                         pVBInfo->ram_channel = 1; /* Single channels */
 916                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x42);
 917
 918                         if (XGINew_ReadWriteRest(8, 4, pVBInfo) == 1)
 919                                 return;
 920                         else
 921                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x43);
 922                 }
 923
 924                 break;
 925
 926         case XG42:
 927                 /*
 928                  XG42 SR14 D[3] Reserve
 929                  D[2] = 1, Dual Channel
 930                  = 0, Single Channel
 931
 932                  It's Different from Other XG40 Series.
 933                  */
 934                 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII, DDR2x */
 935                         pVBInfo->ram_bus = 32; /* 32 bits */
 936                         pVBInfo->ram_channel = 2; /* 2 Channel */
 937                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 938                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x44);
 939
 940                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 941                                 return;
 942
 943                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 944                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x34);
 945                         if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
 946                                 return;
 947
 948                         pVBInfo->ram_channel = 1; /* Single Channel */
 949                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 950                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x40);
 951
 952                         if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
 953                                 return;
 954                         else {
 955                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 956                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
 957                         }
 958                 } else { /* DDR */
 959                         pVBInfo->ram_bus = 64; /* 64 bits */
 960                         pVBInfo->ram_channel = 1; /* 1 channels */
 961                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 962                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
 963
 964                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 965                                 return;
 966                         else {
 967                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 968                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x42);
 969                         }
 970                 }
 971
 972                 break;
 973
 974         default: /* XG40 */
 975
 976                 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII */
 977                         pVBInfo->ram_bus = 32; /* 32 bits */
 978                         pVBInfo->ram_channel = 3;
 979                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 980                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4C);
 981
 982                         if (XGINew_ReadWriteRest(25, 23, pVBInfo) == 1)
 983                                 return;
 984
 985                         pVBInfo->ram_channel = 2; /* 2 channels */
 986                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x48);
 987
 988                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 989                                 return;
 990
 991                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 992                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x3C);
 993
 994                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1) {
 995                                 pVBInfo->ram_channel = 3; /* 4 channels */
 996                         } else {
 997                                 pVBInfo->ram_channel = 2; /* 2 channels */
 998                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x38);
 999                         }
1000                 } else { /* DDR */
1001                         pVBInfo->ram_bus = 64; /* 64 bits */
1002                         pVBInfo->ram_channel = 2; /* 2 channels */
1003                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
1004                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x5A);
1005
1006                         if (XGINew_ReadWriteRest(25, 24, pVBInfo) == 1) {
1007                                 return;
1008                         } else {
1009                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
1010                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4A);
1011                         }
1012                 }
1013                 break;
1014         }
1015 }
1016
1017 static int XGINew_DDRSizing340(struct xgi_hw_device_info *HwDeviceExtension,
1018                 struct vb_device_info *pVBInfo)
1019 {
1020         int i;
1021         unsigned short memsize, addr;
1022
1023         xgifb_reg_set(pVBInfo->P3c4, 0x15, 0x00); /* noninterleaving */
1024         xgifb_reg_set(pVBInfo->P3c4, 0x1C, 0x00); /* nontiling */
1025         XGINew_CheckChannel(HwDeviceExtension, pVBInfo);
1026
1027         if (HwDeviceExtension->jChipType >= XG20) {
1028                 for (i = 0; i < 12; i++) {
1029                         XGINew_SetDRAMSizingType(i,
1030                                                  XGINew_DDRDRAM_TYPE20,
1031                                                  pVBInfo);
1032                         memsize = XGINew_SetDRAMSize20Reg(i,
1033                                                           XGINew_DDRDRAM_TYPE20,
1034                                                           pVBInfo);
1035                         if (memsize == 0)
1036                                 continue;
1037
1038                         addr = memsize + (pVBInfo->ram_channel - 2) + 20;
1039                         if ((HwDeviceExtension->ulVideoMemorySize - 1) <
1040                             (unsigned long) (1 << addr))
1041                                 continue;
1042
1043                         if (XGINew_ReadWriteRest(addr, 5, pVBInfo) == 1)
1044                                 return 1;
1045                 }
1046         } else {
1047                 for (i = 0; i < 4; i++) {
1048                         XGINew_SetDRAMSizingType(i,
1049                                                  XGINew_DDRDRAM_TYPE340,
1050                                                  pVBInfo);
1051                         memsize = XGINew_SetDRAMSizeReg(i,
1052                                                         XGINew_DDRDRAM_TYPE340,
1053                                                         pVBInfo);
1054
1055                         if (memsize == 0)
1056                                 continue;
1057
1058                         addr = memsize + (pVBInfo->ram_channel - 2) + 20;
1059                         if ((HwDeviceExtension->ulVideoMemorySize - 1) <
1060                             (unsigned long) (1 << addr))
1061                                 continue;
1062
1063                         if (XGINew_ReadWriteRest(addr, 9, pVBInfo) == 1)
1064                                 return 1;
1065                 }
1066         }
1067         return 0;
1068 }
1069
1070 static void XGINew_SetDRAMSize_340(struct xgi_hw_device_info *HwDeviceExtension,
1071                 struct vb_device_info *pVBInfo)
1072 {
1073         unsigned short data;
1074
1075         pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase;
1076         pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
1077
1078         XGISetModeNew(HwDeviceExtension, 0x2e);
1079
1080         data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
1081         /* disable read cache */
1082         xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short) (data & 0xDF));
1083         XGI_DisplayOff(HwDeviceExtension, pVBInfo);
1084
1085         /* data = xgifb_reg_get(pVBInfo->P3c4, 0x1); */
1086         /* data |= 0x20 ; */
1087         /* xgifb_reg_set(pVBInfo->P3c4, 0x01, data); *//* Turn OFF Display */
1088         XGINew_DDRSizing340(HwDeviceExtension, pVBInfo);
1089         data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
1090         /* enable read cache */
1091         xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short) (data | 0x20));
1092 }
1093
1094 static void ReadVBIOSTablData(unsigned char ChipType,
1095                               struct vb_device_info *pVBInfo)
1096 {
1097         volatile unsigned char *pVideoMemory =
1098                 (unsigned char *) pVBInfo->ROMAddr;
1099         unsigned long i;
1100         unsigned char j, k;
1101         /* Volari customize data area end */
1102
1103         if (ChipType != XG21)
1104                 return;
1105         pVBInfo->IF_DEF_LVDS = 0;
1106         if (!(pVideoMemory[0x65] & 0x1))
1107                 return;
1108         pVBInfo->IF_DEF_LVDS = 1;
1109         i = pVideoMemory[0x316] | (pVideoMemory[0x317] << 8);
1110         j = pVideoMemory[i - 1];
1111         if (j == 0xff)
1112                 j = 1;
1113         k = 0;
1114         do {
1115                 pVBInfo->XG21_LVDSCapList[k].LVDS_Capability
1116                                 = pVideoMemory[i] | (pVideoMemory[i + 1] << 8);
1117                 pVBInfo->XG21_LVDSCapList[k].LVDSHT
1118                                 = pVideoMemory[i + 2] |
1119                                   (pVideoMemory[i + 3] << 8);
1120                 pVBInfo->XG21_LVDSCapList[k].LVDSVT
1121                                 = pVideoMemory[i + 4] |
1122                                   (pVideoMemory[i + 5] << 8);
1123                 pVBInfo->XG21_LVDSCapList[k].LVDSHDE
1124                                 = pVideoMemory[i + 6] |
1125                                   (pVideoMemory[i + 7] << 8);
1126                 pVBInfo->XG21_LVDSCapList[k].LVDSVDE
1127                                 = pVideoMemory[i + 8] |
1128                                   (pVideoMemory[i + 9] << 8);
1129                 pVBInfo->XG21_LVDSCapList[k].LVDSHFP
1130                                 = pVideoMemory[i + 10] |
1131                                   (pVideoMemory[i + 11] << 8);
1132                 pVBInfo->XG21_LVDSCapList[k].LVDSVFP
1133                                 = pVideoMemory[i + 12] |
1134                                   (pVideoMemory[i + 13] << 8);
1135                 pVBInfo->XG21_LVDSCapList[k].LVDSHSYNC
1136                                 = pVideoMemory[i + 14] |
1137                                   (pVideoMemory[i + 15] << 8);
1138                 pVBInfo->XG21_LVDSCapList[k].LVDSVSYNC
1139                                 = pVideoMemory[i + 16] |
1140                                   (pVideoMemory[i + 17] << 8);
1141                 pVBInfo->XG21_LVDSCapList[k].VCLKData1 = pVideoMemory[i + 18];
1142                 pVBInfo->XG21_LVDSCapList[k].VCLKData2 = pVideoMemory[i + 19];
1143                 pVBInfo->XG21_LVDSCapList[k].PSC_S1 = pVideoMemory[i + 20];
1144                 pVBInfo->XG21_LVDSCapList[k].PSC_S2 = pVideoMemory[i + 21];
1145                 pVBInfo->XG21_LVDSCapList[k].PSC_S3 = pVideoMemory[i + 22];
1146                 pVBInfo->XG21_LVDSCapList[k].PSC_S4 = pVideoMemory[i + 23];
1147                 pVBInfo->XG21_LVDSCapList[k].PSC_S5 = pVideoMemory[i + 24];
1148                 i += 25;
1149                 j--;
1150                 k++;
1151         } while (j > 0 && k < ARRAY_SIZE(XGI21_LCDCapList));
1152 }
1153
1154 static void XGINew_ChkSenseStatus(struct xgi_hw_device_info *HwDeviceExtension,
1155                 struct vb_device_info *pVBInfo)
1156 {
1157         unsigned short tempbx = 0, temp, tempcx, CR3CData;
1158
1159         temp = xgifb_reg_get(pVBInfo->P3d4, 0x32);
1160
1161         if (temp & Monitor1Sense)
1162                 tempbx |= ActiveCRT1;
1163         if (temp & LCDSense)
1164                 tempbx |= ActiveLCD;
1165         if (temp & Monitor2Sense)
1166                 tempbx |= ActiveCRT2;
1167         if (temp & TVSense) {
1168                 tempbx |= ActiveTV;
1169                 if (temp & AVIDEOSense)
1170                         tempbx |= (ActiveAVideo << 8);
1171                 if (temp & SVIDEOSense)
1172                         tempbx |= (ActiveSVideo << 8);
1173                 if (temp & SCARTSense)
1174                         tempbx |= (ActiveSCART << 8);
1175                 if (temp & HiTVSense)
1176                         tempbx |= (ActiveHiTV << 8);
1177                 if (temp & YPbPrSense)
1178                         tempbx |= (ActiveYPbPr << 8);
1179         }
1180
1181         tempcx = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
1182         tempcx |= (xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8);
1183
1184         if (tempbx & tempcx) {
1185                 CR3CData = xgifb_reg_get(pVBInfo->P3d4, 0x3c);
1186                 if (!(CR3CData & DisplayDeviceFromCMOS)) {
1187                         tempcx = 0x1FF0;
1188                         if (*pVBInfo->pSoftSetting & ModeSoftSetting)
1189                                 tempbx = 0x1FF0;
1190                 }
1191         } else {
1192                 tempcx = 0x1FF0;
1193                 if (*pVBInfo->pSoftSetting & ModeSoftSetting)
1194                         tempbx = 0x1FF0;
1195         }
1196
1197         tempbx &= tempcx;
1198         xgifb_reg_set(pVBInfo->P3d4, 0x3d, (tempbx & 0x00FF));
1199         xgifb_reg_set(pVBInfo->P3d4, 0x3e, ((tempbx & 0xFF00) >> 8));
1200 }
1201
1202 static void XGINew_SetModeScratch(struct xgi_hw_device_info *HwDeviceExtension,
1203                 struct vb_device_info *pVBInfo)
1204 {
1205         unsigned short temp, tempcl = 0, tempch = 0, CR31Data, CR38Data;
1206
1207         temp = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
1208         temp |= xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8;
1209         temp |= (xgifb_reg_get(pVBInfo->P3d4, 0x31) & (DriverMode >> 8)) << 8;
1210
1211         if (pVBInfo->IF_DEF_CRT2Monitor == 1) {
1212                 if (temp & ActiveCRT2)
1213                         tempcl = SetCRT2ToRAMDAC;
1214         }
1215
1216         if (temp & ActiveLCD) {
1217                 tempcl |= SetCRT2ToLCD;
1218                 if (temp & DriverMode) {
1219                         if (temp & ActiveTV) {
1220                                 tempch = SetToLCDA | EnableDualEdge;
1221                                 temp ^= SetCRT2ToLCD;
1222
1223                                 if ((temp >> 8) & ActiveAVideo)
1224                                         tempcl |= SetCRT2ToAVIDEO;
1225                                 if ((temp >> 8) & ActiveSVideo)
1226                                         tempcl |= SetCRT2ToSVIDEO;
1227                                 if ((temp >> 8) & ActiveSCART)
1228                                         tempcl |= SetCRT2ToSCART;
1229
1230                                 if (pVBInfo->IF_DEF_HiVision == 1) {
1231                                         if ((temp >> 8) & ActiveHiTV)
1232                                                 tempcl |= SetCRT2ToHiVisionTV;
1233                                 }
1234
1235                                 if (pVBInfo->IF_DEF_YPbPr == 1) {
1236                                         if ((temp >> 8) & ActiveYPbPr)
1237                                                 tempch |= SetYPbPr;
1238                                 }
1239                         }
1240                 }
1241         } else {
1242                 if ((temp >> 8) & ActiveAVideo)
1243                         tempcl |= SetCRT2ToAVIDEO;
1244                 if ((temp >> 8) & ActiveSVideo)
1245                         tempcl |= SetCRT2ToSVIDEO;
1246                 if ((temp >> 8) & ActiveSCART)
1247                         tempcl |= SetCRT2ToSCART;
1248
1249                 if (pVBInfo->IF_DEF_HiVision == 1) {
1250                         if ((temp >> 8) & ActiveHiTV)
1251                                 tempcl |= SetCRT2ToHiVisionTV;
1252                 }
1253
1254                 if (pVBInfo->IF_DEF_YPbPr == 1) {
1255                         if ((temp >> 8) & ActiveYPbPr)
1256                                 tempch |= SetYPbPr;
1257                 }
1258         }
1259
1260         tempcl |= SetSimuScanMode;
1261         if ((!(temp & ActiveCRT1)) && ((temp & ActiveLCD) || (temp & ActiveTV)
1262                         || (temp & ActiveCRT2)))
1263                 tempcl ^= (SetSimuScanMode | SwitchToCRT2);
1264         if ((temp & ActiveLCD) && (temp & ActiveTV))
1265                 tempcl ^= (SetSimuScanMode | SwitchToCRT2);
1266         xgifb_reg_set(pVBInfo->P3d4, 0x30, tempcl);
1267
1268         CR31Data = xgifb_reg_get(pVBInfo->P3d4, 0x31);
1269         CR31Data &= ~(SetNotSimuMode >> 8);
1270         if (!(temp & ActiveCRT1))
1271                 CR31Data |= (SetNotSimuMode >> 8);
1272         CR31Data &= ~(DisableCRT2Display >> 8);
1273         if (!((temp & ActiveLCD) || (temp & ActiveTV) || (temp & ActiveCRT2)))
1274                 CR31Data |= (DisableCRT2Display >> 8);
1275         xgifb_reg_set(pVBInfo->P3d4, 0x31, CR31Data);
1276
1277         CR38Data = xgifb_reg_get(pVBInfo->P3d4, 0x38);
1278         CR38Data &= ~SetYPbPr;
1279         CR38Data |= tempch;
1280         xgifb_reg_set(pVBInfo->P3d4, 0x38, CR38Data);
1281
1282 }
1283
1284 static unsigned short XGINew_SenseLCD(struct xgi_hw_device_info
1285                                                         *HwDeviceExtension,
1286                                       struct vb_device_info *pVBInfo)
1287 {
1288         unsigned short temp;
1289
1290         /* add lcd sense */
1291         if (HwDeviceExtension->ulCRT2LCDType == LCD_UNKNOWN) {
1292                 return 0;
1293         } else {
1294                 temp = (unsigned short) HwDeviceExtension->ulCRT2LCDType;
1295                 switch (HwDeviceExtension->ulCRT2LCDType) {
1296                 case LCD_INVALID:
1297                 case LCD_800x600:
1298                 case LCD_1024x768:
1299                 case LCD_1280x1024:
1300                         break;
1301
1302                 case LCD_640x480:
1303                 case LCD_1024x600:
1304                 case LCD_1152x864:
1305                 case LCD_1280x960:
1306                 case LCD_1152x768:
1307                         temp = 0;
1308                         break;
1309
1310                 case LCD_1400x1050:
1311                 case LCD_1280x768:
1312                 case LCD_1600x1200:
1313                         break;
1314
1315                 case LCD_1920x1440:
1316                 case LCD_2048x1536:
1317                         temp = 0;
1318                         break;
1319
1320                 default:
1321                         break;
1322                 }
1323                 xgifb_reg_and_or(pVBInfo->P3d4, 0x36, 0xF0, temp);
1324                 return 1;
1325         }
1326 }
1327
1328 static void XGINew_GetXG21Sense(struct xgi_hw_device_info *HwDeviceExtension,
1329                 struct vb_device_info *pVBInfo)
1330 {
1331         unsigned char Temp;
1332         volatile unsigned char *pVideoMemory =
1333                         (unsigned char *) pVBInfo->ROMAddr;
1334
1335         pVBInfo->IF_DEF_LVDS = 0;
1336
1337 #if 1
1338         if ((pVideoMemory[0x65] & 0x01)) { /* For XG21 LVDS */
1339                 pVBInfo->IF_DEF_LVDS = 1;
1340                 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1341                 /* LVDS on chip */
1342                 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
1343         } else {
1344 #endif
1345                 /* Enable GPIOA/B read  */
1346                 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
1347                 Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0xC0;
1348                 if (Temp == 0xC0) { /* DVI & DVO GPIOA/B pull high */
1349                         XGINew_SenseLCD(HwDeviceExtension, pVBInfo);
1350                         xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1351                         /* Enable read GPIOF */
1352                         xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x20, 0x20);
1353                         Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x04;
1354                         if (!Temp)
1355                                 xgifb_reg_and_or(pVBInfo->P3d4,
1356                                                  0x38,
1357                                                  ~0xE0,
1358                                                  0x80); /* TMDS on chip */
1359                         else
1360                                 xgifb_reg_and_or(pVBInfo->P3d4,
1361                                                  0x38,
1362                                                  ~0xE0,
1363                                                  0xA0); /* Only DVO on chip */
1364                         /* Disable read GPIOF */
1365                         xgifb_reg_and(pVBInfo->P3d4, 0x4A, ~0x20);
1366                 }
1367 #if 1
1368         }
1369 #endif
1370 }
1371
1372 static void XGINew_GetXG27Sense(struct xgi_hw_device_info *HwDeviceExtension,
1373                 struct vb_device_info *pVBInfo)
1374 {
1375         unsigned char Temp, bCR4A;
1376
1377         pVBInfo->IF_DEF_LVDS = 0;
1378         bCR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1379         /* Enable GPIOA/B/C read  */
1380         xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x07, 0x07);
1381         Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x07;
1382         xgifb_reg_set(pVBInfo->P3d4, 0x4A, bCR4A);
1383
1384         if (Temp <= 0x02) {
1385                 pVBInfo->IF_DEF_LVDS = 1;
1386                 /* LVDS setting */
1387                 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
1388                 xgifb_reg_set(pVBInfo->P3d4, 0x30, 0x21);
1389         } else {
1390                 /* TMDS/DVO setting */
1391                 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xA0);
1392         }
1393         xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1394
1395 }
1396
1397 static unsigned char GetXG21FPBits(struct vb_device_info *pVBInfo)
1398 {
1399         unsigned char CR38, CR4A, temp;
1400
1401         CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1402         /* enable GPIOE read */
1403         xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x10, 0x10);
1404         CR38 = xgifb_reg_get(pVBInfo->P3d4, 0x38);
1405         temp = 0;
1406         if ((CR38 & 0xE0) > 0x80) {
1407                 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
1408                 temp &= 0x08;
1409                 temp >>= 3;
1410         }
1411
1412         xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
1413
1414         return temp;
1415 }
1416
1417 static unsigned char GetXG27FPBits(struct vb_device_info *pVBInfo)
1418 {
1419         unsigned char CR4A, temp;
1420
1421         CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1422         /* enable GPIOA/B/C read */
1423         xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
1424         temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
1425         if (temp <= 2)
1426                 temp &= 0x03;
1427         else
1428                 temp = ((temp & 0x04) >> 1) || ((~temp) & 0x01);
1429
1430         xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
1431
1432         return temp;
1433 }
1434
1435 unsigned char XGIInitNew(struct pci_dev *pdev)
1436 {
1437         struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
1438         struct xgi_hw_device_info *HwDeviceExtension = &xgifb_info->hw_info;
1439         struct vb_device_info VBINF;
1440         struct vb_device_info *pVBInfo = &VBINF;
1441         unsigned char i, temp = 0, temp1;
1442         /* VBIOSVersion[5]; */
1443         volatile unsigned char *pVideoMemory;
1444
1445         /* unsigned long j, k; */
1446
1447         pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase;
1448
1449         pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
1450
1451         pVBInfo->BaseAddr = (unsigned long) HwDeviceExtension->pjIOAddress;
1452
1453         pVideoMemory = (unsigned char *) pVBInfo->ROMAddr;
1454
1455         /* Newdebugcode(0x99); */
1456
1457
1458         /* if (pVBInfo->ROMAddr == 0) */
1459         /* return(0); */
1460
1461         if (pVBInfo->FBAddr == NULL) {
1462                 printk("\n pVBInfo->FBAddr == 0 ");
1463                 return 0;
1464         }
1465         printk("1");
1466         if (pVBInfo->BaseAddr == 0) {
1467                 printk("\npVBInfo->BaseAddr == 0 ");
1468                 return 0;
1469         }
1470         printk("2");
1471
1472         outb(0x67, (pVBInfo->BaseAddr + 0x12)); /* 3c2 <- 67 ,ynlai */
1473
1474         pVBInfo->ISXPDOS = 0;
1475         printk("3");
1476
1477         printk("4");
1478
1479         /* VBIOSVersion[4] = 0x0; */
1480
1481         /* 09/07/99 modify by domao */
1482
1483         pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14;
1484         pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24;
1485         pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10;
1486         pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e;
1487         pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12;
1488         pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a;
1489         pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16;
1490         pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17;
1491         pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18;
1492         pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19;
1493         pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A;
1494         pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00;
1495         pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04;
1496         pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10;
1497         pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12;
1498         pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14;
1499         pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2;
1500         printk("5");
1501
1502         if (HwDeviceExtension->jChipType < XG20) /* kuku 2004/06/25 */
1503                 /* Run XGI_GetVBType before InitTo330Pointer */
1504                 XGI_GetVBType(pVBInfo);
1505
1506         InitTo330Pointer(HwDeviceExtension->jChipType, pVBInfo);
1507
1508         /* ReadVBIOSData */
1509         ReadVBIOSTablData(HwDeviceExtension->jChipType, pVBInfo);
1510
1511         /* 1.Openkey */
1512         xgifb_reg_set(pVBInfo->P3c4, 0x05, 0x86);
1513         printk("6");
1514
1515         /* GetXG21Sense (GPIO) */
1516         if (HwDeviceExtension->jChipType == XG21)
1517                 XGINew_GetXG21Sense(HwDeviceExtension, pVBInfo);
1518
1519         if (HwDeviceExtension->jChipType == XG27)
1520                 XGINew_GetXG27Sense(HwDeviceExtension, pVBInfo);
1521
1522         printk("7");
1523
1524         /* 2.Reset Extended register */
1525
1526         for (i = 0x06; i < 0x20; i++)
1527                 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1528
1529         for (i = 0x21; i <= 0x27; i++)
1530                 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1531
1532         /* for(i = 0x06; i <= 0x27; i++) */
1533         /* xgifb_reg_set(pVBInfo->P3c4, i, 0); */
1534
1535         printk("8");
1536
1537         for (i = 0x31; i <= 0x3B; i++)
1538                 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1539         printk("9");
1540
1541         /* [Hsuan] 2004/08/20 Auto over driver for XG42 */
1542         if (HwDeviceExtension->jChipType == XG42)
1543                 xgifb_reg_set(pVBInfo->P3c4, 0x3B, 0xC0);
1544
1545         /* for (i = 0x30; i <= 0x3F; i++) */
1546         /* xgifb_reg_set(pVBInfo->P3d4, i, 0); */
1547
1548         for (i = 0x79; i <= 0x7C; i++)
1549                 xgifb_reg_set(pVBInfo->P3d4, i, 0); /* shampoo 0208 */
1550
1551         printk("10");
1552
1553         if (HwDeviceExtension->jChipType >= XG20)
1554                 xgifb_reg_set(pVBInfo->P3d4, 0x97, *pVBInfo->pXGINew_CR97);
1555
1556         /* 3.SetMemoryClock
1557
1558         pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
1559         */
1560
1561         printk("11");
1562
1563         /* 4.SetDefExt1Regs begin */
1564         xgifb_reg_set(pVBInfo->P3c4, 0x07, *pVBInfo->pSR07);
1565         if (HwDeviceExtension->jChipType == XG27) {
1566                 xgifb_reg_set(pVBInfo->P3c4, 0x40, *pVBInfo->pSR40);
1567                 xgifb_reg_set(pVBInfo->P3c4, 0x41, *pVBInfo->pSR41);
1568         }
1569         xgifb_reg_set(pVBInfo->P3c4, 0x11, 0x0F);
1570         xgifb_reg_set(pVBInfo->P3c4, 0x1F, *pVBInfo->pSR1F);
1571         /* xgifb_reg_set(pVBInfo->P3c4, 0x20, 0x20); */
1572         /* alan, 2001/6/26 Frame buffer can read/write SR20 */
1573         xgifb_reg_set(pVBInfo->P3c4, 0x20, 0xA0);
1574         /* Hsuan, 2006/01/01 H/W request for slow corner chip */
1575         xgifb_reg_set(pVBInfo->P3c4, 0x36, 0x70);
1576         if (HwDeviceExtension->jChipType == XG27) /* Alan 12/07/2006 */
1577                 xgifb_reg_set(pVBInfo->P3c4, 0x36, *pVBInfo->pSR36);
1578
1579         /* SR11 = 0x0F; */
1580         /* xgifb_reg_set(pVBInfo->P3c4, 0x11, SR11); */
1581
1582         printk("12");
1583
1584         if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
1585                 u32 Temp;
1586
1587                 /* Set AGP Rate */
1588                 /*
1589                 temp1 = xgifb_reg_get(pVBInfo->P3c4, 0x3B);
1590                 temp1 &= 0x02;
1591                 if (temp1 == 0x02) {
1592                         outl(0x80000000, 0xcf8);
1593                         ChipsetID = inl(0x0cfc);
1594                         outl(0x8000002C, 0xcf8);
1595                         VendorID = inl(0x0cfc);
1596                         VendorID &= 0x0000FFFF;
1597                         outl(0x8001002C, 0xcf8);
1598                         GraphicVendorID = inl(0x0cfc);
1599                         GraphicVendorID &= 0x0000FFFF;
1600
1601                         if (ChipsetID == 0x7301039)
1602                                 xgifb_reg_set(pVBInfo->P3d4, 0x5F, 0x09);
1603
1604                         ChipsetID &= 0x0000FFFF;
1605
1606                         if ((ChipsetID == 0x700E) ||
1607                             (ChipsetID == 0x1022) ||
1608                             (ChipsetID == 0x1106) ||
1609                             (ChipsetID == 0x10DE)) {
1610                                 if (ChipsetID == 0x1106) {
1611                                         if ((VendorID == 0x1019) &&
1612                                             (GraphicVendorID == 0x1019))
1613                                                 xgifb_reg_set(pVBInfo->P3d4,
1614                                                               0x5F,
1615                                                               0x0D);
1616                                         else
1617                                                 xgifb_reg_set(pVBInfo->P3d4,
1618                                                               0x5F,
1619                                                               0x0B);
1620                                 } else {
1621                                         xgifb_reg_set(pVBInfo->P3d4,
1622                                                       0x5F,
1623                                                       0x0B);
1624                                 }
1625                         }
1626                 }
1627                 */
1628
1629                 printk("13");
1630
1631                 /* Set AGP customize registers (in SetDefAGPRegs) Start */
1632                 for (i = 0x47; i <= 0x4C; i++)
1633                         xgifb_reg_set(pVBInfo->P3d4,
1634                                       i,
1635                                       pVBInfo->AGPReg[i - 0x47]);
1636
1637                 for (i = 0x70; i <= 0x71; i++)
1638                         xgifb_reg_set(pVBInfo->P3d4,
1639                                       i,
1640                                       pVBInfo->AGPReg[6 + i - 0x70]);
1641
1642                 for (i = 0x74; i <= 0x77; i++)
1643                         xgifb_reg_set(pVBInfo->P3d4,
1644                                       i,
1645                                       pVBInfo->AGPReg[8 + i - 0x74]);
1646                 /* Set AGP customize registers (in SetDefAGPRegs) End */
1647                 /* [Hsuan]2004/12/14 AGP Input Delay Adjustment on 850 */
1648                 /*        outl(0x80000000, 0xcf8); */
1649                 /*        ChipsetID = inl(0x0cfc); */
1650                 /*        if (ChipsetID == 0x25308086) */
1651                 /*            xgifb_reg_set(pVBInfo->P3d4, 0x77, 0xF0); */
1652
1653                 pci_read_config_dword(pdev, 0x50, &Temp);
1654                 Temp >>= 20;
1655                 Temp &= 0xF;
1656
1657                 if (Temp == 1)
1658                         xgifb_reg_set(pVBInfo->P3d4, 0x48, 0x20); /* CR48 */
1659                 printk("14");
1660         } /* != XG20 */
1661
1662         /* Set PCI */
1663         xgifb_reg_set(pVBInfo->P3c4, 0x23, *pVBInfo->pSR23);
1664         xgifb_reg_set(pVBInfo->P3c4, 0x24, *pVBInfo->pSR24);
1665         xgifb_reg_set(pVBInfo->P3c4, 0x25, pVBInfo->SR25[0]);
1666         printk("15");
1667
1668         if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
1669                 /* Set VB */
1670                 XGI_UnLockCRT2(HwDeviceExtension, pVBInfo);
1671                 /* alan, disable VideoCapture */
1672                 xgifb_reg_and_or(pVBInfo->Part0Port, 0x3F, 0xEF, 0x00);
1673                 xgifb_reg_set(pVBInfo->Part1Port, 0x00, 0x00);
1674                 /* chk if BCLK>=100MHz */
1675                 temp1 = (unsigned char) xgifb_reg_get(pVBInfo->P3d4, 0x7B);
1676                 temp = (unsigned char) ((temp1 >> 4) & 0x0F);
1677
1678                 xgifb_reg_set(pVBInfo->Part1Port,
1679                               0x02,
1680                               (*pVBInfo->pCRT2Data_1_2));
1681
1682                 printk("16");
1683
1684                 xgifb_reg_set(pVBInfo->Part1Port, 0x2E, 0x08); /* use VB */
1685         } /* != XG20 */
1686
1687         xgifb_reg_set(pVBInfo->P3c4, 0x27, 0x1F);
1688
1689         if ((HwDeviceExtension->jChipType == XG42) &&
1690             XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo) != 0) {
1691                 /* Not DDR */
1692                 xgifb_reg_set(pVBInfo->P3c4,
1693                               0x31,
1694                               (*pVBInfo->pSR31 & 0x3F) | 0x40);
1695                 xgifb_reg_set(pVBInfo->P3c4,
1696                               0x32,
1697                               (*pVBInfo->pSR32 & 0xFC) | 0x01);
1698         } else {
1699                 xgifb_reg_set(pVBInfo->P3c4, 0x31, *pVBInfo->pSR31);
1700                 xgifb_reg_set(pVBInfo->P3c4, 0x32, *pVBInfo->pSR32);
1701         }
1702         xgifb_reg_set(pVBInfo->P3c4, 0x33, *pVBInfo->pSR33);
1703         printk("17");
1704
1705         /*
1706          SetPowerConsume (HwDeviceExtension, pVBInfo->P3c4);    */
1707
1708         if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
1709                 if (XGI_BridgeIsOn(pVBInfo) == 1) {
1710                         if (pVBInfo->IF_DEF_LVDS == 0) {
1711                                 xgifb_reg_set(pVBInfo->Part2Port, 0x00, 0x1C);
1712                                 xgifb_reg_set(pVBInfo->Part4Port,
1713                                               0x0D,
1714                                               *pVBInfo->pCRT2Data_4_D);
1715                                 xgifb_reg_set(pVBInfo->Part4Port,
1716                                               0x0E,
1717                                               *pVBInfo->pCRT2Data_4_E);
1718                                 xgifb_reg_set(pVBInfo->Part4Port,
1719                                               0x10,
1720                                               *pVBInfo->pCRT2Data_4_10);
1721                                 xgifb_reg_set(pVBInfo->Part4Port, 0x0F, 0x3F);
1722                         }
1723
1724                         XGI_LockCRT2(HwDeviceExtension, pVBInfo);
1725                 }
1726         } /* != XG20 */
1727         printk("18");
1728
1729         printk("181");
1730
1731         printk("182");
1732
1733         XGI_SenseCRT1(pVBInfo);
1734
1735         printk("183");
1736         /* XGINew_DetectMonitor(HwDeviceExtension); */
1737         if (HwDeviceExtension->jChipType == XG21) {
1738                 printk("186");
1739
1740                 xgifb_reg_and_or(pVBInfo->P3d4,
1741                                  0x32,
1742                                  ~Monitor1Sense,
1743                                  Monitor1Sense); /* Z9 default has CRT */
1744                 temp = GetXG21FPBits(pVBInfo);
1745                 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x01, temp);
1746                 printk("187");
1747
1748         }
1749         if (HwDeviceExtension->jChipType == XG27) {
1750                 xgifb_reg_and_or(pVBInfo->P3d4,
1751                                  0x32,
1752                                  ~Monitor1Sense,
1753                                  Monitor1Sense); /* Z9 default has CRT */
1754                 temp = GetXG27FPBits(pVBInfo);
1755                 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x03, temp);
1756         }
1757         printk("19");
1758
1759         pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
1760
1761         XGINew_SetDRAMDefaultRegister340(HwDeviceExtension,
1762                                          pVBInfo->P3d4,
1763                                          pVBInfo);
1764
1765         printk("20");
1766         XGINew_SetDRAMSize_340(HwDeviceExtension, pVBInfo);
1767         printk("21");
1768
1769         printk("22");
1770
1771         /* SetDefExt2Regs begin */
1772         /*
1773         AGP = 1;
1774         temp = (unsigned char) xgifb_reg_get(pVBInfo->P3c4, 0x3A);
1775         temp &= 0x30;
1776         if (temp == 0x30)
1777                 AGP = 0;
1778
1779         if (AGP == 0)
1780                 *pVBInfo->pSR21 &= 0xEF;
1781
1782         xgifb_reg_set(pVBInfo->P3c4, 0x21, *pVBInfo->pSR21);
1783         if (AGP == 1)
1784                 *pVBInfo->pSR22 &= 0x20;
1785         xgifb_reg_set(pVBInfo->P3c4, 0x22, *pVBInfo->pSR22);
1786         */
1787         /* base = 0x80000000; */
1788         /* OutPortLong(0xcf8, base); */
1789         /* Temp = (InPortLong(0xcfc) & 0xFFFF); */
1790         /* if (Temp == 0x1039) { */
1791         xgifb_reg_set(pVBInfo->P3c4,
1792                       0x22,
1793                       (unsigned char) ((*pVBInfo->pSR22) & 0xFE));
1794         /* } else { */
1795         /*      xgifb_reg_set(pVBInfo->P3c4, 0x22, *pVBInfo->pSR22); */
1796         /* } */
1797
1798         xgifb_reg_set(pVBInfo->P3c4, 0x21, *pVBInfo->pSR21);
1799
1800         printk("23");
1801
1802         XGINew_ChkSenseStatus(HwDeviceExtension, pVBInfo);
1803         XGINew_SetModeScratch(HwDeviceExtension, pVBInfo);
1804
1805         printk("24");
1806
1807         xgifb_reg_set(pVBInfo->P3d4, 0x8c, 0x87);
1808         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x31);
1809         printk("25");
1810
1811         return 1;
1812 } /* end of init */