2 * exynos_tmu.c - Samsung EXYNOS TMU (Thermal Management Unit)
4 * Copyright (C) 2011 Samsung Electronics
5 * Donggeun Kim <dg77.kim@samsung.com>
6 * Amit Daniel Kachhap <amit.kachhap@linaro.org>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #include <linux/clk.h>
26 #include <linux/interrupt.h>
27 #include <linux/module.h>
29 #include <linux/of_address.h>
30 #include <linux/of_irq.h>
31 #include <linux/platform_device.h>
32 #include <linux/regulator/consumer.h>
34 #include "exynos_thermal_common.h"
35 #include "exynos_tmu.h"
36 #include "exynos_tmu_data.h"
39 * struct exynos_tmu_data : A structure to hold the private data of the TMU
41 * @id: identifier of the one instance of the TMU controller.
42 * @pdata: pointer to the tmu platform/configuration data
43 * @base: base address of the single instance of the TMU controller.
44 * @base_second: base address of the common registers of the TMU controller.
45 * @irq: irq number of the TMU controller.
46 * @soc: id of the SOC type.
47 * @irq_work: pointer to the irq work structure.
48 * @lock: lock to implement synchronization.
49 * @clk: pointer to the clock structure.
50 * @clk_sec: pointer to the clock structure for accessing the base_second.
51 * @temp_error1: fused value of the first point trim.
52 * @temp_error2: fused value of the second point trim.
53 * @regulator: pointer to the TMU regulator structure.
54 * @reg_conf: pointer to structure to register with core thermal.
55 * @tmu_initialize: SoC specific TMU initialization method
57 struct exynos_tmu_data {
59 struct exynos_tmu_platform_data *pdata;
61 void __iomem *base_second;
64 struct work_struct irq_work;
66 struct clk *clk, *clk_sec;
67 u8 temp_error1, temp_error2;
68 struct regulator *regulator;
69 struct thermal_sensor_conf *reg_conf;
70 int (*tmu_initialize)(struct platform_device *pdev);
74 * TMU treats temperature as a mapped temperature code.
75 * The temperature is converted differently depending on the calibration type.
77 static int temp_to_code(struct exynos_tmu_data *data, u8 temp)
79 struct exynos_tmu_platform_data *pdata = data->pdata;
82 switch (pdata->cal_type) {
83 case TYPE_TWO_POINT_TRIMMING:
84 temp_code = (temp - pdata->first_point_trim) *
85 (data->temp_error2 - data->temp_error1) /
86 (pdata->second_point_trim - pdata->first_point_trim) +
89 case TYPE_ONE_POINT_TRIMMING:
90 temp_code = temp + data->temp_error1 - pdata->first_point_trim;
93 temp_code = temp + pdata->default_temp_offset;
101 * Calculate a temperature value from a temperature code.
102 * The unit of the temperature is degree Celsius.
104 static int code_to_temp(struct exynos_tmu_data *data, u8 temp_code)
106 struct exynos_tmu_platform_data *pdata = data->pdata;
109 switch (pdata->cal_type) {
110 case TYPE_TWO_POINT_TRIMMING:
111 temp = (temp_code - data->temp_error1) *
112 (pdata->second_point_trim - pdata->first_point_trim) /
113 (data->temp_error2 - data->temp_error1) +
114 pdata->first_point_trim;
116 case TYPE_ONE_POINT_TRIMMING:
117 temp = temp_code - data->temp_error1 + pdata->first_point_trim;
120 temp = temp_code - pdata->default_temp_offset;
127 static void exynos_tmu_clear_irqs(struct exynos_tmu_data *data)
129 const struct exynos_tmu_registers *reg = data->pdata->registers;
130 unsigned int val_irq;
132 val_irq = readl(data->base + reg->tmu_intstat);
134 * Clear the interrupts. Please note that the documentation for
135 * Exynos3250, Exynos4412, Exynos5250 and Exynos5260 incorrectly
136 * states that INTCLEAR register has a different placing of bits
137 * responsible for FALL IRQs than INTSTAT register. Exynos5420
138 * and Exynos5440 documentation is correct (Exynos4210 doesn't
139 * support FALL IRQs at all).
141 writel(val_irq, data->base + reg->tmu_intclear);
144 static void sanitize_temp_error(struct exynos_tmu_data *data, u32 trim_info)
146 struct exynos_tmu_platform_data *pdata = data->pdata;
148 data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
149 data->temp_error2 = ((trim_info >> EXYNOS_TRIMINFO_85_SHIFT) &
150 EXYNOS_TMU_TEMP_MASK);
152 if (!data->temp_error1 ||
153 (pdata->min_efuse_value > data->temp_error1) ||
154 (data->temp_error1 > pdata->max_efuse_value))
155 data->temp_error1 = pdata->efuse_value & EXYNOS_TMU_TEMP_MASK;
157 if (!data->temp_error2)
159 (pdata->efuse_value >> EXYNOS_TRIMINFO_85_SHIFT) &
160 EXYNOS_TMU_TEMP_MASK;
163 static u32 get_th_reg(struct exynos_tmu_data *data, u32 threshold, bool falling)
165 struct exynos_tmu_platform_data *pdata = data->pdata;
168 for (i = 0; i < pdata->non_hw_trigger_levels; i++) {
169 u8 temp = pdata->trigger_levels[i];
172 temp -= pdata->threshold_falling;
174 threshold &= ~(0xff << 8 * i);
176 threshold |= temp_to_code(data, temp) << 8 * i;
182 static int exynos_tmu_initialize(struct platform_device *pdev)
184 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
187 mutex_lock(&data->lock);
188 clk_enable(data->clk);
189 if (!IS_ERR(data->clk_sec))
190 clk_enable(data->clk_sec);
191 ret = data->tmu_initialize(pdev);
192 clk_disable(data->clk);
193 mutex_unlock(&data->lock);
194 if (!IS_ERR(data->clk_sec))
195 clk_disable(data->clk_sec);
200 static u32 get_con_reg(struct exynos_tmu_data *data, u32 con)
202 struct exynos_tmu_platform_data *pdata = data->pdata;
205 con |= (pdata->test_mux << EXYNOS4412_MUX_ADDR_SHIFT);
207 con &= ~(EXYNOS_TMU_REF_VOLTAGE_MASK << EXYNOS_TMU_REF_VOLTAGE_SHIFT);
208 con |= pdata->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT;
210 con &= ~(EXYNOS_TMU_BUF_SLOPE_SEL_MASK << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT);
211 con |= (pdata->gain << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT);
213 if (pdata->noise_cancel_mode) {
214 con &= ~(EXYNOS_TMU_TRIP_MODE_MASK << EXYNOS_TMU_TRIP_MODE_SHIFT);
215 con |= (pdata->noise_cancel_mode << EXYNOS_TMU_TRIP_MODE_SHIFT);
221 static void exynos_tmu_control(struct platform_device *pdev, bool on)
223 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
224 struct exynos_tmu_platform_data *pdata = data->pdata;
225 const struct exynos_tmu_registers *reg = pdata->registers;
226 unsigned int con, interrupt_en;
228 mutex_lock(&data->lock);
229 clk_enable(data->clk);
231 con = get_con_reg(data, readl(data->base + reg->tmu_ctrl));
234 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT);
236 pdata->trigger_enable[3] << reg->inten_rise3_shift |
237 pdata->trigger_enable[2] << reg->inten_rise2_shift |
238 pdata->trigger_enable[1] << reg->inten_rise1_shift |
239 pdata->trigger_enable[0] << reg->inten_rise0_shift;
240 if (TMU_SUPPORTS(pdata, FALLING_TRIP))
242 interrupt_en << reg->inten_fall0_shift;
244 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT);
245 interrupt_en = 0; /* Disable all interrupts */
247 writel(interrupt_en, data->base + reg->tmu_inten);
248 writel(con, data->base + reg->tmu_ctrl);
250 clk_disable(data->clk);
251 mutex_unlock(&data->lock);
254 static int exynos4210_tmu_initialize(struct platform_device *pdev)
256 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
257 struct exynos_tmu_platform_data *pdata = data->pdata;
259 int ret = 0, threshold_code, i;
261 status = readb(data->base + EXYNOS_TMU_REG_STATUS);
267 sanitize_temp_error(data, readl(data->base + EXYNOS_TMU_REG_TRIMINFO));
269 /* Write temperature code for threshold */
270 threshold_code = temp_to_code(data, pdata->threshold);
271 writeb(threshold_code, data->base + EXYNOS4210_TMU_REG_THRESHOLD_TEMP);
273 for (i = 0; i < pdata->non_hw_trigger_levels; i++)
274 writeb(pdata->trigger_levels[i], data->base +
275 EXYNOS4210_TMU_REG_TRIG_LEVEL0 + i * 4);
277 exynos_tmu_clear_irqs(data);
282 static int exynos4412_tmu_initialize(struct platform_device *pdev)
284 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
285 struct exynos_tmu_platform_data *pdata = data->pdata;
286 unsigned int status, trim_info, con, ctrl, rising_threshold;
287 int ret = 0, threshold_code, i;
289 status = readb(data->base + EXYNOS_TMU_REG_STATUS);
295 if (data->soc == SOC_ARCH_EXYNOS3250 ||
296 data->soc == SOC_ARCH_EXYNOS4412 ||
297 data->soc == SOC_ARCH_EXYNOS5250) {
298 if (data->soc == SOC_ARCH_EXYNOS3250) {
299 ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON1);
300 ctrl |= EXYNOS_TRIMINFO_RELOAD_ENABLE;
301 writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON1);
303 ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON2);
304 ctrl |= EXYNOS_TRIMINFO_RELOAD_ENABLE;
305 writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON2);
308 /* On exynos5420 the triminfo register is in the shared space */
309 if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO)
310 trim_info = readl(data->base_second + EXYNOS_TMU_REG_TRIMINFO);
312 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
314 sanitize_temp_error(data, trim_info);
316 /* Write temperature code for rising and falling threshold */
317 rising_threshold = readl(data->base + EXYNOS_THD_TEMP_RISE);
318 rising_threshold = get_th_reg(data, rising_threshold, false);
319 writel(rising_threshold, data->base + EXYNOS_THD_TEMP_RISE);
320 writel(get_th_reg(data, 0, true), data->base + EXYNOS_THD_TEMP_FALL);
322 exynos_tmu_clear_irqs(data);
324 /* if last threshold limit is also present */
325 i = pdata->max_trigger_level - 1;
326 if (pdata->trigger_levels[i] && pdata->trigger_type[i] == HW_TRIP) {
327 threshold_code = temp_to_code(data, pdata->trigger_levels[i]);
328 /* 1-4 level to be assigned in th0 reg */
329 rising_threshold &= ~(0xff << 8 * i);
330 rising_threshold |= threshold_code << 8 * i;
331 writel(rising_threshold, data->base + EXYNOS_THD_TEMP_RISE);
332 con = readl(data->base + EXYNOS_TMU_REG_CONTROL);
333 con |= (1 << EXYNOS_TMU_THERM_TRIP_EN_SHIFT);
334 writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
340 static int exynos5440_tmu_initialize(struct platform_device *pdev)
342 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
343 struct exynos_tmu_platform_data *pdata = data->pdata;
344 unsigned int trim_info = 0, con, rising_threshold;
345 int ret = 0, threshold_code, i;
348 * For exynos5440 soc triminfo value is swapped between TMU0 and
349 * TMU2, so the below logic is needed.
353 trim_info = readl(data->base + EXYNOS5440_EFUSE_SWAP_OFFSET +
354 EXYNOS5440_TMU_S0_7_TRIM);
357 trim_info = readl(data->base + EXYNOS5440_TMU_S0_7_TRIM);
360 trim_info = readl(data->base - EXYNOS5440_EFUSE_SWAP_OFFSET +
361 EXYNOS5440_TMU_S0_7_TRIM);
363 sanitize_temp_error(data, trim_info);
365 /* Write temperature code for rising and falling threshold */
366 rising_threshold = readl(data->base + EXYNOS5440_TMU_S0_7_TH0);
367 rising_threshold = get_th_reg(data, rising_threshold, false);
368 writel(rising_threshold, data->base + EXYNOS5440_TMU_S0_7_TH0);
369 writel(0, data->base + EXYNOS5440_TMU_S0_7_TH1);
371 exynos_tmu_clear_irqs(data);
373 /* if last threshold limit is also present */
374 i = pdata->max_trigger_level - 1;
375 if (pdata->trigger_levels[i] && pdata->trigger_type[i] == HW_TRIP) {
376 threshold_code = temp_to_code(data, pdata->trigger_levels[i]);
377 /* 5th level to be assigned in th2 reg */
379 threshold_code << EXYNOS5440_TMU_TH_RISE4_SHIFT;
380 writel(rising_threshold, data->base + EXYNOS5440_TMU_S0_7_TH2);
381 con = readl(data->base + EXYNOS5440_TMU_S0_7_CTRL);
382 con |= (1 << EXYNOS_TMU_THERM_TRIP_EN_SHIFT);
383 writel(con, data->base + EXYNOS5440_TMU_S0_7_CTRL);
385 /* Clear the PMIN in the common TMU register */
387 writel(0, data->base_second + EXYNOS5440_TMU_PMIN);
391 static int exynos_tmu_read(struct exynos_tmu_data *data)
393 struct exynos_tmu_platform_data *pdata = data->pdata;
394 const struct exynos_tmu_registers *reg = pdata->registers;
398 mutex_lock(&data->lock);
399 clk_enable(data->clk);
401 temp_code = readb(data->base + reg->tmu_cur_temp);
403 if (data->soc == SOC_ARCH_EXYNOS4210)
404 /* temp_code should range between 75 and 175 */
405 if (temp_code < 75 || temp_code > 175) {
410 temp = code_to_temp(data, temp_code);
412 clk_disable(data->clk);
413 mutex_unlock(&data->lock);
418 #ifdef CONFIG_THERMAL_EMULATION
419 static int exynos_tmu_set_emulation(void *drv_data, unsigned long temp)
421 struct exynos_tmu_data *data = drv_data;
422 struct exynos_tmu_platform_data *pdata = data->pdata;
423 const struct exynos_tmu_registers *reg = pdata->registers;
427 if (!TMU_SUPPORTS(pdata, EMULATION))
430 if (temp && temp < MCELSIUS)
433 mutex_lock(&data->lock);
434 clk_enable(data->clk);
436 val = readl(data->base + reg->emul_con);
441 if (TMU_SUPPORTS(pdata, EMUL_TIME)) {
442 val &= ~(EXYNOS_EMUL_TIME_MASK << EXYNOS_EMUL_TIME_SHIFT);
443 val |= (EXYNOS_EMUL_TIME << EXYNOS_EMUL_TIME_SHIFT);
445 val &= ~(EXYNOS_EMUL_DATA_MASK << EXYNOS_EMUL_DATA_SHIFT);
446 val |= (temp_to_code(data, temp) << EXYNOS_EMUL_DATA_SHIFT) |
449 val &= ~EXYNOS_EMUL_ENABLE;
452 writel(val, data->base + reg->emul_con);
454 clk_disable(data->clk);
455 mutex_unlock(&data->lock);
461 static int exynos_tmu_set_emulation(void *drv_data, unsigned long temp)
463 #endif/*CONFIG_THERMAL_EMULATION*/
465 static void exynos_tmu_work(struct work_struct *work)
467 struct exynos_tmu_data *data = container_of(work,
468 struct exynos_tmu_data, irq_work);
469 unsigned int val_type;
471 if (!IS_ERR(data->clk_sec))
472 clk_enable(data->clk_sec);
473 /* Find which sensor generated this interrupt */
474 if (data->soc == SOC_ARCH_EXYNOS5440) {
475 val_type = readl(data->base_second + EXYNOS5440_TMU_IRQ_STATUS);
476 if (!((val_type >> data->id) & 0x1))
479 if (!IS_ERR(data->clk_sec))
480 clk_disable(data->clk_sec);
482 exynos_report_trigger(data->reg_conf);
483 mutex_lock(&data->lock);
484 clk_enable(data->clk);
486 /* TODO: take action based on particular interrupt */
487 exynos_tmu_clear_irqs(data);
489 clk_disable(data->clk);
490 mutex_unlock(&data->lock);
492 enable_irq(data->irq);
495 static irqreturn_t exynos_tmu_irq(int irq, void *id)
497 struct exynos_tmu_data *data = id;
499 disable_irq_nosync(irq);
500 schedule_work(&data->irq_work);
505 static const struct of_device_id exynos_tmu_match[] = {
507 .compatible = "samsung,exynos3250-tmu",
508 .data = (void *)EXYNOS3250_TMU_DRV_DATA,
511 .compatible = "samsung,exynos4210-tmu",
512 .data = (void *)EXYNOS4210_TMU_DRV_DATA,
515 .compatible = "samsung,exynos4412-tmu",
516 .data = (void *)EXYNOS4412_TMU_DRV_DATA,
519 .compatible = "samsung,exynos5250-tmu",
520 .data = (void *)EXYNOS5250_TMU_DRV_DATA,
523 .compatible = "samsung,exynos5260-tmu",
524 .data = (void *)EXYNOS5260_TMU_DRV_DATA,
527 .compatible = "samsung,exynos5420-tmu",
528 .data = (void *)EXYNOS5420_TMU_DRV_DATA,
531 .compatible = "samsung,exynos5420-tmu-ext-triminfo",
532 .data = (void *)EXYNOS5420_TMU_DRV_DATA,
535 .compatible = "samsung,exynos5440-tmu",
536 .data = (void *)EXYNOS5440_TMU_DRV_DATA,
540 MODULE_DEVICE_TABLE(of, exynos_tmu_match);
542 static inline struct exynos_tmu_platform_data *exynos_get_driver_data(
543 struct platform_device *pdev, int id)
545 struct exynos_tmu_init_data *data_table;
546 struct exynos_tmu_platform_data *tmu_data;
547 const struct of_device_id *match;
549 match = of_match_node(exynos_tmu_match, pdev->dev.of_node);
552 data_table = (struct exynos_tmu_init_data *) match->data;
553 if (!data_table || id >= data_table->tmu_count)
555 tmu_data = data_table->tmu_data;
556 return (struct exynos_tmu_platform_data *) (tmu_data + id);
559 static int exynos_map_dt_data(struct platform_device *pdev)
561 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
562 struct exynos_tmu_platform_data *pdata;
566 if (!data || !pdev->dev.of_node)
570 * Try enabling the regulator if found
571 * TODO: Add regulator as an SOC feature, so that regulator enable
572 * is a compulsory call.
574 data->regulator = devm_regulator_get(&pdev->dev, "vtmu");
575 if (!IS_ERR(data->regulator)) {
576 ret = regulator_enable(data->regulator);
578 dev_err(&pdev->dev, "failed to enable vtmu\n");
582 dev_info(&pdev->dev, "Regulator node (vtmu) not found\n");
585 data->id = of_alias_get_id(pdev->dev.of_node, "tmuctrl");
589 data->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
590 if (data->irq <= 0) {
591 dev_err(&pdev->dev, "failed to get IRQ\n");
595 if (of_address_to_resource(pdev->dev.of_node, 0, &res)) {
596 dev_err(&pdev->dev, "failed to get Resource 0\n");
600 data->base = devm_ioremap(&pdev->dev, res.start, resource_size(&res));
602 dev_err(&pdev->dev, "Failed to ioremap memory\n");
603 return -EADDRNOTAVAIL;
606 pdata = exynos_get_driver_data(pdev, data->id);
608 dev_err(&pdev->dev, "No platform init data supplied.\n");
613 * Check if the TMU shares some registers and then try to map the
614 * memory of common registers.
616 if (!TMU_SUPPORTS(pdata, ADDRESS_MULTIPLE))
619 if (of_address_to_resource(pdev->dev.of_node, 1, &res)) {
620 dev_err(&pdev->dev, "failed to get Resource 1\n");
624 data->base_second = devm_ioremap(&pdev->dev, res.start,
625 resource_size(&res));
626 if (!data->base_second) {
627 dev_err(&pdev->dev, "Failed to ioremap memory\n");
634 static int exynos_tmu_probe(struct platform_device *pdev)
636 struct exynos_tmu_data *data;
637 struct exynos_tmu_platform_data *pdata;
638 struct thermal_sensor_conf *sensor_conf;
641 data = devm_kzalloc(&pdev->dev, sizeof(struct exynos_tmu_data),
646 platform_set_drvdata(pdev, data);
647 mutex_init(&data->lock);
649 ret = exynos_map_dt_data(pdev);
655 INIT_WORK(&data->irq_work, exynos_tmu_work);
657 data->clk = devm_clk_get(&pdev->dev, "tmu_apbif");
658 if (IS_ERR(data->clk)) {
659 dev_err(&pdev->dev, "Failed to get clock\n");
660 return PTR_ERR(data->clk);
663 data->clk_sec = devm_clk_get(&pdev->dev, "tmu_triminfo_apbif");
664 if (IS_ERR(data->clk_sec)) {
665 if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO) {
666 dev_err(&pdev->dev, "Failed to get triminfo clock\n");
667 return PTR_ERR(data->clk_sec);
670 ret = clk_prepare(data->clk_sec);
672 dev_err(&pdev->dev, "Failed to get clock\n");
677 ret = clk_prepare(data->clk);
679 dev_err(&pdev->dev, "Failed to get clock\n");
683 data->soc = pdata->type;
686 case SOC_ARCH_EXYNOS4210:
687 data->tmu_initialize = exynos4210_tmu_initialize;
689 case SOC_ARCH_EXYNOS3250:
690 case SOC_ARCH_EXYNOS4412:
691 case SOC_ARCH_EXYNOS5250:
692 case SOC_ARCH_EXYNOS5260:
693 case SOC_ARCH_EXYNOS5420:
694 case SOC_ARCH_EXYNOS5420_TRIMINFO:
695 data->tmu_initialize = exynos4412_tmu_initialize;
697 case SOC_ARCH_EXYNOS5440:
698 data->tmu_initialize = exynos5440_tmu_initialize;
702 dev_err(&pdev->dev, "Platform not supported\n");
706 ret = exynos_tmu_initialize(pdev);
708 dev_err(&pdev->dev, "Failed to initialize TMU\n");
712 exynos_tmu_control(pdev, true);
714 /* Allocate a structure to register with the exynos core thermal */
715 sensor_conf = devm_kzalloc(&pdev->dev,
716 sizeof(struct thermal_sensor_conf), GFP_KERNEL);
721 sprintf(sensor_conf->name, "therm_zone%d", data->id);
722 sensor_conf->read_temperature = (int (*)(void *))exynos_tmu_read;
723 sensor_conf->write_emul_temp =
724 (int (*)(void *, unsigned long))exynos_tmu_set_emulation;
725 sensor_conf->driver_data = data;
726 sensor_conf->trip_data.trip_count = pdata->trigger_enable[0] +
727 pdata->trigger_enable[1] + pdata->trigger_enable[2]+
728 pdata->trigger_enable[3];
730 for (i = 0; i < sensor_conf->trip_data.trip_count; i++) {
731 sensor_conf->trip_data.trip_val[i] =
732 pdata->threshold + pdata->trigger_levels[i];
733 sensor_conf->trip_data.trip_type[i] =
734 pdata->trigger_type[i];
737 sensor_conf->trip_data.trigger_falling = pdata->threshold_falling;
739 sensor_conf->cooling_data.freq_clip_count = pdata->freq_tab_count;
740 for (i = 0; i < pdata->freq_tab_count; i++) {
741 sensor_conf->cooling_data.freq_data[i].freq_clip_max =
742 pdata->freq_tab[i].freq_clip_max;
743 sensor_conf->cooling_data.freq_data[i].temp_level =
744 pdata->freq_tab[i].temp_level;
746 sensor_conf->dev = &pdev->dev;
747 /* Register the sensor with thermal management interface */
748 ret = exynos_register_thermal(sensor_conf);
750 dev_err(&pdev->dev, "Failed to register thermal interface\n");
753 data->reg_conf = sensor_conf;
755 ret = devm_request_irq(&pdev->dev, data->irq, exynos_tmu_irq,
756 IRQF_TRIGGER_RISING | IRQF_SHARED, dev_name(&pdev->dev), data);
758 dev_err(&pdev->dev, "Failed to request irq: %d\n", data->irq);
764 clk_unprepare(data->clk);
766 if (!IS_ERR(data->clk_sec))
767 clk_unprepare(data->clk_sec);
771 static int exynos_tmu_remove(struct platform_device *pdev)
773 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
775 exynos_unregister_thermal(data->reg_conf);
777 exynos_tmu_control(pdev, false);
779 clk_unprepare(data->clk);
780 if (!IS_ERR(data->clk_sec))
781 clk_unprepare(data->clk_sec);
783 if (!IS_ERR(data->regulator))
784 regulator_disable(data->regulator);
789 #ifdef CONFIG_PM_SLEEP
790 static int exynos_tmu_suspend(struct device *dev)
792 exynos_tmu_control(to_platform_device(dev), false);
797 static int exynos_tmu_resume(struct device *dev)
799 struct platform_device *pdev = to_platform_device(dev);
801 exynos_tmu_initialize(pdev);
802 exynos_tmu_control(pdev, true);
807 static SIMPLE_DEV_PM_OPS(exynos_tmu_pm,
808 exynos_tmu_suspend, exynos_tmu_resume);
809 #define EXYNOS_TMU_PM (&exynos_tmu_pm)
811 #define EXYNOS_TMU_PM NULL
814 static struct platform_driver exynos_tmu_driver = {
816 .name = "exynos-tmu",
817 .owner = THIS_MODULE,
819 .of_match_table = exynos_tmu_match,
821 .probe = exynos_tmu_probe,
822 .remove = exynos_tmu_remove,
825 module_platform_driver(exynos_tmu_driver);
827 MODULE_DESCRIPTION("EXYNOS TMU Driver");
828 MODULE_AUTHOR("Donggeun Kim <dg77.kim@samsung.com>");
829 MODULE_LICENSE("GPL");
830 MODULE_ALIAS("platform:exynos-tmu");