drivers/thermal/samsung/exynos_tmu_data.c

   1 /*
   2  * exynos_tmu_data.c - Samsung EXYNOS tmu data file
   3  *
   4  *  Copyright (C) 2013 Samsung Electronics
   5  *  Amit Daniel Kachhap <amit.daniel@samsung.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  *
  21  */
  22
  23 #include "exynos_thermal_common.h"
  24 #include "exynos_tmu.h"
  25 #include "exynos_tmu_data.h"
  26
  27 #if defined(CONFIG_CPU_EXYNOS4210)
  28 static const struct exynos_tmu_registers exynos4210_tmu_registers = {
  29         .triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
  30         .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
  31         .tmu_status = EXYNOS_TMU_REG_STATUS,
  32         .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
  33         .threshold_temp = EXYNOS4210_TMU_REG_THRESHOLD_TEMP,
  34         .threshold_th0 = EXYNOS4210_TMU_REG_TRIG_LEVEL0,
  35         .tmu_inten = EXYNOS_TMU_REG_INTEN,
  36         .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
  37         .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
  38         .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
  39         .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
  40         .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
  41         .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
  42         .intclr_rise_mask = EXYNOS4210_TMU_TRIG_LEVEL_MASK,
  43 };
  44
  45 struct exynos_tmu_init_data const exynos4210_default_tmu_data = {
  46         .tmu_data = {
  47                 {
  48                 .threshold = 80,
  49                 .trigger_levels[0] = 5,
  50                 .trigger_levels[1] = 20,
  51                 .trigger_levels[2] = 30,
  52                 .trigger_enable[0] = true,
  53                 .trigger_enable[1] = true,
  54                 .trigger_enable[2] = true,
  55                 .trigger_enable[3] = false,
  56                 .trigger_type[0] = THROTTLE_ACTIVE,
  57                 .trigger_type[1] = THROTTLE_ACTIVE,
  58                 .trigger_type[2] = SW_TRIP,
  59                 .max_trigger_level = 4,
  60                 .non_hw_trigger_levels = 3,
  61                 .gain = 15,
  62                 .reference_voltage = 7,
  63                 .cal_type = TYPE_ONE_POINT_TRIMMING,
  64                 .min_efuse_value = 40,
  65                 .max_efuse_value = 100,
  66                 .first_point_trim = 25,
  67                 .second_point_trim = 85,
  68                 .default_temp_offset = 50,
  69                 .freq_tab[0] = {
  70                         .freq_clip_max = 800 * 1000,
  71                         .temp_level = 85,
  72                         },
  73                 .freq_tab[1] = {
  74                         .freq_clip_max = 200 * 1000,
  75                         .temp_level = 100,
  76                 },
  77                 .freq_tab_count = 2,
  78                 .type = SOC_ARCH_EXYNOS4210,
  79                 .registers = &exynos4210_tmu_registers,
  80                 .features = TMU_SUPPORT_READY_STATUS,
  81                 },
  82         },
  83         .tmu_count = 1,
  84 };
  85 #endif
  86
  87 #if defined(CONFIG_SOC_EXYNOS3250)
  88 static const struct exynos_tmu_registers exynos3250_tmu_registers = {
  89         .triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
  90         .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
  91         .test_mux_addr_shift = EXYNOS4412_MUX_ADDR_SHIFT,
  92         .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
  93         .therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
  94         .therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
  95         .tmu_status = EXYNOS_TMU_REG_STATUS,
  96         .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
  97         .threshold_th0 = EXYNOS_THD_TEMP_RISE,
  98         .threshold_th1 = EXYNOS_THD_TEMP_FALL,
  99         .tmu_inten = EXYNOS_TMU_REG_INTEN,
 100         .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
 101         .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
 102         .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
 103         .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
 104         .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
 105         .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
 106         .intclr_fall_shift = EXYNOS_TMU_CLEAR_FALL_INT_SHIFT,
 107         .intclr_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
 108         .intclr_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
 109         .intclr_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
 110         .emul_con = EXYNOS_EMUL_CON,
 111         .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
 112         .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
 113 };
 114
 115 #define EXYNOS3250_TMU_DATA \
 116         .threshold_falling = 10, \
 117         .trigger_levels[0] = 70, \
 118         .trigger_levels[1] = 95, \
 119         .trigger_levels[2] = 110, \
 120         .trigger_levels[3] = 120, \
 121         .trigger_enable[0] = true, \
 122         .trigger_enable[1] = true, \
 123         .trigger_enable[2] = true, \
 124         .trigger_enable[3] = false, \
 125         .trigger_type[0] = THROTTLE_ACTIVE, \
 126         .trigger_type[1] = THROTTLE_ACTIVE, \
 127         .trigger_type[2] = SW_TRIP, \
 128         .trigger_type[3] = HW_TRIP, \
 129         .max_trigger_level = 4, \
 130         .non_hw_trigger_levels = 3, \
 131         .gain = 8, \
 132         .reference_voltage = 16, \
 133         .noise_cancel_mode = 4, \
 134         .cal_type = TYPE_TWO_POINT_TRIMMING, \
 135         .efuse_value = 55, \
 136         .min_efuse_value = 40, \
 137         .max_efuse_value = 100, \
 138         .first_point_trim = 25, \
 139         .second_point_trim = 85, \
 140         .default_temp_offset = 50, \
 141         .freq_tab[0] = { \
 142                 .freq_clip_max = 800 * 1000, \
 143                 .temp_level = 70, \
 144         }, \
 145         .freq_tab[1] = { \
 146                 .freq_clip_max = 400 * 1000, \
 147                 .temp_level = 95, \
 148         }, \
 149         .freq_tab_count = 2, \
 150         .registers = &exynos3250_tmu_registers, \
 151         .features = (TMU_SUPPORT_EMULATION | \
 152                         TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
 153                         TMU_SUPPORT_EMUL_TIME)
 154 #endif
 155
 156 #if defined(CONFIG_SOC_EXYNOS3250)
 157 struct exynos_tmu_init_data const exynos3250_default_tmu_data = {
 158         .tmu_data = {
 159                 {
 160                         EXYNOS3250_TMU_DATA,
 161                         .type = SOC_ARCH_EXYNOS3250,
 162                         .test_mux = EXYNOS4412_MUX_ADDR_VALUE,
 163                 },
 164         },
 165         .tmu_count = 1,
 166 };
 167 #endif
 168
 169 #if defined(CONFIG_SOC_EXYNOS4412) || defined(CONFIG_SOC_EXYNOS5250)
 170 static const struct exynos_tmu_registers exynos4412_tmu_registers = {
 171         .triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
 172         .triminfo_ctrl[0] = EXYNOS_TMU_TRIMINFO_CON,
 173         .triminfo_ctrl_count = 1,
 174         .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
 175         .test_mux_addr_shift = EXYNOS4412_MUX_ADDR_SHIFT,
 176         .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
 177         .therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
 178         .therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
 179         .tmu_status = EXYNOS_TMU_REG_STATUS,
 180         .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
 181         .threshold_th0 = EXYNOS_THD_TEMP_RISE,
 182         .threshold_th1 = EXYNOS_THD_TEMP_FALL,
 183         .tmu_inten = EXYNOS_TMU_REG_INTEN,
 184         .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
 185         .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
 186         .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
 187         .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
 188         .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
 189         .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
 190         .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
 191         .intclr_fall_shift = EXYNOS_TMU_CLEAR_FALL_INT_SHIFT,
 192         .intclr_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
 193         .intclr_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
 194         .intclr_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
 195         .emul_con = EXYNOS_EMUL_CON,
 196         .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
 197         .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
 198 };
 199
 200 #define EXYNOS4412_TMU_DATA \
 201         .threshold_falling = 10, \
 202         .trigger_levels[0] = 70, \
 203         .trigger_levels[1] = 95, \
 204         .trigger_levels[2] = 110, \
 205         .trigger_levels[3] = 120, \
 206         .trigger_enable[0] = true, \
 207         .trigger_enable[1] = true, \
 208         .trigger_enable[2] = true, \
 209         .trigger_enable[3] = false, \
 210         .trigger_type[0] = THROTTLE_ACTIVE, \
 211         .trigger_type[1] = THROTTLE_ACTIVE, \
 212         .trigger_type[2] = SW_TRIP, \
 213         .trigger_type[3] = HW_TRIP, \
 214         .max_trigger_level = 4, \
 215         .non_hw_trigger_levels = 3, \
 216         .gain = 8, \
 217         .reference_voltage = 16, \
 218         .noise_cancel_mode = 4, \
 219         .cal_type = TYPE_ONE_POINT_TRIMMING, \
 220         .efuse_value = 55, \
 221         .min_efuse_value = 40, \
 222         .max_efuse_value = 100, \
 223         .first_point_trim = 25, \
 224         .second_point_trim = 85, \
 225         .default_temp_offset = 50, \
 226         .freq_tab[0] = { \
 227                 .freq_clip_max = 1400 * 1000, \
 228                 .temp_level = 70, \
 229         }, \
 230         .freq_tab[1] = { \
 231                 .freq_clip_max = 400 * 1000, \
 232                 .temp_level = 95, \
 233         }, \
 234         .freq_tab_count = 2, \
 235         .triminfo_reload[0] = EXYNOS_TRIMINFO_RELOAD_ENABLE, \
 236         .registers = &exynos4412_tmu_registers, \
 237         .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
 238                         TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
 239                         TMU_SUPPORT_EMUL_TIME)
 240 #endif
 241
 242 #if defined(CONFIG_SOC_EXYNOS4412)
 243 struct exynos_tmu_init_data const exynos4412_default_tmu_data = {
 244         .tmu_data = {
 245                 {
 246                         EXYNOS4412_TMU_DATA,
 247                         .type = SOC_ARCH_EXYNOS4412,
 248                         .test_mux = EXYNOS4412_MUX_ADDR_VALUE,
 249                 },
 250         },
 251         .tmu_count = 1,
 252 };
 253 #endif
 254
 255 #if defined(CONFIG_SOC_EXYNOS5250)
 256 struct exynos_tmu_init_data const exynos5250_default_tmu_data = {
 257         .tmu_data = {
 258                 {
 259                         EXYNOS4412_TMU_DATA,
 260                         .type = SOC_ARCH_EXYNOS5250,
 261                 },
 262         },
 263         .tmu_count = 1,
 264 };
 265 #endif
 266
 267 #if defined(CONFIG_SOC_EXYNOS5260)
 268 static const struct exynos_tmu_registers exynos5260_tmu_registers = {
 269         .triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
 270         .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
 271         .tmu_ctrl = EXYNOS_TMU_REG_CONTROL1,
 272         .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
 273         .therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
 274         .therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
 275         .tmu_status = EXYNOS_TMU_REG_STATUS,
 276         .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
 277         .threshold_th0 = EXYNOS_THD_TEMP_RISE,
 278         .threshold_th1 = EXYNOS_THD_TEMP_FALL,
 279         .tmu_inten = EXYNOS5260_TMU_REG_INTEN,
 280         .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
 281         .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
 282         .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
 283         .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
 284         .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
 285         .tmu_intstat = EXYNOS5260_TMU_REG_INTSTAT,
 286         .tmu_intclear = EXYNOS5260_TMU_REG_INTCLEAR,
 287         .intclr_fall_shift = EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT,
 288         .intclr_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
 289         .intclr_rise_mask = EXYNOS5260_TMU_RISE_INT_MASK,
 290         .intclr_fall_mask = EXYNOS5260_TMU_FALL_INT_MASK,
 291         .emul_con = EXYNOS5260_EMUL_CON,
 292         .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
 293         .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
 294 };
 295
 296 #define __EXYNOS5260_TMU_DATA   \
 297         .threshold_falling = 10, \
 298         .trigger_levels[0] = 85, \
 299         .trigger_levels[1] = 103, \
 300         .trigger_levels[2] = 110, \
 301         .trigger_levels[3] = 120, \
 302         .trigger_enable[0] = true, \
 303         .trigger_enable[1] = true, \
 304         .trigger_enable[2] = true, \
 305         .trigger_enable[3] = false, \
 306         .trigger_type[0] = THROTTLE_ACTIVE, \
 307         .trigger_type[1] = THROTTLE_ACTIVE, \
 308         .trigger_type[2] = SW_TRIP, \
 309         .trigger_type[3] = HW_TRIP, \
 310         .max_trigger_level = 4, \
 311         .non_hw_trigger_levels = 3, \
 312         .gain = 8, \
 313         .reference_voltage = 16, \
 314         .noise_cancel_mode = 4, \
 315         .cal_type = TYPE_ONE_POINT_TRIMMING, \
 316         .efuse_value = 55, \
 317         .min_efuse_value = 40, \
 318         .max_efuse_value = 100, \
 319         .first_point_trim = 25, \
 320         .second_point_trim = 85, \
 321         .default_temp_offset = 50, \
 322         .freq_tab[0] = { \
 323                 .freq_clip_max = 800 * 1000, \
 324                 .temp_level = 85, \
 325         }, \
 326         .freq_tab[1] = { \
 327                 .freq_clip_max = 200 * 1000, \
 328                 .temp_level = 103, \
 329         }, \
 330         .freq_tab_count = 2, \
 331         .registers = &exynos5260_tmu_registers, \
 332
 333 #define EXYNOS5260_TMU_DATA \
 334         __EXYNOS5260_TMU_DATA \
 335         .type = SOC_ARCH_EXYNOS5260, \
 336         .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
 337                         TMU_SUPPORT_READY_STATUS | TMU_SUPPORT_EMUL_TIME)
 338
 339 struct exynos_tmu_init_data const exynos5260_default_tmu_data = {
 340         .tmu_data = {
 341                 { EXYNOS5260_TMU_DATA },
 342                 { EXYNOS5260_TMU_DATA },
 343                 { EXYNOS5260_TMU_DATA },
 344                 { EXYNOS5260_TMU_DATA },
 345                 { EXYNOS5260_TMU_DATA },
 346         },
 347         .tmu_count = 5,
 348 };
 349 #endif
 350
 351 #if defined(CONFIG_SOC_EXYNOS5420)
 352 static const struct exynos_tmu_registers exynos5420_tmu_registers = {
 353         .triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
 354         .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
 355         .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
 356         .therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
 357         .therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
 358         .tmu_status = EXYNOS_TMU_REG_STATUS,
 359         .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
 360         .threshold_th0 = EXYNOS_THD_TEMP_RISE,
 361         .threshold_th1 = EXYNOS_THD_TEMP_FALL,
 362         .tmu_inten = EXYNOS_TMU_REG_INTEN,
 363         .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
 364         .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
 365         .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
 366         /* INTEN_RISE3 Not availble in exynos5420 */
 367         .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
 368         .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
 369         .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
 370         .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
 371         .intclr_fall_shift = EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT,
 372         .intclr_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
 373         .intclr_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
 374         .intclr_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
 375         .emul_con = EXYNOS_EMUL_CON,
 376         .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
 377         .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
 378 };
 379
 380 #define __EXYNOS5420_TMU_DATA   \
 381         .threshold_falling = 10, \
 382         .trigger_levels[0] = 85, \
 383         .trigger_levels[1] = 103, \
 384         .trigger_levels[2] = 110, \
 385         .trigger_levels[3] = 120, \
 386         .trigger_enable[0] = true, \
 387         .trigger_enable[1] = true, \
 388         .trigger_enable[2] = true, \
 389         .trigger_enable[3] = false, \
 390         .trigger_type[0] = THROTTLE_ACTIVE, \
 391         .trigger_type[1] = THROTTLE_ACTIVE, \
 392         .trigger_type[2] = SW_TRIP, \
 393         .trigger_type[3] = HW_TRIP, \
 394         .max_trigger_level = 4, \
 395         .non_hw_trigger_levels = 3, \
 396         .gain = 8, \
 397         .reference_voltage = 16, \
 398         .noise_cancel_mode = 4, \
 399         .cal_type = TYPE_ONE_POINT_TRIMMING, \
 400         .efuse_value = 55, \
 401         .min_efuse_value = 40, \
 402         .max_efuse_value = 100, \
 403         .first_point_trim = 25, \
 404         .second_point_trim = 85, \
 405         .default_temp_offset = 50, \
 406         .freq_tab[0] = { \
 407                 .freq_clip_max = 800 * 1000, \
 408                 .temp_level = 85, \
 409         }, \
 410         .freq_tab[1] = { \
 411                 .freq_clip_max = 200 * 1000, \
 412                 .temp_level = 103, \
 413         }, \
 414         .freq_tab_count = 2, \
 415         .registers = &exynos5420_tmu_registers, \
 416
 417 #define EXYNOS5420_TMU_DATA \
 418         __EXYNOS5420_TMU_DATA \
 419         .type = SOC_ARCH_EXYNOS5250, \
 420         .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
 421                         TMU_SUPPORT_READY_STATUS | TMU_SUPPORT_EMUL_TIME)
 422
 423 #define EXYNOS5420_TMU_DATA_SHARED \
 424         __EXYNOS5420_TMU_DATA \
 425         .type = SOC_ARCH_EXYNOS5420_TRIMINFO, \
 426         .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
 427                         TMU_SUPPORT_READY_STATUS | TMU_SUPPORT_EMUL_TIME | \
 428                         TMU_SUPPORT_ADDRESS_MULTIPLE)
 429
 430 struct exynos_tmu_init_data const exynos5420_default_tmu_data = {
 431         .tmu_data = {
 432                 { EXYNOS5420_TMU_DATA },
 433                 { EXYNOS5420_TMU_DATA },
 434                 { EXYNOS5420_TMU_DATA_SHARED },
 435                 { EXYNOS5420_TMU_DATA_SHARED },
 436                 { EXYNOS5420_TMU_DATA_SHARED },
 437         },
 438         .tmu_count = 5,
 439 };
 440 #endif
 441
 442 #if defined(CONFIG_SOC_EXYNOS5440)
 443 static const struct exynos_tmu_registers exynos5440_tmu_registers = {
 444         .triminfo_data = EXYNOS5440_TMU_S0_7_TRIM,
 445         .tmu_ctrl = EXYNOS5440_TMU_S0_7_CTRL,
 446         .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
 447         .therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
 448         .therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
 449         .tmu_status = EXYNOS5440_TMU_S0_7_STATUS,
 450         .tmu_cur_temp = EXYNOS5440_TMU_S0_7_TEMP,
 451         .threshold_th0 = EXYNOS5440_TMU_S0_7_TH0,
 452         .threshold_th1 = EXYNOS5440_TMU_S0_7_TH1,
 453         .threshold_th2 = EXYNOS5440_TMU_S0_7_TH2,
 454         .threshold_th3_l0_shift = EXYNOS5440_TMU_TH_RISE4_SHIFT,
 455         .tmu_inten = EXYNOS5440_TMU_S0_7_IRQEN,
 456         .inten_rise0_shift = EXYNOS5440_TMU_INTEN_RISE0_SHIFT,
 457         .inten_rise1_shift = EXYNOS5440_TMU_INTEN_RISE1_SHIFT,
 458         .inten_rise2_shift = EXYNOS5440_TMU_INTEN_RISE2_SHIFT,
 459         .inten_rise3_shift = EXYNOS5440_TMU_INTEN_RISE3_SHIFT,
 460         .inten_fall0_shift = EXYNOS5440_TMU_INTEN_FALL0_SHIFT,
 461         .tmu_intstat = EXYNOS5440_TMU_S0_7_IRQ,
 462         .tmu_intclear = EXYNOS5440_TMU_S0_7_IRQ,
 463         .intclr_fall_shift = EXYNOS5440_TMU_CLEAR_FALL_INT_SHIFT,
 464         .intclr_rise_shift = EXYNOS5440_TMU_RISE_INT_SHIFT,
 465         .intclr_rise_mask = EXYNOS5440_TMU_RISE_INT_MASK,
 466         .intclr_fall_mask = EXYNOS5440_TMU_FALL_INT_MASK,
 467         .tmu_irqstatus = EXYNOS5440_TMU_IRQ_STATUS,
 468         .emul_con = EXYNOS5440_TMU_S0_7_DEBUG,
 469         .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
 470         .tmu_pmin = EXYNOS5440_TMU_PMIN,
 471 };
 472
 473 #define EXYNOS5440_TMU_DATA \
 474         .trigger_levels[0] = 100, \
 475         .trigger_levels[4] = 105, \
 476         .trigger_enable[0] = 1, \
 477         .trigger_type[0] = SW_TRIP, \
 478         .trigger_type[4] = HW_TRIP, \
 479         .max_trigger_level = 5, \
 480         .non_hw_trigger_levels = 1, \
 481         .gain = 5, \
 482         .reference_voltage = 16, \
 483         .noise_cancel_mode = 4, \
 484         .cal_type = TYPE_ONE_POINT_TRIMMING, \
 485         .efuse_value = 0x5b2d, \
 486         .min_efuse_value = 16, \
 487         .max_efuse_value = 76, \
 488         .first_point_trim = 25, \
 489         .second_point_trim = 70, \
 490         .default_temp_offset = 25, \
 491         .type = SOC_ARCH_EXYNOS5440, \
 492         .registers = &exynos5440_tmu_registers, \
 493         .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
 494                         TMU_SUPPORT_MULTI_INST | TMU_SUPPORT_ADDRESS_MULTIPLE),
 495
 496 struct exynos_tmu_init_data const exynos5440_default_tmu_data = {
 497         .tmu_data = {
 498                 { EXYNOS5440_TMU_DATA } ,
 499                 { EXYNOS5440_TMU_DATA } ,
 500                 { EXYNOS5440_TMU_DATA } ,
 501         },
 502         .tmu_count = 3,
 503 };
 504 #endif