drivers/thermal/samsung/exynos_tmu_data.c

   1 /*
   2  * exynos_tmu_data.c - Samsung EXYNOS tmu data file
   3  *
   4  *  Copyright (C) 2013 Samsung Electronics
   5  *  Amit Daniel Kachhap <amit.daniel@samsung.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  *
  21  */
  22
  23 #include "exynos_thermal_common.h"
  24 #include "exynos_tmu.h"
  25 #include "exynos_tmu_data.h"
  26
  27 #if defined(CONFIG_CPU_EXYNOS4210)
  28 static const struct exynos_tmu_registers exynos4210_tmu_registers = {
  29         .triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
  30         .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
  31         .tmu_status = EXYNOS_TMU_REG_STATUS,
  32         .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
  33         .threshold_temp = EXYNOS4210_TMU_REG_THRESHOLD_TEMP,
  34         .threshold_th0 = EXYNOS4210_TMU_REG_TRIG_LEVEL0,
  35         .tmu_inten = EXYNOS_TMU_REG_INTEN,
  36         .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
  37         .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
  38         .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
  39         .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
  40         .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
  41         .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
  42         .intclr_rise_mask = EXYNOS4210_TMU_TRIG_LEVEL_MASK,
  43 };
  44
  45 struct exynos_tmu_init_data const exynos4210_default_tmu_data = {
  46         .tmu_data = {
  47                 {
  48                 .threshold = 80,
  49                 .trigger_levels[0] = 5,
  50                 .trigger_levels[1] = 20,
  51                 .trigger_levels[2] = 30,
  52                 .trigger_enable[0] = true,
  53                 .trigger_enable[1] = true,
  54                 .trigger_enable[2] = true,
  55                 .trigger_enable[3] = false,
  56                 .trigger_type[0] = THROTTLE_ACTIVE,
  57                 .trigger_type[1] = THROTTLE_ACTIVE,
  58                 .trigger_type[2] = SW_TRIP,
  59                 .max_trigger_level = 4,
  60                 .non_hw_trigger_levels = 3,
  61                 .gain = 15,
  62                 .reference_voltage = 7,
  63                 .cal_type = TYPE_ONE_POINT_TRIMMING,
  64                 .min_efuse_value = 40,
  65                 .max_efuse_value = 100,
  66                 .first_point_trim = 25,
  67                 .second_point_trim = 85,
  68                 .default_temp_offset = 50,
  69                 .freq_tab[0] = {
  70                         .freq_clip_max = 800 * 1000,
  71                         .temp_level = 85,
  72                         },
  73                 .freq_tab[1] = {
  74                         .freq_clip_max = 200 * 1000,
  75                         .temp_level = 100,
  76                 },
  77                 .freq_tab_count = 2,
  78                 .type = SOC_ARCH_EXYNOS4210,
  79                 .registers = &exynos4210_tmu_registers,
  80                 .features = TMU_SUPPORT_READY_STATUS,
  81                 },
  82         },
  83         .tmu_count = 1,
  84 };
  85 #endif
  86
  87 #if defined(CONFIG_SOC_EXYNOS3250)
  88 static const struct exynos_tmu_registers exynos3250_tmu_registers = {
  89         .triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
  90         .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
  91         .test_mux_addr_shift = EXYNOS4412_MUX_ADDR_SHIFT,
  92         .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
  93         .therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
  94         .therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
  95         .tmu_status = EXYNOS_TMU_REG_STATUS,
  96         .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
  97         .threshold_th0 = EXYNOS_THD_TEMP_RISE,
  98         .threshold_th1 = EXYNOS_THD_TEMP_FALL,
  99         .tmu_inten = EXYNOS_TMU_REG_INTEN,
 100         .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
 101         .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
 102         .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
 103         .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
 104         .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
 105         .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
 106         .intclr_fall_shift = EXYNOS_TMU_CLEAR_FALL_INT_SHIFT,
 107         .intclr_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
 108         .intclr_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
 109         .intclr_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
 110         .emul_con = EXYNOS_EMUL_CON,
 111         .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
 112         .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
 113 };
 114
 115 #define EXYNOS3250_TMU_DATA \
 116         .threshold_falling = 10, \
 117         .trigger_levels[0] = 70, \
 118         .trigger_levels[1] = 95, \
 119         .trigger_levels[2] = 110, \
 120         .trigger_levels[3] = 120, \
 121         .trigger_enable[0] = true, \
 122         .trigger_enable[1] = true, \
 123         .trigger_enable[2] = true, \
 124         .trigger_enable[3] = false, \
 125         .trigger_type[0] = THROTTLE_ACTIVE, \
 126         .trigger_type[1] = THROTTLE_ACTIVE, \
 127         .trigger_type[2] = SW_TRIP, \
 128         .trigger_type[3] = HW_TRIP, \
 129         .max_trigger_level = 4, \
 130         .non_hw_trigger_levels = 3, \
 131         .gain = 8, \
 132         .reference_voltage = 16, \
 133         .noise_cancel_mode = 4, \
 134         .cal_type = TYPE_TWO_POINT_TRIMMING, \
 135         .efuse_value = 55, \
 136         .min_efuse_value = 40, \
 137         .max_efuse_value = 100, \
 138         .first_point_trim = 25, \
 139         .second_point_trim = 85, \
 140         .default_temp_offset = 50, \
 141         .freq_tab[0] = { \
 142                 .freq_clip_max = 800 * 1000, \
 143                 .temp_level = 70, \
 144         }, \
 145         .freq_tab[1] = { \
 146                 .freq_clip_max = 400 * 1000, \
 147                 .temp_level = 95, \
 148         }, \
 149         .freq_tab_count = 2, \
 150         .registers = &exynos3250_tmu_registers, \
 151         .features = (TMU_SUPPORT_EMULATION | \
 152                         TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
 153                         TMU_SUPPORT_EMUL_TIME)
 154 #endif
 155
 156 #if defined(CONFIG_SOC_EXYNOS3250)
 157 struct exynos_tmu_init_data const exynos3250_default_tmu_data = {
 158         .tmu_data = {
 159                 {
 160                         EXYNOS3250_TMU_DATA,
 161                         .type = SOC_ARCH_EXYNOS3250,
 162                         .test_mux = EXYNOS4412_MUX_ADDR_VALUE,
 163                 },
 164         },
 165         .tmu_count = 1,
 166 };
 167 #endif
 168
 169 #if defined(CONFIG_SOC_EXYNOS4412) || defined(CONFIG_SOC_EXYNOS5250)
 170 static const struct exynos_tmu_registers exynos4412_tmu_registers = {
 171         .triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
 172         .triminfo_ctrl = EXYNOS_TMU_TRIMINFO_CON,
 173         .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
 174         .test_mux_addr_shift = EXYNOS4412_MUX_ADDR_SHIFT,
 175         .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
 176         .therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
 177         .therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
 178         .tmu_status = EXYNOS_TMU_REG_STATUS,
 179         .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
 180         .threshold_th0 = EXYNOS_THD_TEMP_RISE,
 181         .threshold_th1 = EXYNOS_THD_TEMP_FALL,
 182         .tmu_inten = EXYNOS_TMU_REG_INTEN,
 183         .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
 184         .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
 185         .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
 186         .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
 187         .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
 188         .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
 189         .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
 190         .intclr_fall_shift = EXYNOS_TMU_CLEAR_FALL_INT_SHIFT,
 191         .intclr_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
 192         .intclr_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
 193         .intclr_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
 194         .emul_con = EXYNOS_EMUL_CON,
 195         .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
 196         .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
 197 };
 198
 199 #define EXYNOS4412_TMU_DATA \
 200         .threshold_falling = 10, \
 201         .trigger_levels[0] = 70, \
 202         .trigger_levels[1] = 95, \
 203         .trigger_levels[2] = 110, \
 204         .trigger_levels[3] = 120, \
 205         .trigger_enable[0] = true, \
 206         .trigger_enable[1] = true, \
 207         .trigger_enable[2] = true, \
 208         .trigger_enable[3] = false, \
 209         .trigger_type[0] = THROTTLE_ACTIVE, \
 210         .trigger_type[1] = THROTTLE_ACTIVE, \
 211         .trigger_type[2] = SW_TRIP, \
 212         .trigger_type[3] = HW_TRIP, \
 213         .max_trigger_level = 4, \
 214         .non_hw_trigger_levels = 3, \
 215         .gain = 8, \
 216         .reference_voltage = 16, \
 217         .noise_cancel_mode = 4, \
 218         .cal_type = TYPE_ONE_POINT_TRIMMING, \
 219         .efuse_value = 55, \
 220         .min_efuse_value = 40, \
 221         .max_efuse_value = 100, \
 222         .first_point_trim = 25, \
 223         .second_point_trim = 85, \
 224         .default_temp_offset = 50, \
 225         .freq_tab[0] = { \
 226                 .freq_clip_max = 1400 * 1000, \
 227                 .temp_level = 70, \
 228         }, \
 229         .freq_tab[1] = { \
 230                 .freq_clip_max = 400 * 1000, \
 231                 .temp_level = 95, \
 232         }, \
 233         .freq_tab_count = 2, \
 234         .registers = &exynos4412_tmu_registers, \
 235         .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
 236                         TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
 237                         TMU_SUPPORT_EMUL_TIME)
 238 #endif
 239
 240 #if defined(CONFIG_SOC_EXYNOS4412)
 241 struct exynos_tmu_init_data const exynos4412_default_tmu_data = {
 242         .tmu_data = {
 243                 {
 244                         EXYNOS4412_TMU_DATA,
 245                         .type = SOC_ARCH_EXYNOS4412,
 246                         .test_mux = EXYNOS4412_MUX_ADDR_VALUE,
 247                 },
 248         },
 249         .tmu_count = 1,
 250 };
 251 #endif
 252
 253 #if defined(CONFIG_SOC_EXYNOS5250)
 254 struct exynos_tmu_init_data const exynos5250_default_tmu_data = {
 255         .tmu_data = {
 256                 {
 257                         EXYNOS4412_TMU_DATA,
 258                         .type = SOC_ARCH_EXYNOS5250,
 259                 },
 260         },
 261         .tmu_count = 1,
 262 };
 263 #endif
 264
 265 #if defined(CONFIG_SOC_EXYNOS5260)
 266 static const struct exynos_tmu_registers exynos5260_tmu_registers = {
 267         .triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
 268         .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
 269         .tmu_ctrl = EXYNOS_TMU_REG_CONTROL1,
 270         .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
 271         .therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
 272         .therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
 273         .tmu_status = EXYNOS_TMU_REG_STATUS,
 274         .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
 275         .threshold_th0 = EXYNOS_THD_TEMP_RISE,
 276         .threshold_th1 = EXYNOS_THD_TEMP_FALL,
 277         .tmu_inten = EXYNOS5260_TMU_REG_INTEN,
 278         .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
 279         .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
 280         .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
 281         .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
 282         .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
 283         .tmu_intstat = EXYNOS5260_TMU_REG_INTSTAT,
 284         .tmu_intclear = EXYNOS5260_TMU_REG_INTCLEAR,
 285         .intclr_fall_shift = EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT,
 286         .intclr_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
 287         .intclr_rise_mask = EXYNOS5260_TMU_RISE_INT_MASK,
 288         .intclr_fall_mask = EXYNOS5260_TMU_FALL_INT_MASK,
 289         .emul_con = EXYNOS5260_EMUL_CON,
 290         .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
 291         .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
 292 };
 293
 294 #define __EXYNOS5260_TMU_DATA   \
 295         .threshold_falling = 10, \
 296         .trigger_levels[0] = 85, \
 297         .trigger_levels[1] = 103, \
 298         .trigger_levels[2] = 110, \
 299         .trigger_levels[3] = 120, \
 300         .trigger_enable[0] = true, \
 301         .trigger_enable[1] = true, \
 302         .trigger_enable[2] = true, \
 303         .trigger_enable[3] = false, \
 304         .trigger_type[0] = THROTTLE_ACTIVE, \
 305         .trigger_type[1] = THROTTLE_ACTIVE, \
 306         .trigger_type[2] = SW_TRIP, \
 307         .trigger_type[3] = HW_TRIP, \
 308         .max_trigger_level = 4, \
 309         .non_hw_trigger_levels = 3, \
 310         .gain = 8, \
 311         .reference_voltage = 16, \
 312         .noise_cancel_mode = 4, \
 313         .cal_type = TYPE_ONE_POINT_TRIMMING, \
 314         .efuse_value = 55, \
 315         .min_efuse_value = 40, \
 316         .max_efuse_value = 100, \
 317         .first_point_trim = 25, \
 318         .second_point_trim = 85, \
 319         .default_temp_offset = 50, \
 320         .freq_tab[0] = { \
 321                 .freq_clip_max = 800 * 1000, \
 322                 .temp_level = 85, \
 323         }, \
 324         .freq_tab[1] = { \
 325                 .freq_clip_max = 200 * 1000, \
 326                 .temp_level = 103, \
 327         }, \
 328         .freq_tab_count = 2, \
 329         .registers = &exynos5260_tmu_registers, \
 330
 331 #define EXYNOS5260_TMU_DATA \
 332         __EXYNOS5260_TMU_DATA \
 333         .type = SOC_ARCH_EXYNOS5260, \
 334         .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
 335                         TMU_SUPPORT_READY_STATUS | TMU_SUPPORT_EMUL_TIME)
 336
 337 struct exynos_tmu_init_data const exynos5260_default_tmu_data = {
 338         .tmu_data = {
 339                 { EXYNOS5260_TMU_DATA },
 340                 { EXYNOS5260_TMU_DATA },
 341                 { EXYNOS5260_TMU_DATA },
 342                 { EXYNOS5260_TMU_DATA },
 343                 { EXYNOS5260_TMU_DATA },
 344         },
 345         .tmu_count = 5,
 346 };
 347 #endif
 348
 349 #if defined(CONFIG_SOC_EXYNOS5420)
 350 static const struct exynos_tmu_registers exynos5420_tmu_registers = {
 351         .triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
 352         .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
 353         .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
 354         .therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
 355         .therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
 356         .tmu_status = EXYNOS_TMU_REG_STATUS,
 357         .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
 358         .threshold_th0 = EXYNOS_THD_TEMP_RISE,
 359         .threshold_th1 = EXYNOS_THD_TEMP_FALL,
 360         .tmu_inten = EXYNOS_TMU_REG_INTEN,
 361         .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
 362         .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
 363         .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
 364         /* INTEN_RISE3 Not availble in exynos5420 */
 365         .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
 366         .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
 367         .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
 368         .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
 369         .intclr_fall_shift = EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT,
 370         .intclr_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
 371         .intclr_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
 372         .intclr_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
 373         .emul_con = EXYNOS_EMUL_CON,
 374         .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
 375         .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
 376 };
 377
 378 #define __EXYNOS5420_TMU_DATA   \
 379         .threshold_falling = 10, \
 380         .trigger_levels[0] = 85, \
 381         .trigger_levels[1] = 103, \
 382         .trigger_levels[2] = 110, \
 383         .trigger_levels[3] = 120, \
 384         .trigger_enable[0] = true, \
 385         .trigger_enable[1] = true, \
 386         .trigger_enable[2] = true, \
 387         .trigger_enable[3] = false, \
 388         .trigger_type[0] = THROTTLE_ACTIVE, \
 389         .trigger_type[1] = THROTTLE_ACTIVE, \
 390         .trigger_type[2] = SW_TRIP, \
 391         .trigger_type[3] = HW_TRIP, \
 392         .max_trigger_level = 4, \
 393         .non_hw_trigger_levels = 3, \
 394         .gain = 8, \
 395         .reference_voltage = 16, \
 396         .noise_cancel_mode = 4, \
 397         .cal_type = TYPE_ONE_POINT_TRIMMING, \
 398         .efuse_value = 55, \
 399         .min_efuse_value = 40, \
 400         .max_efuse_value = 100, \
 401         .first_point_trim = 25, \
 402         .second_point_trim = 85, \
 403         .default_temp_offset = 50, \
 404         .freq_tab[0] = { \
 405                 .freq_clip_max = 800 * 1000, \
 406                 .temp_level = 85, \
 407         }, \
 408         .freq_tab[1] = { \
 409                 .freq_clip_max = 200 * 1000, \
 410                 .temp_level = 103, \
 411         }, \
 412         .freq_tab_count = 2, \
 413         .registers = &exynos5420_tmu_registers, \
 414
 415 #define EXYNOS5420_TMU_DATA \
 416         __EXYNOS5420_TMU_DATA \
 417         .type = SOC_ARCH_EXYNOS5250, \
 418         .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
 419                         TMU_SUPPORT_READY_STATUS | TMU_SUPPORT_EMUL_TIME)
 420
 421 #define EXYNOS5420_TMU_DATA_SHARED \
 422         __EXYNOS5420_TMU_DATA \
 423         .type = SOC_ARCH_EXYNOS5420_TRIMINFO, \
 424         .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
 425                         TMU_SUPPORT_READY_STATUS | TMU_SUPPORT_EMUL_TIME | \
 426                         TMU_SUPPORT_ADDRESS_MULTIPLE)
 427
 428 struct exynos_tmu_init_data const exynos5420_default_tmu_data = {
 429         .tmu_data = {
 430                 { EXYNOS5420_TMU_DATA },
 431                 { EXYNOS5420_TMU_DATA },
 432                 { EXYNOS5420_TMU_DATA_SHARED },
 433                 { EXYNOS5420_TMU_DATA_SHARED },
 434                 { EXYNOS5420_TMU_DATA_SHARED },
 435         },
 436         .tmu_count = 5,
 437 };
 438 #endif
 439
 440 #if defined(CONFIG_SOC_EXYNOS5440)
 441 static const struct exynos_tmu_registers exynos5440_tmu_registers = {
 442         .triminfo_data = EXYNOS5440_TMU_S0_7_TRIM,
 443         .tmu_ctrl = EXYNOS5440_TMU_S0_7_CTRL,
 444         .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
 445         .therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
 446         .therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
 447         .tmu_status = EXYNOS5440_TMU_S0_7_STATUS,
 448         .tmu_cur_temp = EXYNOS5440_TMU_S0_7_TEMP,
 449         .threshold_th0 = EXYNOS5440_TMU_S0_7_TH0,
 450         .threshold_th1 = EXYNOS5440_TMU_S0_7_TH1,
 451         .threshold_th2 = EXYNOS5440_TMU_S0_7_TH2,
 452         .threshold_th3_l0_shift = EXYNOS5440_TMU_TH_RISE4_SHIFT,
 453         .tmu_inten = EXYNOS5440_TMU_S0_7_IRQEN,
 454         .inten_rise0_shift = EXYNOS5440_TMU_INTEN_RISE0_SHIFT,
 455         .inten_rise1_shift = EXYNOS5440_TMU_INTEN_RISE1_SHIFT,
 456         .inten_rise2_shift = EXYNOS5440_TMU_INTEN_RISE2_SHIFT,
 457         .inten_rise3_shift = EXYNOS5440_TMU_INTEN_RISE3_SHIFT,
 458         .inten_fall0_shift = EXYNOS5440_TMU_INTEN_FALL0_SHIFT,
 459         .tmu_intstat = EXYNOS5440_TMU_S0_7_IRQ,
 460         .tmu_intclear = EXYNOS5440_TMU_S0_7_IRQ,
 461         .intclr_fall_shift = EXYNOS5440_TMU_CLEAR_FALL_INT_SHIFT,
 462         .intclr_rise_shift = EXYNOS5440_TMU_RISE_INT_SHIFT,
 463         .intclr_rise_mask = EXYNOS5440_TMU_RISE_INT_MASK,
 464         .intclr_fall_mask = EXYNOS5440_TMU_FALL_INT_MASK,
 465         .tmu_irqstatus = EXYNOS5440_TMU_IRQ_STATUS,
 466         .emul_con = EXYNOS5440_TMU_S0_7_DEBUG,
 467         .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
 468         .tmu_pmin = EXYNOS5440_TMU_PMIN,
 469 };
 470
 471 #define EXYNOS5440_TMU_DATA \
 472         .trigger_levels[0] = 100, \
 473         .trigger_levels[4] = 105, \
 474         .trigger_enable[0] = 1, \
 475         .trigger_type[0] = SW_TRIP, \
 476         .trigger_type[4] = HW_TRIP, \
 477         .max_trigger_level = 5, \
 478         .non_hw_trigger_levels = 1, \
 479         .gain = 5, \
 480         .reference_voltage = 16, \
 481         .noise_cancel_mode = 4, \
 482         .cal_type = TYPE_ONE_POINT_TRIMMING, \
 483         .efuse_value = 0x5b2d, \
 484         .min_efuse_value = 16, \
 485         .max_efuse_value = 76, \
 486         .first_point_trim = 25, \
 487         .second_point_trim = 70, \
 488         .default_temp_offset = 25, \
 489         .type = SOC_ARCH_EXYNOS5440, \
 490         .registers = &exynos5440_tmu_registers, \
 491         .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
 492                         TMU_SUPPORT_MULTI_INST | TMU_SUPPORT_ADDRESS_MULTIPLE),
 493
 494 struct exynos_tmu_init_data const exynos5440_default_tmu_data = {
 495         .tmu_data = {
 496                 { EXYNOS5440_TMU_DATA } ,
 497                 { EXYNOS5440_TMU_DATA } ,
 498                 { EXYNOS5440_TMU_DATA } ,
 499         },
 500         .tmu_count = 3,
 501 };
 502 #endif