drivers/thermal/samsung/exynos_tmu_data.c

   1 /*
   2  * exynos_tmu_data.c - Samsung EXYNOS tmu data file
   3  *
   4  *  Copyright (C) 2013 Samsung Electronics
   5  *  Amit Daniel Kachhap <amit.daniel@samsung.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  *
  21  */
  22
  23 #include "exynos_thermal_common.h"
  24 #include "exynos_tmu.h"
  25 #include "exynos_tmu_data.h"
  26
  27 #if defined(CONFIG_CPU_EXYNOS4210)
  28 static const struct exynos_tmu_registers exynos4210_tmu_registers = {
  29         .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
  30         .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
  31         .threshold_th0 = EXYNOS4210_TMU_REG_TRIG_LEVEL0,
  32         .tmu_inten = EXYNOS_TMU_REG_INTEN,
  33         .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
  34         .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
  35         .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
  36         .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
  37         .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
  38         .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
  39 };
  40
  41 struct exynos_tmu_init_data const exynos4210_default_tmu_data = {
  42         .tmu_data = {
  43                 {
  44                 .threshold = 80,
  45                 .trigger_levels[0] = 5,
  46                 .trigger_levels[1] = 20,
  47                 .trigger_levels[2] = 30,
  48                 .trigger_enable[0] = true,
  49                 .trigger_enable[1] = true,
  50                 .trigger_enable[2] = true,
  51                 .trigger_enable[3] = false,
  52                 .trigger_type[0] = THROTTLE_ACTIVE,
  53                 .trigger_type[1] = THROTTLE_ACTIVE,
  54                 .trigger_type[2] = SW_TRIP,
  55                 .max_trigger_level = 4,
  56                 .non_hw_trigger_levels = 3,
  57                 .gain = 15,
  58                 .reference_voltage = 7,
  59                 .cal_type = TYPE_ONE_POINT_TRIMMING,
  60                 .min_efuse_value = 40,
  61                 .max_efuse_value = 100,
  62                 .first_point_trim = 25,
  63                 .second_point_trim = 85,
  64                 .default_temp_offset = 50,
  65                 .freq_tab[0] = {
  66                         .freq_clip_max = 800 * 1000,
  67                         .temp_level = 85,
  68                         },
  69                 .freq_tab[1] = {
  70                         .freq_clip_max = 200 * 1000,
  71                         .temp_level = 100,
  72                 },
  73                 .freq_tab_count = 2,
  74                 .type = SOC_ARCH_EXYNOS4210,
  75                 .registers = &exynos4210_tmu_registers,
  76                 .features = TMU_SUPPORT_READY_STATUS,
  77                 },
  78         },
  79         .tmu_count = 1,
  80 };
  81 #endif
  82
  83 #if defined(CONFIG_SOC_EXYNOS3250)
  84 static const struct exynos_tmu_registers exynos3250_tmu_registers = {
  85         .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
  86         .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
  87         .threshold_th0 = EXYNOS_THD_TEMP_RISE,
  88         .threshold_th1 = EXYNOS_THD_TEMP_FALL,
  89         .tmu_inten = EXYNOS_TMU_REG_INTEN,
  90         .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
  91         .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
  92         .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
  93         .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
  94         .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
  95         .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
  96         .emul_con = EXYNOS_EMUL_CON,
  97         .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
  98 };
  99
 100 #define EXYNOS3250_TMU_DATA \
 101         .threshold_falling = 10, \
 102         .trigger_levels[0] = 70, \
 103         .trigger_levels[1] = 95, \
 104         .trigger_levels[2] = 110, \
 105         .trigger_levels[3] = 120, \
 106         .trigger_enable[0] = true, \
 107         .trigger_enable[1] = true, \
 108         .trigger_enable[2] = true, \
 109         .trigger_enable[3] = false, \
 110         .trigger_type[0] = THROTTLE_ACTIVE, \
 111         .trigger_type[1] = THROTTLE_ACTIVE, \
 112         .trigger_type[2] = SW_TRIP, \
 113         .trigger_type[3] = HW_TRIP, \
 114         .max_trigger_level = 4, \
 115         .non_hw_trigger_levels = 3, \
 116         .gain = 8, \
 117         .reference_voltage = 16, \
 118         .noise_cancel_mode = 4, \
 119         .cal_type = TYPE_TWO_POINT_TRIMMING, \
 120         .efuse_value = 55, \
 121         .min_efuse_value = 40, \
 122         .max_efuse_value = 100, \
 123         .first_point_trim = 25, \
 124         .second_point_trim = 85, \
 125         .default_temp_offset = 50, \
 126         .freq_tab[0] = { \
 127                 .freq_clip_max = 800 * 1000, \
 128                 .temp_level = 70, \
 129         }, \
 130         .freq_tab[1] = { \
 131                 .freq_clip_max = 400 * 1000, \
 132                 .temp_level = 95, \
 133         }, \
 134         .freq_tab_count = 2, \
 135         .registers = &exynos3250_tmu_registers, \
 136         .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
 137                         TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
 138                         TMU_SUPPORT_EMUL_TIME)
 139 #endif
 140
 141 #if defined(CONFIG_SOC_EXYNOS3250)
 142 struct exynos_tmu_init_data const exynos3250_default_tmu_data = {
 143         .tmu_data = {
 144                 {
 145                         EXYNOS3250_TMU_DATA,
 146                         .type = SOC_ARCH_EXYNOS3250,
 147                         .test_mux = EXYNOS4412_MUX_ADDR_VALUE,
 148                 },
 149         },
 150         .tmu_count = 1,
 151 };
 152 #endif
 153
 154 #if defined(CONFIG_SOC_EXYNOS4412) || defined(CONFIG_SOC_EXYNOS5250)
 155 static const struct exynos_tmu_registers exynos4412_tmu_registers = {
 156         .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
 157         .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
 158         .threshold_th0 = EXYNOS_THD_TEMP_RISE,
 159         .threshold_th1 = EXYNOS_THD_TEMP_FALL,
 160         .tmu_inten = EXYNOS_TMU_REG_INTEN,
 161         .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
 162         .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
 163         .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
 164         .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
 165         .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
 166         .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
 167         .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
 168         .emul_con = EXYNOS_EMUL_CON,
 169         .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
 170 };
 171
 172 #define EXYNOS4412_TMU_DATA \
 173         .threshold_falling = 10, \
 174         .trigger_levels[0] = 70, \
 175         .trigger_levels[1] = 95, \
 176         .trigger_levels[2] = 110, \
 177         .trigger_levels[3] = 120, \
 178         .trigger_enable[0] = true, \
 179         .trigger_enable[1] = true, \
 180         .trigger_enable[2] = true, \
 181         .trigger_enable[3] = false, \
 182         .trigger_type[0] = THROTTLE_ACTIVE, \
 183         .trigger_type[1] = THROTTLE_ACTIVE, \
 184         .trigger_type[2] = SW_TRIP, \
 185         .trigger_type[3] = HW_TRIP, \
 186         .max_trigger_level = 4, \
 187         .non_hw_trigger_levels = 3, \
 188         .gain = 8, \
 189         .reference_voltage = 16, \
 190         .noise_cancel_mode = 4, \
 191         .cal_type = TYPE_ONE_POINT_TRIMMING, \
 192         .efuse_value = 55, \
 193         .min_efuse_value = 40, \
 194         .max_efuse_value = 100, \
 195         .first_point_trim = 25, \
 196         .second_point_trim = 85, \
 197         .default_temp_offset = 50, \
 198         .freq_tab[0] = { \
 199                 .freq_clip_max = 1400 * 1000, \
 200                 .temp_level = 70, \
 201         }, \
 202         .freq_tab[1] = { \
 203                 .freq_clip_max = 400 * 1000, \
 204                 .temp_level = 95, \
 205         }, \
 206         .freq_tab_count = 2, \
 207         .registers = &exynos4412_tmu_registers, \
 208         .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
 209                         TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
 210                         TMU_SUPPORT_EMUL_TIME)
 211 #endif
 212
 213 #if defined(CONFIG_SOC_EXYNOS4412)
 214 struct exynos_tmu_init_data const exynos4412_default_tmu_data = {
 215         .tmu_data = {
 216                 {
 217                         EXYNOS4412_TMU_DATA,
 218                         .type = SOC_ARCH_EXYNOS4412,
 219                         .test_mux = EXYNOS4412_MUX_ADDR_VALUE,
 220                 },
 221         },
 222         .tmu_count = 1,
 223 };
 224 #endif
 225
 226 #if defined(CONFIG_SOC_EXYNOS5250)
 227 struct exynos_tmu_init_data const exynos5250_default_tmu_data = {
 228         .tmu_data = {
 229                 {
 230                         EXYNOS4412_TMU_DATA,
 231                         .type = SOC_ARCH_EXYNOS5250,
 232                 },
 233         },
 234         .tmu_count = 1,
 235 };
 236 #endif
 237
 238 #if defined(CONFIG_SOC_EXYNOS5260)
 239 static const struct exynos_tmu_registers exynos5260_tmu_registers = {
 240         .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
 241         .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
 242         .threshold_th0 = EXYNOS_THD_TEMP_RISE,
 243         .threshold_th1 = EXYNOS_THD_TEMP_FALL,
 244         .tmu_inten = EXYNOS5260_TMU_REG_INTEN,
 245         .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
 246         .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
 247         .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
 248         .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
 249         .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
 250         .tmu_intstat = EXYNOS5260_TMU_REG_INTSTAT,
 251         .tmu_intclear = EXYNOS5260_TMU_REG_INTCLEAR,
 252         .emul_con = EXYNOS5260_EMUL_CON,
 253         .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
 254 };
 255
 256 #define __EXYNOS5260_TMU_DATA   \
 257         .threshold_falling = 10, \
 258         .trigger_levels[0] = 85, \
 259         .trigger_levels[1] = 103, \
 260         .trigger_levels[2] = 110, \
 261         .trigger_levels[3] = 120, \
 262         .trigger_enable[0] = true, \
 263         .trigger_enable[1] = true, \
 264         .trigger_enable[2] = true, \
 265         .trigger_enable[3] = false, \
 266         .trigger_type[0] = THROTTLE_ACTIVE, \
 267         .trigger_type[1] = THROTTLE_ACTIVE, \
 268         .trigger_type[2] = SW_TRIP, \
 269         .trigger_type[3] = HW_TRIP, \
 270         .max_trigger_level = 4, \
 271         .non_hw_trigger_levels = 3, \
 272         .gain = 8, \
 273         .reference_voltage = 16, \
 274         .noise_cancel_mode = 4, \
 275         .cal_type = TYPE_ONE_POINT_TRIMMING, \
 276         .efuse_value = 55, \
 277         .min_efuse_value = 40, \
 278         .max_efuse_value = 100, \
 279         .first_point_trim = 25, \
 280         .second_point_trim = 85, \
 281         .default_temp_offset = 50, \
 282         .freq_tab[0] = { \
 283                 .freq_clip_max = 800 * 1000, \
 284                 .temp_level = 85, \
 285         }, \
 286         .freq_tab[1] = { \
 287                 .freq_clip_max = 200 * 1000, \
 288                 .temp_level = 103, \
 289         }, \
 290         .freq_tab_count = 2, \
 291         .registers = &exynos5260_tmu_registers, \
 292
 293 #define EXYNOS5260_TMU_DATA \
 294         __EXYNOS5260_TMU_DATA \
 295         .type = SOC_ARCH_EXYNOS5260, \
 296         .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
 297                         TMU_SUPPORT_READY_STATUS | TMU_SUPPORT_EMUL_TIME)
 298
 299 struct exynos_tmu_init_data const exynos5260_default_tmu_data = {
 300         .tmu_data = {
 301                 { EXYNOS5260_TMU_DATA },
 302                 { EXYNOS5260_TMU_DATA },
 303                 { EXYNOS5260_TMU_DATA },
 304                 { EXYNOS5260_TMU_DATA },
 305                 { EXYNOS5260_TMU_DATA },
 306         },
 307         .tmu_count = 5,
 308 };
 309 #endif
 310
 311 #if defined(CONFIG_SOC_EXYNOS5420)
 312 static const struct exynos_tmu_registers exynos5420_tmu_registers = {
 313         .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
 314         .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
 315         .threshold_th0 = EXYNOS_THD_TEMP_RISE,
 316         .threshold_th1 = EXYNOS_THD_TEMP_FALL,
 317         .tmu_inten = EXYNOS_TMU_REG_INTEN,
 318         .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
 319         .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
 320         .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
 321         /* INTEN_RISE3 Not availble in exynos5420 */
 322         .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
 323         .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
 324         .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
 325         .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
 326         .emul_con = EXYNOS_EMUL_CON,
 327         .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
 328 };
 329
 330 #define __EXYNOS5420_TMU_DATA   \
 331         .threshold_falling = 10, \
 332         .trigger_levels[0] = 85, \
 333         .trigger_levels[1] = 103, \
 334         .trigger_levels[2] = 110, \
 335         .trigger_levels[3] = 120, \
 336         .trigger_enable[0] = true, \
 337         .trigger_enable[1] = true, \
 338         .trigger_enable[2] = true, \
 339         .trigger_enable[3] = false, \
 340         .trigger_type[0] = THROTTLE_ACTIVE, \
 341         .trigger_type[1] = THROTTLE_ACTIVE, \
 342         .trigger_type[2] = SW_TRIP, \
 343         .trigger_type[3] = HW_TRIP, \
 344         .max_trigger_level = 4, \
 345         .non_hw_trigger_levels = 3, \
 346         .gain = 8, \
 347         .reference_voltage = 16, \
 348         .noise_cancel_mode = 4, \
 349         .cal_type = TYPE_ONE_POINT_TRIMMING, \
 350         .efuse_value = 55, \
 351         .min_efuse_value = 40, \
 352         .max_efuse_value = 100, \
 353         .first_point_trim = 25, \
 354         .second_point_trim = 85, \
 355         .default_temp_offset = 50, \
 356         .freq_tab[0] = { \
 357                 .freq_clip_max = 800 * 1000, \
 358                 .temp_level = 85, \
 359         }, \
 360         .freq_tab[1] = { \
 361                 .freq_clip_max = 200 * 1000, \
 362                 .temp_level = 103, \
 363         }, \
 364         .freq_tab_count = 2, \
 365         .registers = &exynos5420_tmu_registers, \
 366
 367 #define EXYNOS5420_TMU_DATA \
 368         __EXYNOS5420_TMU_DATA \
 369         .type = SOC_ARCH_EXYNOS5250, \
 370         .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
 371                         TMU_SUPPORT_READY_STATUS | TMU_SUPPORT_EMUL_TIME)
 372
 373 #define EXYNOS5420_TMU_DATA_SHARED \
 374         __EXYNOS5420_TMU_DATA \
 375         .type = SOC_ARCH_EXYNOS5420_TRIMINFO, \
 376         .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
 377                         TMU_SUPPORT_READY_STATUS | TMU_SUPPORT_EMUL_TIME | \
 378                         TMU_SUPPORT_ADDRESS_MULTIPLE)
 379
 380 struct exynos_tmu_init_data const exynos5420_default_tmu_data = {
 381         .tmu_data = {
 382                 { EXYNOS5420_TMU_DATA },
 383                 { EXYNOS5420_TMU_DATA },
 384                 { EXYNOS5420_TMU_DATA_SHARED },
 385                 { EXYNOS5420_TMU_DATA_SHARED },
 386                 { EXYNOS5420_TMU_DATA_SHARED },
 387         },
 388         .tmu_count = 5,
 389 };
 390 #endif
 391
 392 #if defined(CONFIG_SOC_EXYNOS5440)
 393 static const struct exynos_tmu_registers exynos5440_tmu_registers = {
 394         .tmu_ctrl = EXYNOS5440_TMU_S0_7_CTRL,
 395         .tmu_cur_temp = EXYNOS5440_TMU_S0_7_TEMP,
 396         .threshold_th0 = EXYNOS5440_TMU_S0_7_TH0,
 397         .threshold_th1 = EXYNOS5440_TMU_S0_7_TH1,
 398         .threshold_th2 = EXYNOS5440_TMU_S0_7_TH2,
 399         .threshold_th3_l0_shift = EXYNOS5440_TMU_TH_RISE4_SHIFT,
 400         .tmu_inten = EXYNOS5440_TMU_S0_7_IRQEN,
 401         .inten_rise0_shift = EXYNOS5440_TMU_INTEN_RISE0_SHIFT,
 402         .inten_rise1_shift = EXYNOS5440_TMU_INTEN_RISE1_SHIFT,
 403         .inten_rise2_shift = EXYNOS5440_TMU_INTEN_RISE2_SHIFT,
 404         .inten_rise3_shift = EXYNOS5440_TMU_INTEN_RISE3_SHIFT,
 405         .inten_fall0_shift = EXYNOS5440_TMU_INTEN_FALL0_SHIFT,
 406         .tmu_intstat = EXYNOS5440_TMU_S0_7_IRQ,
 407         .tmu_intclear = EXYNOS5440_TMU_S0_7_IRQ,
 408         .tmu_irqstatus = EXYNOS5440_TMU_IRQ_STATUS,
 409         .emul_con = EXYNOS5440_TMU_S0_7_DEBUG,
 410         .tmu_pmin = EXYNOS5440_TMU_PMIN,
 411 };
 412
 413 #define EXYNOS5440_TMU_DATA \
 414         .trigger_levels[0] = 100, \
 415         .trigger_levels[4] = 105, \
 416         .trigger_enable[0] = 1, \
 417         .trigger_type[0] = SW_TRIP, \
 418         .trigger_type[4] = HW_TRIP, \
 419         .max_trigger_level = 5, \
 420         .non_hw_trigger_levels = 1, \
 421         .gain = 5, \
 422         .reference_voltage = 16, \
 423         .noise_cancel_mode = 4, \
 424         .cal_type = TYPE_ONE_POINT_TRIMMING, \
 425         .efuse_value = 0x5b2d, \
 426         .min_efuse_value = 16, \
 427         .max_efuse_value = 76, \
 428         .first_point_trim = 25, \
 429         .second_point_trim = 70, \
 430         .default_temp_offset = 25, \
 431         .type = SOC_ARCH_EXYNOS5440, \
 432         .registers = &exynos5440_tmu_registers, \
 433         .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
 434                         TMU_SUPPORT_MULTI_INST | TMU_SUPPORT_ADDRESS_MULTIPLE),
 435
 436 struct exynos_tmu_init_data const exynos5440_default_tmu_data = {
 437         .tmu_data = {
 438                 { EXYNOS5440_TMU_DATA } ,
 439                 { EXYNOS5440_TMU_DATA } ,
 440                 { EXYNOS5440_TMU_DATA } ,
 441         },
 442         .tmu_count = 3,
 443 };
 444 #endif