drivers/thermal/samsung/exynos_tmu_data.c

   1 /*
   2  * exynos_tmu_data.c - Samsung EXYNOS tmu data file
   3  *
   4  *  Copyright (C) 2013 Samsung Electronics
   5  *  Amit Daniel Kachhap <amit.daniel@samsung.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  *
  21  */
  22
  23 #include "exynos_thermal_common.h"
  24 #include "exynos_tmu.h"
  25 #include "exynos_tmu_data.h"
  26
  27 #if defined(CONFIG_CPU_EXYNOS4210)
  28 struct exynos_tmu_init_data const exynos4210_default_tmu_data = {
  29         .tmu_data = {
  30                 {
  31                 .threshold = 80,
  32                 .trigger_levels[0] = 5,
  33                 .trigger_levels[1] = 20,
  34                 .trigger_levels[2] = 30,
  35                 .trigger_enable[0] = true,
  36                 .trigger_enable[1] = true,
  37                 .trigger_enable[2] = true,
  38                 .trigger_enable[3] = false,
  39                 .trigger_type[0] = THROTTLE_ACTIVE,
  40                 .trigger_type[1] = THROTTLE_ACTIVE,
  41                 .trigger_type[2] = SW_TRIP,
  42                 .max_trigger_level = 4,
  43                 .non_hw_trigger_levels = 3,
  44                 .gain = 15,
  45                 .reference_voltage = 7,
  46                 .cal_type = TYPE_ONE_POINT_TRIMMING,
  47                 .min_efuse_value = 40,
  48                 .max_efuse_value = 100,
  49                 .first_point_trim = 25,
  50                 .second_point_trim = 85,
  51                 .default_temp_offset = 50,
  52                 .freq_tab[0] = {
  53                         .freq_clip_max = 800 * 1000,
  54                         .temp_level = 85,
  55                         },
  56                 .freq_tab[1] = {
  57                         .freq_clip_max = 200 * 1000,
  58                         .temp_level = 100,
  59                 },
  60                 .freq_tab_count = 2,
  61                 .type = SOC_ARCH_EXYNOS4210,
  62                 },
  63         },
  64         .tmu_count = 1,
  65 };
  66 #endif
  67
  68 #if defined(CONFIG_SOC_EXYNOS3250)
  69 #define EXYNOS3250_TMU_DATA \
  70         .threshold_falling = 10, \
  71         .trigger_levels[0] = 70, \
  72         .trigger_levels[1] = 95, \
  73         .trigger_levels[2] = 110, \
  74         .trigger_levels[3] = 120, \
  75         .trigger_enable[0] = true, \
  76         .trigger_enable[1] = true, \
  77         .trigger_enable[2] = true, \
  78         .trigger_enable[3] = false, \
  79         .trigger_type[0] = THROTTLE_ACTIVE, \
  80         .trigger_type[1] = THROTTLE_ACTIVE, \
  81         .trigger_type[2] = SW_TRIP, \
  82         .trigger_type[3] = HW_TRIP, \
  83         .max_trigger_level = 4, \
  84         .non_hw_trigger_levels = 3, \
  85         .gain = 8, \
  86         .reference_voltage = 16, \
  87         .noise_cancel_mode = 4, \
  88         .cal_type = TYPE_TWO_POINT_TRIMMING, \
  89         .efuse_value = 55, \
  90         .min_efuse_value = 40, \
  91         .max_efuse_value = 100, \
  92         .first_point_trim = 25, \
  93         .second_point_trim = 85, \
  94         .default_temp_offset = 50, \
  95         .freq_tab[0] = { \
  96                 .freq_clip_max = 800 * 1000, \
  97                 .temp_level = 70, \
  98         }, \
  99         .freq_tab[1] = { \
 100                 .freq_clip_max = 400 * 1000, \
 101                 .temp_level = 95, \
 102         }, \
 103         .freq_tab_count = 2, \
 104         .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
 105                         TMU_SUPPORT_EMUL_TIME)
 106 #endif
 107
 108 #if defined(CONFIG_SOC_EXYNOS3250)
 109 struct exynos_tmu_init_data const exynos3250_default_tmu_data = {
 110         .tmu_data = {
 111                 {
 112                         EXYNOS3250_TMU_DATA,
 113                         .type = SOC_ARCH_EXYNOS3250,
 114                         .test_mux = EXYNOS4412_MUX_ADDR_VALUE,
 115                 },
 116         },
 117         .tmu_count = 1,
 118 };
 119 #endif
 120
 121 #if defined(CONFIG_SOC_EXYNOS4412) || defined(CONFIG_SOC_EXYNOS5250)
 122 #define EXYNOS4412_TMU_DATA \
 123         .threshold_falling = 10, \
 124         .trigger_levels[0] = 70, \
 125         .trigger_levels[1] = 95, \
 126         .trigger_levels[2] = 110, \
 127         .trigger_levels[3] = 120, \
 128         .trigger_enable[0] = true, \
 129         .trigger_enable[1] = true, \
 130         .trigger_enable[2] = true, \
 131         .trigger_enable[3] = false, \
 132         .trigger_type[0] = THROTTLE_ACTIVE, \
 133         .trigger_type[1] = THROTTLE_ACTIVE, \
 134         .trigger_type[2] = SW_TRIP, \
 135         .trigger_type[3] = HW_TRIP, \
 136         .max_trigger_level = 4, \
 137         .non_hw_trigger_levels = 3, \
 138         .gain = 8, \
 139         .reference_voltage = 16, \
 140         .noise_cancel_mode = 4, \
 141         .cal_type = TYPE_ONE_POINT_TRIMMING, \
 142         .efuse_value = 55, \
 143         .min_efuse_value = 40, \
 144         .max_efuse_value = 100, \
 145         .first_point_trim = 25, \
 146         .second_point_trim = 85, \
 147         .default_temp_offset = 50, \
 148         .freq_tab[0] = { \
 149                 .freq_clip_max = 1400 * 1000, \
 150                 .temp_level = 70, \
 151         }, \
 152         .freq_tab[1] = { \
 153                 .freq_clip_max = 400 * 1000, \
 154                 .temp_level = 95, \
 155         }, \
 156         .freq_tab_count = 2, \
 157         .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
 158                         TMU_SUPPORT_EMUL_TIME)
 159 #endif
 160
 161 #if defined(CONFIG_SOC_EXYNOS4412)
 162 struct exynos_tmu_init_data const exynos4412_default_tmu_data = {
 163         .tmu_data = {
 164                 {
 165                         EXYNOS4412_TMU_DATA,
 166                         .type = SOC_ARCH_EXYNOS4412,
 167                         .test_mux = EXYNOS4412_MUX_ADDR_VALUE,
 168                 },
 169         },
 170         .tmu_count = 1,
 171 };
 172 #endif
 173
 174 #if defined(CONFIG_SOC_EXYNOS5250)
 175 struct exynos_tmu_init_data const exynos5250_default_tmu_data = {
 176         .tmu_data = {
 177                 {
 178                         EXYNOS4412_TMU_DATA,
 179                         .type = SOC_ARCH_EXYNOS5250,
 180                 },
 181         },
 182         .tmu_count = 1,
 183 };
 184 #endif
 185
 186 #if defined(CONFIG_SOC_EXYNOS5260)
 187 #define __EXYNOS5260_TMU_DATA   \
 188         .threshold_falling = 10, \
 189         .trigger_levels[0] = 85, \
 190         .trigger_levels[1] = 103, \
 191         .trigger_levels[2] = 110, \
 192         .trigger_levels[3] = 120, \
 193         .trigger_enable[0] = true, \
 194         .trigger_enable[1] = true, \
 195         .trigger_enable[2] = true, \
 196         .trigger_enable[3] = false, \
 197         .trigger_type[0] = THROTTLE_ACTIVE, \
 198         .trigger_type[1] = THROTTLE_ACTIVE, \
 199         .trigger_type[2] = SW_TRIP, \
 200         .trigger_type[3] = HW_TRIP, \
 201         .max_trigger_level = 4, \
 202         .non_hw_trigger_levels = 3, \
 203         .gain = 8, \
 204         .reference_voltage = 16, \
 205         .noise_cancel_mode = 4, \
 206         .cal_type = TYPE_ONE_POINT_TRIMMING, \
 207         .efuse_value = 55, \
 208         .min_efuse_value = 40, \
 209         .max_efuse_value = 100, \
 210         .first_point_trim = 25, \
 211         .second_point_trim = 85, \
 212         .default_temp_offset = 50, \
 213         .freq_tab[0] = { \
 214                 .freq_clip_max = 800 * 1000, \
 215                 .temp_level = 85, \
 216         }, \
 217         .freq_tab[1] = { \
 218                 .freq_clip_max = 200 * 1000, \
 219                 .temp_level = 103, \
 220         }, \
 221         .freq_tab_count = 2, \
 222
 223 #define EXYNOS5260_TMU_DATA \
 224         __EXYNOS5260_TMU_DATA \
 225         .type = SOC_ARCH_EXYNOS5260, \
 226         .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
 227                         TMU_SUPPORT_EMUL_TIME)
 228
 229 struct exynos_tmu_init_data const exynos5260_default_tmu_data = {
 230         .tmu_data = {
 231                 { EXYNOS5260_TMU_DATA },
 232                 { EXYNOS5260_TMU_DATA },
 233                 { EXYNOS5260_TMU_DATA },
 234                 { EXYNOS5260_TMU_DATA },
 235                 { EXYNOS5260_TMU_DATA },
 236         },
 237         .tmu_count = 5,
 238 };
 239 #endif
 240
 241 #if defined(CONFIG_SOC_EXYNOS5420)
 242 #define __EXYNOS5420_TMU_DATA   \
 243         .threshold_falling = 10, \
 244         .trigger_levels[0] = 85, \
 245         .trigger_levels[1] = 103, \
 246         .trigger_levels[2] = 110, \
 247         .trigger_levels[3] = 120, \
 248         .trigger_enable[0] = true, \
 249         .trigger_enable[1] = true, \
 250         .trigger_enable[2] = true, \
 251         .trigger_enable[3] = false, \
 252         .trigger_type[0] = THROTTLE_ACTIVE, \
 253         .trigger_type[1] = THROTTLE_ACTIVE, \
 254         .trigger_type[2] = SW_TRIP, \
 255         .trigger_type[3] = HW_TRIP, \
 256         .max_trigger_level = 4, \
 257         .non_hw_trigger_levels = 3, \
 258         .gain = 8, \
 259         .reference_voltage = 16, \
 260         .noise_cancel_mode = 4, \
 261         .cal_type = TYPE_ONE_POINT_TRIMMING, \
 262         .efuse_value = 55, \
 263         .min_efuse_value = 40, \
 264         .max_efuse_value = 100, \
 265         .first_point_trim = 25, \
 266         .second_point_trim = 85, \
 267         .default_temp_offset = 50, \
 268         .freq_tab[0] = { \
 269                 .freq_clip_max = 800 * 1000, \
 270                 .temp_level = 85, \
 271         }, \
 272         .freq_tab[1] = { \
 273                 .freq_clip_max = 200 * 1000, \
 274                 .temp_level = 103, \
 275         }, \
 276         .freq_tab_count = 2, \
 277
 278 #define EXYNOS5420_TMU_DATA \
 279         __EXYNOS5420_TMU_DATA \
 280         .type = SOC_ARCH_EXYNOS5420, \
 281         .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
 282                         TMU_SUPPORT_EMUL_TIME)
 283
 284 #define EXYNOS5420_TMU_DATA_SHARED \
 285         __EXYNOS5420_TMU_DATA \
 286         .type = SOC_ARCH_EXYNOS5420_TRIMINFO, \
 287         .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
 288                         TMU_SUPPORT_EMUL_TIME | TMU_SUPPORT_ADDRESS_MULTIPLE)
 289
 290 struct exynos_tmu_init_data const exynos5420_default_tmu_data = {
 291         .tmu_data = {
 292                 { EXYNOS5420_TMU_DATA },
 293                 { EXYNOS5420_TMU_DATA },
 294                 { EXYNOS5420_TMU_DATA_SHARED },
 295                 { EXYNOS5420_TMU_DATA_SHARED },
 296                 { EXYNOS5420_TMU_DATA_SHARED },
 297         },
 298         .tmu_count = 5,
 299 };
 300 #endif
 301
 302 #if defined(CONFIG_SOC_EXYNOS5440)
 303 #define EXYNOS5440_TMU_DATA \
 304         .trigger_levels[0] = 100, \
 305         .trigger_levels[4] = 105, \
 306         .trigger_enable[0] = 1, \
 307         .trigger_type[0] = SW_TRIP, \
 308         .trigger_type[4] = HW_TRIP, \
 309         .max_trigger_level = 5, \
 310         .non_hw_trigger_levels = 1, \
 311         .gain = 5, \
 312         .reference_voltage = 16, \
 313         .noise_cancel_mode = 4, \
 314         .cal_type = TYPE_ONE_POINT_TRIMMING, \
 315         .efuse_value = 0x5b2d, \
 316         .min_efuse_value = 16, \
 317         .max_efuse_value = 76, \
 318         .first_point_trim = 25, \
 319         .second_point_trim = 70, \
 320         .default_temp_offset = 25, \
 321         .type = SOC_ARCH_EXYNOS5440, \
 322         .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
 323                         TMU_SUPPORT_MULTI_INST | TMU_SUPPORT_ADDRESS_MULTIPLE),
 324
 325 struct exynos_tmu_init_data const exynos5440_default_tmu_data = {
 326         .tmu_data = {
 327                 { EXYNOS5440_TMU_DATA } ,
 328                 { EXYNOS5440_TMU_DATA } ,
 329                 { EXYNOS5440_TMU_DATA } ,
 330         },
 331         .tmu_count = 3,
 332 };
 333 #endif