2 * exynos_tmu_data.c - Samsung EXYNOS tmu data file
4 * Copyright (C) 2013 Samsung Electronics
5 * Amit Daniel Kachhap <amit.daniel@samsung.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #include "exynos_thermal_common.h"
24 #include "exynos_tmu.h"
25 #include "exynos_tmu_data.h"
27 #if defined(CONFIG_CPU_EXYNOS4210)
28 static const struct exynos_tmu_registers exynos4210_tmu_registers = {
29 .triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
30 .triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
31 .triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
32 .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
33 .buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
34 .buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
35 .buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
36 .buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
37 .core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
38 .tmu_status = EXYNOS_TMU_REG_STATUS,
39 .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
40 .threshold_temp = EXYNOS4210_TMU_REG_THRESHOLD_TEMP,
41 .threshold_th0 = EXYNOS4210_TMU_REG_TRIG_LEVEL0,
42 .tmu_inten = EXYNOS_TMU_REG_INTEN,
43 .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
44 .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
45 .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
46 .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
47 .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
48 .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
49 .intclr_rise_mask = EXYNOS4210_TMU_TRIG_LEVEL_MASK,
52 struct exynos_tmu_init_data const exynos4210_default_tmu_data = {
56 .trigger_levels[0] = 5,
57 .trigger_levels[1] = 20,
58 .trigger_levels[2] = 30,
59 .trigger_enable[0] = true,
60 .trigger_enable[1] = true,
61 .trigger_enable[2] = true,
62 .trigger_enable[3] = false,
63 .trigger_type[0] = THROTTLE_ACTIVE,
64 .trigger_type[1] = THROTTLE_ACTIVE,
65 .trigger_type[2] = SW_TRIP,
66 .max_trigger_level = 4,
68 .reference_voltage = 7,
69 .cal_type = TYPE_ONE_POINT_TRIMMING,
70 .min_efuse_value = 40,
71 .max_efuse_value = 100,
72 .first_point_trim = 25,
73 .second_point_trim = 85,
74 .default_temp_offset = 50,
76 .freq_clip_max = 800 * 1000,
80 .freq_clip_max = 200 * 1000,
84 .type = SOC_ARCH_EXYNOS4210,
85 .registers = &exynos4210_tmu_registers,
86 .features = TMU_SUPPORT_READY_STATUS,
93 #if defined(CONFIG_SOC_EXYNOS3250)
94 static const struct exynos_tmu_registers exynos3250_tmu_registers = {
95 .triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
96 .triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
97 .triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
98 .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
99 .test_mux_addr_shift = EXYNOS4412_MUX_ADDR_SHIFT,
100 .buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
101 .buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
102 .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
103 .therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
104 .therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
105 .buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
106 .buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
107 .core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
108 .tmu_status = EXYNOS_TMU_REG_STATUS,
109 .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
110 .threshold_th0 = EXYNOS_THD_TEMP_RISE,
111 .threshold_th1 = EXYNOS_THD_TEMP_FALL,
112 .tmu_inten = EXYNOS_TMU_REG_INTEN,
113 .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
114 .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
115 .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
116 .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
117 .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
118 .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
119 .intclr_fall_shift = EXYNOS_TMU_CLEAR_FALL_INT_SHIFT,
120 .intclr_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
121 .intclr_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
122 .intclr_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
123 .emul_con = EXYNOS_EMUL_CON,
124 .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
125 .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
128 #define EXYNOS3250_TMU_DATA \
129 .threshold_falling = 10, \
130 .trigger_levels[0] = 70, \
131 .trigger_levels[1] = 95, \
132 .trigger_levels[2] = 110, \
133 .trigger_levels[3] = 120, \
134 .trigger_enable[0] = true, \
135 .trigger_enable[1] = true, \
136 .trigger_enable[2] = true, \
137 .trigger_enable[3] = false, \
138 .trigger_type[0] = THROTTLE_ACTIVE, \
139 .trigger_type[1] = THROTTLE_ACTIVE, \
140 .trigger_type[2] = SW_TRIP, \
141 .trigger_type[3] = HW_TRIP, \
142 .max_trigger_level = 4, \
144 .reference_voltage = 16, \
145 .noise_cancel_mode = 4, \
146 .cal_type = TYPE_TWO_POINT_TRIMMING, \
148 .min_efuse_value = 40, \
149 .max_efuse_value = 100, \
150 .first_point_trim = 25, \
151 .second_point_trim = 85, \
152 .default_temp_offset = 50, \
154 .freq_clip_max = 800 * 1000, \
158 .freq_clip_max = 400 * 1000, \
161 .freq_tab_count = 2, \
162 .registers = &exynos3250_tmu_registers, \
163 .features = (TMU_SUPPORT_EMULATION | \
164 TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
165 TMU_SUPPORT_EMUL_TIME)
168 #if defined(CONFIG_SOC_EXYNOS3250)
169 struct exynos_tmu_init_data const exynos3250_default_tmu_data = {
173 .type = SOC_ARCH_EXYNOS3250,
174 .test_mux = EXYNOS4412_MUX_ADDR_VALUE,
181 #if defined(CONFIG_SOC_EXYNOS4412) || defined(CONFIG_SOC_EXYNOS5250)
182 static const struct exynos_tmu_registers exynos4412_tmu_registers = {
183 .triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
184 .triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
185 .triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
186 .triminfo_ctrl = EXYNOS_TMU_TRIMINFO_CON,
187 .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
188 .test_mux_addr_shift = EXYNOS4412_MUX_ADDR_SHIFT,
189 .buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
190 .buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
191 .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
192 .therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
193 .therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
194 .buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
195 .buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
196 .core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
197 .tmu_status = EXYNOS_TMU_REG_STATUS,
198 .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
199 .threshold_th0 = EXYNOS_THD_TEMP_RISE,
200 .threshold_th1 = EXYNOS_THD_TEMP_FALL,
201 .tmu_inten = EXYNOS_TMU_REG_INTEN,
202 .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
203 .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
204 .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
205 .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
206 .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
207 .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
208 .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
209 .intclr_fall_shift = EXYNOS_TMU_CLEAR_FALL_INT_SHIFT,
210 .intclr_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
211 .intclr_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
212 .intclr_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
213 .emul_con = EXYNOS_EMUL_CON,
214 .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
215 .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
218 #define EXYNOS4412_TMU_DATA \
219 .threshold_falling = 10, \
220 .trigger_levels[0] = 70, \
221 .trigger_levels[1] = 95, \
222 .trigger_levels[2] = 110, \
223 .trigger_levels[3] = 120, \
224 .trigger_enable[0] = true, \
225 .trigger_enable[1] = true, \
226 .trigger_enable[2] = true, \
227 .trigger_enable[3] = false, \
228 .trigger_type[0] = THROTTLE_ACTIVE, \
229 .trigger_type[1] = THROTTLE_ACTIVE, \
230 .trigger_type[2] = SW_TRIP, \
231 .trigger_type[3] = HW_TRIP, \
232 .max_trigger_level = 4, \
234 .reference_voltage = 16, \
235 .noise_cancel_mode = 4, \
236 .cal_type = TYPE_ONE_POINT_TRIMMING, \
238 .min_efuse_value = 40, \
239 .max_efuse_value = 100, \
240 .first_point_trim = 25, \
241 .second_point_trim = 85, \
242 .default_temp_offset = 50, \
244 .freq_clip_max = 1400 * 1000, \
248 .freq_clip_max = 400 * 1000, \
251 .freq_tab_count = 2, \
252 .registers = &exynos4412_tmu_registers, \
253 .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
254 TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
255 TMU_SUPPORT_EMUL_TIME)
258 #if defined(CONFIG_SOC_EXYNOS4412)
259 struct exynos_tmu_init_data const exynos4412_default_tmu_data = {
263 .type = SOC_ARCH_EXYNOS4412,
264 .test_mux = EXYNOS4412_MUX_ADDR_VALUE,
271 #if defined(CONFIG_SOC_EXYNOS5250)
272 struct exynos_tmu_init_data const exynos5250_default_tmu_data = {
276 .type = SOC_ARCH_EXYNOS5250,
283 #if defined(CONFIG_SOC_EXYNOS5260)
284 static const struct exynos_tmu_registers exynos5260_tmu_registers = {
285 .triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
286 .triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
287 .triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
288 .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
289 .tmu_ctrl = EXYNOS_TMU_REG_CONTROL1,
290 .buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
291 .buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
292 .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
293 .therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
294 .therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
295 .buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
296 .buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
297 .core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
298 .tmu_status = EXYNOS_TMU_REG_STATUS,
299 .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
300 .threshold_th0 = EXYNOS_THD_TEMP_RISE,
301 .threshold_th1 = EXYNOS_THD_TEMP_FALL,
302 .tmu_inten = EXYNOS5260_TMU_REG_INTEN,
303 .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
304 .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
305 .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
306 .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
307 .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
308 .tmu_intstat = EXYNOS5260_TMU_REG_INTSTAT,
309 .tmu_intclear = EXYNOS5260_TMU_REG_INTCLEAR,
310 .intclr_fall_shift = EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT,
311 .intclr_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
312 .intclr_rise_mask = EXYNOS5260_TMU_RISE_INT_MASK,
313 .intclr_fall_mask = EXYNOS5260_TMU_FALL_INT_MASK,
314 .emul_con = EXYNOS5260_EMUL_CON,
315 .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
316 .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
319 #define __EXYNOS5260_TMU_DATA \
320 .threshold_falling = 10, \
321 .trigger_levels[0] = 85, \
322 .trigger_levels[1] = 103, \
323 .trigger_levels[2] = 110, \
324 .trigger_levels[3] = 120, \
325 .trigger_enable[0] = true, \
326 .trigger_enable[1] = true, \
327 .trigger_enable[2] = true, \
328 .trigger_enable[3] = false, \
329 .trigger_type[0] = THROTTLE_ACTIVE, \
330 .trigger_type[1] = THROTTLE_ACTIVE, \
331 .trigger_type[2] = SW_TRIP, \
332 .trigger_type[3] = HW_TRIP, \
333 .max_trigger_level = 4, \
335 .reference_voltage = 16, \
336 .noise_cancel_mode = 4, \
337 .cal_type = TYPE_ONE_POINT_TRIMMING, \
339 .min_efuse_value = 40, \
340 .max_efuse_value = 100, \
341 .first_point_trim = 25, \
342 .second_point_trim = 85, \
343 .default_temp_offset = 50, \
345 .freq_clip_max = 800 * 1000, \
349 .freq_clip_max = 200 * 1000, \
352 .freq_tab_count = 2, \
353 .registers = &exynos5260_tmu_registers, \
355 #define EXYNOS5260_TMU_DATA \
356 __EXYNOS5260_TMU_DATA \
357 .type = SOC_ARCH_EXYNOS5260, \
358 .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
359 TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
360 TMU_SUPPORT_EMUL_TIME)
362 struct exynos_tmu_init_data const exynos5260_default_tmu_data = {
364 { EXYNOS5260_TMU_DATA },
365 { EXYNOS5260_TMU_DATA },
366 { EXYNOS5260_TMU_DATA },
367 { EXYNOS5260_TMU_DATA },
368 { EXYNOS5260_TMU_DATA },
374 #if defined(CONFIG_SOC_EXYNOS5420)
375 static const struct exynos_tmu_registers exynos5420_tmu_registers = {
376 .triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
377 .triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
378 .triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
379 .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
380 .buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
381 .buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
382 .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
383 .therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
384 .therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
385 .buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
386 .buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
387 .core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
388 .tmu_status = EXYNOS_TMU_REG_STATUS,
389 .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
390 .threshold_th0 = EXYNOS_THD_TEMP_RISE,
391 .threshold_th1 = EXYNOS_THD_TEMP_FALL,
392 .tmu_inten = EXYNOS_TMU_REG_INTEN,
393 .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
394 .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
395 .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
396 /* INTEN_RISE3 Not availble in exynos5420 */
397 .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
398 .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
399 .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
400 .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
401 .intclr_fall_shift = EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT,
402 .intclr_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
403 .intclr_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
404 .intclr_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
405 .emul_con = EXYNOS_EMUL_CON,
406 .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
407 .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
410 #define __EXYNOS5420_TMU_DATA \
411 .threshold_falling = 10, \
412 .trigger_levels[0] = 85, \
413 .trigger_levels[1] = 103, \
414 .trigger_levels[2] = 110, \
415 .trigger_levels[3] = 120, \
416 .trigger_enable[0] = true, \
417 .trigger_enable[1] = true, \
418 .trigger_enable[2] = true, \
419 .trigger_enable[3] = false, \
420 .trigger_type[0] = THROTTLE_ACTIVE, \
421 .trigger_type[1] = THROTTLE_ACTIVE, \
422 .trigger_type[2] = SW_TRIP, \
423 .trigger_type[3] = HW_TRIP, \
424 .max_trigger_level = 4, \
426 .reference_voltage = 16, \
427 .noise_cancel_mode = 4, \
428 .cal_type = TYPE_ONE_POINT_TRIMMING, \
430 .min_efuse_value = 40, \
431 .max_efuse_value = 100, \
432 .first_point_trim = 25, \
433 .second_point_trim = 85, \
434 .default_temp_offset = 50, \
436 .freq_clip_max = 800 * 1000, \
440 .freq_clip_max = 200 * 1000, \
443 .freq_tab_count = 2, \
444 .registers = &exynos5420_tmu_registers, \
446 #define EXYNOS5420_TMU_DATA \
447 __EXYNOS5420_TMU_DATA \
448 .type = SOC_ARCH_EXYNOS5250, \
449 .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
450 TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
451 TMU_SUPPORT_EMUL_TIME)
453 #define EXYNOS5420_TMU_DATA_SHARED \
454 __EXYNOS5420_TMU_DATA \
455 .type = SOC_ARCH_EXYNOS5420_TRIMINFO, \
456 .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
457 TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
458 TMU_SUPPORT_EMUL_TIME | TMU_SUPPORT_ADDRESS_MULTIPLE)
460 struct exynos_tmu_init_data const exynos5420_default_tmu_data = {
462 { EXYNOS5420_TMU_DATA },
463 { EXYNOS5420_TMU_DATA },
464 { EXYNOS5420_TMU_DATA_SHARED },
465 { EXYNOS5420_TMU_DATA_SHARED },
466 { EXYNOS5420_TMU_DATA_SHARED },
472 #if defined(CONFIG_SOC_EXYNOS5440)
473 static const struct exynos_tmu_registers exynos5440_tmu_registers = {
474 .triminfo_data = EXYNOS5440_TMU_S0_7_TRIM,
475 .triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
476 .triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
477 .tmu_ctrl = EXYNOS5440_TMU_S0_7_CTRL,
478 .buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
479 .buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
480 .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
481 .therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
482 .therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
483 .buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
484 .buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
485 .core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
486 .tmu_status = EXYNOS5440_TMU_S0_7_STATUS,
487 .tmu_cur_temp = EXYNOS5440_TMU_S0_7_TEMP,
488 .threshold_th0 = EXYNOS5440_TMU_S0_7_TH0,
489 .threshold_th1 = EXYNOS5440_TMU_S0_7_TH1,
490 .threshold_th2 = EXYNOS5440_TMU_S0_7_TH2,
491 .threshold_th3_l0_shift = EXYNOS5440_TMU_TH_RISE4_SHIFT,
492 .tmu_inten = EXYNOS5440_TMU_S0_7_IRQEN,
493 .inten_rise0_shift = EXYNOS5440_TMU_INTEN_RISE0_SHIFT,
494 .inten_rise1_shift = EXYNOS5440_TMU_INTEN_RISE1_SHIFT,
495 .inten_rise2_shift = EXYNOS5440_TMU_INTEN_RISE2_SHIFT,
496 .inten_rise3_shift = EXYNOS5440_TMU_INTEN_RISE3_SHIFT,
497 .inten_fall0_shift = EXYNOS5440_TMU_INTEN_FALL0_SHIFT,
498 .tmu_intstat = EXYNOS5440_TMU_S0_7_IRQ,
499 .tmu_intclear = EXYNOS5440_TMU_S0_7_IRQ,
500 .intclr_fall_shift = EXYNOS5440_TMU_CLEAR_FALL_INT_SHIFT,
501 .intclr_rise_shift = EXYNOS5440_TMU_RISE_INT_SHIFT,
502 .intclr_rise_mask = EXYNOS5440_TMU_RISE_INT_MASK,
503 .intclr_fall_mask = EXYNOS5440_TMU_FALL_INT_MASK,
504 .tmu_irqstatus = EXYNOS5440_TMU_IRQ_STATUS,
505 .emul_con = EXYNOS5440_TMU_S0_7_DEBUG,
506 .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
507 .tmu_pmin = EXYNOS5440_TMU_PMIN,
510 #define EXYNOS5440_TMU_DATA \
511 .trigger_levels[0] = 100, \
512 .trigger_levels[4] = 105, \
513 .trigger_enable[0] = 1, \
514 .trigger_type[0] = SW_TRIP, \
515 .trigger_type[4] = HW_TRIP, \
516 .max_trigger_level = 5, \
518 .reference_voltage = 16, \
519 .noise_cancel_mode = 4, \
520 .cal_type = TYPE_ONE_POINT_TRIMMING, \
521 .efuse_value = 0x5b2d, \
522 .min_efuse_value = 16, \
523 .max_efuse_value = 76, \
524 .first_point_trim = 25, \
525 .second_point_trim = 70, \
526 .default_temp_offset = 25, \
527 .type = SOC_ARCH_EXYNOS5440, \
528 .registers = &exynos5440_tmu_registers, \
529 .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
530 TMU_SUPPORT_MULTI_INST | TMU_SUPPORT_ADDRESS_MULTIPLE),
532 struct exynos_tmu_init_data const exynos5440_default_tmu_data = {
534 { EXYNOS5440_TMU_DATA } ,
535 { EXYNOS5440_TMU_DATA } ,
536 { EXYNOS5440_TMU_DATA } ,