2 * exynos_tmu_data.h - Samsung EXYNOS tmu data header file
4 * Copyright (C) 2013 Samsung Electronics
5 * Amit Daniel Kachhap <amit.daniel@samsung.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #ifndef _EXYNOS_TMU_DATA_H
24 #define _EXYNOS_TMU_DATA_H
26 /* Exynos generic registers */
27 #define EXYNOS_TMU_REG_TRIMINFO 0x0
28 #define EXYNOS_TMU_REG_CONTROL 0x20
29 #define EXYNOS_TMU_REG_STATUS 0x28
30 #define EXYNOS_TMU_REG_CURRENT_TEMP 0x40
31 #define EXYNOS_TMU_REG_INTEN 0x70
32 #define EXYNOS_TMU_REG_INTSTAT 0x74
33 #define EXYNOS_TMU_REG_INTCLEAR 0x78
35 #define EXYNOS_TMU_TEMP_MASK 0xff
36 #define EXYNOS_TMU_REF_VOLTAGE_SHIFT 24
37 #define EXYNOS_TMU_REF_VOLTAGE_MASK 0x1f
38 #define EXYNOS_TMU_BUF_SLOPE_SEL_MASK 0xf
39 #define EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT 8
40 #define EXYNOS_TMU_CORE_EN_SHIFT 0
42 /* Exynos4210 specific registers */
43 #define EXYNOS4210_TMU_REG_THRESHOLD_TEMP 0x44
44 #define EXYNOS4210_TMU_REG_TRIG_LEVEL0 0x50
45 #define EXYNOS4210_TMU_REG_TRIG_LEVEL1 0x54
46 #define EXYNOS4210_TMU_REG_TRIG_LEVEL2 0x58
47 #define EXYNOS4210_TMU_REG_TRIG_LEVEL3 0x5C
48 #define EXYNOS4210_TMU_REG_PAST_TEMP0 0x60
49 #define EXYNOS4210_TMU_REG_PAST_TEMP1 0x64
50 #define EXYNOS4210_TMU_REG_PAST_TEMP2 0x68
51 #define EXYNOS4210_TMU_REG_PAST_TEMP3 0x6C
53 #define EXYNOS4210_TMU_TRIG_LEVEL0_MASK 0x1
54 #define EXYNOS4210_TMU_TRIG_LEVEL1_MASK 0x10
55 #define EXYNOS4210_TMU_TRIG_LEVEL2_MASK 0x100
56 #define EXYNOS4210_TMU_TRIG_LEVEL3_MASK 0x1000
57 #define EXYNOS4210_TMU_TRIG_LEVEL_MASK 0x1111
58 #define EXYNOS4210_TMU_INTCLEAR_VAL 0x1111
60 /* Exynos5250 and Exynos4412 specific registers */
61 #define EXYNOS_TMU_TRIMINFO_CON 0x14
62 #define EXYNOS_THD_TEMP_RISE 0x50
63 #define EXYNOS_THD_TEMP_FALL 0x54
64 #define EXYNOS_EMUL_CON 0x80
66 #define EXYNOS_TRIMINFO_RELOAD_SHIFT 1
67 #define EXYNOS_TRIMINFO_25_SHIFT 0
68 #define EXYNOS_TRIMINFO_85_SHIFT 8
69 #define EXYNOS_TMU_RISE_INT_MASK 0x111
70 #define EXYNOS_TMU_RISE_INT_SHIFT 0
71 #define EXYNOS_TMU_FALL_INT_MASK 0x111
72 #define EXYNOS_TMU_FALL_INT_SHIFT 12
73 #define EXYNOS_TMU_CLEAR_RISE_INT 0x111
74 #define EXYNOS_TMU_CLEAR_FALL_INT (0x111 << 12)
75 #define EXYNOS_TMU_TRIP_MODE_SHIFT 13
76 #define EXYNOS_TMU_TRIP_MODE_MASK 0x7
77 #define EXYNOS_TMU_THERM_TRIP_EN_SHIFT 12
79 #define EXYNOS_TMU_INTEN_RISE0_SHIFT 0
80 #define EXYNOS_TMU_INTEN_RISE1_SHIFT 4
81 #define EXYNOS_TMU_INTEN_RISE2_SHIFT 8
82 #define EXYNOS_TMU_INTEN_RISE3_SHIFT 12
83 #define EXYNOS_TMU_INTEN_FALL0_SHIFT 16
84 #define EXYNOS_TMU_INTEN_FALL1_SHIFT 20
85 #define EXYNOS_TMU_INTEN_FALL2_SHIFT 24
87 #define EXYNOS_EMUL_TIME 0x57F0
88 #define EXYNOS_EMUL_TIME_MASK 0xffff
89 #define EXYNOS_EMUL_TIME_SHIFT 16
90 #define EXYNOS_EMUL_DATA_SHIFT 8
91 #define EXYNOS_EMUL_DATA_MASK 0xFF
92 #define EXYNOS_EMUL_ENABLE 0x1
94 #if defined(CONFIG_CPU_EXYNOS4210)
95 extern struct exynos_tmu_platform_data const exynos4210_default_tmu_data;
96 #define EXYNOS4210_TMU_DRV_DATA (&exynos4210_default_tmu_data)
98 #define EXYNOS4210_TMU_DRV_DATA (NULL)
101 #if (defined(CONFIG_SOC_EXYNOS5250) || defined(CONFIG_SOC_EXYNOS4412))
102 extern struct exynos_tmu_platform_data const exynos5250_default_tmu_data;
103 #define EXYNOS5250_TMU_DRV_DATA (&exynos5250_default_tmu_data)
105 #define EXYNOS5250_TMU_DRV_DATA (NULL)
108 #endif /*_EXYNOS_TMU_DATA_H*/