2 * exynos_tmu_data.h - Samsung EXYNOS tmu data header file
4 * Copyright (C) 2013 Samsung Electronics
5 * Amit Daniel Kachhap <amit.daniel@samsung.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #ifndef _EXYNOS_TMU_DATA_H
24 #define _EXYNOS_TMU_DATA_H
26 /* Exynos generic registers */
27 #define EXYNOS_TMU_REG_TRIMINFO 0x0
28 #define EXYNOS_TMU_REG_CONTROL 0x20
29 #define EXYNOS_TMU_REG_STATUS 0x28
30 #define EXYNOS_TMU_REG_CURRENT_TEMP 0x40
31 #define EXYNOS_TMU_REG_INTEN 0x70
32 #define EXYNOS_TMU_REG_INTSTAT 0x74
33 #define EXYNOS_TMU_REG_INTCLEAR 0x78
35 #define EXYNOS_TMU_TEMP_MASK 0xff
36 #define EXYNOS_TMU_REF_VOLTAGE_SHIFT 24
37 #define EXYNOS_TMU_REF_VOLTAGE_MASK 0x1f
38 #define EXYNOS_TMU_BUF_SLOPE_SEL_MASK 0xf
39 #define EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT 8
40 #define EXYNOS_TMU_CORE_EN_SHIFT 0
42 /* Exynos4210 specific registers */
43 #define EXYNOS4210_TMU_REG_THRESHOLD_TEMP 0x44
44 #define EXYNOS4210_TMU_REG_TRIG_LEVEL0 0x50
46 #define EXYNOS4210_TMU_TRIG_LEVEL_MASK 0x1111
48 /* Exynos5250 and Exynos4412 specific registers */
49 #define EXYNOS_TMU_TRIMINFO_CON 0x14
50 #define EXYNOS_THD_TEMP_RISE 0x50
51 #define EXYNOS_THD_TEMP_FALL 0x54
52 #define EXYNOS_EMUL_CON 0x80
54 #define EXYNOS_TRIMINFO_25_SHIFT 0
55 #define EXYNOS_TRIMINFO_85_SHIFT 8
56 #define EXYNOS_TMU_RISE_INT_MASK 0x111
57 #define EXYNOS_TMU_RISE_INT_SHIFT 0
58 #define EXYNOS_TMU_FALL_INT_MASK 0x111
59 #define EXYNOS_TMU_CLEAR_FALL_INT_SHIFT 12
60 #define EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT 16
61 #define EXYNOS5440_TMU_CLEAR_FALL_INT_SHIFT 4
62 #define EXYNOS_TMU_TRIP_MODE_SHIFT 13
63 #define EXYNOS_TMU_TRIP_MODE_MASK 0x7
64 #define EXYNOS_TMU_THERM_TRIP_EN_SHIFT 12
66 #define EXYNOS_TMU_INTEN_RISE0_SHIFT 0
67 #define EXYNOS_TMU_INTEN_RISE1_SHIFT 4
68 #define EXYNOS_TMU_INTEN_RISE2_SHIFT 8
69 #define EXYNOS_TMU_INTEN_RISE3_SHIFT 12
70 #define EXYNOS_TMU_INTEN_FALL0_SHIFT 16
72 #define EXYNOS_EMUL_TIME 0x57F0
73 #define EXYNOS_EMUL_TIME_MASK 0xffff
74 #define EXYNOS_EMUL_TIME_SHIFT 16
75 #define EXYNOS_EMUL_DATA_SHIFT 8
76 #define EXYNOS_EMUL_DATA_MASK 0xFF
77 #define EXYNOS_EMUL_ENABLE 0x1
79 #define EXYNOS_MAX_TRIGGER_PER_REG 4
81 /* Exynos5260 specific */
82 #define EXYNOS_TMU_REG_CONTROL1 0x24
83 #define EXYNOS5260_TMU_REG_INTEN 0xC0
84 #define EXYNOS5260_TMU_REG_INTSTAT 0xC4
85 #define EXYNOS5260_TMU_REG_INTCLEAR 0xC8
86 #define EXYNOS5260_TMU_CLEAR_RISE_INT 0x1111
87 #define EXYNOS5260_TMU_CLEAR_FALL_INT (0x1111 << 16)
88 #define EXYNOS5260_TMU_RISE_INT_MASK 0x1111
89 #define EXYNOS5260_TMU_FALL_INT_MASK 0x1111
90 #define EXYNOS5260_EMUL_CON 0x100
92 /* Exynos4412 specific */
93 #define EXYNOS4412_MUX_ADDR_VALUE 6
94 #define EXYNOS4412_MUX_ADDR_SHIFT 20
96 /*exynos5440 specific registers*/
97 #define EXYNOS5440_TMU_S0_7_TRIM 0x000
98 #define EXYNOS5440_TMU_S0_7_CTRL 0x020
99 #define EXYNOS5440_TMU_S0_7_DEBUG 0x040
100 #define EXYNOS5440_TMU_S0_7_STATUS 0x060
101 #define EXYNOS5440_TMU_S0_7_TEMP 0x0f0
102 #define EXYNOS5440_TMU_S0_7_TH0 0x110
103 #define EXYNOS5440_TMU_S0_7_TH1 0x130
104 #define EXYNOS5440_TMU_S0_7_TH2 0x150
105 #define EXYNOS5440_TMU_S0_7_IRQEN 0x210
106 #define EXYNOS5440_TMU_S0_7_IRQ 0x230
107 /* exynos5440 common registers */
108 #define EXYNOS5440_TMU_IRQ_STATUS 0x000
109 #define EXYNOS5440_TMU_PMIN 0x004
111 #define EXYNOS5440_TMU_RISE_INT_MASK 0xf
112 #define EXYNOS5440_TMU_RISE_INT_SHIFT 0
113 #define EXYNOS5440_TMU_FALL_INT_MASK 0xf
114 #define EXYNOS5440_TMU_INTEN_RISE0_SHIFT 0
115 #define EXYNOS5440_TMU_INTEN_RISE1_SHIFT 1
116 #define EXYNOS5440_TMU_INTEN_RISE2_SHIFT 2
117 #define EXYNOS5440_TMU_INTEN_RISE3_SHIFT 3
118 #define EXYNOS5440_TMU_INTEN_FALL0_SHIFT 4
119 #define EXYNOS5440_TMU_TH_RISE4_SHIFT 24
120 #define EXYNOS5440_EFUSE_SWAP_OFFSET 8
122 #if defined(CONFIG_SOC_EXYNOS3250)
123 extern struct exynos_tmu_init_data const exynos3250_default_tmu_data;
124 #define EXYNOS3250_TMU_DRV_DATA (&exynos3250_default_tmu_data)
126 #define EXYNOS3250_TMU_DRV_DATA (NULL)
129 #if defined(CONFIG_CPU_EXYNOS4210)
130 extern struct exynos_tmu_init_data const exynos4210_default_tmu_data;
131 #define EXYNOS4210_TMU_DRV_DATA (&exynos4210_default_tmu_data)
133 #define EXYNOS4210_TMU_DRV_DATA (NULL)
136 #if defined(CONFIG_SOC_EXYNOS4412)
137 extern struct exynos_tmu_init_data const exynos4412_default_tmu_data;
138 #define EXYNOS4412_TMU_DRV_DATA (&exynos4412_default_tmu_data)
140 #define EXYNOS4412_TMU_DRV_DATA (NULL)
143 #if defined(CONFIG_SOC_EXYNOS5250)
144 extern struct exynos_tmu_init_data const exynos5250_default_tmu_data;
145 #define EXYNOS5250_TMU_DRV_DATA (&exynos5250_default_tmu_data)
147 #define EXYNOS5250_TMU_DRV_DATA (NULL)
150 #if defined(CONFIG_SOC_EXYNOS5260)
151 extern struct exynos_tmu_init_data const exynos5260_default_tmu_data;
152 #define EXYNOS5260_TMU_DRV_DATA (&exynos5260_default_tmu_data)
154 #define EXYNOS5260_TMU_DRV_DATA (NULL)
157 #if defined(CONFIG_SOC_EXYNOS5420)
158 extern struct exynos_tmu_init_data const exynos5420_default_tmu_data;
159 #define EXYNOS5420_TMU_DRV_DATA (&exynos5420_default_tmu_data)
161 #define EXYNOS5420_TMU_DRV_DATA (NULL)
164 #if defined(CONFIG_SOC_EXYNOS5440)
165 extern struct exynos_tmu_init_data const exynos5440_default_tmu_data;
166 #define EXYNOS5440_TMU_DRV_DATA (&exynos5440_default_tmu_data)
168 #define EXYNOS5440_TMU_DRV_DATA (NULL)
171 #endif /*_EXYNOS_TMU_DATA_H*/