2 * Thunderbolt Cactus Ridge driver - eeprom access
4 * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
7 #include <linux/crc32.h>
11 * tb_eeprom_ctl_write() - write control word
13 static int tb_eeprom_ctl_write(struct tb_switch *sw, struct tb_eeprom_ctl *ctl)
15 return tb_sw_write(sw, ctl, TB_CFG_SWITCH, sw->cap_plug_events + 4, 1);
19 * tb_eeprom_ctl_write() - read control word
21 static int tb_eeprom_ctl_read(struct tb_switch *sw, struct tb_eeprom_ctl *ctl)
23 return tb_sw_read(sw, ctl, TB_CFG_SWITCH, sw->cap_plug_events + 4, 1);
26 enum tb_eeprom_transfer {
32 * tb_eeprom_active - enable rom access
34 * WARNING: Always disable access after usage. Otherwise the controller will
37 static int tb_eeprom_active(struct tb_switch *sw, bool enable)
39 struct tb_eeprom_ctl ctl;
40 int res = tb_eeprom_ctl_read(sw, &ctl);
45 res = tb_eeprom_ctl_write(sw, &ctl);
49 return tb_eeprom_ctl_write(sw, &ctl);
52 res = tb_eeprom_ctl_write(sw, &ctl);
56 return tb_eeprom_ctl_write(sw, &ctl);
61 * tb_eeprom_transfer - transfer one bit
63 * If TB_EEPROM_IN is passed, then the bit can be retrieved from ctl->data_in.
64 * If TB_EEPROM_OUT is passed, then ctl->data_out will be written.
66 static int tb_eeprom_transfer(struct tb_switch *sw, struct tb_eeprom_ctl *ctl,
67 enum tb_eeprom_transfer direction)
70 if (direction == TB_EEPROM_OUT) {
71 res = tb_eeprom_ctl_write(sw, ctl);
76 res = tb_eeprom_ctl_write(sw, ctl);
79 if (direction == TB_EEPROM_IN) {
80 res = tb_eeprom_ctl_read(sw, ctl);
85 return tb_eeprom_ctl_write(sw, ctl);
89 * tb_eeprom_out - write one byte to the bus
91 static int tb_eeprom_out(struct tb_switch *sw, u8 val)
93 struct tb_eeprom_ctl ctl;
95 int res = tb_eeprom_ctl_read(sw, &ctl);
98 for (i = 0; i < 8; i++) {
99 ctl.data_out = val & 0x80;
100 res = tb_eeprom_transfer(sw, &ctl, TB_EEPROM_OUT);
109 * tb_eeprom_in - read one byte from the bus
111 static int tb_eeprom_in(struct tb_switch *sw, u8 *val)
113 struct tb_eeprom_ctl ctl;
115 int res = tb_eeprom_ctl_read(sw, &ctl);
119 for (i = 0; i < 8; i++) {
121 res = tb_eeprom_transfer(sw, &ctl, TB_EEPROM_IN);
130 * tb_eeprom_read_n - read count bytes from offset into val
132 static int tb_eeprom_read_n(struct tb_switch *sw, u16 offset, u8 *val,
136 res = tb_eeprom_active(sw, true);
139 res = tb_eeprom_out(sw, 3);
142 res = tb_eeprom_out(sw, offset >> 8);
145 res = tb_eeprom_out(sw, offset);
148 for (i = 0; i < count; i++) {
149 res = tb_eeprom_in(sw, val + i);
153 return tb_eeprom_active(sw, false);
156 static u8 tb_crc8(u8 *data, int len)
160 for (i = 0; i < len; i++) {
162 for (j = 0; j < 8; j++)
163 val = (val << 1) ^ ((val & 0x80) ? 7 : 0);
168 static u32 tb_crc32(void *data, size_t len)
170 return ~__crc32c_le(~0, data, len);
173 #define TB_DROM_DATA_START 13
174 struct tb_drom_header {
176 u8 uid_crc8; /* checksum for uid */
180 u32 data_crc32; /* checksum for data_len bytes starting at byte 13 */
182 u8 device_rom_revision; /* should be <= 1 */
192 enum tb_drom_entry_type {
193 TB_DROM_ENTRY_GENERIC,
197 struct tb_drom_entry_header {
200 bool port_disabled:1; /* only valid if type is TB_DROM_ENTRY_PORT */
201 enum tb_drom_entry_type type:1;
204 struct tb_drom_entry_port {
206 struct tb_drom_entry_header header;
208 u8 dual_link_port_rid:4;
211 bool has_dual_link_port:1;
214 u8 dual_link_port_nr:6;
217 /* BYTES 4 - 5 TODO decode */
222 /* BYTES 5-6, TODO: verify (find hardware that has these set) */
225 bool has_peer_port:1;
232 * tb_eeprom_get_drom_offset - get drom offset within eeprom
234 int tb_eeprom_get_drom_offset(struct tb_switch *sw, u16 *offset)
236 struct tb_cap_plug_events cap;
238 if (!sw->cap_plug_events) {
239 tb_sw_warn(sw, "no TB_CAP_PLUG_EVENTS, cannot read eeprom\n");
242 res = tb_sw_read(sw, &cap, TB_CFG_SWITCH, sw->cap_plug_events,
247 if (!cap.eeprom_ctl.present || cap.eeprom_ctl.not_present) {
248 tb_sw_warn(sw, "no NVM\n");
252 if (cap.drom_offset > 0xffff) {
253 tb_sw_warn(sw, "drom offset is larger than 0xffff: %#x\n",
257 *offset = cap.drom_offset;
262 * tb_drom_read_uid_only - read uid directly from drom
264 * Does not use the cached copy in sw->drom. Used during resume to check switch
267 int tb_drom_read_uid_only(struct tb_switch *sw, u64 *uid)
272 int res = tb_eeprom_get_drom_offset(sw, &drom_offset);
277 res = tb_eeprom_read_n(sw, drom_offset, data, 9);
281 crc = tb_crc8(data + 1, 8);
282 if (crc != data[0]) {
283 tb_sw_warn(sw, "uid crc8 missmatch (expected: %#x, got: %#x)\n",
288 *uid = *(u64 *)(data+1);
292 static void tb_drom_parse_port_entry(struct tb_port *port,
293 struct tb_drom_entry_port *entry)
295 port->link_nr = entry->link_nr;
296 if (entry->has_dual_link_port)
297 port->dual_link_port =
298 &port->sw->ports[entry->dual_link_port_nr];
301 static int tb_drom_parse_entry(struct tb_switch *sw,
302 struct tb_drom_entry_header *header)
304 struct tb_port *port;
306 enum tb_port_type type;
308 if (header->type != TB_DROM_ENTRY_PORT)
311 port = &sw->ports[header->index];
312 port->disabled = header->port_disabled;
316 res = tb_port_read(port, &type, TB_CFG_PORT, 2, 1);
321 if (type == TB_TYPE_PORT) {
322 struct tb_drom_entry_port *entry = (void *) header;
323 if (header->len != sizeof(*entry)) {
325 "port entry has size %#x (expected %#lx)\n",
326 header->len, sizeof(struct tb_drom_entry_port));
329 tb_drom_parse_port_entry(port, entry);
335 * tb_drom_parse_entries - parse the linked list of drom entries
337 * Drom must have been copied to sw->drom.
339 static int tb_drom_parse_entries(struct tb_switch *sw)
341 struct tb_drom_header *header = (void *) sw->drom;
342 u16 pos = sizeof(*header);
343 u16 drom_size = header->data_len + TB_DROM_DATA_START;
345 while (pos < drom_size) {
346 struct tb_drom_entry_header *entry = (void *) (sw->drom + pos);
347 if (pos + 1 == drom_size || pos + entry->len > drom_size
349 tb_sw_warn(sw, "drom buffer overrun, aborting\n");
353 tb_drom_parse_entry(sw, entry);
361 * tb_drom_read - copy drom to sw->drom and parse it
363 int tb_drom_read(struct tb_switch *sw)
368 struct tb_drom_header *header;
373 if (tb_route(sw) == 0) {
375 * The root switch contains only a dummy drom (header only,
376 * no entries). Hardcode the configuration here.
378 tb_drom_read_uid_only(sw, &sw->uid);
380 sw->ports[1].link_nr = 0;
381 sw->ports[2].link_nr = 1;
382 sw->ports[1].dual_link_port = &sw->ports[2];
383 sw->ports[2].dual_link_port = &sw->ports[1];
385 sw->ports[3].link_nr = 0;
386 sw->ports[4].link_nr = 1;
387 sw->ports[3].dual_link_port = &sw->ports[4];
388 sw->ports[4].dual_link_port = &sw->ports[3];
392 res = tb_eeprom_get_drom_offset(sw, &drom_offset);
396 res = tb_eeprom_read_n(sw, drom_offset + 14, (u8 *) &size, 2);
400 size += TB_DROM_DATA_START;
401 tb_sw_info(sw, "reading drom (length: %#x)\n", size);
402 if (size < sizeof(*header)) {
403 tb_sw_warn(sw, "drom too small, aborting\n");
407 sw->drom = kzalloc(size, GFP_KERNEL);
410 res = tb_eeprom_read_n(sw, drom_offset, sw->drom, size);
414 header = (void *) sw->drom;
416 if (header->data_len + TB_DROM_DATA_START != size) {
417 tb_sw_warn(sw, "drom size mismatch, aborting\n");
421 crc = tb_crc8((u8 *) &header->uid, 8);
422 if (crc != header->uid_crc8) {
424 "drom uid crc8 mismatch (expected: %#x, got: %#x), aborting\n",
425 header->uid_crc8, crc);
428 sw->uid = header->uid;
430 crc = tb_crc32(sw->drom + TB_DROM_DATA_START, header->data_len);
431 if (crc != header->data_crc32) {
433 "drom data crc32 mismatch (expected: %#x, got: %#x), aborting\n",
434 header->data_crc32, crc);
438 if (header->device_rom_revision > 1)
439 tb_sw_warn(sw, "drom device_rom_revision %#x unknown\n",
440 header->device_rom_revision);
442 return tb_drom_parse_entries(sw);