2 * Thunderbolt Cactus Ridge driver - eeprom access
4 * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
7 #include <linux/crc32.h>
8 #include <linux/slab.h>
12 * tb_eeprom_ctl_write() - write control word
14 static int tb_eeprom_ctl_write(struct tb_switch *sw, struct tb_eeprom_ctl *ctl)
16 return tb_sw_write(sw, ctl, TB_CFG_SWITCH, sw->cap_plug_events + 4, 1);
20 * tb_eeprom_ctl_write() - read control word
22 static int tb_eeprom_ctl_read(struct tb_switch *sw, struct tb_eeprom_ctl *ctl)
24 return tb_sw_read(sw, ctl, TB_CFG_SWITCH, sw->cap_plug_events + 4, 1);
27 enum tb_eeprom_transfer {
33 * tb_eeprom_active - enable rom access
35 * WARNING: Always disable access after usage. Otherwise the controller will
38 static int tb_eeprom_active(struct tb_switch *sw, bool enable)
40 struct tb_eeprom_ctl ctl;
41 int res = tb_eeprom_ctl_read(sw, &ctl);
46 res = tb_eeprom_ctl_write(sw, &ctl);
50 return tb_eeprom_ctl_write(sw, &ctl);
53 res = tb_eeprom_ctl_write(sw, &ctl);
57 return tb_eeprom_ctl_write(sw, &ctl);
62 * tb_eeprom_transfer - transfer one bit
64 * If TB_EEPROM_IN is passed, then the bit can be retrieved from ctl->data_in.
65 * If TB_EEPROM_OUT is passed, then ctl->data_out will be written.
67 static int tb_eeprom_transfer(struct tb_switch *sw, struct tb_eeprom_ctl *ctl,
68 enum tb_eeprom_transfer direction)
71 if (direction == TB_EEPROM_OUT) {
72 res = tb_eeprom_ctl_write(sw, ctl);
77 res = tb_eeprom_ctl_write(sw, ctl);
80 if (direction == TB_EEPROM_IN) {
81 res = tb_eeprom_ctl_read(sw, ctl);
86 return tb_eeprom_ctl_write(sw, ctl);
90 * tb_eeprom_out - write one byte to the bus
92 static int tb_eeprom_out(struct tb_switch *sw, u8 val)
94 struct tb_eeprom_ctl ctl;
96 int res = tb_eeprom_ctl_read(sw, &ctl);
99 for (i = 0; i < 8; i++) {
100 ctl.data_out = val & 0x80;
101 res = tb_eeprom_transfer(sw, &ctl, TB_EEPROM_OUT);
110 * tb_eeprom_in - read one byte from the bus
112 static int tb_eeprom_in(struct tb_switch *sw, u8 *val)
114 struct tb_eeprom_ctl ctl;
116 int res = tb_eeprom_ctl_read(sw, &ctl);
120 for (i = 0; i < 8; i++) {
122 res = tb_eeprom_transfer(sw, &ctl, TB_EEPROM_IN);
131 * tb_eeprom_read_n - read count bytes from offset into val
133 static int tb_eeprom_read_n(struct tb_switch *sw, u16 offset, u8 *val,
137 res = tb_eeprom_active(sw, true);
140 res = tb_eeprom_out(sw, 3);
143 res = tb_eeprom_out(sw, offset >> 8);
146 res = tb_eeprom_out(sw, offset);
149 for (i = 0; i < count; i++) {
150 res = tb_eeprom_in(sw, val + i);
154 return tb_eeprom_active(sw, false);
157 static u8 tb_crc8(u8 *data, int len)
161 for (i = 0; i < len; i++) {
163 for (j = 0; j < 8; j++)
164 val = (val << 1) ^ ((val & 0x80) ? 7 : 0);
169 static u32 tb_crc32(void *data, size_t len)
171 return ~__crc32c_le(~0, data, len);
174 #define TB_DROM_DATA_START 13
175 struct tb_drom_header {
177 u8 uid_crc8; /* checksum for uid */
181 u32 data_crc32; /* checksum for data_len bytes starting at byte 13 */
183 u8 device_rom_revision; /* should be <= 1 */
193 enum tb_drom_entry_type {
194 TB_DROM_ENTRY_GENERIC,
198 struct tb_drom_entry_header {
201 bool port_disabled:1; /* only valid if type is TB_DROM_ENTRY_PORT */
202 enum tb_drom_entry_type type:1;
205 struct tb_drom_entry_port {
207 struct tb_drom_entry_header header;
209 u8 dual_link_port_rid:4;
212 bool has_dual_link_port:1;
215 u8 dual_link_port_nr:6;
218 /* BYTES 4 - 5 TODO decode */
223 /* BYTES 5-6, TODO: verify (find hardware that has these set) */
226 bool has_peer_port:1;
233 * tb_eeprom_get_drom_offset - get drom offset within eeprom
235 int tb_eeprom_get_drom_offset(struct tb_switch *sw, u16 *offset)
237 struct tb_cap_plug_events cap;
239 if (!sw->cap_plug_events) {
240 tb_sw_warn(sw, "no TB_CAP_PLUG_EVENTS, cannot read eeprom\n");
243 res = tb_sw_read(sw, &cap, TB_CFG_SWITCH, sw->cap_plug_events,
248 if (!cap.eeprom_ctl.present || cap.eeprom_ctl.not_present) {
249 tb_sw_warn(sw, "no NVM\n");
253 if (cap.drom_offset > 0xffff) {
254 tb_sw_warn(sw, "drom offset is larger than 0xffff: %#x\n",
258 *offset = cap.drom_offset;
263 * tb_drom_read_uid_only - read uid directly from drom
265 * Does not use the cached copy in sw->drom. Used during resume to check switch
268 int tb_drom_read_uid_only(struct tb_switch *sw, u64 *uid)
273 int res = tb_eeprom_get_drom_offset(sw, &drom_offset);
278 res = tb_eeprom_read_n(sw, drom_offset, data, 9);
282 crc = tb_crc8(data + 1, 8);
283 if (crc != data[0]) {
284 tb_sw_warn(sw, "uid crc8 missmatch (expected: %#x, got: %#x)\n",
289 *uid = *(u64 *)(data+1);
293 static void tb_drom_parse_port_entry(struct tb_port *port,
294 struct tb_drom_entry_port *entry)
296 port->link_nr = entry->link_nr;
297 if (entry->has_dual_link_port)
298 port->dual_link_port =
299 &port->sw->ports[entry->dual_link_port_nr];
302 static int tb_drom_parse_entry(struct tb_switch *sw,
303 struct tb_drom_entry_header *header)
305 struct tb_port *port;
307 enum tb_port_type type;
309 if (header->type != TB_DROM_ENTRY_PORT)
312 port = &sw->ports[header->index];
313 port->disabled = header->port_disabled;
317 res = tb_port_read(port, &type, TB_CFG_PORT, 2, 1);
322 if (type == TB_TYPE_PORT) {
323 struct tb_drom_entry_port *entry = (void *) header;
324 if (header->len != sizeof(*entry)) {
326 "port entry has size %#x (expected %#zx)\n",
327 header->len, sizeof(struct tb_drom_entry_port));
330 tb_drom_parse_port_entry(port, entry);
336 * tb_drom_parse_entries - parse the linked list of drom entries
338 * Drom must have been copied to sw->drom.
340 static int tb_drom_parse_entries(struct tb_switch *sw)
342 struct tb_drom_header *header = (void *) sw->drom;
343 u16 pos = sizeof(*header);
344 u16 drom_size = header->data_len + TB_DROM_DATA_START;
346 while (pos < drom_size) {
347 struct tb_drom_entry_header *entry = (void *) (sw->drom + pos);
348 if (pos + 1 == drom_size || pos + entry->len > drom_size
350 tb_sw_warn(sw, "drom buffer overrun, aborting\n");
354 tb_drom_parse_entry(sw, entry);
362 * tb_drom_read - copy drom to sw->drom and parse it
364 int tb_drom_read(struct tb_switch *sw)
369 struct tb_drom_header *header;
374 if (tb_route(sw) == 0) {
376 * The root switch contains only a dummy drom (header only,
377 * no entries). Hardcode the configuration here.
379 tb_drom_read_uid_only(sw, &sw->uid);
381 sw->ports[1].link_nr = 0;
382 sw->ports[2].link_nr = 1;
383 sw->ports[1].dual_link_port = &sw->ports[2];
384 sw->ports[2].dual_link_port = &sw->ports[1];
386 sw->ports[3].link_nr = 0;
387 sw->ports[4].link_nr = 1;
388 sw->ports[3].dual_link_port = &sw->ports[4];
389 sw->ports[4].dual_link_port = &sw->ports[3];
393 res = tb_eeprom_get_drom_offset(sw, &drom_offset);
397 res = tb_eeprom_read_n(sw, drom_offset + 14, (u8 *) &size, 2);
401 size += TB_DROM_DATA_START;
402 tb_sw_info(sw, "reading drom (length: %#x)\n", size);
403 if (size < sizeof(*header)) {
404 tb_sw_warn(sw, "drom too small, aborting\n");
408 sw->drom = kzalloc(size, GFP_KERNEL);
411 res = tb_eeprom_read_n(sw, drom_offset, sw->drom, size);
415 header = (void *) sw->drom;
417 if (header->data_len + TB_DROM_DATA_START != size) {
418 tb_sw_warn(sw, "drom size mismatch, aborting\n");
422 crc = tb_crc8((u8 *) &header->uid, 8);
423 if (crc != header->uid_crc8) {
425 "drom uid crc8 mismatch (expected: %#x, got: %#x), aborting\n",
426 header->uid_crc8, crc);
429 sw->uid = header->uid;
431 crc = tb_crc32(sw->drom + TB_DROM_DATA_START, header->data_len);
432 if (crc != header->data_crc32) {
434 "drom data crc32 mismatch (expected: %#x, got: %#x), aborting\n",
435 header->data_crc32, crc);
439 if (header->device_rom_revision > 1)
440 tb_sw_warn(sw, "drom device_rom_revision %#x unknown\n",
441 header->device_rom_revision);
443 return tb_drom_parse_entries(sw);