2 * Driver for 8250/16550-type serial ports
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Copyright (C) 2001 Russell King.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * A note about mapbase / membase
15 * mapbase is the physical address of the IO port.
16 * membase is an 'ioremapped' cookie.
19 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
23 #include <linux/module.h>
24 #include <linux/moduleparam.h>
25 #include <linux/ioport.h>
26 #include <linux/init.h>
27 #include <linux/console.h>
28 #include <linux/sysrq.h>
29 #include <linux/delay.h>
30 #include <linux/platform_device.h>
31 #include <linux/tty.h>
32 #include <linux/ratelimit.h>
33 #include <linux/tty_flip.h>
34 #include <linux/serial_reg.h>
35 #include <linux/serial_core.h>
36 #include <linux/serial.h>
37 #include <linux/serial_8250.h>
38 #include <linux/nmi.h>
39 #include <linux/mutex.h>
40 #include <linux/slab.h>
42 #include <linux/sunserialcore.h>
52 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
53 * is unsafe when used on edge-triggered interrupts.
55 static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
57 static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
59 static struct uart_driver serial8250_reg;
61 static int serial_index(struct uart_port *port)
63 return (serial8250_reg.minor - 64) + port->line;
66 static unsigned int skip_txen_test; /* force skip of txen test at init time */
72 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
74 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
78 #define DEBUG_INTR(fmt...) printk(fmt)
80 #define DEBUG_INTR(fmt...) do { } while (0)
83 #define PASS_LIMIT 512
85 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
88 #ifdef CONFIG_SERIAL_8250_DETECT_IRQ
89 #define CONFIG_SERIAL_DETECT_IRQ 1
91 #ifdef CONFIG_SERIAL_8250_MANY_PORTS
92 #define CONFIG_SERIAL_MANY_PORTS 1
96 * HUB6 is always on. This will be removed once the header
97 * files have been cleaned.
101 #include <asm/serial.h>
103 * SERIAL_PORT_DFNS tells us about built-in ports that have no
104 * standard enumeration mechanism. Platforms that can find all
105 * serial ports via mechanisms like ACPI or PCI need not supply it.
107 #ifndef SERIAL_PORT_DFNS
108 #define SERIAL_PORT_DFNS
111 static const struct old_serial_port old_serial_port[] = {
112 SERIAL_PORT_DFNS /* defined in asm/serial.h */
115 #define UART_NR CONFIG_SERIAL_8250_NR_UARTS
117 #ifdef CONFIG_SERIAL_8250_RSA
119 #define PORT_RSA_MAX 4
120 static unsigned long probe_rsa[PORT_RSA_MAX];
121 static unsigned int probe_rsa_count;
122 #endif /* CONFIG_SERIAL_8250_RSA */
125 struct hlist_node node;
127 spinlock_t lock; /* Protects list not the hash */
128 struct list_head *head;
131 #define NR_IRQ_HASH 32 /* Can be adjusted later */
132 static struct hlist_head irq_lists[NR_IRQ_HASH];
133 static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
136 * Here we define the default xmit fifo size used for each type of UART.
138 static const struct serial8250_config uart_config[] = {
163 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
164 .flags = UART_CAP_FIFO,
175 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
181 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
183 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
189 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
191 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
199 .name = "16C950/954",
202 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
203 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
204 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
210 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
212 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
218 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
219 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
225 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
226 .flags = UART_CAP_FIFO,
232 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
233 .flags = UART_CAP_FIFO | UART_NATSEMI,
239 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
240 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
246 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
247 .flags = UART_CAP_FIFO,
253 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
254 .flags = UART_CAP_FIFO,
260 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
261 .flags = UART_CAP_FIFO | UART_CAP_AFE,
267 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
268 .flags = UART_CAP_FIFO | UART_CAP_AFE,
274 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
276 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
282 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
283 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR,
287 #if defined(CONFIG_MIPS_ALCHEMY)
289 /* Au1x00 UART hardware has a weird register layout */
290 static const u8 au_io_in_map[] = {
300 static const u8 au_io_out_map[] = {
308 /* sane hardware needs no mapping */
309 static inline int map_8250_in_reg(struct uart_port *p, int offset)
311 if (p->iotype != UPIO_AU)
313 return au_io_in_map[offset];
316 static inline int map_8250_out_reg(struct uart_port *p, int offset)
318 if (p->iotype != UPIO_AU)
320 return au_io_out_map[offset];
323 #elif defined(CONFIG_SERIAL_8250_RM9K)
347 static inline int map_8250_in_reg(struct uart_port *p, int offset)
349 if (p->iotype != UPIO_RM9000)
351 return regmap_in[offset];
354 static inline int map_8250_out_reg(struct uart_port *p, int offset)
356 if (p->iotype != UPIO_RM9000)
358 return regmap_out[offset];
363 /* sane hardware needs no mapping */
364 #define map_8250_in_reg(up, offset) (offset)
365 #define map_8250_out_reg(up, offset) (offset)
369 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
371 offset = map_8250_in_reg(p, offset) << p->regshift;
372 outb(p->hub6 - 1 + offset, p->iobase);
373 return inb(p->iobase + 1);
376 static void hub6_serial_out(struct uart_port *p, int offset, int value)
378 offset = map_8250_out_reg(p, offset) << p->regshift;
379 outb(p->hub6 - 1 + offset, p->iobase);
380 outb(value, p->iobase + 1);
383 static unsigned int mem_serial_in(struct uart_port *p, int offset)
385 offset = map_8250_in_reg(p, offset) << p->regshift;
386 return readb(p->membase + offset);
389 static void mem_serial_out(struct uart_port *p, int offset, int value)
391 offset = map_8250_out_reg(p, offset) << p->regshift;
392 writeb(value, p->membase + offset);
395 static void mem32_serial_out(struct uart_port *p, int offset, int value)
397 offset = map_8250_out_reg(p, offset) << p->regshift;
398 writel(value, p->membase + offset);
401 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
403 offset = map_8250_in_reg(p, offset) << p->regshift;
404 return readl(p->membase + offset);
407 static unsigned int au_serial_in(struct uart_port *p, int offset)
409 offset = map_8250_in_reg(p, offset) << p->regshift;
410 return __raw_readl(p->membase + offset);
413 static void au_serial_out(struct uart_port *p, int offset, int value)
415 offset = map_8250_out_reg(p, offset) << p->regshift;
416 __raw_writel(value, p->membase + offset);
419 static unsigned int io_serial_in(struct uart_port *p, int offset)
421 offset = map_8250_in_reg(p, offset) << p->regshift;
422 return inb(p->iobase + offset);
425 static void io_serial_out(struct uart_port *p, int offset, int value)
427 offset = map_8250_out_reg(p, offset) << p->regshift;
428 outb(value, p->iobase + offset);
431 static int serial8250_default_handle_irq(struct uart_port *port);
433 static void set_io_from_upio(struct uart_port *p)
435 struct uart_8250_port *up =
436 container_of(p, struct uart_8250_port, port);
439 p->serial_in = hub6_serial_in;
440 p->serial_out = hub6_serial_out;
444 p->serial_in = mem_serial_in;
445 p->serial_out = mem_serial_out;
450 p->serial_in = mem32_serial_in;
451 p->serial_out = mem32_serial_out;
455 p->serial_in = au_serial_in;
456 p->serial_out = au_serial_out;
460 p->serial_in = io_serial_in;
461 p->serial_out = io_serial_out;
464 /* Remember loaded iotype */
465 up->cur_iotype = p->iotype;
466 p->handle_irq = serial8250_default_handle_irq;
470 serial_out_sync(struct uart_8250_port *up, int offset, int value)
472 struct uart_port *p = &up->port;
477 p->serial_out(p, offset, value);
478 p->serial_in(p, UART_LCR); /* safe, no side-effects */
481 p->serial_out(p, offset, value);
485 #define serial_in(up, offset) \
486 (up->port.serial_in(&(up)->port, (offset)))
487 #define serial_out(up, offset, value) \
488 (up->port.serial_out(&(up)->port, (offset), (value)))
490 /* Uart divisor latch read */
491 static inline int _serial_dl_read(struct uart_8250_port *up)
493 return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;
496 /* Uart divisor latch write */
497 static inline void _serial_dl_write(struct uart_8250_port *up, int value)
499 serial_out(up, UART_DLL, value & 0xff);
500 serial_out(up, UART_DLM, value >> 8 & 0xff);
503 #if defined(CONFIG_MIPS_ALCHEMY)
504 /* Au1x00 haven't got a standard divisor latch */
505 static int serial_dl_read(struct uart_8250_port *up)
507 if (up->port.iotype == UPIO_AU)
508 return __raw_readl(up->port.membase + 0x28);
510 return _serial_dl_read(up);
513 static void serial_dl_write(struct uart_8250_port *up, int value)
515 if (up->port.iotype == UPIO_AU)
516 __raw_writel(value, up->port.membase + 0x28);
518 _serial_dl_write(up, value);
520 #elif defined(CONFIG_SERIAL_8250_RM9K)
521 static int serial_dl_read(struct uart_8250_port *up)
523 return (up->port.iotype == UPIO_RM9000) ?
524 (((__raw_readl(up->port.membase + 0x10) << 8) |
525 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
529 static void serial_dl_write(struct uart_8250_port *up, int value)
531 if (up->port.iotype == UPIO_RM9000) {
532 __raw_writel(value, up->port.membase + 0x08);
533 __raw_writel(value >> 8, up->port.membase + 0x10);
535 _serial_dl_write(up, value);
539 #define serial_dl_read(up) _serial_dl_read(up)
540 #define serial_dl_write(up, value) _serial_dl_write(up, value)
546 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
548 serial_out(up, UART_SCR, offset);
549 serial_out(up, UART_ICR, value);
552 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
556 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
557 serial_out(up, UART_SCR, offset);
558 value = serial_in(up, UART_ICR);
559 serial_icr_write(up, UART_ACR, up->acr);
567 static void serial8250_clear_fifos(struct uart_8250_port *p)
569 if (p->capabilities & UART_CAP_FIFO) {
570 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
571 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
572 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
573 serial_out(p, UART_FCR, 0);
578 * IER sleep support. UARTs which have EFRs need the "extended
579 * capability" bit enabled. Note that on XR16C850s, we need to
580 * reset LCR to write to IER.
582 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
584 if (p->capabilities & UART_CAP_SLEEP) {
585 if (p->capabilities & UART_CAP_EFR) {
586 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
587 serial_out(p, UART_EFR, UART_EFR_ECB);
588 serial_out(p, UART_LCR, 0);
590 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
591 if (p->capabilities & UART_CAP_EFR) {
592 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
593 serial_out(p, UART_EFR, 0);
594 serial_out(p, UART_LCR, 0);
599 #ifdef CONFIG_SERIAL_8250_RSA
601 * Attempts to turn on the RSA FIFO. Returns zero on failure.
602 * We set the port uart clock rate if we succeed.
604 static int __enable_rsa(struct uart_8250_port *up)
609 mode = serial_in(up, UART_RSA_MSR);
610 result = mode & UART_RSA_MSR_FIFO;
613 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
614 mode = serial_in(up, UART_RSA_MSR);
615 result = mode & UART_RSA_MSR_FIFO;
619 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
624 static void enable_rsa(struct uart_8250_port *up)
626 if (up->port.type == PORT_RSA) {
627 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
628 spin_lock_irq(&up->port.lock);
630 spin_unlock_irq(&up->port.lock);
632 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
633 serial_out(up, UART_RSA_FRR, 0);
638 * Attempts to turn off the RSA FIFO. Returns zero on failure.
639 * It is unknown why interrupts were disabled in here. However,
640 * the caller is expected to preserve this behaviour by grabbing
641 * the spinlock before calling this function.
643 static void disable_rsa(struct uart_8250_port *up)
648 if (up->port.type == PORT_RSA &&
649 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
650 spin_lock_irq(&up->port.lock);
652 mode = serial_in(up, UART_RSA_MSR);
653 result = !(mode & UART_RSA_MSR_FIFO);
656 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
657 mode = serial_in(up, UART_RSA_MSR);
658 result = !(mode & UART_RSA_MSR_FIFO);
662 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
663 spin_unlock_irq(&up->port.lock);
666 #endif /* CONFIG_SERIAL_8250_RSA */
669 * This is a quickie test to see how big the FIFO is.
670 * It doesn't work at all the time, more's the pity.
672 static int size_fifo(struct uart_8250_port *up)
674 unsigned char old_fcr, old_mcr, old_lcr;
675 unsigned short old_dl;
678 old_lcr = serial_in(up, UART_LCR);
679 serial_out(up, UART_LCR, 0);
680 old_fcr = serial_in(up, UART_FCR);
681 old_mcr = serial_in(up, UART_MCR);
682 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
683 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
684 serial_out(up, UART_MCR, UART_MCR_LOOP);
685 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
686 old_dl = serial_dl_read(up);
687 serial_dl_write(up, 0x0001);
688 serial_out(up, UART_LCR, 0x03);
689 for (count = 0; count < 256; count++)
690 serial_out(up, UART_TX, count);
691 mdelay(20);/* FIXME - schedule_timeout */
692 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
693 (count < 256); count++)
694 serial_in(up, UART_RX);
695 serial_out(up, UART_FCR, old_fcr);
696 serial_out(up, UART_MCR, old_mcr);
697 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
698 serial_dl_write(up, old_dl);
699 serial_out(up, UART_LCR, old_lcr);
705 * Read UART ID using the divisor method - set DLL and DLM to zero
706 * and the revision will be in DLL and device type in DLM. We
707 * preserve the device state across this.
709 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
711 unsigned char old_dll, old_dlm, old_lcr;
714 old_lcr = serial_in(p, UART_LCR);
715 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
717 old_dll = serial_in(p, UART_DLL);
718 old_dlm = serial_in(p, UART_DLM);
720 serial_out(p, UART_DLL, 0);
721 serial_out(p, UART_DLM, 0);
723 id = serial_in(p, UART_DLL) | serial_in(p, UART_DLM) << 8;
725 serial_out(p, UART_DLL, old_dll);
726 serial_out(p, UART_DLM, old_dlm);
727 serial_out(p, UART_LCR, old_lcr);
733 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
734 * When this function is called we know it is at least a StarTech
735 * 16650 V2, but it might be one of several StarTech UARTs, or one of
736 * its clones. (We treat the broken original StarTech 16650 V1 as a
737 * 16550, and why not? Startech doesn't seem to even acknowledge its
740 * What evil have men's minds wrought...
742 static void autoconfig_has_efr(struct uart_8250_port *up)
744 unsigned int id1, id2, id3, rev;
747 * Everything with an EFR has SLEEP
749 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
752 * First we check to see if it's an Oxford Semiconductor UART.
754 * If we have to do this here because some non-National
755 * Semiconductor clone chips lock up if you try writing to the
756 * LSR register (which serial_icr_read does)
760 * Check for Oxford Semiconductor 16C950.
762 * EFR [4] must be set else this test fails.
764 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
765 * claims that it's needed for 952 dual UART's (which are not
766 * recommended for new designs).
769 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
770 serial_out(up, UART_EFR, UART_EFR_ECB);
771 serial_out(up, UART_LCR, 0x00);
772 id1 = serial_icr_read(up, UART_ID1);
773 id2 = serial_icr_read(up, UART_ID2);
774 id3 = serial_icr_read(up, UART_ID3);
775 rev = serial_icr_read(up, UART_REV);
777 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
779 if (id1 == 0x16 && id2 == 0xC9 &&
780 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
781 up->port.type = PORT_16C950;
784 * Enable work around for the Oxford Semiconductor 952 rev B
785 * chip which causes it to seriously miscalculate baud rates
788 if (id3 == 0x52 && rev == 0x01)
789 up->bugs |= UART_BUG_QUOT;
794 * We check for a XR16C850 by setting DLL and DLM to 0, and then
795 * reading back DLL and DLM. The chip type depends on the DLM
797 * 0x10 - XR16C850 and the DLL contains the chip revision.
801 id1 = autoconfig_read_divisor_id(up);
802 DEBUG_AUTOCONF("850id=%04x ", id1);
805 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
806 up->port.type = PORT_16850;
811 * It wasn't an XR16C850.
813 * We distinguish between the '654 and the '650 by counting
814 * how many bytes are in the FIFO. I'm using this for now,
815 * since that's the technique that was sent to me in the
816 * serial driver update, but I'm not convinced this works.
817 * I've had problems doing this in the past. -TYT
819 if (size_fifo(up) == 64)
820 up->port.type = PORT_16654;
822 up->port.type = PORT_16650V2;
826 * We detected a chip without a FIFO. Only two fall into
827 * this category - the original 8250 and the 16450. The
828 * 16450 has a scratch register (accessible with LCR=0)
830 static void autoconfig_8250(struct uart_8250_port *up)
832 unsigned char scratch, status1, status2;
834 up->port.type = PORT_8250;
836 scratch = serial_in(up, UART_SCR);
837 serial_out(up, UART_SCR, 0xa5);
838 status1 = serial_in(up, UART_SCR);
839 serial_out(up, UART_SCR, 0x5a);
840 status2 = serial_in(up, UART_SCR);
841 serial_out(up, UART_SCR, scratch);
843 if (status1 == 0xa5 && status2 == 0x5a)
844 up->port.type = PORT_16450;
847 static int broken_efr(struct uart_8250_port *up)
850 * Exar ST16C2550 "A2" devices incorrectly detect as
851 * having an EFR, and report an ID of 0x0201. See
852 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
854 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
860 static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)
862 unsigned char status;
864 status = serial_in(up, 0x04); /* EXCR2 */
865 #define PRESL(x) ((x) & 0x30)
866 if (PRESL(status) == 0x10) {
867 /* already in high speed mode */
870 status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
871 status |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
872 serial_out(up, 0x04, status);
878 * We know that the chip has FIFOs. Does it have an EFR? The
879 * EFR is located in the same register position as the IIR and
880 * we know the top two bits of the IIR are currently set. The
881 * EFR should contain zero. Try to read the EFR.
883 static void autoconfig_16550a(struct uart_8250_port *up)
885 unsigned char status1, status2;
886 unsigned int iersave;
888 up->port.type = PORT_16550A;
889 up->capabilities |= UART_CAP_FIFO;
892 * Check for presence of the EFR when DLAB is set.
893 * Only ST16C650V1 UARTs pass this test.
895 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
896 if (serial_in(up, UART_EFR) == 0) {
897 serial_out(up, UART_EFR, 0xA8);
898 if (serial_in(up, UART_EFR) != 0) {
899 DEBUG_AUTOCONF("EFRv1 ");
900 up->port.type = PORT_16650;
901 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
903 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
905 serial_out(up, UART_EFR, 0);
910 * Maybe it requires 0xbf to be written to the LCR.
911 * (other ST16C650V2 UARTs, TI16C752A, etc)
913 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
914 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
915 DEBUG_AUTOCONF("EFRv2 ");
916 autoconfig_has_efr(up);
921 * Check for a National Semiconductor SuperIO chip.
922 * Attempt to switch to bank 2, read the value of the LOOP bit
923 * from EXCR1. Switch back to bank 0, change it in MCR. Then
924 * switch back to bank 2, read it from EXCR1 again and check
925 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
927 serial_out(up, UART_LCR, 0);
928 status1 = serial_in(up, UART_MCR);
929 serial_out(up, UART_LCR, 0xE0);
930 status2 = serial_in(up, 0x02); /* EXCR1 */
932 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
933 serial_out(up, UART_LCR, 0);
934 serial_out(up, UART_MCR, status1 ^ UART_MCR_LOOP);
935 serial_out(up, UART_LCR, 0xE0);
936 status2 = serial_in(up, 0x02); /* EXCR1 */
937 serial_out(up, UART_LCR, 0);
938 serial_out(up, UART_MCR, status1);
940 if ((status2 ^ status1) & UART_MCR_LOOP) {
943 serial_out(up, UART_LCR, 0xE0);
945 quot = serial_dl_read(up);
948 if (ns16550a_goto_highspeed(up))
949 serial_dl_write(up, quot);
951 serial_out(up, UART_LCR, 0);
953 up->port.uartclk = 921600*16;
954 up->port.type = PORT_NS16550A;
955 up->capabilities |= UART_NATSEMI;
961 * No EFR. Try to detect a TI16750, which only sets bit 5 of
962 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
963 * Try setting it with and without DLAB set. Cheap clones
964 * set bit 5 without DLAB set.
966 serial_out(up, UART_LCR, 0);
967 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
968 status1 = serial_in(up, UART_IIR) >> 5;
969 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
970 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
971 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
972 status2 = serial_in(up, UART_IIR) >> 5;
973 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
974 serial_out(up, UART_LCR, 0);
976 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
978 if (status1 == 6 && status2 == 7) {
979 up->port.type = PORT_16750;
980 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
985 * Try writing and reading the UART_IER_UUE bit (b6).
986 * If it works, this is probably one of the Xscale platform's
988 * We're going to explicitly set the UUE bit to 0 before
989 * trying to write and read a 1 just to make sure it's not
990 * already a 1 and maybe locked there before we even start start.
992 iersave = serial_in(up, UART_IER);
993 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
994 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
996 * OK it's in a known zero state, try writing and reading
997 * without disturbing the current state of the other bits.
999 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1000 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1003 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1005 DEBUG_AUTOCONF("Xscale ");
1006 up->port.type = PORT_XSCALE;
1007 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1012 * If we got here we couldn't force the IER_UUE bit to 0.
1013 * Log it and continue.
1015 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1017 serial_out(up, UART_IER, iersave);
1020 * Exar uarts have EFR in a weird location
1022 if (up->port.flags & UPF_EXAR_EFR) {
1023 up->port.type = PORT_XR17D15X;
1024 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR;
1028 * We distinguish between 16550A and U6 16550A by counting
1029 * how many bytes are in the FIFO.
1031 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1032 up->port.type = PORT_U6_16550A;
1033 up->capabilities |= UART_CAP_AFE;
1038 * This routine is called by rs_init() to initialize a specific serial
1039 * port. It determines what type of UART chip this serial port is
1040 * using: 8250, 16450, 16550, 16550A. The important question is
1041 * whether or not this UART is a 16550A or not, since this will
1042 * determine whether or not we can use its FIFO features or not.
1044 static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1046 unsigned char status1, scratch, scratch2, scratch3;
1047 unsigned char save_lcr, save_mcr;
1048 unsigned long flags;
1050 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
1053 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1054 serial_index(&up->port), up->port.iobase, up->port.membase);
1057 * We really do need global IRQs disabled here - we're going to
1058 * be frobbing the chips IRQ enable register to see if it exists.
1060 spin_lock_irqsave(&up->port.lock, flags);
1062 up->capabilities = 0;
1065 if (!(up->port.flags & UPF_BUGGY_UART)) {
1067 * Do a simple existence test first; if we fail this,
1068 * there's no point trying anything else.
1070 * 0x80 is used as a nonsense port to prevent against
1071 * false positives due to ISA bus float. The
1072 * assumption is that 0x80 is a non-existent port;
1073 * which should be safe since include/asm/io.h also
1074 * makes this assumption.
1076 * Note: this is safe as long as MCR bit 4 is clear
1077 * and the device is in "PC" mode.
1079 scratch = serial_in(up, UART_IER);
1080 serial_out(up, UART_IER, 0);
1085 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1086 * 16C754B) allow only to modify them if an EFR bit is set.
1088 scratch2 = serial_in(up, UART_IER) & 0x0f;
1089 serial_out(up, UART_IER, 0x0F);
1093 scratch3 = serial_in(up, UART_IER) & 0x0f;
1094 serial_out(up, UART_IER, scratch);
1095 if (scratch2 != 0 || scratch3 != 0x0F) {
1097 * We failed; there's nothing here
1099 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1100 scratch2, scratch3);
1105 save_mcr = serial_in(up, UART_MCR);
1106 save_lcr = serial_in(up, UART_LCR);
1109 * Check to see if a UART is really there. Certain broken
1110 * internal modems based on the Rockwell chipset fail this
1111 * test, because they apparently don't implement the loopback
1112 * test mode. So this test is skipped on the COM 1 through
1113 * COM 4 ports. This *should* be safe, since no board
1114 * manufacturer would be stupid enough to design a board
1115 * that conflicts with COM 1-4 --- we hope!
1117 if (!(up->port.flags & UPF_SKIP_TEST)) {
1118 serial_out(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1119 status1 = serial_in(up, UART_MSR) & 0xF0;
1120 serial_out(up, UART_MCR, save_mcr);
1121 if (status1 != 0x90) {
1122 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1129 * We're pretty sure there's a port here. Lets find out what
1130 * type of port it is. The IIR top two bits allows us to find
1131 * out if it's 8250 or 16450, 16550, 16550A or later. This
1132 * determines what we test for next.
1134 * We also initialise the EFR (if any) to zero for later. The
1135 * EFR occupies the same register location as the FCR and IIR.
1137 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1138 serial_out(up, UART_EFR, 0);
1139 serial_out(up, UART_LCR, 0);
1141 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1142 scratch = serial_in(up, UART_IIR) >> 6;
1144 DEBUG_AUTOCONF("iir=%d ", scratch);
1148 autoconfig_8250(up);
1151 up->port.type = PORT_UNKNOWN;
1154 up->port.type = PORT_16550;
1157 autoconfig_16550a(up);
1161 #ifdef CONFIG_SERIAL_8250_RSA
1163 * Only probe for RSA ports if we got the region.
1165 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1168 for (i = 0 ; i < probe_rsa_count; ++i) {
1169 if (probe_rsa[i] == up->port.iobase &&
1171 up->port.type = PORT_RSA;
1178 serial_out(up, UART_LCR, save_lcr);
1180 if (up->capabilities != uart_config[up->port.type].flags) {
1182 "ttyS%d: detected caps %08x should be %08x\n",
1183 serial_index(&up->port), up->capabilities,
1184 uart_config[up->port.type].flags);
1187 up->port.fifosize = uart_config[up->port.type].fifo_size;
1188 up->capabilities = uart_config[up->port.type].flags;
1189 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1191 if (up->port.type == PORT_UNKNOWN)
1197 #ifdef CONFIG_SERIAL_8250_RSA
1198 if (up->port.type == PORT_RSA)
1199 serial_out(up, UART_RSA_FRR, 0);
1201 serial_out(up, UART_MCR, save_mcr);
1202 serial8250_clear_fifos(up);
1203 serial_in(up, UART_RX);
1204 if (up->capabilities & UART_CAP_UUE)
1205 serial_out(up, UART_IER, UART_IER_UUE);
1207 serial_out(up, UART_IER, 0);
1210 spin_unlock_irqrestore(&up->port.lock, flags);
1211 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1214 static void autoconfig_irq(struct uart_8250_port *up)
1216 unsigned char save_mcr, save_ier;
1217 unsigned char save_ICP = 0;
1218 unsigned int ICP = 0;
1222 if (up->port.flags & UPF_FOURPORT) {
1223 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1224 save_ICP = inb_p(ICP);
1229 /* forget possible initially masked and pending IRQ */
1230 probe_irq_off(probe_irq_on());
1231 save_mcr = serial_in(up, UART_MCR);
1232 save_ier = serial_in(up, UART_IER);
1233 serial_out(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1235 irqs = probe_irq_on();
1236 serial_out(up, UART_MCR, 0);
1238 if (up->port.flags & UPF_FOURPORT) {
1239 serial_out(up, UART_MCR,
1240 UART_MCR_DTR | UART_MCR_RTS);
1242 serial_out(up, UART_MCR,
1243 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1245 serial_out(up, UART_IER, 0x0f); /* enable all intrs */
1246 (void)serial_in(up, UART_LSR);
1247 (void)serial_in(up, UART_RX);
1248 (void)serial_in(up, UART_IIR);
1249 (void)serial_in(up, UART_MSR);
1250 serial_out(up, UART_TX, 0xFF);
1252 irq = probe_irq_off(irqs);
1254 serial_out(up, UART_MCR, save_mcr);
1255 serial_out(up, UART_IER, save_ier);
1257 if (up->port.flags & UPF_FOURPORT)
1258 outb_p(save_ICP, ICP);
1260 up->port.irq = (irq > 0) ? irq : 0;
1263 static inline void __stop_tx(struct uart_8250_port *p)
1265 if (p->ier & UART_IER_THRI) {
1266 p->ier &= ~UART_IER_THRI;
1267 serial_out(p, UART_IER, p->ier);
1271 static void serial8250_stop_tx(struct uart_port *port)
1273 struct uart_8250_port *up =
1274 container_of(port, struct uart_8250_port, port);
1279 * We really want to stop the transmitter from sending.
1281 if (up->port.type == PORT_16C950) {
1282 up->acr |= UART_ACR_TXDIS;
1283 serial_icr_write(up, UART_ACR, up->acr);
1287 static void serial8250_start_tx(struct uart_port *port)
1289 struct uart_8250_port *up =
1290 container_of(port, struct uart_8250_port, port);
1292 if (!(up->ier & UART_IER_THRI)) {
1293 up->ier |= UART_IER_THRI;
1294 serial_out(up, UART_IER, up->ier);
1296 if (up->bugs & UART_BUG_TXEN) {
1298 lsr = serial_in(up, UART_LSR);
1299 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1300 if ((up->port.type == PORT_RM9000) ?
1301 (lsr & UART_LSR_THRE) :
1302 (lsr & UART_LSR_TEMT))
1303 serial8250_tx_chars(up);
1308 * Re-enable the transmitter if we disabled it.
1310 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1311 up->acr &= ~UART_ACR_TXDIS;
1312 serial_icr_write(up, UART_ACR, up->acr);
1316 static void serial8250_stop_rx(struct uart_port *port)
1318 struct uart_8250_port *up =
1319 container_of(port, struct uart_8250_port, port);
1321 up->ier &= ~UART_IER_RLSI;
1322 up->port.read_status_mask &= ~UART_LSR_DR;
1323 serial_out(up, UART_IER, up->ier);
1326 static void serial8250_enable_ms(struct uart_port *port)
1328 struct uart_8250_port *up =
1329 container_of(port, struct uart_8250_port, port);
1331 /* no MSR capabilities */
1332 if (up->bugs & UART_BUG_NOMSR)
1335 up->ier |= UART_IER_MSI;
1336 serial_out(up, UART_IER, up->ier);
1340 * Clear the Tegra rx fifo after a break
1342 * FIXME: This needs to become a port specific callback once we have a
1343 * framework for this
1345 static void clear_rx_fifo(struct uart_8250_port *up)
1347 unsigned int status, tmout = 10000;
1349 status = serial_in(up, UART_LSR);
1350 if (status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS))
1351 status = serial_in(up, UART_RX);
1361 * serial8250_rx_chars: processes according to the passed in LSR
1362 * value, and returns the remaining LSR bits not handled
1363 * by this Rx routine.
1366 serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1368 struct tty_struct *tty = up->port.state->port.tty;
1370 int max_count = 256;
1374 if (likely(lsr & UART_LSR_DR))
1375 ch = serial_in(up, UART_RX);
1378 * Intel 82571 has a Serial Over Lan device that will
1379 * set UART_LSR_BI without setting UART_LSR_DR when
1380 * it receives a break. To avoid reading from the
1381 * receive buffer without UART_LSR_DR bit set, we
1382 * just force the read character to be 0
1387 up->port.icount.rx++;
1389 lsr |= up->lsr_saved_flags;
1390 up->lsr_saved_flags = 0;
1392 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1394 * For statistics only
1396 if (lsr & UART_LSR_BI) {
1397 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1398 up->port.icount.brk++;
1400 * If tegra port then clear the rx fifo to
1401 * accept another break/character.
1403 if (up->port.type == PORT_TEGRA)
1407 * We do the SysRQ and SAK checking
1408 * here because otherwise the break
1409 * may get masked by ignore_status_mask
1410 * or read_status_mask.
1412 if (uart_handle_break(&up->port))
1414 } else if (lsr & UART_LSR_PE)
1415 up->port.icount.parity++;
1416 else if (lsr & UART_LSR_FE)
1417 up->port.icount.frame++;
1418 if (lsr & UART_LSR_OE)
1419 up->port.icount.overrun++;
1422 * Mask off conditions which should be ignored.
1424 lsr &= up->port.read_status_mask;
1426 if (lsr & UART_LSR_BI) {
1427 DEBUG_INTR("handling break....");
1429 } else if (lsr & UART_LSR_PE)
1431 else if (lsr & UART_LSR_FE)
1434 if (uart_handle_sysrq_char(&up->port, ch))
1437 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1440 lsr = serial_in(up, UART_LSR);
1441 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1442 spin_unlock(&up->port.lock);
1443 tty_flip_buffer_push(tty);
1444 spin_lock(&up->port.lock);
1447 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1449 void serial8250_tx_chars(struct uart_8250_port *up)
1451 struct circ_buf *xmit = &up->port.state->xmit;
1454 if (up->port.x_char) {
1455 serial_out(up, UART_TX, up->port.x_char);
1456 up->port.icount.tx++;
1457 up->port.x_char = 0;
1460 if (uart_tx_stopped(&up->port)) {
1461 serial8250_stop_tx(&up->port);
1464 if (uart_circ_empty(xmit)) {
1469 count = up->tx_loadsz;
1471 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1472 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1473 up->port.icount.tx++;
1474 if (uart_circ_empty(xmit))
1476 } while (--count > 0);
1478 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1479 uart_write_wakeup(&up->port);
1481 DEBUG_INTR("THRE...");
1483 if (uart_circ_empty(xmit))
1486 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1488 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1490 unsigned int status = serial_in(up, UART_MSR);
1492 status |= up->msr_saved_flags;
1493 up->msr_saved_flags = 0;
1494 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1495 up->port.state != NULL) {
1496 if (status & UART_MSR_TERI)
1497 up->port.icount.rng++;
1498 if (status & UART_MSR_DDSR)
1499 up->port.icount.dsr++;
1500 if (status & UART_MSR_DDCD)
1501 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1502 if (status & UART_MSR_DCTS)
1503 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1505 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
1510 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1513 * This handles the interrupt from one port.
1515 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1517 unsigned char status;
1518 unsigned long flags;
1519 struct uart_8250_port *up =
1520 container_of(port, struct uart_8250_port, port);
1522 if (iir & UART_IIR_NO_INT)
1525 spin_lock_irqsave(&up->port.lock, flags);
1527 status = serial_in(up, UART_LSR);
1529 DEBUG_INTR("status = %x...", status);
1531 if (status & (UART_LSR_DR | UART_LSR_BI))
1532 status = serial8250_rx_chars(up, status);
1533 serial8250_modem_status(up);
1534 if (status & UART_LSR_THRE)
1535 serial8250_tx_chars(up);
1537 spin_unlock_irqrestore(&up->port.lock, flags);
1540 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1542 static int serial8250_default_handle_irq(struct uart_port *port)
1544 struct uart_8250_port *up =
1545 container_of(port, struct uart_8250_port, port);
1546 unsigned int iir = serial_in(up, UART_IIR);
1548 return serial8250_handle_irq(port, iir);
1552 * This is the serial driver's interrupt routine.
1554 * Arjan thinks the old way was overly complex, so it got simplified.
1555 * Alan disagrees, saying that need the complexity to handle the weird
1556 * nature of ISA shared interrupts. (This is a special exception.)
1558 * In order to handle ISA shared interrupts properly, we need to check
1559 * that all ports have been serviced, and therefore the ISA interrupt
1560 * line has been de-asserted.
1562 * This means we need to loop through all ports. checking that they
1563 * don't have an interrupt pending.
1565 static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1567 struct irq_info *i = dev_id;
1568 struct list_head *l, *end = NULL;
1569 int pass_counter = 0, handled = 0;
1571 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1573 spin_lock(&i->lock);
1577 struct uart_8250_port *up;
1578 struct uart_port *port;
1581 up = list_entry(l, struct uart_8250_port, list);
1583 skip = pass_counter && up->port.flags & UPF_IIR_ONCE;
1585 if (!skip && port->handle_irq(port)) {
1588 } else if (end == NULL)
1593 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1594 /* If we hit this, we're dead. */
1595 printk_ratelimited(KERN_ERR
1596 "serial8250: too much work for irq%d\n", irq);
1601 spin_unlock(&i->lock);
1603 DEBUG_INTR("end.\n");
1605 return IRQ_RETVAL(handled);
1609 * To support ISA shared interrupts, we need to have one interrupt
1610 * handler that ensures that the IRQ line has been deasserted
1611 * before returning. Failing to do this will result in the IRQ
1612 * line being stuck active, and, since ISA irqs are edge triggered,
1613 * no more IRQs will be seen.
1615 static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1617 spin_lock_irq(&i->lock);
1619 if (!list_empty(i->head)) {
1620 if (i->head == &up->list)
1621 i->head = i->head->next;
1622 list_del(&up->list);
1624 BUG_ON(i->head != &up->list);
1627 spin_unlock_irq(&i->lock);
1628 /* List empty so throw away the hash node */
1629 if (i->head == NULL) {
1630 hlist_del(&i->node);
1635 static int serial_link_irq_chain(struct uart_8250_port *up)
1637 struct hlist_head *h;
1638 struct hlist_node *n;
1640 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1642 mutex_lock(&hash_mutex);
1644 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1646 hlist_for_each(n, h) {
1647 i = hlist_entry(n, struct irq_info, node);
1648 if (i->irq == up->port.irq)
1653 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1655 mutex_unlock(&hash_mutex);
1658 spin_lock_init(&i->lock);
1659 i->irq = up->port.irq;
1660 hlist_add_head(&i->node, h);
1662 mutex_unlock(&hash_mutex);
1664 spin_lock_irq(&i->lock);
1667 list_add(&up->list, i->head);
1668 spin_unlock_irq(&i->lock);
1672 INIT_LIST_HEAD(&up->list);
1673 i->head = &up->list;
1674 spin_unlock_irq(&i->lock);
1675 irq_flags |= up->port.irqflags;
1676 ret = request_irq(up->port.irq, serial8250_interrupt,
1677 irq_flags, "serial", i);
1679 serial_do_unlink(i, up);
1685 static void serial_unlink_irq_chain(struct uart_8250_port *up)
1688 struct hlist_node *n;
1689 struct hlist_head *h;
1691 mutex_lock(&hash_mutex);
1693 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1695 hlist_for_each(n, h) {
1696 i = hlist_entry(n, struct irq_info, node);
1697 if (i->irq == up->port.irq)
1702 BUG_ON(i->head == NULL);
1704 if (list_empty(i->head))
1705 free_irq(up->port.irq, i);
1707 serial_do_unlink(i, up);
1708 mutex_unlock(&hash_mutex);
1712 * This function is used to handle ports that do not have an
1713 * interrupt. This doesn't work very well for 16450's, but gives
1714 * barely passable results for a 16550A. (Although at the expense
1715 * of much CPU overhead).
1717 static void serial8250_timeout(unsigned long data)
1719 struct uart_8250_port *up = (struct uart_8250_port *)data;
1721 up->port.handle_irq(&up->port);
1722 mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
1725 static void serial8250_backup_timeout(unsigned long data)
1727 struct uart_8250_port *up = (struct uart_8250_port *)data;
1728 unsigned int iir, ier = 0, lsr;
1729 unsigned long flags;
1731 spin_lock_irqsave(&up->port.lock, flags);
1734 * Must disable interrupts or else we risk racing with the interrupt
1738 ier = serial_in(up, UART_IER);
1739 serial_out(up, UART_IER, 0);
1742 iir = serial_in(up, UART_IIR);
1745 * This should be a safe test for anyone who doesn't trust the
1746 * IIR bits on their UART, but it's specifically designed for
1747 * the "Diva" UART used on the management processor on many HP
1748 * ia64 and parisc boxes.
1750 lsr = serial_in(up, UART_LSR);
1751 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1752 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1753 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
1754 (lsr & UART_LSR_THRE)) {
1755 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1756 iir |= UART_IIR_THRI;
1759 if (!(iir & UART_IIR_NO_INT))
1760 serial8250_tx_chars(up);
1763 serial_out(up, UART_IER, ier);
1765 spin_unlock_irqrestore(&up->port.lock, flags);
1767 /* Standard timer interval plus 0.2s to keep the port running */
1768 mod_timer(&up->timer,
1769 jiffies + uart_poll_timeout(&up->port) + HZ / 5);
1772 static unsigned int serial8250_tx_empty(struct uart_port *port)
1774 struct uart_8250_port *up =
1775 container_of(port, struct uart_8250_port, port);
1776 unsigned long flags;
1779 spin_lock_irqsave(&up->port.lock, flags);
1780 lsr = serial_in(up, UART_LSR);
1781 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1782 spin_unlock_irqrestore(&up->port.lock, flags);
1784 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1787 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1789 struct uart_8250_port *up =
1790 container_of(port, struct uart_8250_port, port);
1791 unsigned int status;
1794 status = serial8250_modem_status(up);
1797 if (status & UART_MSR_DCD)
1799 if (status & UART_MSR_RI)
1801 if (status & UART_MSR_DSR)
1803 if (status & UART_MSR_CTS)
1808 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1810 struct uart_8250_port *up =
1811 container_of(port, struct uart_8250_port, port);
1812 unsigned char mcr = 0;
1814 if (mctrl & TIOCM_RTS)
1815 mcr |= UART_MCR_RTS;
1816 if (mctrl & TIOCM_DTR)
1817 mcr |= UART_MCR_DTR;
1818 if (mctrl & TIOCM_OUT1)
1819 mcr |= UART_MCR_OUT1;
1820 if (mctrl & TIOCM_OUT2)
1821 mcr |= UART_MCR_OUT2;
1822 if (mctrl & TIOCM_LOOP)
1823 mcr |= UART_MCR_LOOP;
1825 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1827 serial_out(up, UART_MCR, mcr);
1830 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1832 struct uart_8250_port *up =
1833 container_of(port, struct uart_8250_port, port);
1834 unsigned long flags;
1836 spin_lock_irqsave(&up->port.lock, flags);
1837 if (break_state == -1)
1838 up->lcr |= UART_LCR_SBC;
1840 up->lcr &= ~UART_LCR_SBC;
1841 serial_out(up, UART_LCR, up->lcr);
1842 spin_unlock_irqrestore(&up->port.lock, flags);
1846 * Wait for transmitter & holding register to empty
1848 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1850 unsigned int status, tmout = 10000;
1852 /* Wait up to 10ms for the character(s) to be sent. */
1854 status = serial_in(up, UART_LSR);
1856 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1858 if ((status & bits) == bits)
1865 /* Wait up to 1s for flow control if necessary */
1866 if (up->port.flags & UPF_CONS_FLOW) {
1868 for (tmout = 1000000; tmout; tmout--) {
1869 unsigned int msr = serial_in(up, UART_MSR);
1870 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1871 if (msr & UART_MSR_CTS)
1874 touch_nmi_watchdog();
1879 #ifdef CONFIG_CONSOLE_POLL
1881 * Console polling routines for writing and reading from the uart while
1882 * in an interrupt or debug context.
1885 static int serial8250_get_poll_char(struct uart_port *port)
1887 struct uart_8250_port *up =
1888 container_of(port, struct uart_8250_port, port);
1889 unsigned char lsr = serial_in(up, UART_LSR);
1891 if (!(lsr & UART_LSR_DR))
1892 return NO_POLL_CHAR;
1894 return serial_in(up, UART_RX);
1898 static void serial8250_put_poll_char(struct uart_port *port,
1902 struct uart_8250_port *up =
1903 container_of(port, struct uart_8250_port, port);
1906 * First save the IER then disable the interrupts
1908 ier = serial_in(up, UART_IER);
1909 if (up->capabilities & UART_CAP_UUE)
1910 serial_out(up, UART_IER, UART_IER_UUE);
1912 serial_out(up, UART_IER, 0);
1914 wait_for_xmitr(up, BOTH_EMPTY);
1916 * Send the character out.
1917 * If a LF, also do CR...
1919 serial_out(up, UART_TX, c);
1921 wait_for_xmitr(up, BOTH_EMPTY);
1922 serial_out(up, UART_TX, 13);
1926 * Finally, wait for transmitter to become empty
1927 * and restore the IER
1929 wait_for_xmitr(up, BOTH_EMPTY);
1930 serial_out(up, UART_IER, ier);
1933 #endif /* CONFIG_CONSOLE_POLL */
1935 static int serial8250_startup(struct uart_port *port)
1937 struct uart_8250_port *up =
1938 container_of(port, struct uart_8250_port, port);
1939 unsigned long flags;
1940 unsigned char lsr, iir;
1943 up->port.fifosize = uart_config[up->port.type].fifo_size;
1944 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1945 up->capabilities = uart_config[up->port.type].flags;
1948 if (up->port.iotype != up->cur_iotype)
1949 set_io_from_upio(port);
1951 if (up->port.type == PORT_16C950) {
1952 /* Wake up and initialize UART */
1954 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1955 serial_out(up, UART_EFR, UART_EFR_ECB);
1956 serial_out(up, UART_IER, 0);
1957 serial_out(up, UART_LCR, 0);
1958 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1959 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1960 serial_out(up, UART_EFR, UART_EFR_ECB);
1961 serial_out(up, UART_LCR, 0);
1964 #ifdef CONFIG_SERIAL_8250_RSA
1966 * If this is an RSA port, see if we can kick it up to the
1967 * higher speed clock.
1973 * Clear the FIFO buffers and disable them.
1974 * (they will be reenabled in set_termios())
1976 serial8250_clear_fifos(up);
1979 * Clear the interrupt registers.
1981 (void) serial_in(up, UART_LSR);
1982 (void) serial_in(up, UART_RX);
1983 (void) serial_in(up, UART_IIR);
1984 (void) serial_in(up, UART_MSR);
1987 * At this point, there's no way the LSR could still be 0xff;
1988 * if it is, then bail out, because there's likely no UART
1991 if (!(up->port.flags & UPF_BUGGY_UART) &&
1992 (serial_in(up, UART_LSR) == 0xff)) {
1993 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
1994 serial_index(&up->port));
1999 * For a XR16C850, we need to set the trigger levels
2001 if (up->port.type == PORT_16850) {
2004 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2006 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2007 serial_out(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2008 serial_out(up, UART_TRG, UART_TRG_96);
2009 serial_out(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2010 serial_out(up, UART_TRG, UART_TRG_96);
2012 serial_out(up, UART_LCR, 0);
2018 * Test for UARTs that do not reassert THRE when the
2019 * transmitter is idle and the interrupt has already
2020 * been cleared. Real 16550s should always reassert
2021 * this interrupt whenever the transmitter is idle and
2022 * the interrupt is enabled. Delays are necessary to
2023 * allow register changes to become visible.
2025 spin_lock_irqsave(&up->port.lock, flags);
2026 if (up->port.irqflags & IRQF_SHARED)
2027 disable_irq_nosync(up->port.irq);
2029 wait_for_xmitr(up, UART_LSR_THRE);
2030 serial_out_sync(up, UART_IER, UART_IER_THRI);
2031 udelay(1); /* allow THRE to set */
2032 iir1 = serial_in(up, UART_IIR);
2033 serial_out(up, UART_IER, 0);
2034 serial_out_sync(up, UART_IER, UART_IER_THRI);
2035 udelay(1); /* allow a working UART time to re-assert THRE */
2036 iir = serial_in(up, UART_IIR);
2037 serial_out(up, UART_IER, 0);
2039 if (up->port.irqflags & IRQF_SHARED)
2040 enable_irq(up->port.irq);
2041 spin_unlock_irqrestore(&up->port.lock, flags);
2044 * If the interrupt is not reasserted, setup a timer to
2045 * kick the UART on a regular basis.
2047 if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) {
2048 up->bugs |= UART_BUG_THRE;
2049 pr_debug("ttyS%d - using backup timer\n",
2050 serial_index(port));
2055 * The above check will only give an accurate result the first time
2056 * the port is opened so this value needs to be preserved.
2058 if (up->bugs & UART_BUG_THRE) {
2059 up->timer.function = serial8250_backup_timeout;
2060 up->timer.data = (unsigned long)up;
2061 mod_timer(&up->timer, jiffies +
2062 uart_poll_timeout(port) + HZ / 5);
2066 * If the "interrupt" for this port doesn't correspond with any
2067 * hardware interrupt, we use a timer-based system. The original
2068 * driver used to do this with IRQ0.
2070 if (!up->port.irq) {
2071 up->timer.data = (unsigned long)up;
2072 mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
2074 retval = serial_link_irq_chain(up);
2080 * Now, initialize the UART
2082 serial_out(up, UART_LCR, UART_LCR_WLEN8);
2084 spin_lock_irqsave(&up->port.lock, flags);
2085 if (up->port.flags & UPF_FOURPORT) {
2087 up->port.mctrl |= TIOCM_OUT1;
2090 * Most PC uarts need OUT2 raised to enable interrupts.
2093 up->port.mctrl |= TIOCM_OUT2;
2095 serial8250_set_mctrl(&up->port, up->port.mctrl);
2097 /* Serial over Lan (SoL) hack:
2098 Intel 8257x Gigabit ethernet chips have a
2099 16550 emulation, to be used for Serial Over Lan.
2100 Those chips take a longer time than a normal
2101 serial device to signalize that a transmission
2102 data was queued. Due to that, the above test generally
2103 fails. One solution would be to delay the reading of
2104 iir. However, this is not reliable, since the timeout
2105 is variable. So, let's just don't test if we receive
2106 TX irq. This way, we'll never enable UART_BUG_TXEN.
2108 if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
2109 goto dont_test_tx_en;
2112 * Do a quick test to see if we receive an
2113 * interrupt when we enable the TX irq.
2115 serial_out(up, UART_IER, UART_IER_THRI);
2116 lsr = serial_in(up, UART_LSR);
2117 iir = serial_in(up, UART_IIR);
2118 serial_out(up, UART_IER, 0);
2120 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2121 if (!(up->bugs & UART_BUG_TXEN)) {
2122 up->bugs |= UART_BUG_TXEN;
2123 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2124 serial_index(port));
2127 up->bugs &= ~UART_BUG_TXEN;
2131 spin_unlock_irqrestore(&up->port.lock, flags);
2134 * Clear the interrupt registers again for luck, and clear the
2135 * saved flags to avoid getting false values from polling
2136 * routines or the previous session.
2138 serial_in(up, UART_LSR);
2139 serial_in(up, UART_RX);
2140 serial_in(up, UART_IIR);
2141 serial_in(up, UART_MSR);
2142 up->lsr_saved_flags = 0;
2143 up->msr_saved_flags = 0;
2146 * Finally, enable interrupts. Note: Modem status interrupts
2147 * are set via set_termios(), which will be occurring imminently
2148 * anyway, so we don't enable them here.
2150 up->ier = UART_IER_RLSI | UART_IER_RDI;
2151 serial_out(up, UART_IER, up->ier);
2153 if (up->port.flags & UPF_FOURPORT) {
2156 * Enable interrupts on the AST Fourport board
2158 icp = (up->port.iobase & 0xfe0) | 0x01f;
2166 static void serial8250_shutdown(struct uart_port *port)
2168 struct uart_8250_port *up =
2169 container_of(port, struct uart_8250_port, port);
2170 unsigned long flags;
2173 * Disable interrupts from this port
2176 serial_out(up, UART_IER, 0);
2178 spin_lock_irqsave(&up->port.lock, flags);
2179 if (up->port.flags & UPF_FOURPORT) {
2180 /* reset interrupts on the AST Fourport board */
2181 inb((up->port.iobase & 0xfe0) | 0x1f);
2182 up->port.mctrl |= TIOCM_OUT1;
2184 up->port.mctrl &= ~TIOCM_OUT2;
2186 serial8250_set_mctrl(&up->port, up->port.mctrl);
2187 spin_unlock_irqrestore(&up->port.lock, flags);
2190 * Disable break condition and FIFOs
2192 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
2193 serial8250_clear_fifos(up);
2195 #ifdef CONFIG_SERIAL_8250_RSA
2197 * Reset the RSA board back to 115kbps compat mode.
2203 * Read data port to reset things, and then unlink from
2206 (void) serial_in(up, UART_RX);
2208 del_timer_sync(&up->timer);
2209 up->timer.function = serial8250_timeout;
2211 serial_unlink_irq_chain(up);
2214 static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2219 * Handle magic divisors for baud rates above baud_base on
2220 * SMSC SuperIO chips.
2222 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2223 baud == (port->uartclk/4))
2225 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2226 baud == (port->uartclk/8))
2229 quot = uart_get_divisor(port, baud);
2235 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2236 struct ktermios *old)
2238 struct uart_8250_port *up =
2239 container_of(port, struct uart_8250_port, port);
2240 unsigned char cval, fcr = 0;
2241 unsigned long flags;
2242 unsigned int baud, quot;
2244 switch (termios->c_cflag & CSIZE) {
2246 cval = UART_LCR_WLEN5;
2249 cval = UART_LCR_WLEN6;
2252 cval = UART_LCR_WLEN7;
2256 cval = UART_LCR_WLEN8;
2260 if (termios->c_cflag & CSTOPB)
2261 cval |= UART_LCR_STOP;
2262 if (termios->c_cflag & PARENB)
2263 cval |= UART_LCR_PARITY;
2264 if (!(termios->c_cflag & PARODD))
2265 cval |= UART_LCR_EPAR;
2267 if (termios->c_cflag & CMSPAR)
2268 cval |= UART_LCR_SPAR;
2272 * Ask the core to calculate the divisor for us.
2274 baud = uart_get_baud_rate(port, termios, old,
2275 port->uartclk / 16 / 0xffff,
2276 port->uartclk / 16);
2277 quot = serial8250_get_divisor(port, baud);
2280 * Oxford Semi 952 rev B workaround
2282 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2285 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
2287 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
2289 fcr = uart_config[up->port.type].fcr;
2293 * MCR-based auto flow control. When AFE is enabled, RTS will be
2294 * deasserted when the receive FIFO contains more characters than
2295 * the trigger, or the MCR RTS bit is cleared. In the case where
2296 * the remote UART is not using CTS auto flow control, we must
2297 * have sufficient FIFO entries for the latency of the remote
2298 * UART to respond. IOW, at least 32 bytes of FIFO.
2300 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
2301 up->mcr &= ~UART_MCR_AFE;
2302 if (termios->c_cflag & CRTSCTS)
2303 up->mcr |= UART_MCR_AFE;
2307 * Ok, we're now changing the port state. Do it with
2308 * interrupts disabled.
2310 spin_lock_irqsave(&up->port.lock, flags);
2313 * Update the per-port timeout.
2315 uart_update_timeout(port, termios->c_cflag, baud);
2317 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2318 if (termios->c_iflag & INPCK)
2319 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2320 if (termios->c_iflag & (BRKINT | PARMRK))
2321 up->port.read_status_mask |= UART_LSR_BI;
2324 * Characteres to ignore
2326 up->port.ignore_status_mask = 0;
2327 if (termios->c_iflag & IGNPAR)
2328 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2329 if (termios->c_iflag & IGNBRK) {
2330 up->port.ignore_status_mask |= UART_LSR_BI;
2332 * If we're ignoring parity and break indicators,
2333 * ignore overruns too (for real raw support).
2335 if (termios->c_iflag & IGNPAR)
2336 up->port.ignore_status_mask |= UART_LSR_OE;
2340 * ignore all characters if CREAD is not set
2342 if ((termios->c_cflag & CREAD) == 0)
2343 up->port.ignore_status_mask |= UART_LSR_DR;
2346 * CTS flow control flag and modem status interrupts
2348 up->ier &= ~UART_IER_MSI;
2349 if (!(up->bugs & UART_BUG_NOMSR) &&
2350 UART_ENABLE_MS(&up->port, termios->c_cflag))
2351 up->ier |= UART_IER_MSI;
2352 if (up->capabilities & UART_CAP_UUE)
2353 up->ier |= UART_IER_UUE;
2354 if (up->capabilities & UART_CAP_RTOIE)
2355 up->ier |= UART_IER_RTOIE;
2357 serial_out(up, UART_IER, up->ier);
2359 if (up->capabilities & UART_CAP_EFR) {
2360 unsigned char efr = 0;
2362 * TI16C752/Startech hardware flow control. FIXME:
2363 * - TI16C752 requires control thresholds to be set.
2364 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2366 if (termios->c_cflag & CRTSCTS)
2367 efr |= UART_EFR_CTS;
2369 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2370 if (up->port.flags & UPF_EXAR_EFR)
2371 serial_out(up, UART_XR_EFR, efr);
2373 serial_out(up, UART_EFR, efr);
2376 #ifdef CONFIG_ARCH_OMAP
2377 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2378 if (cpu_is_omap1510() && is_omap_port(up)) {
2379 if (baud == 115200) {
2381 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2383 serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2387 if (up->capabilities & UART_NATSEMI) {
2388 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2389 serial_out(up, UART_LCR, 0xe0);
2391 serial_out(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
2394 serial_dl_write(up, quot);
2397 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2398 * is written without DLAB set, this mode will be disabled.
2400 if (up->port.type == PORT_16750)
2401 serial_out(up, UART_FCR, fcr);
2403 serial_out(up, UART_LCR, cval); /* reset DLAB */
2404 up->lcr = cval; /* Save LCR */
2405 if (up->port.type != PORT_16750) {
2406 if (fcr & UART_FCR_ENABLE_FIFO) {
2407 /* emulated UARTs (Lucent Venus 167x) need two steps */
2408 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2410 serial_out(up, UART_FCR, fcr); /* set fcr */
2412 serial8250_set_mctrl(&up->port, up->port.mctrl);
2413 spin_unlock_irqrestore(&up->port.lock, flags);
2414 /* Don't rewrite B0 */
2415 if (tty_termios_baud_rate(termios))
2416 tty_termios_encode_baud_rate(termios, baud, baud);
2418 EXPORT_SYMBOL(serial8250_do_set_termios);
2421 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2422 struct ktermios *old)
2424 if (port->set_termios)
2425 port->set_termios(port, termios, old);
2427 serial8250_do_set_termios(port, termios, old);
2431 serial8250_set_ldisc(struct uart_port *port, int new)
2434 port->flags |= UPF_HARDPPS_CD;
2435 serial8250_enable_ms(port);
2437 port->flags &= ~UPF_HARDPPS_CD;
2441 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2442 unsigned int oldstate)
2444 struct uart_8250_port *p =
2445 container_of(port, struct uart_8250_port, port);
2447 serial8250_set_sleep(p, state != 0);
2449 EXPORT_SYMBOL(serial8250_do_pm);
2452 serial8250_pm(struct uart_port *port, unsigned int state,
2453 unsigned int oldstate)
2456 port->pm(port, state, oldstate);
2458 serial8250_do_pm(port, state, oldstate);
2461 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2463 if (pt->port.iotype == UPIO_AU)
2465 #ifdef CONFIG_ARCH_OMAP
2466 if (is_omap_port(pt))
2467 return 0x16 << pt->port.regshift;
2469 return 8 << pt->port.regshift;
2473 * Resource handling.
2475 static int serial8250_request_std_resource(struct uart_8250_port *up)
2477 unsigned int size = serial8250_port_size(up);
2480 switch (up->port.iotype) {
2485 if (!up->port.mapbase)
2488 if (!request_mem_region(up->port.mapbase, size, "serial")) {
2493 if (up->port.flags & UPF_IOREMAP) {
2494 up->port.membase = ioremap_nocache(up->port.mapbase,
2496 if (!up->port.membase) {
2497 release_mem_region(up->port.mapbase, size);
2505 if (!request_region(up->port.iobase, size, "serial"))
2512 static void serial8250_release_std_resource(struct uart_8250_port *up)
2514 unsigned int size = serial8250_port_size(up);
2516 switch (up->port.iotype) {
2521 if (!up->port.mapbase)
2524 if (up->port.flags & UPF_IOREMAP) {
2525 iounmap(up->port.membase);
2526 up->port.membase = NULL;
2529 release_mem_region(up->port.mapbase, size);
2534 release_region(up->port.iobase, size);
2539 static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2541 unsigned long start = UART_RSA_BASE << up->port.regshift;
2542 unsigned int size = 8 << up->port.regshift;
2545 switch (up->port.iotype) {
2548 start += up->port.iobase;
2549 if (request_region(start, size, "serial-rsa"))
2559 static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2561 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2562 unsigned int size = 8 << up->port.regshift;
2564 switch (up->port.iotype) {
2567 release_region(up->port.iobase + offset, size);
2572 static void serial8250_release_port(struct uart_port *port)
2574 struct uart_8250_port *up =
2575 container_of(port, struct uart_8250_port, port);
2577 serial8250_release_std_resource(up);
2578 if (up->port.type == PORT_RSA)
2579 serial8250_release_rsa_resource(up);
2582 static int serial8250_request_port(struct uart_port *port)
2584 struct uart_8250_port *up =
2585 container_of(port, struct uart_8250_port, port);
2588 ret = serial8250_request_std_resource(up);
2589 if (ret == 0 && up->port.type == PORT_RSA) {
2590 ret = serial8250_request_rsa_resource(up);
2592 serial8250_release_std_resource(up);
2598 static void serial8250_config_port(struct uart_port *port, int flags)
2600 struct uart_8250_port *up =
2601 container_of(port, struct uart_8250_port, port);
2602 int probeflags = PROBE_ANY;
2606 * Find the region that we can probe for. This in turn
2607 * tells us whether we can probe for the type of port.
2609 ret = serial8250_request_std_resource(up);
2613 ret = serial8250_request_rsa_resource(up);
2615 probeflags &= ~PROBE_RSA;
2617 if (up->port.iotype != up->cur_iotype)
2618 set_io_from_upio(port);
2620 if (flags & UART_CONFIG_TYPE)
2621 autoconfig(up, probeflags);
2623 /* if access method is AU, it is a 16550 with a quirk */
2624 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
2625 up->bugs |= UART_BUG_NOMSR;
2627 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2630 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2631 serial8250_release_rsa_resource(up);
2632 if (up->port.type == PORT_UNKNOWN)
2633 serial8250_release_std_resource(up);
2637 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2639 if (ser->irq >= nr_irqs || ser->irq < 0 ||
2640 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2641 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2642 ser->type == PORT_STARTECH)
2648 serial8250_type(struct uart_port *port)
2650 int type = port->type;
2652 if (type >= ARRAY_SIZE(uart_config))
2654 return uart_config[type].name;
2657 static struct uart_ops serial8250_pops = {
2658 .tx_empty = serial8250_tx_empty,
2659 .set_mctrl = serial8250_set_mctrl,
2660 .get_mctrl = serial8250_get_mctrl,
2661 .stop_tx = serial8250_stop_tx,
2662 .start_tx = serial8250_start_tx,
2663 .stop_rx = serial8250_stop_rx,
2664 .enable_ms = serial8250_enable_ms,
2665 .break_ctl = serial8250_break_ctl,
2666 .startup = serial8250_startup,
2667 .shutdown = serial8250_shutdown,
2668 .set_termios = serial8250_set_termios,
2669 .set_ldisc = serial8250_set_ldisc,
2670 .pm = serial8250_pm,
2671 .type = serial8250_type,
2672 .release_port = serial8250_release_port,
2673 .request_port = serial8250_request_port,
2674 .config_port = serial8250_config_port,
2675 .verify_port = serial8250_verify_port,
2676 #ifdef CONFIG_CONSOLE_POLL
2677 .poll_get_char = serial8250_get_poll_char,
2678 .poll_put_char = serial8250_put_poll_char,
2682 static struct uart_8250_port serial8250_ports[UART_NR];
2684 static void (*serial8250_isa_config)(int port, struct uart_port *up,
2685 unsigned short *capabilities);
2687 void serial8250_set_isa_configurator(
2688 void (*v)(int port, struct uart_port *up, unsigned short *capabilities))
2690 serial8250_isa_config = v;
2692 EXPORT_SYMBOL(serial8250_set_isa_configurator);
2694 static void __init serial8250_isa_init_ports(void)
2696 struct uart_8250_port *up;
2697 static int first = 1;
2704 for (i = 0; i < nr_uarts; i++) {
2705 struct uart_8250_port *up = &serial8250_ports[i];
2708 spin_lock_init(&up->port.lock);
2710 init_timer(&up->timer);
2711 up->timer.function = serial8250_timeout;
2714 * ALPHA_KLUDGE_MCR needs to be killed.
2716 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2717 up->mcr_force = ALPHA_KLUDGE_MCR;
2719 up->port.ops = &serial8250_pops;
2723 irqflag = IRQF_SHARED;
2725 for (i = 0, up = serial8250_ports;
2726 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2728 up->port.iobase = old_serial_port[i].port;
2729 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2730 up->port.irqflags = old_serial_port[i].irqflags;
2731 up->port.uartclk = old_serial_port[i].baud_base * 16;
2732 up->port.flags = old_serial_port[i].flags;
2733 up->port.hub6 = old_serial_port[i].hub6;
2734 up->port.membase = old_serial_port[i].iomem_base;
2735 up->port.iotype = old_serial_port[i].io_type;
2736 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2737 set_io_from_upio(&up->port);
2738 up->port.irqflags |= irqflag;
2739 if (serial8250_isa_config != NULL)
2740 serial8250_isa_config(i, &up->port, &up->capabilities);
2746 serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2748 up->port.type = type;
2749 up->port.fifosize = uart_config[type].fifo_size;
2750 up->capabilities = uart_config[type].flags;
2751 up->tx_loadsz = uart_config[type].tx_loadsz;
2755 serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2759 for (i = 0; i < nr_uarts; i++) {
2760 struct uart_8250_port *up = &serial8250_ports[i];
2761 up->cur_iotype = 0xFF;
2764 serial8250_isa_init_ports();
2766 for (i = 0; i < nr_uarts; i++) {
2767 struct uart_8250_port *up = &serial8250_ports[i];
2771 if (up->port.flags & UPF_FIXED_TYPE)
2772 serial8250_init_fixed_type_port(up, up->port.type);
2774 uart_add_one_port(drv, &up->port);
2778 #ifdef CONFIG_SERIAL_8250_CONSOLE
2780 static void serial8250_console_putchar(struct uart_port *port, int ch)
2782 struct uart_8250_port *up =
2783 container_of(port, struct uart_8250_port, port);
2785 wait_for_xmitr(up, UART_LSR_THRE);
2786 serial_out(up, UART_TX, ch);
2790 * Print a string to the serial port trying not to disturb
2791 * any possible real use of the port...
2793 * The console_lock must be held when we get here.
2796 serial8250_console_write(struct console *co, const char *s, unsigned int count)
2798 struct uart_8250_port *up = &serial8250_ports[co->index];
2799 unsigned long flags;
2803 touch_nmi_watchdog();
2805 local_irq_save(flags);
2806 if (up->port.sysrq) {
2807 /* serial8250_handle_irq() already took the lock */
2809 } else if (oops_in_progress) {
2810 locked = spin_trylock(&up->port.lock);
2812 spin_lock(&up->port.lock);
2815 * First save the IER then disable the interrupts
2817 ier = serial_in(up, UART_IER);
2819 if (up->capabilities & UART_CAP_UUE)
2820 serial_out(up, UART_IER, UART_IER_UUE);
2822 serial_out(up, UART_IER, 0);
2824 uart_console_write(&up->port, s, count, serial8250_console_putchar);
2827 * Finally, wait for transmitter to become empty
2828 * and restore the IER
2830 wait_for_xmitr(up, BOTH_EMPTY);
2831 serial_out(up, UART_IER, ier);
2834 * The receive handling will happen properly because the
2835 * receive ready bit will still be set; it is not cleared
2836 * on read. However, modem control will not, we must
2837 * call it if we have saved something in the saved flags
2838 * while processing with interrupts off.
2840 if (up->msr_saved_flags)
2841 serial8250_modem_status(up);
2844 spin_unlock(&up->port.lock);
2845 local_irq_restore(flags);
2848 static int __init serial8250_console_setup(struct console *co, char *options)
2850 struct uart_port *port;
2857 * Check whether an invalid uart number has been specified, and
2858 * if so, search for the first available port that does have
2861 if (co->index >= nr_uarts)
2863 port = &serial8250_ports[co->index].port;
2864 if (!port->iobase && !port->membase)
2868 uart_parse_options(options, &baud, &parity, &bits, &flow);
2870 return uart_set_options(port, co, baud, parity, bits, flow);
2873 static int serial8250_console_early_setup(void)
2875 return serial8250_find_port_for_earlycon();
2878 static struct console serial8250_console = {
2880 .write = serial8250_console_write,
2881 .device = uart_console_device,
2882 .setup = serial8250_console_setup,
2883 .early_setup = serial8250_console_early_setup,
2884 .flags = CON_PRINTBUFFER | CON_ANYTIME,
2886 .data = &serial8250_reg,
2889 static int __init serial8250_console_init(void)
2891 if (nr_uarts > UART_NR)
2894 serial8250_isa_init_ports();
2895 register_console(&serial8250_console);
2898 console_initcall(serial8250_console_init);
2900 int serial8250_find_port(struct uart_port *p)
2903 struct uart_port *port;
2905 for (line = 0; line < nr_uarts; line++) {
2906 port = &serial8250_ports[line].port;
2907 if (uart_match_port(p, port))
2913 #define SERIAL8250_CONSOLE &serial8250_console
2915 #define SERIAL8250_CONSOLE NULL
2918 static struct uart_driver serial8250_reg = {
2919 .owner = THIS_MODULE,
2920 .driver_name = "serial",
2924 .cons = SERIAL8250_CONSOLE,
2928 * early_serial_setup - early registration for 8250 ports
2930 * Setup an 8250 port structure prior to console initialisation. Use
2931 * after console initialisation will cause undefined behaviour.
2933 int __init early_serial_setup(struct uart_port *port)
2935 struct uart_port *p;
2937 if (port->line >= ARRAY_SIZE(serial8250_ports))
2940 serial8250_isa_init_ports();
2941 p = &serial8250_ports[port->line].port;
2942 p->iobase = port->iobase;
2943 p->membase = port->membase;
2945 p->irqflags = port->irqflags;
2946 p->uartclk = port->uartclk;
2947 p->fifosize = port->fifosize;
2948 p->regshift = port->regshift;
2949 p->iotype = port->iotype;
2950 p->flags = port->flags;
2951 p->mapbase = port->mapbase;
2952 p->private_data = port->private_data;
2953 p->type = port->type;
2954 p->line = port->line;
2956 set_io_from_upio(p);
2957 if (port->serial_in)
2958 p->serial_in = port->serial_in;
2959 if (port->serial_out)
2960 p->serial_out = port->serial_out;
2961 if (port->handle_irq)
2962 p->handle_irq = port->handle_irq;
2964 p->handle_irq = serial8250_default_handle_irq;
2970 * serial8250_suspend_port - suspend one serial port
2971 * @line: serial line number
2973 * Suspend one serial port.
2975 void serial8250_suspend_port(int line)
2977 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2981 * serial8250_resume_port - resume one serial port
2982 * @line: serial line number
2984 * Resume one serial port.
2986 void serial8250_resume_port(int line)
2988 struct uart_8250_port *up = &serial8250_ports[line];
2990 if (up->capabilities & UART_NATSEMI) {
2991 /* Ensure it's still in high speed mode */
2992 serial_out(up, UART_LCR, 0xE0);
2994 ns16550a_goto_highspeed(up);
2996 serial_out(up, UART_LCR, 0);
2997 up->port.uartclk = 921600*16;
2999 uart_resume_port(&serial8250_reg, &up->port);
3003 * Register a set of serial devices attached to a platform device. The
3004 * list is terminated with a zero flags entry, which means we expect
3005 * all entries to have at least UPF_BOOT_AUTOCONF set.
3007 static int __devinit serial8250_probe(struct platform_device *dev)
3009 struct plat_serial8250_port *p = dev->dev.platform_data;
3010 struct uart_port port;
3011 int ret, i, irqflag = 0;
3013 memset(&port, 0, sizeof(struct uart_port));
3016 irqflag = IRQF_SHARED;
3018 for (i = 0; p && p->flags != 0; p++, i++) {
3019 port.iobase = p->iobase;
3020 port.membase = p->membase;
3022 port.irqflags = p->irqflags;
3023 port.uartclk = p->uartclk;
3024 port.regshift = p->regshift;
3025 port.iotype = p->iotype;
3026 port.flags = p->flags;
3027 port.mapbase = p->mapbase;
3028 port.hub6 = p->hub6;
3029 port.private_data = p->private_data;
3030 port.type = p->type;
3031 port.serial_in = p->serial_in;
3032 port.serial_out = p->serial_out;
3033 port.handle_irq = p->handle_irq;
3034 port.set_termios = p->set_termios;
3036 port.dev = &dev->dev;
3037 port.irqflags |= irqflag;
3038 ret = serial8250_register_port(&port);
3040 dev_err(&dev->dev, "unable to register port at index %d "
3041 "(IO%lx MEM%llx IRQ%d): %d\n", i,
3042 p->iobase, (unsigned long long)p->mapbase,
3050 * Remove serial ports registered against a platform device.
3052 static int __devexit serial8250_remove(struct platform_device *dev)
3056 for (i = 0; i < nr_uarts; i++) {
3057 struct uart_8250_port *up = &serial8250_ports[i];
3059 if (up->port.dev == &dev->dev)
3060 serial8250_unregister_port(i);
3065 static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
3069 for (i = 0; i < UART_NR; i++) {
3070 struct uart_8250_port *up = &serial8250_ports[i];
3072 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3073 uart_suspend_port(&serial8250_reg, &up->port);
3079 static int serial8250_resume(struct platform_device *dev)
3083 for (i = 0; i < UART_NR; i++) {
3084 struct uart_8250_port *up = &serial8250_ports[i];
3086 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3087 serial8250_resume_port(i);
3093 static struct platform_driver serial8250_isa_driver = {
3094 .probe = serial8250_probe,
3095 .remove = __devexit_p(serial8250_remove),
3096 .suspend = serial8250_suspend,
3097 .resume = serial8250_resume,
3099 .name = "serial8250",
3100 .owner = THIS_MODULE,
3105 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3106 * in the table in include/asm/serial.h
3108 static struct platform_device *serial8250_isa_devs;
3111 * serial8250_register_port and serial8250_unregister_port allows for
3112 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3113 * modems and PCI multiport cards.
3115 static DEFINE_MUTEX(serial_mutex);
3117 static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3122 * First, find a port entry which matches.
3124 for (i = 0; i < nr_uarts; i++)
3125 if (uart_match_port(&serial8250_ports[i].port, port))
3126 return &serial8250_ports[i];
3129 * We didn't find a matching entry, so look for the first
3130 * free entry. We look for one which hasn't been previously
3131 * used (indicated by zero iobase).
3133 for (i = 0; i < nr_uarts; i++)
3134 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3135 serial8250_ports[i].port.iobase == 0)
3136 return &serial8250_ports[i];
3139 * That also failed. Last resort is to find any entry which
3140 * doesn't have a real port associated with it.
3142 for (i = 0; i < nr_uarts; i++)
3143 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3144 return &serial8250_ports[i];
3150 * serial8250_register_port - register a serial port
3151 * @port: serial port template
3153 * Configure the serial port specified by the request. If the
3154 * port exists and is in use, it is hung up and unregistered
3157 * The port is then probed and if necessary the IRQ is autodetected
3158 * If this fails an error is returned.
3160 * On success the port is ready to use and the line number is returned.
3162 int serial8250_register_port(struct uart_port *port)
3164 struct uart_8250_port *uart;
3167 if (port->uartclk == 0)
3170 mutex_lock(&serial_mutex);
3172 uart = serial8250_find_match_or_unused(port);
3174 uart_remove_one_port(&serial8250_reg, &uart->port);
3176 uart->port.iobase = port->iobase;
3177 uart->port.membase = port->membase;
3178 uart->port.irq = port->irq;
3179 uart->port.irqflags = port->irqflags;
3180 uart->port.uartclk = port->uartclk;
3181 uart->port.fifosize = port->fifosize;
3182 uart->port.regshift = port->regshift;
3183 uart->port.iotype = port->iotype;
3184 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
3185 uart->port.mapbase = port->mapbase;
3186 uart->port.private_data = port->private_data;
3188 uart->port.dev = port->dev;
3190 if (port->flags & UPF_FIXED_TYPE)
3191 serial8250_init_fixed_type_port(uart, port->type);
3193 set_io_from_upio(&uart->port);
3194 /* Possibly override default I/O functions. */
3195 if (port->serial_in)
3196 uart->port.serial_in = port->serial_in;
3197 if (port->serial_out)
3198 uart->port.serial_out = port->serial_out;
3199 if (port->handle_irq)
3200 uart->port.handle_irq = port->handle_irq;
3201 /* Possibly override set_termios call */
3202 if (port->set_termios)
3203 uart->port.set_termios = port->set_termios;
3205 uart->port.pm = port->pm;
3207 if (serial8250_isa_config != NULL)
3208 serial8250_isa_config(0, &uart->port,
3209 &uart->capabilities);
3211 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3213 ret = uart->port.line;
3215 mutex_unlock(&serial_mutex);
3219 EXPORT_SYMBOL(serial8250_register_port);
3222 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3223 * @line: serial line number
3225 * Remove one serial port. This may not be called from interrupt
3226 * context. We hand the port back to the our control.
3228 void serial8250_unregister_port(int line)
3230 struct uart_8250_port *uart = &serial8250_ports[line];
3232 mutex_lock(&serial_mutex);
3233 uart_remove_one_port(&serial8250_reg, &uart->port);
3234 if (serial8250_isa_devs) {
3235 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3236 uart->port.type = PORT_UNKNOWN;
3237 uart->port.dev = &serial8250_isa_devs->dev;
3238 uart->capabilities = uart_config[uart->port.type].flags;
3239 uart_add_one_port(&serial8250_reg, &uart->port);
3241 uart->port.dev = NULL;
3243 mutex_unlock(&serial_mutex);
3245 EXPORT_SYMBOL(serial8250_unregister_port);
3247 static int __init serial8250_init(void)
3251 if (nr_uarts > UART_NR)
3254 printk(KERN_INFO "Serial: 8250/16550 driver, "
3255 "%d ports, IRQ sharing %sabled\n", nr_uarts,
3256 share_irqs ? "en" : "dis");
3259 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3261 serial8250_reg.nr = UART_NR;
3262 ret = uart_register_driver(&serial8250_reg);
3267 serial8250_isa_devs = platform_device_alloc("serial8250",
3268 PLAT8250_DEV_LEGACY);
3269 if (!serial8250_isa_devs) {
3271 goto unreg_uart_drv;
3274 ret = platform_device_add(serial8250_isa_devs);
3278 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3280 ret = platform_driver_register(&serial8250_isa_driver);
3284 platform_device_del(serial8250_isa_devs);
3286 platform_device_put(serial8250_isa_devs);
3289 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3291 uart_unregister_driver(&serial8250_reg);
3297 static void __exit serial8250_exit(void)
3299 struct platform_device *isa_dev = serial8250_isa_devs;
3302 * This tells serial8250_unregister_port() not to re-register
3303 * the ports (thereby making serial8250_isa_driver permanently
3306 serial8250_isa_devs = NULL;
3308 platform_driver_unregister(&serial8250_isa_driver);
3309 platform_device_unregister(isa_dev);
3312 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3314 uart_unregister_driver(&serial8250_reg);
3318 module_init(serial8250_init);
3319 module_exit(serial8250_exit);
3321 EXPORT_SYMBOL(serial8250_suspend_port);
3322 EXPORT_SYMBOL(serial8250_resume_port);
3324 MODULE_LICENSE("GPL");
3325 MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
3327 module_param(share_irqs, uint, 0644);
3328 MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3331 module_param(nr_uarts, uint, 0644);
3332 MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3334 module_param(skip_txen_test, uint, 0644);
3335 MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3337 #ifdef CONFIG_SERIAL_8250_RSA
3338 module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3339 MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3341 MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);