2 * Probe module for 8250/16550-type PCI serial ports.
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Copyright (C) 2001 Russell King, All Rights Reserved.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
13 #include <linux/module.h>
14 #include <linux/pci.h>
15 #include <linux/string.h>
16 #include <linux/kernel.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
19 #include <linux/tty.h>
20 #include <linux/serial_reg.h>
21 #include <linux/serial_core.h>
22 #include <linux/8250_pci.h>
23 #include <linux/bitops.h>
25 #include <asm/byteorder.h>
28 #include <linux/dmaengine.h>
29 #include <linux/platform_data/dma-dw.h>
34 * init function returns:
35 * > 0 - number of ports
36 * = 0 - use board->num_ports
39 struct pci_serial_quirk {
44 int (*probe)(struct pci_dev *dev);
45 int (*init)(struct pci_dev *dev);
46 int (*setup)(struct serial_private *,
47 const struct pciserial_board *,
48 struct uart_8250_port *, int);
49 void (*exit)(struct pci_dev *dev);
52 #define PCI_NUM_BAR_RESOURCES 6
54 struct serial_private {
57 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
58 struct pci_serial_quirk *quirk;
62 static int pci_default_setup(struct serial_private*,
63 const struct pciserial_board*, struct uart_8250_port *, int);
65 static void moan_device(const char *str, struct pci_dev *dev)
69 "Please send the output of lspci -vv, this\n"
70 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
71 "manufacturer and name of serial board or\n"
72 "modem board to rmk+serial@arm.linux.org.uk.\n",
73 pci_name(dev), str, dev->vendor, dev->device,
74 dev->subsystem_vendor, dev->subsystem_device);
78 setup_port(struct serial_private *priv, struct uart_8250_port *port,
79 int bar, int offset, int regshift)
81 struct pci_dev *dev = priv->dev;
83 if (bar >= PCI_NUM_BAR_RESOURCES)
86 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
87 if (!priv->remapped_bar[bar])
88 priv->remapped_bar[bar] = pci_ioremap_bar(dev, bar);
89 if (!priv->remapped_bar[bar])
92 port->port.iotype = UPIO_MEM;
93 port->port.iobase = 0;
94 port->port.mapbase = pci_resource_start(dev, bar) + offset;
95 port->port.membase = priv->remapped_bar[bar] + offset;
96 port->port.regshift = regshift;
98 port->port.iotype = UPIO_PORT;
99 port->port.iobase = pci_resource_start(dev, bar) + offset;
100 port->port.mapbase = 0;
101 port->port.membase = NULL;
102 port->port.regshift = 0;
108 * ADDI-DATA GmbH communication cards <info@addi-data.com>
110 static int addidata_apci7800_setup(struct serial_private *priv,
111 const struct pciserial_board *board,
112 struct uart_8250_port *port, int idx)
114 unsigned int bar = 0, offset = board->first_offset;
115 bar = FL_GET_BASE(board->flags);
118 offset += idx * board->uart_offset;
119 } else if ((idx >= 2) && (idx < 4)) {
121 offset += ((idx - 2) * board->uart_offset);
122 } else if ((idx >= 4) && (idx < 6)) {
124 offset += ((idx - 4) * board->uart_offset);
125 } else if (idx >= 6) {
127 offset += ((idx - 6) * board->uart_offset);
130 return setup_port(priv, port, bar, offset, board->reg_shift);
134 * AFAVLAB uses a different mixture of BARs and offsets
135 * Not that ugly ;) -- HW
138 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
139 struct uart_8250_port *port, int idx)
141 unsigned int bar, offset = board->first_offset;
143 bar = FL_GET_BASE(board->flags);
148 offset += (idx - 4) * board->uart_offset;
151 return setup_port(priv, port, bar, offset, board->reg_shift);
155 * HP's Remote Management Console. The Diva chip came in several
156 * different versions. N-class, L2000 and A500 have two Diva chips, each
157 * with 3 UARTs (the third UART on the second chip is unused). Superdome
158 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
159 * one Diva chip, but it has been expanded to 5 UARTs.
161 static int pci_hp_diva_init(struct pci_dev *dev)
165 switch (dev->subsystem_device) {
166 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
167 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
168 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
169 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
172 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
175 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
178 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
179 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
188 * HP's Diva chip puts the 4th/5th serial port further out, and
189 * some serial ports are supposed to be hidden on certain models.
192 pci_hp_diva_setup(struct serial_private *priv,
193 const struct pciserial_board *board,
194 struct uart_8250_port *port, int idx)
196 unsigned int offset = board->first_offset;
197 unsigned int bar = FL_GET_BASE(board->flags);
199 switch (priv->dev->subsystem_device) {
200 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
204 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
214 offset += idx * board->uart_offset;
216 return setup_port(priv, port, bar, offset, board->reg_shift);
220 * Added for EKF Intel i960 serial boards
222 static int pci_inteli960ni_init(struct pci_dev *dev)
226 if (!(dev->subsystem_device & 0x1000))
229 /* is firmware started? */
230 pci_read_config_dword(dev, 0x44, &oldval);
231 if (oldval == 0x00001000L) { /* RESET value */
232 dev_dbg(&dev->dev, "Local i960 firmware missing\n");
239 * Some PCI serial cards using the PLX 9050 PCI interface chip require
240 * that the card interrupt be explicitly enabled or disabled. This
241 * seems to be mainly needed on card using the PLX which also use I/O
244 static int pci_plx9050_init(struct pci_dev *dev)
249 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
250 moan_device("no memory in bar 0", dev);
255 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
256 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
259 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
260 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
262 * As the megawolf cards have the int pins active
263 * high, and have 2 UART chips, both ints must be
264 * enabled on the 9050. Also, the UARTS are set in
265 * 16450 mode by default, so we have to enable the
266 * 16C950 'enhanced' mode so that we can use the
271 * enable/disable interrupts
273 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
276 writel(irq_config, p + 0x4c);
279 * Read the register back to ensure that it took effect.
287 static void pci_plx9050_exit(struct pci_dev *dev)
291 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
297 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
302 * Read the register back to ensure that it took effect.
309 #define NI8420_INT_ENABLE_REG 0x38
310 #define NI8420_INT_ENABLE_BIT 0x2000
312 static void pci_ni8420_exit(struct pci_dev *dev)
315 unsigned int bar = 0;
317 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
318 moan_device("no memory in bar", dev);
322 p = pci_ioremap_bar(dev, bar);
326 /* Disable the CPU Interrupt */
327 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
328 p + NI8420_INT_ENABLE_REG);
334 #define MITE_IOWBSR1 0xc4
335 #define MITE_IOWCR1 0xf4
336 #define MITE_LCIMR1 0x08
337 #define MITE_LCIMR2 0x10
339 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
341 static void pci_ni8430_exit(struct pci_dev *dev)
344 unsigned int bar = 0;
346 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
347 moan_device("no memory in bar", dev);
351 p = pci_ioremap_bar(dev, bar);
355 /* Disable the CPU Interrupt */
356 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
360 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
362 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
363 struct uart_8250_port *port, int idx)
365 unsigned int bar, offset = board->first_offset;
370 /* first four channels map to 0, 0x100, 0x200, 0x300 */
371 offset += idx * board->uart_offset;
372 } else if (idx < 8) {
373 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
374 offset += idx * board->uart_offset + 0xC00;
375 } else /* we have only 8 ports on PMC-OCTALPRO */
378 return setup_port(priv, port, bar, offset, board->reg_shift);
382 * This does initialization for PMC OCTALPRO cards:
383 * maps the device memory, resets the UARTs (needed, bc
384 * if the module is removed and inserted again, the card
385 * is in the sleep mode) and enables global interrupt.
388 /* global control register offset for SBS PMC-OctalPro */
389 #define OCT_REG_CR_OFF 0x500
391 static int sbs_init(struct pci_dev *dev)
395 p = pci_ioremap_bar(dev, 0);
399 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
400 writeb(0x10, p + OCT_REG_CR_OFF);
402 writeb(0x0, p + OCT_REG_CR_OFF);
404 /* Set bit-2 (INTENABLE) of Control Register */
405 writeb(0x4, p + OCT_REG_CR_OFF);
412 * Disables the global interrupt of PMC-OctalPro
415 static void sbs_exit(struct pci_dev *dev)
419 p = pci_ioremap_bar(dev, 0);
420 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
422 writeb(0, p + OCT_REG_CR_OFF);
427 * SIIG serial cards have an PCI interface chip which also controls
428 * the UART clocking frequency. Each UART can be clocked independently
429 * (except cards equipped with 4 UARTs) and initial clocking settings
430 * are stored in the EEPROM chip. It can cause problems because this
431 * version of serial driver doesn't support differently clocked UART's
432 * on single PCI card. To prevent this, initialization functions set
433 * high frequency clocking for all UART's on given card. It is safe (I
434 * hope) because it doesn't touch EEPROM settings to prevent conflicts
435 * with other OSes (like M$ DOS).
437 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
439 * There is two family of SIIG serial cards with different PCI
440 * interface chip and different configuration methods:
441 * - 10x cards have control registers in IO and/or memory space;
442 * - 20x cards have control registers in standard PCI configuration space.
444 * Note: all 10x cards have PCI device ids 0x10..
445 * all 20x cards have PCI device ids 0x20..
447 * There are also Quartet Serial cards which use Oxford Semiconductor
448 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
450 * Note: some SIIG cards are probed by the parport_serial object.
453 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
454 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
456 static int pci_siig10x_init(struct pci_dev *dev)
461 switch (dev->device & 0xfff8) {
462 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
465 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
468 default: /* 1S1P, 4S */
473 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
477 writew(readw(p + 0x28) & data, p + 0x28);
483 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
484 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
486 static int pci_siig20x_init(struct pci_dev *dev)
490 /* Change clock frequency for the first UART. */
491 pci_read_config_byte(dev, 0x6f, &data);
492 pci_write_config_byte(dev, 0x6f, data & 0xef);
494 /* If this card has 2 UART, we have to do the same with second UART. */
495 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
496 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
497 pci_read_config_byte(dev, 0x73, &data);
498 pci_write_config_byte(dev, 0x73, data & 0xef);
503 static int pci_siig_init(struct pci_dev *dev)
505 unsigned int type = dev->device & 0xff00;
508 return pci_siig10x_init(dev);
509 else if (type == 0x2000)
510 return pci_siig20x_init(dev);
512 moan_device("Unknown SIIG card", dev);
516 static int pci_siig_setup(struct serial_private *priv,
517 const struct pciserial_board *board,
518 struct uart_8250_port *port, int idx)
520 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
524 offset = (idx - 4) * 8;
527 return setup_port(priv, port, bar, offset, 0);
531 * Timedia has an explosion of boards, and to avoid the PCI table from
532 * growing *huge*, we use this function to collapse some 70 entries
533 * in the PCI table into one, for sanity's and compactness's sake.
535 static const unsigned short timedia_single_port[] = {
536 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
539 static const unsigned short timedia_dual_port[] = {
540 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
541 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
542 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
543 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
547 static const unsigned short timedia_quad_port[] = {
548 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
549 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
550 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
554 static const unsigned short timedia_eight_port[] = {
555 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
556 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
559 static const struct timedia_struct {
561 const unsigned short *ids;
563 { 1, timedia_single_port },
564 { 2, timedia_dual_port },
565 { 4, timedia_quad_port },
566 { 8, timedia_eight_port }
570 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
571 * listing them individually, this driver merely grabs them all with
572 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
573 * and should be left free to be claimed by parport_serial instead.
575 static int pci_timedia_probe(struct pci_dev *dev)
578 * Check the third digit of the subdevice ID
579 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
581 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
583 "ignoring Timedia subdevice %04x for parport_serial\n",
584 dev->subsystem_device);
591 static int pci_timedia_init(struct pci_dev *dev)
593 const unsigned short *ids;
596 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
597 ids = timedia_data[i].ids;
598 for (j = 0; ids[j]; j++)
599 if (dev->subsystem_device == ids[j])
600 return timedia_data[i].num;
606 * Timedia/SUNIX uses a mixture of BARs and offsets
607 * Ugh, this is ugly as all hell --- TYT
610 pci_timedia_setup(struct serial_private *priv,
611 const struct pciserial_board *board,
612 struct uart_8250_port *port, int idx)
614 unsigned int bar = 0, offset = board->first_offset;
621 offset = board->uart_offset;
628 offset = board->uart_offset;
637 return setup_port(priv, port, bar, offset, board->reg_shift);
641 * Some Titan cards are also a little weird
644 titan_400l_800l_setup(struct serial_private *priv,
645 const struct pciserial_board *board,
646 struct uart_8250_port *port, int idx)
648 unsigned int bar, offset = board->first_offset;
659 offset = (idx - 2) * board->uart_offset;
662 return setup_port(priv, port, bar, offset, board->reg_shift);
665 static int pci_xircom_init(struct pci_dev *dev)
671 static int pci_ni8420_init(struct pci_dev *dev)
674 unsigned int bar = 0;
676 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
677 moan_device("no memory in bar", dev);
681 p = pci_ioremap_bar(dev, bar);
685 /* Enable CPU Interrupt */
686 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
687 p + NI8420_INT_ENABLE_REG);
693 #define MITE_IOWBSR1_WSIZE 0xa
694 #define MITE_IOWBSR1_WIN_OFFSET 0x800
695 #define MITE_IOWBSR1_WENAB (1 << 7)
696 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
697 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
698 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
700 static int pci_ni8430_init(struct pci_dev *dev)
703 struct pci_bus_region region;
705 unsigned int bar = 0;
707 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
708 moan_device("no memory in bar", dev);
712 p = pci_ioremap_bar(dev, bar);
717 * Set device window address and size in BAR0, while acknowledging that
718 * the resource structure may contain a translated address that differs
719 * from the address the device responds to.
721 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]);
722 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
723 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
724 writel(device_window, p + MITE_IOWBSR1);
726 /* Set window access to go to RAMSEL IO address space */
727 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
730 /* Enable IO Bus Interrupt 0 */
731 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
733 /* Enable CPU Interrupt */
734 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
740 /* UART Port Control Register */
741 #define NI8430_PORTCON 0x0f
742 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
745 pci_ni8430_setup(struct serial_private *priv,
746 const struct pciserial_board *board,
747 struct uart_8250_port *port, int idx)
749 struct pci_dev *dev = priv->dev;
751 unsigned int bar, offset = board->first_offset;
753 if (idx >= board->num_ports)
756 bar = FL_GET_BASE(board->flags);
757 offset += idx * board->uart_offset;
759 p = pci_ioremap_bar(dev, bar);
763 /* enable the transceiver */
764 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
765 p + offset + NI8430_PORTCON);
769 return setup_port(priv, port, bar, offset, board->reg_shift);
772 static int pci_netmos_9900_setup(struct serial_private *priv,
773 const struct pciserial_board *board,
774 struct uart_8250_port *port, int idx)
778 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
779 (priv->dev->subsystem_device & 0xff00) == 0x3000) {
780 /* netmos apparently orders BARs by datasheet layout, so serial
781 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
785 return setup_port(priv, port, bar, 0, board->reg_shift);
787 return pci_default_setup(priv, board, port, idx);
791 /* the 99xx series comes with a range of device IDs and a variety
794 * 9900 has varying capabilities and can cascade to sub-controllers
795 * (cascading should be purely internal)
796 * 9904 is hardwired with 4 serial ports
797 * 9912 and 9922 are hardwired with 2 serial ports
799 static int pci_netmos_9900_numports(struct pci_dev *dev)
801 unsigned int c = dev->class;
803 unsigned short sub_serports;
809 } else if ((pi == 0) &&
810 (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
811 /* two possibilities: 0x30ps encodes number of parallel and
812 * serial ports, or 0x1000 indicates *something*. This is not
813 * immediately obvious, since the 2s1p+4s configuration seems
814 * to offer all functionality on functions 0..2, while still
815 * advertising the same function 3 as the 4s+2s1p config.
817 sub_serports = dev->subsystem_device & 0xf;
818 if (sub_serports > 0) {
821 dev_err(&dev->dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
826 moan_device("unknown NetMos/Mostech program interface", dev);
830 static int pci_netmos_init(struct pci_dev *dev)
832 /* subdevice 0x00PS means <P> parallel, <S> serial */
833 unsigned int num_serial = dev->subsystem_device & 0xf;
835 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
836 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
839 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
840 dev->subsystem_device == 0x0299)
843 switch (dev->device) { /* FALLTHROUGH on all */
844 case PCI_DEVICE_ID_NETMOS_9904:
845 case PCI_DEVICE_ID_NETMOS_9912:
846 case PCI_DEVICE_ID_NETMOS_9922:
847 case PCI_DEVICE_ID_NETMOS_9900:
848 num_serial = pci_netmos_9900_numports(dev);
852 if (num_serial == 0 ) {
853 moan_device("unknown NetMos/Mostech device", dev);
864 * These chips are available with optionally one parallel port and up to
865 * two serial ports. Unfortunately they all have the same product id.
867 * Basic configuration is done over a region of 32 I/O ports. The base
868 * ioport is called INTA or INTC, depending on docs/other drivers.
870 * The region of the 32 I/O ports is configured in POSIO0R...
874 #define ITE_887x_MISCR 0x9c
875 #define ITE_887x_INTCBAR 0x78
876 #define ITE_887x_UARTBAR 0x7c
877 #define ITE_887x_PS0BAR 0x10
878 #define ITE_887x_POSIO0 0x60
881 #define ITE_887x_IOSIZE 32
882 /* I/O space size (bits 26-24; 8 bytes = 011b) */
883 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
884 /* I/O space size (bits 26-24; 32 bytes = 101b) */
885 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
886 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
887 #define ITE_887x_POSIO_SPEED (3 << 29)
888 /* enable IO_Space bit */
889 #define ITE_887x_POSIO_ENABLE (1 << 31)
891 static int pci_ite887x_init(struct pci_dev *dev)
893 /* inta_addr are the configuration addresses of the ITE */
894 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
897 struct resource *iobase = NULL;
898 u32 miscr, uartbar, ioport;
900 /* search for the base-ioport */
902 while (inta_addr[i] && iobase == NULL) {
903 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
905 if (iobase != NULL) {
906 /* write POSIO0R - speed | size | ioport */
907 pci_write_config_dword(dev, ITE_887x_POSIO0,
908 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
909 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
910 /* write INTCBAR - ioport */
911 pci_write_config_dword(dev, ITE_887x_INTCBAR,
913 ret = inb(inta_addr[i]);
915 /* ioport connected */
918 release_region(iobase->start, ITE_887x_IOSIZE);
925 dev_err(&dev->dev, "ite887x: could not find iobase\n");
929 /* start of undocumented type checking (see parport_pc.c) */
930 type = inb(iobase->start + 0x18) & 0x0f;
933 case 0x2: /* ITE8871 (1P) */
934 case 0xa: /* ITE8875 (1P) */
937 case 0xe: /* ITE8872 (2S1P) */
940 case 0x6: /* ITE8873 (1S) */
943 case 0x8: /* ITE8874 (2S) */
947 moan_device("Unknown ITE887x", dev);
951 /* configure all serial ports */
952 for (i = 0; i < ret; i++) {
953 /* read the I/O port from the device */
954 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
956 ioport &= 0x0000FF00; /* the actual base address */
957 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
958 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
959 ITE_887x_POSIO_IOSIZE_8 | ioport);
961 /* write the ioport to the UARTBAR */
962 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
963 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
964 uartbar |= (ioport << (16 * i)); /* set the ioport */
965 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
967 /* get current config */
968 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
969 /* disable interrupts (UARTx_Routing[3:0]) */
970 miscr &= ~(0xf << (12 - 4 * i));
971 /* activate the UART (UARTx_En) */
972 miscr |= 1 << (23 - i);
973 /* write new config with activated UART */
974 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
978 /* the device has no UARTs if we get here */
979 release_region(iobase->start, ITE_887x_IOSIZE);
985 static void pci_ite887x_exit(struct pci_dev *dev)
988 /* the ioport is bit 0-15 in POSIO0R */
989 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
991 release_region(ioport, ITE_887x_IOSIZE);
995 * EndRun Technologies.
996 * Determine the number of ports available on the device.
998 #define PCI_VENDOR_ID_ENDRUN 0x7401
999 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100
1001 static int pci_endrun_init(struct pci_dev *dev)
1004 unsigned long deviceID;
1005 unsigned int number_uarts = 0;
1007 /* EndRun device is all 0xexxx */
1008 if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1009 (dev->device & 0xf000) != 0xe000)
1012 p = pci_iomap(dev, 0, 5);
1016 deviceID = ioread32(p);
1018 if (deviceID == 0x07000200) {
1019 number_uarts = ioread8(p + 4);
1021 "%d ports detected on EndRun PCI Express device\n",
1024 pci_iounmap(dev, p);
1025 return number_uarts;
1029 * Oxford Semiconductor Inc.
1030 * Check that device is part of the Tornado range of devices, then determine
1031 * the number of ports available on the device.
1033 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1036 unsigned long deviceID;
1037 unsigned int number_uarts = 0;
1039 /* OxSemi Tornado devices are all 0xCxxx */
1040 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1041 (dev->device & 0xF000) != 0xC000)
1044 p = pci_iomap(dev, 0, 5);
1048 deviceID = ioread32(p);
1049 /* Tornado device */
1050 if (deviceID == 0x07000200) {
1051 number_uarts = ioread8(p + 4);
1053 "%d ports detected on Oxford PCI Express device\n",
1056 pci_iounmap(dev, p);
1057 return number_uarts;
1060 static int pci_asix_setup(struct serial_private *priv,
1061 const struct pciserial_board *board,
1062 struct uart_8250_port *port, int idx)
1064 port->bugs |= UART_BUG_PARITY;
1065 return pci_default_setup(priv, board, port, idx);
1068 /* Quatech devices have their own extra interface features */
1070 struct quatech_feature {
1075 #define QPCR_TEST_FOR1 0x3F
1076 #define QPCR_TEST_GET1 0x00
1077 #define QPCR_TEST_FOR2 0x40
1078 #define QPCR_TEST_GET2 0x40
1079 #define QPCR_TEST_FOR3 0x80
1080 #define QPCR_TEST_GET3 0x40
1081 #define QPCR_TEST_FOR4 0xC0
1082 #define QPCR_TEST_GET4 0x80
1084 #define QOPR_CLOCK_X1 0x0000
1085 #define QOPR_CLOCK_X2 0x0001
1086 #define QOPR_CLOCK_X4 0x0002
1087 #define QOPR_CLOCK_X8 0x0003
1088 #define QOPR_CLOCK_RATE_MASK 0x0003
1091 static struct quatech_feature quatech_cards[] = {
1092 { PCI_DEVICE_ID_QUATECH_QSC100, 1 },
1093 { PCI_DEVICE_ID_QUATECH_DSC100, 1 },
1094 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 },
1095 { PCI_DEVICE_ID_QUATECH_DSC200, 1 },
1096 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 },
1097 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 },
1098 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 },
1099 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 },
1100 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 },
1101 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 },
1102 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 },
1103 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1104 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1105 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1106 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1107 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1108 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1109 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1110 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1114 static int pci_quatech_amcc(u16 devid)
1116 struct quatech_feature *qf = &quatech_cards[0];
1118 if (qf->devid == devid)
1122 pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1126 static int pci_quatech_rqopr(struct uart_8250_port *port)
1128 unsigned long base = port->port.iobase;
1131 LCR = inb(base + UART_LCR);
1132 outb(0xBF, base + UART_LCR);
1133 val = inb(base + UART_SCR);
1134 outb(LCR, base + UART_LCR);
1138 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1140 unsigned long base = port->port.iobase;
1143 LCR = inb(base + UART_LCR);
1144 outb(0xBF, base + UART_LCR);
1145 val = inb(base + UART_SCR);
1146 outb(qopr, base + UART_SCR);
1147 outb(LCR, base + UART_LCR);
1150 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1152 unsigned long base = port->port.iobase;
1155 LCR = inb(base + UART_LCR);
1156 outb(0xBF, base + UART_LCR);
1157 val = inb(base + UART_SCR);
1158 outb(val | 0x10, base + UART_SCR);
1159 qmcr = inb(base + UART_MCR);
1160 outb(val, base + UART_SCR);
1161 outb(LCR, base + UART_LCR);
1166 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1168 unsigned long base = port->port.iobase;
1171 LCR = inb(base + UART_LCR);
1172 outb(0xBF, base + UART_LCR);
1173 val = inb(base + UART_SCR);
1174 outb(val | 0x10, base + UART_SCR);
1175 outb(qmcr, base + UART_MCR);
1176 outb(val, base + UART_SCR);
1177 outb(LCR, base + UART_LCR);
1180 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1182 unsigned long base = port->port.iobase;
1185 LCR = inb(base + UART_LCR);
1186 outb(0xBF, base + UART_LCR);
1187 val = inb(base + UART_SCR);
1189 outb(0x80, UART_LCR);
1190 if (!(inb(UART_SCR) & 0x20)) {
1191 outb(LCR, base + UART_LCR);
1198 static int pci_quatech_test(struct uart_8250_port *port)
1201 u8 qopr = pci_quatech_rqopr(port);
1202 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1203 reg = pci_quatech_rqopr(port) & 0xC0;
1204 if (reg != QPCR_TEST_GET1)
1206 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1207 reg = pci_quatech_rqopr(port) & 0xC0;
1208 if (reg != QPCR_TEST_GET2)
1210 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1211 reg = pci_quatech_rqopr(port) & 0xC0;
1212 if (reg != QPCR_TEST_GET3)
1214 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1215 reg = pci_quatech_rqopr(port) & 0xC0;
1216 if (reg != QPCR_TEST_GET4)
1219 pci_quatech_wqopr(port, qopr);
1223 static int pci_quatech_clock(struct uart_8250_port *port)
1226 unsigned long clock;
1228 if (pci_quatech_test(port) < 0)
1231 qopr = pci_quatech_rqopr(port);
1233 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1234 reg = pci_quatech_rqopr(port);
1235 if (reg & QOPR_CLOCK_X8) {
1239 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1240 reg = pci_quatech_rqopr(port);
1241 if (!(reg & QOPR_CLOCK_X8)) {
1245 reg &= QOPR_CLOCK_X8;
1246 if (reg == QOPR_CLOCK_X2) {
1248 set = QOPR_CLOCK_X2;
1249 } else if (reg == QOPR_CLOCK_X4) {
1251 set = QOPR_CLOCK_X4;
1252 } else if (reg == QOPR_CLOCK_X8) {
1254 set = QOPR_CLOCK_X8;
1257 set = QOPR_CLOCK_X1;
1259 qopr &= ~QOPR_CLOCK_RATE_MASK;
1263 pci_quatech_wqopr(port, qopr);
1267 static int pci_quatech_rs422(struct uart_8250_port *port)
1272 if (!pci_quatech_has_qmcr(port))
1274 qmcr = pci_quatech_rqmcr(port);
1275 pci_quatech_wqmcr(port, 0xFF);
1276 if (pci_quatech_rqmcr(port))
1278 pci_quatech_wqmcr(port, qmcr);
1282 static int pci_quatech_init(struct pci_dev *dev)
1284 if (pci_quatech_amcc(dev->device)) {
1285 unsigned long base = pci_resource_start(dev, 0);
1288 outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1289 tmp = inl(base + 0x3c);
1290 outl(tmp | 0x01000000, base + 0x3c);
1291 outl(tmp &= ~0x01000000, base + 0x3c);
1297 static int pci_quatech_setup(struct serial_private *priv,
1298 const struct pciserial_board *board,
1299 struct uart_8250_port *port, int idx)
1301 /* Needed by pci_quatech calls below */
1302 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1303 /* Set up the clocking */
1304 port->port.uartclk = pci_quatech_clock(port);
1305 /* For now just warn about RS422 */
1306 if (pci_quatech_rs422(port))
1307 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1308 return pci_default_setup(priv, board, port, idx);
1311 static void pci_quatech_exit(struct pci_dev *dev)
1315 static int pci_default_setup(struct serial_private *priv,
1316 const struct pciserial_board *board,
1317 struct uart_8250_port *port, int idx)
1319 unsigned int bar, offset = board->first_offset, maxnr;
1321 bar = FL_GET_BASE(board->flags);
1322 if (board->flags & FL_BASE_BARS)
1325 offset += idx * board->uart_offset;
1327 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1328 (board->reg_shift + 3);
1330 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1333 return setup_port(priv, port, bar, offset, board->reg_shift);
1336 static int pci_pericom_setup(struct serial_private *priv,
1337 const struct pciserial_board *board,
1338 struct uart_8250_port *port, int idx)
1340 unsigned int bar, offset = board->first_offset, maxnr;
1342 bar = FL_GET_BASE(board->flags);
1343 if (board->flags & FL_BASE_BARS)
1346 offset += idx * board->uart_offset;
1348 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1349 (board->reg_shift + 3);
1351 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1354 port->port.uartclk = 14745600;
1356 return setup_port(priv, port, bar, offset, board->reg_shift);
1360 ce4100_serial_setup(struct serial_private *priv,
1361 const struct pciserial_board *board,
1362 struct uart_8250_port *port, int idx)
1366 ret = setup_port(priv, port, idx, 0, board->reg_shift);
1367 port->port.iotype = UPIO_MEM32;
1368 port->port.type = PORT_XSCALE;
1369 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1370 port->port.regshift = 2;
1375 #define PCI_DEVICE_ID_INTEL_BYT_UART1 0x0f0a
1376 #define PCI_DEVICE_ID_INTEL_BYT_UART2 0x0f0c
1378 #define PCI_DEVICE_ID_INTEL_BSW_UART1 0x228a
1379 #define PCI_DEVICE_ID_INTEL_BSW_UART2 0x228c
1381 #define BYT_PRV_CLK 0x800
1382 #define BYT_PRV_CLK_EN (1 << 0)
1383 #define BYT_PRV_CLK_M_VAL_SHIFT 1
1384 #define BYT_PRV_CLK_N_VAL_SHIFT 16
1385 #define BYT_PRV_CLK_UPDATE (1 << 31)
1387 #define BYT_TX_OVF_INT 0x820
1388 #define BYT_TX_OVF_INT_MASK (1 << 1)
1391 byt_set_termios(struct uart_port *p, struct ktermios *termios,
1392 struct ktermios *old)
1394 unsigned int baud = tty_termios_baud_rate(termios);
1399 * For baud rates 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M and 4M the
1400 * dividers must be adjusted.
1402 * uartclk = (m / n) * 100 MHz, where m <= n
1411 p->uartclk = 64000000;
1416 p->uartclk = 56000000;
1422 p->uartclk = 48000000;
1427 p->uartclk = 40000000;
1432 p->uartclk = 73728000;
1435 /* Reset the clock */
1436 reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT);
1437 writel(reg, p->membase + BYT_PRV_CLK);
1438 reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE;
1439 writel(reg, p->membase + BYT_PRV_CLK);
1441 serial8250_do_set_termios(p, termios, old);
1444 static bool byt_dma_filter(struct dma_chan *chan, void *param)
1446 struct dw_dma_slave *dws = param;
1448 if (dws->dma_dev != chan->device->dev)
1451 chan->private = dws;
1456 byt_serial_setup(struct serial_private *priv,
1457 const struct pciserial_board *board,
1458 struct uart_8250_port *port, int idx)
1460 struct pci_dev *pdev = priv->dev;
1461 struct device *dev = port->port.dev;
1462 struct uart_8250_dma *dma;
1463 struct dw_dma_slave *tx_param, *rx_param;
1464 struct pci_dev *dma_dev;
1467 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
1471 tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL);
1475 rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL);
1479 switch (pdev->device) {
1480 case PCI_DEVICE_ID_INTEL_BYT_UART1:
1481 case PCI_DEVICE_ID_INTEL_BSW_UART1:
1482 rx_param->src_id = 3;
1483 tx_param->dst_id = 2;
1485 case PCI_DEVICE_ID_INTEL_BYT_UART2:
1486 case PCI_DEVICE_ID_INTEL_BSW_UART2:
1487 rx_param->src_id = 5;
1488 tx_param->dst_id = 4;
1494 rx_param->src_master = 1;
1495 rx_param->dst_master = 0;
1497 dma->rxconf.src_maxburst = 16;
1499 tx_param->src_master = 1;
1500 tx_param->dst_master = 0;
1502 dma->txconf.dst_maxburst = 16;
1504 dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
1505 rx_param->dma_dev = &dma_dev->dev;
1506 tx_param->dma_dev = &dma_dev->dev;
1508 dma->fn = byt_dma_filter;
1509 dma->rx_param = rx_param;
1510 dma->tx_param = tx_param;
1512 ret = pci_default_setup(priv, board, port, idx);
1513 port->port.iotype = UPIO_MEM;
1514 port->port.type = PORT_16550A;
1515 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1516 port->port.set_termios = byt_set_termios;
1517 port->port.fifosize = 64;
1518 port->tx_loadsz = 64;
1520 port->capabilities = UART_CAP_FIFO | UART_CAP_AFE;
1522 /* Disable Tx counter interrupts */
1523 writel(BYT_TX_OVF_INT_MASK, port->port.membase + BYT_TX_OVF_INT);
1529 pci_omegapci_setup(struct serial_private *priv,
1530 const struct pciserial_board *board,
1531 struct uart_8250_port *port, int idx)
1533 return setup_port(priv, port, 2, idx * 8, 0);
1537 pci_brcm_trumanage_setup(struct serial_private *priv,
1538 const struct pciserial_board *board,
1539 struct uart_8250_port *port, int idx)
1541 int ret = pci_default_setup(priv, board, port, idx);
1543 port->port.type = PORT_BRCM_TRUMANAGE;
1544 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1548 static int pci_fintek_setup(struct serial_private *priv,
1549 const struct pciserial_board *board,
1550 struct uart_8250_port *port, int idx)
1552 struct pci_dev *pdev = priv->dev;
1554 unsigned long iobase;
1555 unsigned long ciobase = 0;
1560 * Find each UARTs offset in PCI configuraion space
1600 /* Unknown number of ports, get out of here */
1605 base = pci_resource_start(priv->dev, 3);
1606 ciobase = (int)(base + (0x8 * idx));
1609 /* Get the io address dispatch from the BIOS */
1610 pci_read_config_dword(pdev, 0x24, &bar_data[0]);
1611 pci_read_config_dword(pdev, 0x20, &bar_data[1]);
1612 pci_read_config_dword(pdev, 0x1c, &bar_data[2]);
1614 /* Calculate Real IO Port */
1615 iobase = (bar_data[idx/4] & 0xffffffe0) + (idx % 4) * 8;
1617 dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%lx ciobase=0x%lx config_base=0x%2x\n",
1618 __func__, idx, iobase, ciobase, config_base);
1620 /* Enable UART I/O port */
1621 pci_write_config_byte(pdev, config_base + 0x00, 0x01);
1623 /* Select 128-byte FIFO and 8x FIFO threshold */
1624 pci_write_config_byte(pdev, config_base + 0x01, 0x33);
1627 pci_write_config_byte(pdev, config_base + 0x04, (u8)(iobase & 0xff));
1630 pci_write_config_byte(pdev, config_base + 0x05, (u8)((iobase & 0xff00) >> 8));
1632 /* irq number, this usually fails, but the spec says to do it anyway. */
1633 pci_write_config_byte(pdev, config_base + 0x06, pdev->irq);
1635 port->port.iotype = UPIO_PORT;
1636 port->port.iobase = iobase;
1637 port->port.mapbase = 0;
1638 port->port.membase = NULL;
1639 port->port.regshift = 0;
1644 static int skip_tx_en_setup(struct serial_private *priv,
1645 const struct pciserial_board *board,
1646 struct uart_8250_port *port, int idx)
1648 port->port.flags |= UPF_NO_TXEN_TEST;
1649 dev_dbg(&priv->dev->dev,
1650 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1651 priv->dev->vendor, priv->dev->device,
1652 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1654 return pci_default_setup(priv, board, port, idx);
1657 static void kt_handle_break(struct uart_port *p)
1659 struct uart_8250_port *up = up_to_u8250p(p);
1661 * On receipt of a BI, serial device in Intel ME (Intel
1662 * management engine) needs to have its fifos cleared for sane
1663 * SOL (Serial Over Lan) output.
1665 serial8250_clear_and_reinit_fifos(up);
1668 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1670 struct uart_8250_port *up = up_to_u8250p(p);
1674 * When the Intel ME (management engine) gets reset its serial
1675 * port registers could return 0 momentarily. Functions like
1676 * serial8250_console_write, read and save the IER, perform
1677 * some operation and then restore it. In order to avoid
1678 * setting IER register inadvertently to 0, if the value read
1679 * is 0, double check with ier value in uart_8250_port and use
1680 * that instead. up->ier should be the same value as what is
1681 * currently configured.
1683 val = inb(p->iobase + offset);
1684 if (offset == UART_IER) {
1691 static int kt_serial_setup(struct serial_private *priv,
1692 const struct pciserial_board *board,
1693 struct uart_8250_port *port, int idx)
1695 port->port.flags |= UPF_BUG_THRE;
1696 port->port.serial_in = kt_serial_in;
1697 port->port.handle_break = kt_handle_break;
1698 return skip_tx_en_setup(priv, board, port, idx);
1701 static int pci_eg20t_init(struct pci_dev *dev)
1703 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1711 pci_xr17c154_setup(struct serial_private *priv,
1712 const struct pciserial_board *board,
1713 struct uart_8250_port *port, int idx)
1715 port->port.flags |= UPF_EXAR_EFR;
1716 return pci_default_setup(priv, board, port, idx);
1720 pci_xr17v35x_setup(struct serial_private *priv,
1721 const struct pciserial_board *board,
1722 struct uart_8250_port *port, int idx)
1726 p = pci_ioremap_bar(priv->dev, 0);
1730 port->port.flags |= UPF_EXAR_EFR;
1733 * Setup Multipurpose Input/Output pins.
1736 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/
1737 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/
1738 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/
1739 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/
1740 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/
1741 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/
1742 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/
1743 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/
1744 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/
1745 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/
1746 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/
1747 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/
1749 writeb(0x00, p + UART_EXAR_8XMODE);
1750 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1751 writeb(128, p + UART_EXAR_TXTRG);
1752 writeb(128, p + UART_EXAR_RXTRG);
1755 return pci_default_setup(priv, board, port, idx);
1758 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
1759 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
1760 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
1761 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
1764 pci_fastcom335_setup(struct serial_private *priv,
1765 const struct pciserial_board *board,
1766 struct uart_8250_port *port, int idx)
1770 p = pci_ioremap_bar(priv->dev, 0);
1774 port->port.flags |= UPF_EXAR_EFR;
1777 * Setup Multipurpose Input/Output pins.
1780 switch (priv->dev->device) {
1781 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
1782 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
1783 writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */
1784 writeb(0x00, p + 0x92); /* MPIOINV[7:0] */
1785 writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */
1787 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
1788 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
1789 writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */
1790 writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */
1791 writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */
1794 writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */
1795 writeb(0x00, p + 0x91); /* MPIO3T[7:0] */
1796 writeb(0x00, p + 0x94); /* MPIOOD[7:0] */
1798 writeb(0x00, p + UART_EXAR_8XMODE);
1799 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1800 writeb(32, p + UART_EXAR_TXTRG);
1801 writeb(32, p + UART_EXAR_RXTRG);
1804 return pci_default_setup(priv, board, port, idx);
1808 pci_wch_ch353_setup(struct serial_private *priv,
1809 const struct pciserial_board *board,
1810 struct uart_8250_port *port, int idx)
1812 port->port.flags |= UPF_FIXED_TYPE;
1813 port->port.type = PORT_16550A;
1814 return pci_default_setup(priv, board, port, idx);
1818 pci_wch_ch38x_setup(struct serial_private *priv,
1819 const struct pciserial_board *board,
1820 struct uart_8250_port *port, int idx)
1822 port->port.flags |= UPF_FIXED_TYPE;
1823 port->port.type = PORT_16850;
1824 return pci_default_setup(priv, board, port, idx);
1827 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1828 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1829 #define PCI_DEVICE_ID_OCTPRO 0x0001
1830 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1831 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1832 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1833 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
1834 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
1835 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
1836 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
1837 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1838 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1839 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
1840 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
1841 #define PCI_DEVICE_ID_TITAN_200I 0x8028
1842 #define PCI_DEVICE_ID_TITAN_400I 0x8048
1843 #define PCI_DEVICE_ID_TITAN_800I 0x8088
1844 #define PCI_DEVICE_ID_TITAN_800EH 0xA007
1845 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1846 #define PCI_DEVICE_ID_TITAN_400EH 0xA009
1847 #define PCI_DEVICE_ID_TITAN_100E 0xA010
1848 #define PCI_DEVICE_ID_TITAN_200E 0xA012
1849 #define PCI_DEVICE_ID_TITAN_400E 0xA013
1850 #define PCI_DEVICE_ID_TITAN_800E 0xA014
1851 #define PCI_DEVICE_ID_TITAN_200EI 0xA016
1852 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
1853 #define PCI_DEVICE_ID_TITAN_200V3 0xA306
1854 #define PCI_DEVICE_ID_TITAN_400V3 0xA310
1855 #define PCI_DEVICE_ID_TITAN_410V3 0xA312
1856 #define PCI_DEVICE_ID_TITAN_800V3 0xA314
1857 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315
1858 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
1859 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
1860 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
1861 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1862 #define PCI_VENDOR_ID_WCH 0x4348
1863 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253
1864 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
1865 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
1866 #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053
1867 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
1868 #define PCI_VENDOR_ID_AGESTAR 0x5372
1869 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872
1870 #define PCI_VENDOR_ID_ASIX 0x9710
1871 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
1872 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
1873 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
1874 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1875 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1876 #define PCI_DEVICE_ID_INTEL_QRK_UART 0x0936
1878 #define PCI_VENDOR_ID_SUNIX 0x1fd4
1879 #define PCI_DEVICE_ID_SUNIX_1999 0x1999
1881 #define PCIE_VENDOR_ID_WCH 0x1c00
1882 #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250
1883 #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470
1885 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1886 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1887 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
1890 * Master list of serial port init/setup/exit quirks.
1891 * This does not describe the general nature of the port.
1892 * (ie, baud base, number and location of ports, etc)
1894 * This list is ordered alphabetically by vendor then device.
1895 * Specific entries must come before more generic entries.
1897 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1899 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1902 .vendor = PCI_VENDOR_ID_AMCC,
1903 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
1904 .subvendor = PCI_ANY_ID,
1905 .subdevice = PCI_ANY_ID,
1906 .setup = addidata_apci7800_setup,
1909 * AFAVLAB cards - these may be called via parport_serial
1910 * It is not clear whether this applies to all products.
1913 .vendor = PCI_VENDOR_ID_AFAVLAB,
1914 .device = PCI_ANY_ID,
1915 .subvendor = PCI_ANY_ID,
1916 .subdevice = PCI_ANY_ID,
1917 .setup = afavlab_setup,
1923 .vendor = PCI_VENDOR_ID_HP,
1924 .device = PCI_DEVICE_ID_HP_DIVA,
1925 .subvendor = PCI_ANY_ID,
1926 .subdevice = PCI_ANY_ID,
1927 .init = pci_hp_diva_init,
1928 .setup = pci_hp_diva_setup,
1934 .vendor = PCI_VENDOR_ID_INTEL,
1935 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1936 .subvendor = 0xe4bf,
1937 .subdevice = PCI_ANY_ID,
1938 .init = pci_inteli960ni_init,
1939 .setup = pci_default_setup,
1942 .vendor = PCI_VENDOR_ID_INTEL,
1943 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1944 .subvendor = PCI_ANY_ID,
1945 .subdevice = PCI_ANY_ID,
1946 .setup = skip_tx_en_setup,
1949 .vendor = PCI_VENDOR_ID_INTEL,
1950 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1951 .subvendor = PCI_ANY_ID,
1952 .subdevice = PCI_ANY_ID,
1953 .setup = skip_tx_en_setup,
1956 .vendor = PCI_VENDOR_ID_INTEL,
1957 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1958 .subvendor = PCI_ANY_ID,
1959 .subdevice = PCI_ANY_ID,
1960 .setup = skip_tx_en_setup,
1963 .vendor = PCI_VENDOR_ID_INTEL,
1964 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
1965 .subvendor = PCI_ANY_ID,
1966 .subdevice = PCI_ANY_ID,
1967 .setup = ce4100_serial_setup,
1970 .vendor = PCI_VENDOR_ID_INTEL,
1971 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
1972 .subvendor = PCI_ANY_ID,
1973 .subdevice = PCI_ANY_ID,
1974 .setup = kt_serial_setup,
1977 .vendor = PCI_VENDOR_ID_INTEL,
1978 .device = PCI_DEVICE_ID_INTEL_BYT_UART1,
1979 .subvendor = PCI_ANY_ID,
1980 .subdevice = PCI_ANY_ID,
1981 .setup = byt_serial_setup,
1984 .vendor = PCI_VENDOR_ID_INTEL,
1985 .device = PCI_DEVICE_ID_INTEL_BYT_UART2,
1986 .subvendor = PCI_ANY_ID,
1987 .subdevice = PCI_ANY_ID,
1988 .setup = byt_serial_setup,
1991 .vendor = PCI_VENDOR_ID_INTEL,
1992 .device = PCI_DEVICE_ID_INTEL_QRK_UART,
1993 .subvendor = PCI_ANY_ID,
1994 .subdevice = PCI_ANY_ID,
1995 .setup = pci_default_setup,
1998 .vendor = PCI_VENDOR_ID_INTEL,
1999 .device = PCI_DEVICE_ID_INTEL_BSW_UART1,
2000 .subvendor = PCI_ANY_ID,
2001 .subdevice = PCI_ANY_ID,
2002 .setup = byt_serial_setup,
2005 .vendor = PCI_VENDOR_ID_INTEL,
2006 .device = PCI_DEVICE_ID_INTEL_BSW_UART2,
2007 .subvendor = PCI_ANY_ID,
2008 .subdevice = PCI_ANY_ID,
2009 .setup = byt_serial_setup,
2015 .vendor = PCI_VENDOR_ID_ITE,
2016 .device = PCI_DEVICE_ID_ITE_8872,
2017 .subvendor = PCI_ANY_ID,
2018 .subdevice = PCI_ANY_ID,
2019 .init = pci_ite887x_init,
2020 .setup = pci_default_setup,
2021 .exit = pci_ite887x_exit,
2024 * National Instruments
2027 .vendor = PCI_VENDOR_ID_NI,
2028 .device = PCI_DEVICE_ID_NI_PCI23216,
2029 .subvendor = PCI_ANY_ID,
2030 .subdevice = PCI_ANY_ID,
2031 .init = pci_ni8420_init,
2032 .setup = pci_default_setup,
2033 .exit = pci_ni8420_exit,
2036 .vendor = PCI_VENDOR_ID_NI,
2037 .device = PCI_DEVICE_ID_NI_PCI2328,
2038 .subvendor = PCI_ANY_ID,
2039 .subdevice = PCI_ANY_ID,
2040 .init = pci_ni8420_init,
2041 .setup = pci_default_setup,
2042 .exit = pci_ni8420_exit,
2045 .vendor = PCI_VENDOR_ID_NI,
2046 .device = PCI_DEVICE_ID_NI_PCI2324,
2047 .subvendor = PCI_ANY_ID,
2048 .subdevice = PCI_ANY_ID,
2049 .init = pci_ni8420_init,
2050 .setup = pci_default_setup,
2051 .exit = pci_ni8420_exit,
2054 .vendor = PCI_VENDOR_ID_NI,
2055 .device = PCI_DEVICE_ID_NI_PCI2322,
2056 .subvendor = PCI_ANY_ID,
2057 .subdevice = PCI_ANY_ID,
2058 .init = pci_ni8420_init,
2059 .setup = pci_default_setup,
2060 .exit = pci_ni8420_exit,
2063 .vendor = PCI_VENDOR_ID_NI,
2064 .device = PCI_DEVICE_ID_NI_PCI2324I,
2065 .subvendor = PCI_ANY_ID,
2066 .subdevice = PCI_ANY_ID,
2067 .init = pci_ni8420_init,
2068 .setup = pci_default_setup,
2069 .exit = pci_ni8420_exit,
2072 .vendor = PCI_VENDOR_ID_NI,
2073 .device = PCI_DEVICE_ID_NI_PCI2322I,
2074 .subvendor = PCI_ANY_ID,
2075 .subdevice = PCI_ANY_ID,
2076 .init = pci_ni8420_init,
2077 .setup = pci_default_setup,
2078 .exit = pci_ni8420_exit,
2081 .vendor = PCI_VENDOR_ID_NI,
2082 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
2083 .subvendor = PCI_ANY_ID,
2084 .subdevice = PCI_ANY_ID,
2085 .init = pci_ni8420_init,
2086 .setup = pci_default_setup,
2087 .exit = pci_ni8420_exit,
2090 .vendor = PCI_VENDOR_ID_NI,
2091 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
2092 .subvendor = PCI_ANY_ID,
2093 .subdevice = PCI_ANY_ID,
2094 .init = pci_ni8420_init,
2095 .setup = pci_default_setup,
2096 .exit = pci_ni8420_exit,
2099 .vendor = PCI_VENDOR_ID_NI,
2100 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
2101 .subvendor = PCI_ANY_ID,
2102 .subdevice = PCI_ANY_ID,
2103 .init = pci_ni8420_init,
2104 .setup = pci_default_setup,
2105 .exit = pci_ni8420_exit,
2108 .vendor = PCI_VENDOR_ID_NI,
2109 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
2110 .subvendor = PCI_ANY_ID,
2111 .subdevice = PCI_ANY_ID,
2112 .init = pci_ni8420_init,
2113 .setup = pci_default_setup,
2114 .exit = pci_ni8420_exit,
2117 .vendor = PCI_VENDOR_ID_NI,
2118 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
2119 .subvendor = PCI_ANY_ID,
2120 .subdevice = PCI_ANY_ID,
2121 .init = pci_ni8420_init,
2122 .setup = pci_default_setup,
2123 .exit = pci_ni8420_exit,
2126 .vendor = PCI_VENDOR_ID_NI,
2127 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
2128 .subvendor = PCI_ANY_ID,
2129 .subdevice = PCI_ANY_ID,
2130 .init = pci_ni8420_init,
2131 .setup = pci_default_setup,
2132 .exit = pci_ni8420_exit,
2135 .vendor = PCI_VENDOR_ID_NI,
2136 .device = PCI_ANY_ID,
2137 .subvendor = PCI_ANY_ID,
2138 .subdevice = PCI_ANY_ID,
2139 .init = pci_ni8430_init,
2140 .setup = pci_ni8430_setup,
2141 .exit = pci_ni8430_exit,
2145 .vendor = PCI_VENDOR_ID_QUATECH,
2146 .device = PCI_ANY_ID,
2147 .subvendor = PCI_ANY_ID,
2148 .subdevice = PCI_ANY_ID,
2149 .init = pci_quatech_init,
2150 .setup = pci_quatech_setup,
2151 .exit = pci_quatech_exit,
2157 .vendor = PCI_VENDOR_ID_PANACOM,
2158 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2159 .subvendor = PCI_ANY_ID,
2160 .subdevice = PCI_ANY_ID,
2161 .init = pci_plx9050_init,
2162 .setup = pci_default_setup,
2163 .exit = pci_plx9050_exit,
2166 .vendor = PCI_VENDOR_ID_PANACOM,
2167 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2168 .subvendor = PCI_ANY_ID,
2169 .subdevice = PCI_ANY_ID,
2170 .init = pci_plx9050_init,
2171 .setup = pci_default_setup,
2172 .exit = pci_plx9050_exit,
2180 .subvendor = PCI_ANY_ID,
2181 .subdevice = PCI_ANY_ID,
2182 .setup = pci_pericom_setup,
2187 .subvendor = PCI_ANY_ID,
2188 .subdevice = PCI_ANY_ID,
2189 .setup = pci_pericom_setup,
2194 .subvendor = PCI_ANY_ID,
2195 .subdevice = PCI_ANY_ID,
2196 .setup = pci_pericom_setup,
2203 .vendor = PCI_VENDOR_ID_PLX,
2204 .device = PCI_DEVICE_ID_PLX_9030,
2205 .subvendor = PCI_SUBVENDOR_ID_PERLE,
2206 .subdevice = PCI_ANY_ID,
2207 .setup = pci_default_setup,
2210 .vendor = PCI_VENDOR_ID_PLX,
2211 .device = PCI_DEVICE_ID_PLX_9050,
2212 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
2213 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
2214 .init = pci_plx9050_init,
2215 .setup = pci_default_setup,
2216 .exit = pci_plx9050_exit,
2219 .vendor = PCI_VENDOR_ID_PLX,
2220 .device = PCI_DEVICE_ID_PLX_9050,
2221 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
2222 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2223 .init = pci_plx9050_init,
2224 .setup = pci_default_setup,
2225 .exit = pci_plx9050_exit,
2228 .vendor = PCI_VENDOR_ID_PLX,
2229 .device = PCI_DEVICE_ID_PLX_ROMULUS,
2230 .subvendor = PCI_VENDOR_ID_PLX,
2231 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
2232 .init = pci_plx9050_init,
2233 .setup = pci_default_setup,
2234 .exit = pci_plx9050_exit,
2237 * SBS Technologies, Inc., PMC-OCTALPRO 232
2240 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2241 .device = PCI_DEVICE_ID_OCTPRO,
2242 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2243 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
2249 * SBS Technologies, Inc., PMC-OCTALPRO 422
2252 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2253 .device = PCI_DEVICE_ID_OCTPRO,
2254 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2255 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
2261 * SBS Technologies, Inc., P-Octal 232
2264 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2265 .device = PCI_DEVICE_ID_OCTPRO,
2266 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2267 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
2273 * SBS Technologies, Inc., P-Octal 422
2276 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2277 .device = PCI_DEVICE_ID_OCTPRO,
2278 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2279 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
2285 * SIIG cards - these may be called via parport_serial
2288 .vendor = PCI_VENDOR_ID_SIIG,
2289 .device = PCI_ANY_ID,
2290 .subvendor = PCI_ANY_ID,
2291 .subdevice = PCI_ANY_ID,
2292 .init = pci_siig_init,
2293 .setup = pci_siig_setup,
2299 .vendor = PCI_VENDOR_ID_TITAN,
2300 .device = PCI_DEVICE_ID_TITAN_400L,
2301 .subvendor = PCI_ANY_ID,
2302 .subdevice = PCI_ANY_ID,
2303 .setup = titan_400l_800l_setup,
2306 .vendor = PCI_VENDOR_ID_TITAN,
2307 .device = PCI_DEVICE_ID_TITAN_800L,
2308 .subvendor = PCI_ANY_ID,
2309 .subdevice = PCI_ANY_ID,
2310 .setup = titan_400l_800l_setup,
2316 .vendor = PCI_VENDOR_ID_TIMEDIA,
2317 .device = PCI_DEVICE_ID_TIMEDIA_1889,
2318 .subvendor = PCI_VENDOR_ID_TIMEDIA,
2319 .subdevice = PCI_ANY_ID,
2320 .probe = pci_timedia_probe,
2321 .init = pci_timedia_init,
2322 .setup = pci_timedia_setup,
2325 .vendor = PCI_VENDOR_ID_TIMEDIA,
2326 .device = PCI_ANY_ID,
2327 .subvendor = PCI_ANY_ID,
2328 .subdevice = PCI_ANY_ID,
2329 .setup = pci_timedia_setup,
2332 * SUNIX (Timedia) cards
2333 * Do not "probe" for these cards as there is at least one combination
2334 * card that should be handled by parport_pc that doesn't match the
2335 * rule in pci_timedia_probe.
2336 * It is part number is MIO5079A but its subdevice ID is 0x0102.
2337 * There are some boards with part number SER5037AL that report
2338 * subdevice ID 0x0002.
2341 .vendor = PCI_VENDOR_ID_SUNIX,
2342 .device = PCI_DEVICE_ID_SUNIX_1999,
2343 .subvendor = PCI_VENDOR_ID_SUNIX,
2344 .subdevice = PCI_ANY_ID,
2345 .init = pci_timedia_init,
2346 .setup = pci_timedia_setup,
2352 .vendor = PCI_VENDOR_ID_EXAR,
2353 .device = PCI_DEVICE_ID_EXAR_XR17C152,
2354 .subvendor = PCI_ANY_ID,
2355 .subdevice = PCI_ANY_ID,
2356 .setup = pci_xr17c154_setup,
2359 .vendor = PCI_VENDOR_ID_EXAR,
2360 .device = PCI_DEVICE_ID_EXAR_XR17C154,
2361 .subvendor = PCI_ANY_ID,
2362 .subdevice = PCI_ANY_ID,
2363 .setup = pci_xr17c154_setup,
2366 .vendor = PCI_VENDOR_ID_EXAR,
2367 .device = PCI_DEVICE_ID_EXAR_XR17C158,
2368 .subvendor = PCI_ANY_ID,
2369 .subdevice = PCI_ANY_ID,
2370 .setup = pci_xr17c154_setup,
2373 .vendor = PCI_VENDOR_ID_EXAR,
2374 .device = PCI_DEVICE_ID_EXAR_XR17V352,
2375 .subvendor = PCI_ANY_ID,
2376 .subdevice = PCI_ANY_ID,
2377 .setup = pci_xr17v35x_setup,
2380 .vendor = PCI_VENDOR_ID_EXAR,
2381 .device = PCI_DEVICE_ID_EXAR_XR17V354,
2382 .subvendor = PCI_ANY_ID,
2383 .subdevice = PCI_ANY_ID,
2384 .setup = pci_xr17v35x_setup,
2387 .vendor = PCI_VENDOR_ID_EXAR,
2388 .device = PCI_DEVICE_ID_EXAR_XR17V358,
2389 .subvendor = PCI_ANY_ID,
2390 .subdevice = PCI_ANY_ID,
2391 .setup = pci_xr17v35x_setup,
2397 .vendor = PCI_VENDOR_ID_XIRCOM,
2398 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2399 .subvendor = PCI_ANY_ID,
2400 .subdevice = PCI_ANY_ID,
2401 .init = pci_xircom_init,
2402 .setup = pci_default_setup,
2405 * Netmos cards - these may be called via parport_serial
2408 .vendor = PCI_VENDOR_ID_NETMOS,
2409 .device = PCI_ANY_ID,
2410 .subvendor = PCI_ANY_ID,
2411 .subdevice = PCI_ANY_ID,
2412 .init = pci_netmos_init,
2413 .setup = pci_netmos_9900_setup,
2416 * EndRun Technologies
2419 .vendor = PCI_VENDOR_ID_ENDRUN,
2420 .device = PCI_ANY_ID,
2421 .subvendor = PCI_ANY_ID,
2422 .subdevice = PCI_ANY_ID,
2423 .init = pci_endrun_init,
2424 .setup = pci_default_setup,
2427 * For Oxford Semiconductor Tornado based devices
2430 .vendor = PCI_VENDOR_ID_OXSEMI,
2431 .device = PCI_ANY_ID,
2432 .subvendor = PCI_ANY_ID,
2433 .subdevice = PCI_ANY_ID,
2434 .init = pci_oxsemi_tornado_init,
2435 .setup = pci_default_setup,
2438 .vendor = PCI_VENDOR_ID_MAINPINE,
2439 .device = PCI_ANY_ID,
2440 .subvendor = PCI_ANY_ID,
2441 .subdevice = PCI_ANY_ID,
2442 .init = pci_oxsemi_tornado_init,
2443 .setup = pci_default_setup,
2446 .vendor = PCI_VENDOR_ID_DIGI,
2447 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2448 .subvendor = PCI_SUBVENDOR_ID_IBM,
2449 .subdevice = PCI_ANY_ID,
2450 .init = pci_oxsemi_tornado_init,
2451 .setup = pci_default_setup,
2454 .vendor = PCI_VENDOR_ID_INTEL,
2456 .subvendor = PCI_ANY_ID,
2457 .subdevice = PCI_ANY_ID,
2458 .init = pci_eg20t_init,
2459 .setup = pci_default_setup,
2462 .vendor = PCI_VENDOR_ID_INTEL,
2464 .subvendor = PCI_ANY_ID,
2465 .subdevice = PCI_ANY_ID,
2466 .init = pci_eg20t_init,
2467 .setup = pci_default_setup,
2470 .vendor = PCI_VENDOR_ID_INTEL,
2472 .subvendor = PCI_ANY_ID,
2473 .subdevice = PCI_ANY_ID,
2474 .init = pci_eg20t_init,
2475 .setup = pci_default_setup,
2478 .vendor = PCI_VENDOR_ID_INTEL,
2480 .subvendor = PCI_ANY_ID,
2481 .subdevice = PCI_ANY_ID,
2482 .init = pci_eg20t_init,
2483 .setup = pci_default_setup,
2488 .subvendor = PCI_ANY_ID,
2489 .subdevice = PCI_ANY_ID,
2490 .init = pci_eg20t_init,
2491 .setup = pci_default_setup,
2496 .subvendor = PCI_ANY_ID,
2497 .subdevice = PCI_ANY_ID,
2498 .init = pci_eg20t_init,
2499 .setup = pci_default_setup,
2504 .subvendor = PCI_ANY_ID,
2505 .subdevice = PCI_ANY_ID,
2506 .init = pci_eg20t_init,
2507 .setup = pci_default_setup,
2512 .subvendor = PCI_ANY_ID,
2513 .subdevice = PCI_ANY_ID,
2514 .init = pci_eg20t_init,
2515 .setup = pci_default_setup,
2520 .subvendor = PCI_ANY_ID,
2521 .subdevice = PCI_ANY_ID,
2522 .init = pci_eg20t_init,
2523 .setup = pci_default_setup,
2526 * Cronyx Omega PCI (PLX-chip based)
2529 .vendor = PCI_VENDOR_ID_PLX,
2530 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2531 .subvendor = PCI_ANY_ID,
2532 .subdevice = PCI_ANY_ID,
2533 .setup = pci_omegapci_setup,
2535 /* WCH CH353 1S1P card (16550 clone) */
2537 .vendor = PCI_VENDOR_ID_WCH,
2538 .device = PCI_DEVICE_ID_WCH_CH353_1S1P,
2539 .subvendor = PCI_ANY_ID,
2540 .subdevice = PCI_ANY_ID,
2541 .setup = pci_wch_ch353_setup,
2543 /* WCH CH353 2S1P card (16550 clone) */
2545 .vendor = PCI_VENDOR_ID_WCH,
2546 .device = PCI_DEVICE_ID_WCH_CH353_2S1P,
2547 .subvendor = PCI_ANY_ID,
2548 .subdevice = PCI_ANY_ID,
2549 .setup = pci_wch_ch353_setup,
2551 /* WCH CH353 4S card (16550 clone) */
2553 .vendor = PCI_VENDOR_ID_WCH,
2554 .device = PCI_DEVICE_ID_WCH_CH353_4S,
2555 .subvendor = PCI_ANY_ID,
2556 .subdevice = PCI_ANY_ID,
2557 .setup = pci_wch_ch353_setup,
2559 /* WCH CH353 2S1PF card (16550 clone) */
2561 .vendor = PCI_VENDOR_ID_WCH,
2562 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2563 .subvendor = PCI_ANY_ID,
2564 .subdevice = PCI_ANY_ID,
2565 .setup = pci_wch_ch353_setup,
2567 /* WCH CH352 2S card (16550 clone) */
2569 .vendor = PCI_VENDOR_ID_WCH,
2570 .device = PCI_DEVICE_ID_WCH_CH352_2S,
2571 .subvendor = PCI_ANY_ID,
2572 .subdevice = PCI_ANY_ID,
2573 .setup = pci_wch_ch353_setup,
2575 /* WCH CH382 2S1P card (16850 clone) */
2577 .vendor = PCIE_VENDOR_ID_WCH,
2578 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P,
2579 .subvendor = PCI_ANY_ID,
2580 .subdevice = PCI_ANY_ID,
2581 .setup = pci_wch_ch38x_setup,
2583 /* WCH CH384 4S card (16850 clone) */
2585 .vendor = PCIE_VENDOR_ID_WCH,
2586 .device = PCIE_DEVICE_ID_WCH_CH384_4S,
2587 .subvendor = PCI_ANY_ID,
2588 .subdevice = PCI_ANY_ID,
2589 .setup = pci_wch_ch38x_setup,
2592 * ASIX devices with FIFO bug
2595 .vendor = PCI_VENDOR_ID_ASIX,
2596 .device = PCI_ANY_ID,
2597 .subvendor = PCI_ANY_ID,
2598 .subdevice = PCI_ANY_ID,
2599 .setup = pci_asix_setup,
2602 * Commtech, Inc. Fastcom adapters
2606 .vendor = PCI_VENDOR_ID_COMMTECH,
2607 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335,
2608 .subvendor = PCI_ANY_ID,
2609 .subdevice = PCI_ANY_ID,
2610 .setup = pci_fastcom335_setup,
2613 .vendor = PCI_VENDOR_ID_COMMTECH,
2614 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335,
2615 .subvendor = PCI_ANY_ID,
2616 .subdevice = PCI_ANY_ID,
2617 .setup = pci_fastcom335_setup,
2620 .vendor = PCI_VENDOR_ID_COMMTECH,
2621 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335,
2622 .subvendor = PCI_ANY_ID,
2623 .subdevice = PCI_ANY_ID,
2624 .setup = pci_fastcom335_setup,
2627 .vendor = PCI_VENDOR_ID_COMMTECH,
2628 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335,
2629 .subvendor = PCI_ANY_ID,
2630 .subdevice = PCI_ANY_ID,
2631 .setup = pci_fastcom335_setup,
2634 .vendor = PCI_VENDOR_ID_COMMTECH,
2635 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE,
2636 .subvendor = PCI_ANY_ID,
2637 .subdevice = PCI_ANY_ID,
2638 .setup = pci_xr17v35x_setup,
2641 .vendor = PCI_VENDOR_ID_COMMTECH,
2642 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE,
2643 .subvendor = PCI_ANY_ID,
2644 .subdevice = PCI_ANY_ID,
2645 .setup = pci_xr17v35x_setup,
2648 .vendor = PCI_VENDOR_ID_COMMTECH,
2649 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE,
2650 .subvendor = PCI_ANY_ID,
2651 .subdevice = PCI_ANY_ID,
2652 .setup = pci_xr17v35x_setup,
2655 * Broadcom TruManage (NetXtreme)
2658 .vendor = PCI_VENDOR_ID_BROADCOM,
2659 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2660 .subvendor = PCI_ANY_ID,
2661 .subdevice = PCI_ANY_ID,
2662 .setup = pci_brcm_trumanage_setup,
2667 .subvendor = PCI_ANY_ID,
2668 .subdevice = PCI_ANY_ID,
2669 .setup = pci_fintek_setup,
2674 .subvendor = PCI_ANY_ID,
2675 .subdevice = PCI_ANY_ID,
2676 .setup = pci_fintek_setup,
2681 .subvendor = PCI_ANY_ID,
2682 .subdevice = PCI_ANY_ID,
2683 .setup = pci_fintek_setup,
2687 * Default "match everything" terminator entry
2690 .vendor = PCI_ANY_ID,
2691 .device = PCI_ANY_ID,
2692 .subvendor = PCI_ANY_ID,
2693 .subdevice = PCI_ANY_ID,
2694 .setup = pci_default_setup,
2698 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2700 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2703 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2705 struct pci_serial_quirk *quirk;
2707 for (quirk = pci_serial_quirks; ; quirk++)
2708 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2709 quirk_id_matches(quirk->device, dev->device) &&
2710 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2711 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2716 static inline int get_pci_irq(struct pci_dev *dev,
2717 const struct pciserial_board *board)
2719 if (board->flags & FL_NOIRQ)
2726 * This is the configuration table for all of the PCI serial boards
2727 * which we support. It is directly indexed by the pci_board_num_t enum
2728 * value, which is encoded in the pci_device_id PCI probe table's
2729 * driver_data member.
2731 * The makeup of these names are:
2732 * pbn_bn{_bt}_n_baud{_offsetinhex}
2734 * bn = PCI BAR number
2735 * bt = Index using PCI BARs
2736 * n = number of serial ports
2738 * offsetinhex = offset for each sequential port (in hex)
2740 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2742 * Please note: in theory if n = 1, _bt infix should make no difference.
2743 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2745 enum pci_board_num_t {
2762 pbn_b0_2_1152000_200,
2763 pbn_b0_4_1152000_200,
2764 pbn_b0_8_1152000_200,
2769 pbn_b0_2_1843200_200,
2770 pbn_b0_4_1843200_200,
2771 pbn_b0_8_1843200_200,
2845 * Board-specific versions.
2851 pbn_endrun_2_4000000,
2853 pbn_oxsemi_1_4000000,
2854 pbn_oxsemi_2_4000000,
2855 pbn_oxsemi_4_4000000,
2856 pbn_oxsemi_8_4000000,
2869 pbn_exar_ibm_saturn,
2875 pbn_ADDIDATA_PCIe_1_3906250,
2876 pbn_ADDIDATA_PCIe_2_3906250,
2877 pbn_ADDIDATA_PCIe_4_3906250,
2878 pbn_ADDIDATA_PCIe_8_3906250,
2879 pbn_ce4100_1_115200,
2883 pbn_NETMOS9900_2s_115200,
2892 * uart_offset - the space between channels
2893 * reg_shift - describes how the UART registers are mapped
2894 * to PCI memory by the card.
2895 * For example IER register on SBS, Inc. PMC-OctPro is located at
2896 * offset 0x10 from the UART base, while UART_IER is defined as 1
2897 * in include/linux/serial_reg.h,
2898 * see first lines of serial_in() and serial_out() in 8250.c
2901 static struct pciserial_board pci_boards[] = {
2905 .base_baud = 115200,
2908 [pbn_b0_1_115200] = {
2911 .base_baud = 115200,
2914 [pbn_b0_2_115200] = {
2917 .base_baud = 115200,
2920 [pbn_b0_4_115200] = {
2923 .base_baud = 115200,
2926 [pbn_b0_5_115200] = {
2929 .base_baud = 115200,
2932 [pbn_b0_8_115200] = {
2935 .base_baud = 115200,
2938 [pbn_b0_1_921600] = {
2941 .base_baud = 921600,
2944 [pbn_b0_2_921600] = {
2947 .base_baud = 921600,
2950 [pbn_b0_4_921600] = {
2953 .base_baud = 921600,
2957 [pbn_b0_2_1130000] = {
2960 .base_baud = 1130000,
2964 [pbn_b0_4_1152000] = {
2967 .base_baud = 1152000,
2971 [pbn_b0_2_1152000_200] = {
2974 .base_baud = 1152000,
2975 .uart_offset = 0x200,
2978 [pbn_b0_4_1152000_200] = {
2981 .base_baud = 1152000,
2982 .uart_offset = 0x200,
2985 [pbn_b0_8_1152000_200] = {
2988 .base_baud = 1152000,
2989 .uart_offset = 0x200,
2992 [pbn_b0_2_1843200] = {
2995 .base_baud = 1843200,
2998 [pbn_b0_4_1843200] = {
3001 .base_baud = 1843200,
3005 [pbn_b0_2_1843200_200] = {
3008 .base_baud = 1843200,
3009 .uart_offset = 0x200,
3011 [pbn_b0_4_1843200_200] = {
3014 .base_baud = 1843200,
3015 .uart_offset = 0x200,
3017 [pbn_b0_8_1843200_200] = {
3020 .base_baud = 1843200,
3021 .uart_offset = 0x200,
3023 [pbn_b0_1_4000000] = {
3026 .base_baud = 4000000,
3030 [pbn_b0_bt_1_115200] = {
3031 .flags = FL_BASE0|FL_BASE_BARS,
3033 .base_baud = 115200,
3036 [pbn_b0_bt_2_115200] = {
3037 .flags = FL_BASE0|FL_BASE_BARS,
3039 .base_baud = 115200,
3042 [pbn_b0_bt_4_115200] = {
3043 .flags = FL_BASE0|FL_BASE_BARS,
3045 .base_baud = 115200,
3048 [pbn_b0_bt_8_115200] = {
3049 .flags = FL_BASE0|FL_BASE_BARS,
3051 .base_baud = 115200,
3055 [pbn_b0_bt_1_460800] = {
3056 .flags = FL_BASE0|FL_BASE_BARS,
3058 .base_baud = 460800,
3061 [pbn_b0_bt_2_460800] = {
3062 .flags = FL_BASE0|FL_BASE_BARS,
3064 .base_baud = 460800,
3067 [pbn_b0_bt_4_460800] = {
3068 .flags = FL_BASE0|FL_BASE_BARS,
3070 .base_baud = 460800,
3074 [pbn_b0_bt_1_921600] = {
3075 .flags = FL_BASE0|FL_BASE_BARS,
3077 .base_baud = 921600,
3080 [pbn_b0_bt_2_921600] = {
3081 .flags = FL_BASE0|FL_BASE_BARS,
3083 .base_baud = 921600,
3086 [pbn_b0_bt_4_921600] = {
3087 .flags = FL_BASE0|FL_BASE_BARS,
3089 .base_baud = 921600,
3092 [pbn_b0_bt_8_921600] = {
3093 .flags = FL_BASE0|FL_BASE_BARS,
3095 .base_baud = 921600,
3099 [pbn_b1_1_115200] = {
3102 .base_baud = 115200,
3105 [pbn_b1_2_115200] = {
3108 .base_baud = 115200,
3111 [pbn_b1_4_115200] = {
3114 .base_baud = 115200,
3117 [pbn_b1_8_115200] = {
3120 .base_baud = 115200,
3123 [pbn_b1_16_115200] = {
3126 .base_baud = 115200,
3130 [pbn_b1_1_921600] = {
3133 .base_baud = 921600,
3136 [pbn_b1_2_921600] = {
3139 .base_baud = 921600,
3142 [pbn_b1_4_921600] = {
3145 .base_baud = 921600,
3148 [pbn_b1_8_921600] = {
3151 .base_baud = 921600,
3154 [pbn_b1_2_1250000] = {
3157 .base_baud = 1250000,
3161 [pbn_b1_bt_1_115200] = {
3162 .flags = FL_BASE1|FL_BASE_BARS,
3164 .base_baud = 115200,
3167 [pbn_b1_bt_2_115200] = {
3168 .flags = FL_BASE1|FL_BASE_BARS,
3170 .base_baud = 115200,
3173 [pbn_b1_bt_4_115200] = {
3174 .flags = FL_BASE1|FL_BASE_BARS,
3176 .base_baud = 115200,
3180 [pbn_b1_bt_2_921600] = {
3181 .flags = FL_BASE1|FL_BASE_BARS,
3183 .base_baud = 921600,
3187 [pbn_b1_1_1382400] = {
3190 .base_baud = 1382400,
3193 [pbn_b1_2_1382400] = {
3196 .base_baud = 1382400,
3199 [pbn_b1_4_1382400] = {
3202 .base_baud = 1382400,
3205 [pbn_b1_8_1382400] = {
3208 .base_baud = 1382400,
3212 [pbn_b2_1_115200] = {
3215 .base_baud = 115200,
3218 [pbn_b2_2_115200] = {
3221 .base_baud = 115200,
3224 [pbn_b2_4_115200] = {
3227 .base_baud = 115200,
3230 [pbn_b2_8_115200] = {
3233 .base_baud = 115200,
3237 [pbn_b2_1_460800] = {
3240 .base_baud = 460800,
3243 [pbn_b2_4_460800] = {
3246 .base_baud = 460800,
3249 [pbn_b2_8_460800] = {
3252 .base_baud = 460800,
3255 [pbn_b2_16_460800] = {
3258 .base_baud = 460800,
3262 [pbn_b2_1_921600] = {
3265 .base_baud = 921600,
3268 [pbn_b2_4_921600] = {
3271 .base_baud = 921600,
3274 [pbn_b2_8_921600] = {
3277 .base_baud = 921600,
3281 [pbn_b2_8_1152000] = {
3284 .base_baud = 1152000,
3288 [pbn_b2_bt_1_115200] = {
3289 .flags = FL_BASE2|FL_BASE_BARS,
3291 .base_baud = 115200,
3294 [pbn_b2_bt_2_115200] = {
3295 .flags = FL_BASE2|FL_BASE_BARS,
3297 .base_baud = 115200,
3300 [pbn_b2_bt_4_115200] = {
3301 .flags = FL_BASE2|FL_BASE_BARS,
3303 .base_baud = 115200,
3307 [pbn_b2_bt_2_921600] = {
3308 .flags = FL_BASE2|FL_BASE_BARS,
3310 .base_baud = 921600,
3313 [pbn_b2_bt_4_921600] = {
3314 .flags = FL_BASE2|FL_BASE_BARS,
3316 .base_baud = 921600,
3320 [pbn_b3_2_115200] = {
3323 .base_baud = 115200,
3326 [pbn_b3_4_115200] = {
3329 .base_baud = 115200,
3332 [pbn_b3_8_115200] = {
3335 .base_baud = 115200,
3339 [pbn_b4_bt_2_921600] = {
3342 .base_baud = 921600,
3345 [pbn_b4_bt_4_921600] = {
3348 .base_baud = 921600,
3351 [pbn_b4_bt_8_921600] = {
3354 .base_baud = 921600,
3359 * Entries following this are board-specific.
3368 .base_baud = 921600,
3369 .uart_offset = 0x400,
3373 .flags = FL_BASE2|FL_BASE_BARS,
3375 .base_baud = 921600,
3376 .uart_offset = 0x400,
3380 .flags = FL_BASE2|FL_BASE_BARS,
3382 .base_baud = 921600,
3383 .uart_offset = 0x400,
3387 /* I think this entry is broken - the first_offset looks wrong --rmk */
3388 [pbn_plx_romulus] = {
3391 .base_baud = 921600,
3392 .uart_offset = 8 << 2,
3394 .first_offset = 0x03,
3398 * EndRun Technologies
3399 * Uses the size of PCI Base region 0 to
3400 * signal now many ports are available
3401 * 2 port 952 Uart support
3403 [pbn_endrun_2_4000000] = {
3406 .base_baud = 4000000,
3407 .uart_offset = 0x200,
3408 .first_offset = 0x1000,
3412 * This board uses the size of PCI Base region 0 to
3413 * signal now many ports are available
3416 .flags = FL_BASE0|FL_REGION_SZ_CAP,
3418 .base_baud = 115200,
3421 [pbn_oxsemi_1_4000000] = {
3424 .base_baud = 4000000,
3425 .uart_offset = 0x200,
3426 .first_offset = 0x1000,
3428 [pbn_oxsemi_2_4000000] = {
3431 .base_baud = 4000000,
3432 .uart_offset = 0x200,
3433 .first_offset = 0x1000,
3435 [pbn_oxsemi_4_4000000] = {
3438 .base_baud = 4000000,
3439 .uart_offset = 0x200,
3440 .first_offset = 0x1000,
3442 [pbn_oxsemi_8_4000000] = {
3445 .base_baud = 4000000,
3446 .uart_offset = 0x200,
3447 .first_offset = 0x1000,
3452 * EKF addition for i960 Boards form EKF with serial port.
3455 [pbn_intel_i960] = {
3458 .base_baud = 921600,
3459 .uart_offset = 8 << 2,
3461 .first_offset = 0x10000,
3464 .flags = FL_BASE0|FL_NOIRQ,
3466 .base_baud = 458333,
3469 .first_offset = 0x20178,
3473 * Computone - uses IOMEM.
3475 [pbn_computone_4] = {
3478 .base_baud = 921600,
3479 .uart_offset = 0x40,
3481 .first_offset = 0x200,
3483 [pbn_computone_6] = {
3486 .base_baud = 921600,
3487 .uart_offset = 0x40,
3489 .first_offset = 0x200,
3491 [pbn_computone_8] = {
3494 .base_baud = 921600,
3495 .uart_offset = 0x40,
3497 .first_offset = 0x200,
3502 .base_baud = 460800,
3507 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3508 * Only basic 16550A support.
3509 * XR17C15[24] are not tested, but they should work.
3511 [pbn_exar_XR17C152] = {
3514 .base_baud = 921600,
3515 .uart_offset = 0x200,
3517 [pbn_exar_XR17C154] = {
3520 .base_baud = 921600,
3521 .uart_offset = 0x200,
3523 [pbn_exar_XR17C158] = {
3526 .base_baud = 921600,
3527 .uart_offset = 0x200,
3529 [pbn_exar_XR17V352] = {
3532 .base_baud = 7812500,
3533 .uart_offset = 0x400,
3537 [pbn_exar_XR17V354] = {
3540 .base_baud = 7812500,
3541 .uart_offset = 0x400,
3545 [pbn_exar_XR17V358] = {
3548 .base_baud = 7812500,
3549 .uart_offset = 0x400,
3553 [pbn_exar_ibm_saturn] = {
3556 .base_baud = 921600,
3557 .uart_offset = 0x200,
3561 * PA Semi PWRficient PA6T-1682M on-chip UART
3563 [pbn_pasemi_1682M] = {
3566 .base_baud = 8333333,
3569 * National Instruments 843x
3574 .base_baud = 3686400,
3575 .uart_offset = 0x10,
3576 .first_offset = 0x800,
3581 .base_baud = 3686400,
3582 .uart_offset = 0x10,
3583 .first_offset = 0x800,
3588 .base_baud = 3686400,
3589 .uart_offset = 0x10,
3590 .first_offset = 0x800,
3595 .base_baud = 3686400,
3596 .uart_offset = 0x10,
3597 .first_offset = 0x800,
3600 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3602 [pbn_ADDIDATA_PCIe_1_3906250] = {
3605 .base_baud = 3906250,
3606 .uart_offset = 0x200,
3607 .first_offset = 0x1000,
3609 [pbn_ADDIDATA_PCIe_2_3906250] = {
3612 .base_baud = 3906250,
3613 .uart_offset = 0x200,
3614 .first_offset = 0x1000,
3616 [pbn_ADDIDATA_PCIe_4_3906250] = {
3619 .base_baud = 3906250,
3620 .uart_offset = 0x200,
3621 .first_offset = 0x1000,
3623 [pbn_ADDIDATA_PCIe_8_3906250] = {
3626 .base_baud = 3906250,
3627 .uart_offset = 0x200,
3628 .first_offset = 0x1000,
3630 [pbn_ce4100_1_115200] = {
3631 .flags = FL_BASE_BARS,
3633 .base_baud = 921600,
3637 * Intel BayTrail HSUART reference clock is 44.2368 MHz at power-on,
3638 * but is overridden by byt_set_termios.
3643 .base_baud = 2764800,
3644 .uart_offset = 0x80,
3650 .base_baud = 2764800,
3656 .base_baud = 115200,
3657 .uart_offset = 0x200,
3659 [pbn_NETMOS9900_2s_115200] = {
3662 .base_baud = 115200,
3664 [pbn_brcm_trumanage] = {
3668 .base_baud = 115200,
3673 .base_baud = 115200,
3674 .first_offset = 0x40,
3679 .base_baud = 115200,
3680 .first_offset = 0x40,
3685 .base_baud = 115200,
3686 .first_offset = 0x40,
3692 .base_baud = 115200,
3694 .first_offset = 0xC0,
3698 static const struct pci_device_id blacklist[] = {
3700 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3701 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3702 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3704 /* multi-io cards handled by parport_serial */
3705 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3706 { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
3707 { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */
3708 { PCI_DEVICE(0x1c00, 0x3470), }, /* WCH CH384 4S */
3712 * Given a complete unknown PCI device, try to use some heuristics to
3713 * guess what the configuration might be, based on the pitiful PCI
3714 * serial specs. Returns 0 on success, 1 on failure.
3717 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
3719 const struct pci_device_id *bldev;
3720 int num_iomem, num_port, first_port = -1, i;
3723 * If it is not a communications device or the programming
3724 * interface is greater than 6, give up.
3726 * (Should we try to make guesses for multiport serial devices
3729 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3730 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3731 (dev->class & 0xff) > 6)
3735 * Do not access blacklisted devices that are known not to
3736 * feature serial ports or are handled by other modules.
3738 for (bldev = blacklist;
3739 bldev < blacklist + ARRAY_SIZE(blacklist);
3741 if (dev->vendor == bldev->vendor &&
3742 dev->device == bldev->device)
3746 num_iomem = num_port = 0;
3747 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3748 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3750 if (first_port == -1)
3753 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3758 * If there is 1 or 0 iomem regions, and exactly one port,
3759 * use it. We guess the number of ports based on the IO
3762 if (num_iomem <= 1 && num_port == 1) {
3763 board->flags = first_port;
3764 board->num_ports = pci_resource_len(dev, first_port) / 8;
3769 * Now guess if we've got a board which indexes by BARs.
3770 * Each IO BAR should be 8 bytes, and they should follow
3775 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3776 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3777 pci_resource_len(dev, i) == 8 &&
3778 (first_port == -1 || (first_port + num_port) == i)) {
3780 if (first_port == -1)
3786 board->flags = first_port | FL_BASE_BARS;
3787 board->num_ports = num_port;
3795 serial_pci_matches(const struct pciserial_board *board,
3796 const struct pciserial_board *guessed)
3799 board->num_ports == guessed->num_ports &&
3800 board->base_baud == guessed->base_baud &&
3801 board->uart_offset == guessed->uart_offset &&
3802 board->reg_shift == guessed->reg_shift &&
3803 board->first_offset == guessed->first_offset;
3806 struct serial_private *
3807 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
3809 struct uart_8250_port uart;
3810 struct serial_private *priv;
3811 struct pci_serial_quirk *quirk;
3812 int rc, nr_ports, i;
3814 nr_ports = board->num_ports;
3817 * Find an init and setup quirks.
3819 quirk = find_quirk(dev);
3822 * Run the new-style initialization function.
3823 * The initialization function returns:
3825 * 0 - use board->num_ports
3826 * >0 - number of ports
3829 rc = quirk->init(dev);
3838 priv = kzalloc(sizeof(struct serial_private) +
3839 sizeof(unsigned int) * nr_ports,
3842 priv = ERR_PTR(-ENOMEM);
3847 priv->quirk = quirk;
3849 memset(&uart, 0, sizeof(uart));
3850 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3851 uart.port.uartclk = board->base_baud * 16;
3852 uart.port.irq = get_pci_irq(dev, board);
3853 uart.port.dev = &dev->dev;
3855 for (i = 0; i < nr_ports; i++) {
3856 if (quirk->setup(priv, board, &uart, i))
3859 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
3860 uart.port.iobase, uart.port.irq, uart.port.iotype);
3862 priv->line[i] = serial8250_register_8250_port(&uart);
3863 if (priv->line[i] < 0) {
3865 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
3866 uart.port.iobase, uart.port.irq,
3867 uart.port.iotype, priv->line[i]);
3880 EXPORT_SYMBOL_GPL(pciserial_init_ports);
3882 void pciserial_remove_ports(struct serial_private *priv)
3884 struct pci_serial_quirk *quirk;
3887 for (i = 0; i < priv->nr; i++)
3888 serial8250_unregister_port(priv->line[i]);
3890 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3891 if (priv->remapped_bar[i])
3892 iounmap(priv->remapped_bar[i]);
3893 priv->remapped_bar[i] = NULL;
3897 * Find the exit quirks.
3899 quirk = find_quirk(priv->dev);
3901 quirk->exit(priv->dev);
3905 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
3907 void pciserial_suspend_ports(struct serial_private *priv)
3911 for (i = 0; i < priv->nr; i++)
3912 if (priv->line[i] >= 0)
3913 serial8250_suspend_port(priv->line[i]);
3916 * Ensure that every init quirk is properly torn down
3918 if (priv->quirk->exit)
3919 priv->quirk->exit(priv->dev);
3921 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
3923 void pciserial_resume_ports(struct serial_private *priv)
3928 * Ensure that the board is correctly configured.
3930 if (priv->quirk->init)
3931 priv->quirk->init(priv->dev);
3933 for (i = 0; i < priv->nr; i++)
3934 if (priv->line[i] >= 0)
3935 serial8250_resume_port(priv->line[i]);
3937 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
3940 * Probe one serial board. Unfortunately, there is no rhyme nor reason
3941 * to the arrangement of serial ports on a PCI card.
3944 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
3946 struct pci_serial_quirk *quirk;
3947 struct serial_private *priv;
3948 const struct pciserial_board *board;
3949 struct pciserial_board tmp;
3952 quirk = find_quirk(dev);
3954 rc = quirk->probe(dev);
3959 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
3960 dev_err(&dev->dev, "invalid driver_data: %ld\n",
3965 board = &pci_boards[ent->driver_data];
3967 rc = pci_enable_device(dev);
3968 pci_save_state(dev);
3972 if (ent->driver_data == pbn_default) {
3974 * Use a copy of the pci_board entry for this;
3975 * avoid changing entries in the table.
3977 memcpy(&tmp, board, sizeof(struct pciserial_board));
3981 * We matched one of our class entries. Try to
3982 * determine the parameters of this board.
3984 rc = serial_pci_guess_board(dev, &tmp);
3989 * We matched an explicit entry. If we are able to
3990 * detect this boards settings with our heuristic,
3991 * then we no longer need this entry.
3993 memcpy(&tmp, &pci_boards[pbn_default],
3994 sizeof(struct pciserial_board));
3995 rc = serial_pci_guess_board(dev, &tmp);
3996 if (rc == 0 && serial_pci_matches(board, &tmp))
3997 moan_device("Redundant entry in serial pci_table.",
4001 priv = pciserial_init_ports(dev, board);
4002 if (!IS_ERR(priv)) {
4003 pci_set_drvdata(dev, priv);
4010 pci_disable_device(dev);
4014 static void pciserial_remove_one(struct pci_dev *dev)
4016 struct serial_private *priv = pci_get_drvdata(dev);
4018 pciserial_remove_ports(priv);
4020 pci_disable_device(dev);
4024 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
4026 struct serial_private *priv = pci_get_drvdata(dev);
4029 pciserial_suspend_ports(priv);
4031 pci_save_state(dev);
4032 pci_set_power_state(dev, pci_choose_state(dev, state));
4036 static int pciserial_resume_one(struct pci_dev *dev)
4039 struct serial_private *priv = pci_get_drvdata(dev);
4041 pci_set_power_state(dev, PCI_D0);
4042 pci_restore_state(dev);
4046 * The device may have been disabled. Re-enable it.
4048 err = pci_enable_device(dev);
4049 /* FIXME: We cannot simply error out here */
4051 dev_err(&dev->dev, "Unable to re-enable ports, trying to continue.\n");
4052 pciserial_resume_ports(priv);
4058 static struct pci_device_id serial_pci_tbl[] = {
4059 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
4060 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
4061 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
4063 /* Advantech also use 0x3618 and 0xf618 */
4064 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
4065 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4067 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
4068 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4070 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4071 PCI_SUBVENDOR_ID_CONNECT_TECH,
4072 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4074 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4075 PCI_SUBVENDOR_ID_CONNECT_TECH,
4076 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4078 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4079 PCI_SUBVENDOR_ID_CONNECT_TECH,
4080 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4082 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4083 PCI_SUBVENDOR_ID_CONNECT_TECH,
4084 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4086 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4087 PCI_SUBVENDOR_ID_CONNECT_TECH,
4088 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4090 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4091 PCI_SUBVENDOR_ID_CONNECT_TECH,
4092 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4094 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4095 PCI_SUBVENDOR_ID_CONNECT_TECH,
4096 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
4098 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4099 PCI_SUBVENDOR_ID_CONNECT_TECH,
4100 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
4102 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4103 PCI_SUBVENDOR_ID_CONNECT_TECH,
4104 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
4106 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4107 PCI_SUBVENDOR_ID_CONNECT_TECH,
4108 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
4110 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4111 PCI_SUBVENDOR_ID_CONNECT_TECH,
4112 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
4114 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4115 PCI_SUBVENDOR_ID_CONNECT_TECH,
4116 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
4118 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4119 PCI_SUBVENDOR_ID_CONNECT_TECH,
4120 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
4122 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4123 PCI_SUBVENDOR_ID_CONNECT_TECH,
4124 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4126 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4127 PCI_SUBVENDOR_ID_CONNECT_TECH,
4128 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4130 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4131 PCI_SUBVENDOR_ID_CONNECT_TECH,
4132 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4134 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4135 PCI_SUBVENDOR_ID_CONNECT_TECH,
4136 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4138 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4139 PCI_VENDOR_ID_AFAVLAB,
4140 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4142 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4143 PCI_SUBVENDOR_ID_CONNECT_TECH,
4144 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
4145 pbn_b0_2_1843200_200 },
4146 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4147 PCI_SUBVENDOR_ID_CONNECT_TECH,
4148 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
4149 pbn_b0_4_1843200_200 },
4150 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4151 PCI_SUBVENDOR_ID_CONNECT_TECH,
4152 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
4153 pbn_b0_8_1843200_200 },
4154 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4155 PCI_SUBVENDOR_ID_CONNECT_TECH,
4156 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
4157 pbn_b0_2_1843200_200 },
4158 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4159 PCI_SUBVENDOR_ID_CONNECT_TECH,
4160 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
4161 pbn_b0_4_1843200_200 },
4162 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4163 PCI_SUBVENDOR_ID_CONNECT_TECH,
4164 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
4165 pbn_b0_8_1843200_200 },
4166 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4167 PCI_SUBVENDOR_ID_CONNECT_TECH,
4168 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
4169 pbn_b0_2_1843200_200 },
4170 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4171 PCI_SUBVENDOR_ID_CONNECT_TECH,
4172 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
4173 pbn_b0_4_1843200_200 },
4174 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4175 PCI_SUBVENDOR_ID_CONNECT_TECH,
4176 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
4177 pbn_b0_8_1843200_200 },
4178 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4179 PCI_SUBVENDOR_ID_CONNECT_TECH,
4180 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
4181 pbn_b0_2_1843200_200 },
4182 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4183 PCI_SUBVENDOR_ID_CONNECT_TECH,
4184 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
4185 pbn_b0_4_1843200_200 },
4186 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4187 PCI_SUBVENDOR_ID_CONNECT_TECH,
4188 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
4189 pbn_b0_8_1843200_200 },
4190 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4191 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
4192 0, 0, pbn_exar_ibm_saturn },
4194 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
4195 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4196 pbn_b2_bt_1_115200 },
4197 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
4198 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4199 pbn_b2_bt_2_115200 },
4200 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
4201 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4202 pbn_b2_bt_4_115200 },
4203 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
4204 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4205 pbn_b2_bt_2_115200 },
4206 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
4207 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4208 pbn_b2_bt_4_115200 },
4209 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
4210 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4212 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4213 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4215 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4216 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4219 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4220 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4221 pbn_b2_bt_2_115200 },
4222 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4223 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4224 pbn_b2_bt_2_921600 },
4226 * VScom SPCOM800, from sl@s.pl
4228 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4229 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4231 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
4232 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4234 /* Unknown card - subdevice 0x1584 */
4235 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4237 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
4239 /* Unknown card - subdevice 0x1588 */
4240 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4242 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4244 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4245 PCI_SUBVENDOR_ID_KEYSPAN,
4246 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4248 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4249 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4251 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4252 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4254 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4255 PCI_VENDOR_ID_ESDGMBH,
4256 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4258 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4259 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4260 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4262 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4263 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4264 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4266 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4267 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4268 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4270 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4271 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4272 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4274 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4275 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4276 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4278 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4279 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4280 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4282 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4283 PCI_SUBVENDOR_ID_EXSYS,
4284 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4287 * Megawolf Romulus PCI Serial Card, from Mike Hudson
4290 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4291 0x10b5, 0x106a, 0, 0,
4294 * EndRun Technologies. PCI express device range.
4295 * EndRun PTP/1588 has 2 Native UARTs.
4297 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4298 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4299 pbn_endrun_2_4000000 },
4301 * Quatech cards. These actually have configurable clocks but for
4302 * now we just use the default.
4304 * 100 series are RS232, 200 series RS422,
4306 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4307 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4309 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4310 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4312 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4313 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4315 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4316 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4318 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4319 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4321 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4322 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4324 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4325 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4327 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4328 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4330 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4331 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4333 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4334 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4336 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4337 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4339 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4340 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4342 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4343 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4345 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4346 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4348 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4349 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4351 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4352 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4354 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4355 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4357 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4358 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4360 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4361 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4364 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4365 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4368 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4369 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4372 { PCI_VENDOR_ID_OXSEMI, 0x9505,
4373 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4374 pbn_b0_bt_2_921600 },
4377 * The below card is a little controversial since it is the
4378 * subject of a PCI vendor/device ID clash. (See
4379 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4380 * For now just used the hex ID 0x950a.
4382 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4383 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4384 0, 0, pbn_b0_2_115200 },
4385 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4386 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4387 0, 0, pbn_b0_2_115200 },
4388 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4389 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4391 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4392 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4394 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4395 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4397 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4398 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4399 pbn_b0_bt_2_921600 },
4400 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4401 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
4405 * Oxford Semiconductor Inc. Tornado PCI express device range.
4407 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
4408 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4410 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
4411 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4413 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
4414 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4415 pbn_oxsemi_1_4000000 },
4416 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
4417 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4418 pbn_oxsemi_1_4000000 },
4419 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
4420 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4422 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
4423 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4425 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
4426 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4427 pbn_oxsemi_1_4000000 },
4428 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
4429 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4430 pbn_oxsemi_1_4000000 },
4431 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
4432 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4434 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
4435 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4437 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
4438 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4440 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
4441 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4443 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
4444 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4445 pbn_oxsemi_2_4000000 },
4446 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
4447 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4448 pbn_oxsemi_2_4000000 },
4449 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
4450 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4451 pbn_oxsemi_4_4000000 },
4452 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
4453 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4454 pbn_oxsemi_4_4000000 },
4455 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
4456 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4457 pbn_oxsemi_8_4000000 },
4458 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
4459 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4460 pbn_oxsemi_8_4000000 },
4461 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
4462 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4463 pbn_oxsemi_1_4000000 },
4464 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
4465 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4466 pbn_oxsemi_1_4000000 },
4467 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
4468 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4469 pbn_oxsemi_1_4000000 },
4470 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
4471 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4472 pbn_oxsemi_1_4000000 },
4473 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
4474 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4475 pbn_oxsemi_1_4000000 },
4476 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
4477 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4478 pbn_oxsemi_1_4000000 },
4479 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
4480 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4481 pbn_oxsemi_1_4000000 },
4482 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
4483 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4484 pbn_oxsemi_1_4000000 },
4485 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
4486 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4487 pbn_oxsemi_1_4000000 },
4488 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
4489 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4490 pbn_oxsemi_1_4000000 },
4491 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
4492 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4493 pbn_oxsemi_1_4000000 },
4494 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
4495 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4496 pbn_oxsemi_1_4000000 },
4497 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
4498 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4499 pbn_oxsemi_1_4000000 },
4500 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
4501 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4502 pbn_oxsemi_1_4000000 },
4503 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
4504 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4505 pbn_oxsemi_1_4000000 },
4506 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4507 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4508 pbn_oxsemi_1_4000000 },
4509 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4510 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4511 pbn_oxsemi_1_4000000 },
4512 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4513 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4514 pbn_oxsemi_1_4000000 },
4515 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4516 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4517 pbn_oxsemi_1_4000000 },
4518 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4519 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4520 pbn_oxsemi_1_4000000 },
4521 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4522 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4523 pbn_oxsemi_1_4000000 },
4524 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4525 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4526 pbn_oxsemi_1_4000000 },
4527 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4528 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4529 pbn_oxsemi_1_4000000 },
4530 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4531 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4532 pbn_oxsemi_1_4000000 },
4533 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4534 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4535 pbn_oxsemi_1_4000000 },
4536 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4537 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4538 pbn_oxsemi_1_4000000 },
4540 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4542 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4543 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4544 pbn_oxsemi_1_4000000 },
4545 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4546 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4547 pbn_oxsemi_2_4000000 },
4548 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4549 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4550 pbn_oxsemi_4_4000000 },
4551 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4552 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4553 pbn_oxsemi_8_4000000 },
4556 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4558 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4559 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4560 pbn_oxsemi_2_4000000 },
4563 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4564 * from skokodyn@yahoo.com
4566 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4567 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4569 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4570 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4572 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4573 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4575 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4576 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4580 * Digitan DS560-558, from jimd@esoft.com
4582 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4583 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4587 * Titan Electronic cards
4588 * The 400L and 800L have a custom setup quirk.
4590 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4591 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4593 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4594 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4596 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4597 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4599 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4600 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4602 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4603 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4605 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4606 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4607 pbn_b1_bt_2_921600 },
4608 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4609 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4610 pbn_b0_bt_4_921600 },
4611 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4612 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4613 pbn_b0_bt_8_921600 },
4614 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4615 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4616 pbn_b4_bt_2_921600 },
4617 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4618 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4619 pbn_b4_bt_4_921600 },
4620 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4621 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4622 pbn_b4_bt_8_921600 },
4623 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4624 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4626 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4627 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4629 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4630 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4632 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4633 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4634 pbn_oxsemi_1_4000000 },
4635 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4636 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4637 pbn_oxsemi_2_4000000 },
4638 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4639 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4640 pbn_oxsemi_4_4000000 },
4641 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4642 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4643 pbn_oxsemi_8_4000000 },
4644 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4645 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4646 pbn_oxsemi_2_4000000 },
4647 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4648 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4649 pbn_oxsemi_2_4000000 },
4650 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4651 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4652 pbn_b0_bt_2_921600 },
4653 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4654 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4656 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4657 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4659 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4660 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4662 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4663 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4666 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4667 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4669 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4670 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4672 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4673 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4675 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4676 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4677 pbn_b2_bt_2_921600 },
4678 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4679 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4680 pbn_b2_bt_2_921600 },
4681 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4682 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4683 pbn_b2_bt_2_921600 },
4684 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4685 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4686 pbn_b2_bt_4_921600 },
4687 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4688 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4689 pbn_b2_bt_4_921600 },
4690 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4691 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4692 pbn_b2_bt_4_921600 },
4693 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4694 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4696 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4697 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4699 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4700 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4702 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4703 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4704 pbn_b0_bt_2_921600 },
4705 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4706 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4707 pbn_b0_bt_2_921600 },
4708 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4709 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4710 pbn_b0_bt_2_921600 },
4711 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4712 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4713 pbn_b0_bt_4_921600 },
4714 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4715 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4716 pbn_b0_bt_4_921600 },
4717 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4718 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4719 pbn_b0_bt_4_921600 },
4720 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4721 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4722 pbn_b0_bt_8_921600 },
4723 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4724 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4725 pbn_b0_bt_8_921600 },
4726 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4727 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4728 pbn_b0_bt_8_921600 },
4731 * Computone devices submitted by Doug McNash dmcnash@computone.com
4733 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4734 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4735 0, 0, pbn_computone_4 },
4736 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4737 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4738 0, 0, pbn_computone_8 },
4739 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4740 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4741 0, 0, pbn_computone_6 },
4743 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4744 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4746 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4747 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4748 pbn_b0_bt_1_921600 },
4753 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4754 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4755 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
4756 pbn_b0_bt_1_921600 },
4758 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4759 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4760 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4761 pbn_b0_bt_1_921600 },
4764 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4766 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4767 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4768 pbn_b0_bt_8_115200 },
4769 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4770 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4771 pbn_b0_bt_8_115200 },
4773 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4774 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4775 pbn_b0_bt_2_115200 },
4776 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4777 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4778 pbn_b0_bt_2_115200 },
4779 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4780 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4781 pbn_b0_bt_2_115200 },
4782 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4783 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4784 pbn_b0_bt_2_115200 },
4785 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4786 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4787 pbn_b0_bt_2_115200 },
4788 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4789 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4790 pbn_b0_bt_4_460800 },
4791 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4792 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4793 pbn_b0_bt_4_460800 },
4794 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4795 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4796 pbn_b0_bt_2_460800 },
4797 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4798 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4799 pbn_b0_bt_2_460800 },
4800 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4801 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4802 pbn_b0_bt_2_460800 },
4803 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4804 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4805 pbn_b0_bt_1_115200 },
4806 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4807 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4808 pbn_b0_bt_1_460800 },
4811 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4812 * Cards are identified by their subsystem vendor IDs, which
4813 * (in hex) match the model number.
4815 * Note that JC140x are RS422/485 cards which require ox950
4816 * ACR = 0x10, and as such are not currently fully supported.
4818 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4819 0x1204, 0x0004, 0, 0,
4821 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4822 0x1208, 0x0004, 0, 0,
4824 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4825 0x1402, 0x0002, 0, 0,
4826 pbn_b0_2_921600 }, */
4827 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4828 0x1404, 0x0004, 0, 0,
4829 pbn_b0_4_921600 }, */
4830 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4831 0x1208, 0x0004, 0, 0,
4834 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4835 0x1204, 0x0004, 0, 0,
4837 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4838 0x1208, 0x0004, 0, 0,
4840 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4841 0x1208, 0x0004, 0, 0,
4844 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4846 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4847 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4851 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4853 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4854 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4858 * RAStel 2 port modem, gerg@moreton.com.au
4860 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
4861 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4862 pbn_b2_bt_2_115200 },
4865 * EKF addition for i960 Boards form EKF with serial port
4867 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
4868 0xE4BF, PCI_ANY_ID, 0, 0,
4872 * Xircom Cardbus/Ethernet combos
4874 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
4875 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4878 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
4880 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
4881 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4885 * Untested PCI modems, sent in from various folks...
4889 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
4891 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
4892 0x1048, 0x1500, 0, 0,
4895 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
4902 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4903 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
4905 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4906 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4908 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
4909 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4912 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
4913 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4915 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
4916 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4918 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
4919 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4923 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
4925 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4926 PCI_ANY_ID, PCI_ANY_ID,
4928 0, pbn_exar_XR17C152 },
4929 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4930 PCI_ANY_ID, PCI_ANY_ID,
4932 0, pbn_exar_XR17C154 },
4933 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4934 PCI_ANY_ID, PCI_ANY_ID,
4936 0, pbn_exar_XR17C158 },
4938 * Exar Corp. XR17V35[248] Dual/Quad/Octal PCIe UARTs
4940 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352,
4941 PCI_ANY_ID, PCI_ANY_ID,
4943 0, pbn_exar_XR17V352 },
4944 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354,
4945 PCI_ANY_ID, PCI_ANY_ID,
4947 0, pbn_exar_XR17V354 },
4948 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358,
4949 PCI_ANY_ID, PCI_ANY_ID,
4951 0, pbn_exar_XR17V358 },
4954 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
4956 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
4957 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4962 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
4963 PCI_ANY_ID, PCI_ANY_ID,
4965 pbn_b1_bt_1_115200 },
4970 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
4971 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
4976 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
4977 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
4980 * Perle PCI-RAS cards
4982 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4983 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
4984 0, 0, pbn_b2_4_921600 },
4985 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4986 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
4987 0, 0, pbn_b2_8_921600 },
4990 * Mainpine series cards: Fairly standard layout but fools
4991 * parts of the autodetect in some cases and uses otherwise
4992 * unmatched communications subclasses in the PCI Express case
4995 { /* RockForceDUO */
4996 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4997 PCI_VENDOR_ID_MAINPINE, 0x0200,
4998 0, 0, pbn_b0_2_115200 },
4999 { /* RockForceQUATRO */
5000 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5001 PCI_VENDOR_ID_MAINPINE, 0x0300,
5002 0, 0, pbn_b0_4_115200 },
5003 { /* RockForceDUO+ */
5004 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5005 PCI_VENDOR_ID_MAINPINE, 0x0400,
5006 0, 0, pbn_b0_2_115200 },
5007 { /* RockForceQUATRO+ */
5008 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5009 PCI_VENDOR_ID_MAINPINE, 0x0500,
5010 0, 0, pbn_b0_4_115200 },
5012 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5013 PCI_VENDOR_ID_MAINPINE, 0x0600,
5014 0, 0, pbn_b0_2_115200 },
5016 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5017 PCI_VENDOR_ID_MAINPINE, 0x0700,
5018 0, 0, pbn_b0_4_115200 },
5019 { /* RockForceOCTO+ */
5020 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5021 PCI_VENDOR_ID_MAINPINE, 0x0800,
5022 0, 0, pbn_b0_8_115200 },
5023 { /* RockForceDUO+ */
5024 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5025 PCI_VENDOR_ID_MAINPINE, 0x0C00,
5026 0, 0, pbn_b0_2_115200 },
5027 { /* RockForceQUARTRO+ */
5028 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5029 PCI_VENDOR_ID_MAINPINE, 0x0D00,
5030 0, 0, pbn_b0_4_115200 },
5031 { /* RockForceOCTO+ */
5032 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5033 PCI_VENDOR_ID_MAINPINE, 0x1D00,
5034 0, 0, pbn_b0_8_115200 },
5036 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5037 PCI_VENDOR_ID_MAINPINE, 0x2000,
5038 0, 0, pbn_b0_1_115200 },
5040 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5041 PCI_VENDOR_ID_MAINPINE, 0x2100,
5042 0, 0, pbn_b0_1_115200 },
5044 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5045 PCI_VENDOR_ID_MAINPINE, 0x2200,
5046 0, 0, pbn_b0_2_115200 },
5048 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5049 PCI_VENDOR_ID_MAINPINE, 0x2300,
5050 0, 0, pbn_b0_2_115200 },
5052 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5053 PCI_VENDOR_ID_MAINPINE, 0x2400,
5054 0, 0, pbn_b0_4_115200 },
5056 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5057 PCI_VENDOR_ID_MAINPINE, 0x2500,
5058 0, 0, pbn_b0_4_115200 },
5060 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5061 PCI_VENDOR_ID_MAINPINE, 0x2600,
5062 0, 0, pbn_b0_8_115200 },
5064 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5065 PCI_VENDOR_ID_MAINPINE, 0x2700,
5066 0, 0, pbn_b0_8_115200 },
5067 { /* IQ Express D1 */
5068 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5069 PCI_VENDOR_ID_MAINPINE, 0x3000,
5070 0, 0, pbn_b0_1_115200 },
5071 { /* IQ Express F1 */
5072 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5073 PCI_VENDOR_ID_MAINPINE, 0x3100,
5074 0, 0, pbn_b0_1_115200 },
5075 { /* IQ Express D2 */
5076 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5077 PCI_VENDOR_ID_MAINPINE, 0x3200,
5078 0, 0, pbn_b0_2_115200 },
5079 { /* IQ Express F2 */
5080 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5081 PCI_VENDOR_ID_MAINPINE, 0x3300,
5082 0, 0, pbn_b0_2_115200 },
5083 { /* IQ Express D4 */
5084 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5085 PCI_VENDOR_ID_MAINPINE, 0x3400,
5086 0, 0, pbn_b0_4_115200 },
5087 { /* IQ Express F4 */
5088 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5089 PCI_VENDOR_ID_MAINPINE, 0x3500,
5090 0, 0, pbn_b0_4_115200 },
5091 { /* IQ Express D8 */
5092 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5093 PCI_VENDOR_ID_MAINPINE, 0x3C00,
5094 0, 0, pbn_b0_8_115200 },
5095 { /* IQ Express F8 */
5096 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5097 PCI_VENDOR_ID_MAINPINE, 0x3D00,
5098 0, 0, pbn_b0_8_115200 },
5102 * PA Semi PA6T-1682M on-chip UART
5104 { PCI_VENDOR_ID_PASEMI, 0xa004,
5105 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5109 * National Instruments
5111 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
5112 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5114 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
5115 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5117 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
5118 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5119 pbn_b1_bt_4_115200 },
5120 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
5121 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5122 pbn_b1_bt_2_115200 },
5123 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
5124 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5125 pbn_b1_bt_4_115200 },
5126 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
5127 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5128 pbn_b1_bt_2_115200 },
5129 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
5130 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5132 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
5133 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5135 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
5136 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5137 pbn_b1_bt_4_115200 },
5138 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
5139 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5140 pbn_b1_bt_2_115200 },
5141 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
5142 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5143 pbn_b1_bt_4_115200 },
5144 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
5145 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5146 pbn_b1_bt_2_115200 },
5147 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
5148 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5150 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
5151 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5153 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
5154 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5156 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5157 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5159 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5160 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5162 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5163 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5165 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5166 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5168 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5169 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5171 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5172 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5174 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5175 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5177 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5178 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5180 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5181 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5185 * ADDI-DATA GmbH communication cards <info@addi-data.com>
5187 { PCI_VENDOR_ID_ADDIDATA,
5188 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5195 { PCI_VENDOR_ID_ADDIDATA,
5196 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5203 { PCI_VENDOR_ID_ADDIDATA,
5204 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5211 { PCI_VENDOR_ID_AMCC,
5212 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
5219 { PCI_VENDOR_ID_ADDIDATA,
5220 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5227 { PCI_VENDOR_ID_ADDIDATA,
5228 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5235 { PCI_VENDOR_ID_ADDIDATA,
5236 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5243 { PCI_VENDOR_ID_ADDIDATA,
5244 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5251 { PCI_VENDOR_ID_ADDIDATA,
5252 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5259 { PCI_VENDOR_ID_ADDIDATA,
5260 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5267 { PCI_VENDOR_ID_ADDIDATA,
5268 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5275 { PCI_VENDOR_ID_ADDIDATA,
5276 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5281 pbn_ADDIDATA_PCIe_4_3906250 },
5283 { PCI_VENDOR_ID_ADDIDATA,
5284 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5289 pbn_ADDIDATA_PCIe_2_3906250 },
5291 { PCI_VENDOR_ID_ADDIDATA,
5292 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5297 pbn_ADDIDATA_PCIe_1_3906250 },
5299 { PCI_VENDOR_ID_ADDIDATA,
5300 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5305 pbn_ADDIDATA_PCIe_8_3906250 },
5307 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5308 PCI_VENDOR_ID_IBM, 0x0299,
5309 0, 0, pbn_b0_bt_2_115200 },
5312 * other NetMos 9835 devices are most likely handled by the
5313 * parport_serial driver, check drivers/parport/parport_serial.c
5314 * before adding them here.
5317 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5319 0, 0, pbn_b0_1_115200 },
5321 /* the 9901 is a rebranded 9912 */
5322 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5324 0, 0, pbn_b0_1_115200 },
5326 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5328 0, 0, pbn_b0_1_115200 },
5330 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5332 0, 0, pbn_b0_1_115200 },
5334 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5336 0, 0, pbn_b0_1_115200 },
5338 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5340 0, 0, pbn_NETMOS9900_2s_115200 },
5343 * Best Connectivity and Rosewill PCI Multi I/O cards
5346 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5348 0, 0, pbn_b0_1_115200 },
5350 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5352 0, 0, pbn_b0_bt_2_115200 },
5354 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5356 0, 0, pbn_b0_bt_4_115200 },
5358 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5359 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5360 pbn_ce4100_1_115200 },
5361 /* Intel BayTrail */
5362 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART1,
5363 PCI_ANY_ID, PCI_ANY_ID,
5364 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5366 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART2,
5367 PCI_ANY_ID, PCI_ANY_ID,
5368 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5370 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART1,
5371 PCI_ANY_ID, PCI_ANY_ID,
5372 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5374 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART2,
5375 PCI_ANY_ID, PCI_ANY_ID,
5376 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5382 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_UART,
5383 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5388 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5389 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5393 * Broadcom TruManage
5395 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5396 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5397 pbn_brcm_trumanage },
5400 * AgeStar as-prs2-009
5402 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5403 PCI_ANY_ID, PCI_ANY_ID,
5404 0, 0, pbn_b0_bt_2_115200 },
5407 * WCH CH353 series devices: The 2S1P is handled by parport_serial
5408 * so not listed here.
5410 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5411 PCI_ANY_ID, PCI_ANY_ID,
5412 0, 0, pbn_b0_bt_4_115200 },
5414 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5415 PCI_ANY_ID, PCI_ANY_ID,
5416 0, 0, pbn_b0_bt_2_115200 },
5418 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH352_2S,
5419 PCI_ANY_ID, PCI_ANY_ID,
5420 0, 0, pbn_b0_bt_2_115200 },
5422 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S,
5423 PCI_ANY_ID, PCI_ANY_ID,
5424 0, 0, pbn_wch384_4 },
5427 * Commtech, Inc. Fastcom adapters
5429 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335,
5430 PCI_ANY_ID, PCI_ANY_ID,
5432 0, pbn_b0_2_1152000_200 },
5433 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335,
5434 PCI_ANY_ID, PCI_ANY_ID,
5436 0, pbn_b0_4_1152000_200 },
5437 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335,
5438 PCI_ANY_ID, PCI_ANY_ID,
5440 0, pbn_b0_4_1152000_200 },
5441 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335,
5442 PCI_ANY_ID, PCI_ANY_ID,
5444 0, pbn_b0_8_1152000_200 },
5445 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE,
5446 PCI_ANY_ID, PCI_ANY_ID,
5448 0, pbn_exar_XR17V352 },
5449 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE,
5450 PCI_ANY_ID, PCI_ANY_ID,
5452 0, pbn_exar_XR17V354 },
5453 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE,
5454 PCI_ANY_ID, PCI_ANY_ID,
5456 0, pbn_exar_XR17V358 },
5458 /* Fintek PCI serial cards */
5459 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5460 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5461 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5464 * These entries match devices with class COMMUNICATION_SERIAL,
5465 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5467 { PCI_ANY_ID, PCI_ANY_ID,
5468 PCI_ANY_ID, PCI_ANY_ID,
5469 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5470 0xffff00, pbn_default },
5471 { PCI_ANY_ID, PCI_ANY_ID,
5472 PCI_ANY_ID, PCI_ANY_ID,
5473 PCI_CLASS_COMMUNICATION_MODEM << 8,
5474 0xffff00, pbn_default },
5475 { PCI_ANY_ID, PCI_ANY_ID,
5476 PCI_ANY_ID, PCI_ANY_ID,
5477 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5478 0xffff00, pbn_default },
5482 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5483 pci_channel_state_t state)
5485 struct serial_private *priv = pci_get_drvdata(dev);
5487 if (state == pci_channel_io_perm_failure)
5488 return PCI_ERS_RESULT_DISCONNECT;
5491 pciserial_suspend_ports(priv);
5493 pci_disable_device(dev);
5495 return PCI_ERS_RESULT_NEED_RESET;
5498 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5502 rc = pci_enable_device(dev);
5505 return PCI_ERS_RESULT_DISCONNECT;
5507 pci_restore_state(dev);
5508 pci_save_state(dev);
5510 return PCI_ERS_RESULT_RECOVERED;
5513 static void serial8250_io_resume(struct pci_dev *dev)
5515 struct serial_private *priv = pci_get_drvdata(dev);
5518 pciserial_resume_ports(priv);
5521 static const struct pci_error_handlers serial8250_err_handler = {
5522 .error_detected = serial8250_io_error_detected,
5523 .slot_reset = serial8250_io_slot_reset,
5524 .resume = serial8250_io_resume,
5527 static struct pci_driver serial_pci_driver = {
5529 .probe = pciserial_init_one,
5530 .remove = pciserial_remove_one,
5532 .suspend = pciserial_suspend_one,
5533 .resume = pciserial_resume_one,
5535 .id_table = serial_pci_tbl,
5536 .err_handler = &serial8250_err_handler,
5539 module_pci_driver(serial_pci_driver);
5541 MODULE_LICENSE("GPL");
5542 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5543 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);