2 * Base port operations for 8250/16550-type serial ports
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 * Split from 8250_core.c, Copyright (C) 2001 Russell King.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * A note about mapbase / membase
14 * mapbase is the physical address of the IO port.
15 * membase is an 'ioremapped' cookie.
18 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
22 #include <linux/module.h>
23 #include <linux/moduleparam.h>
24 #include <linux/ioport.h>
25 #include <linux/init.h>
26 #include <linux/console.h>
27 #include <linux/sysrq.h>
28 #include <linux/delay.h>
29 #include <linux/platform_device.h>
30 #include <linux/tty.h>
31 #include <linux/ratelimit.h>
32 #include <linux/tty_flip.h>
33 #include <linux/serial.h>
34 #include <linux/serial_8250.h>
35 #include <linux/nmi.h>
36 #include <linux/mutex.h>
37 #include <linux/slab.h>
38 #include <linux/uaccess.h>
39 #include <linux/pm_runtime.h>
50 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
52 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
55 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
58 * Here we define the default xmit fifo size used for each type of UART.
60 static const struct serial8250_config uart_config[] = {
85 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
86 .rxtrig_bytes = {1, 4, 8, 14},
87 .flags = UART_CAP_FIFO,
98 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
104 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
106 .rxtrig_bytes = {8, 16, 24, 28},
107 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
113 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
115 .rxtrig_bytes = {1, 16, 32, 56},
116 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
124 .name = "16C950/954",
127 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
128 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
129 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
135 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
137 .rxtrig_bytes = {8, 16, 56, 60},
138 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
144 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
145 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
151 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
152 .flags = UART_CAP_FIFO,
158 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
159 .flags = UART_CAP_FIFO | UART_NATSEMI,
165 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
166 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
172 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
173 .flags = UART_CAP_FIFO,
179 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
180 .flags = UART_CAP_FIFO | UART_CAP_AFE,
186 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
187 .flags = UART_CAP_FIFO | UART_CAP_AFE,
193 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
195 .rxtrig_bytes = {1, 4, 8, 14},
196 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
202 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
203 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
210 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
212 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
219 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
220 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
221 .flags = UART_CAP_FIFO,
223 [PORT_BRCM_TRUMANAGE] = {
227 .flags = UART_CAP_HFIFO,
232 [PORT_ALTR_16550_F32] = {
233 .name = "Altera 16550 FIFO32",
236 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
237 .flags = UART_CAP_FIFO | UART_CAP_AFE,
239 [PORT_ALTR_16550_F64] = {
240 .name = "Altera 16550 FIFO64",
243 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
244 .flags = UART_CAP_FIFO | UART_CAP_AFE,
246 [PORT_ALTR_16550_F128] = {
247 .name = "Altera 16550 FIFO128",
250 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
251 .flags = UART_CAP_FIFO | UART_CAP_AFE,
253 /* tx_loadsz is set to 63-bytes instead of 64-bytes to implement
254 workaround of errata A-008006 which states that tx_loadsz should be
255 configured less than Maximum supported fifo bytes */
256 [PORT_16550A_FSL64] = {
257 .name = "16550A_FSL64",
260 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
262 .flags = UART_CAP_FIFO,
265 .name = "Palmchip BK-3103",
268 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
269 .rxtrig_bytes = {1, 4, 8, 14},
270 .flags = UART_CAP_FIFO,
274 /* Uart divisor latch read */
275 static int default_serial_dl_read(struct uart_8250_port *up)
277 return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;
280 /* Uart divisor latch write */
281 static void default_serial_dl_write(struct uart_8250_port *up, int value)
283 serial_out(up, UART_DLL, value & 0xff);
284 serial_out(up, UART_DLM, value >> 8 & 0xff);
287 #ifdef CONFIG_SERIAL_8250_RT288X
289 /* Au1x00/RT288x UART hardware has a weird register layout */
290 static const s8 au_io_in_map[8] = {
298 -1, /* UART_SCR (unmapped) */
301 static const s8 au_io_out_map[8] = {
307 -1, /* UART_LSR (unmapped) */
308 -1, /* UART_MSR (unmapped) */
309 -1, /* UART_SCR (unmapped) */
312 static unsigned int au_serial_in(struct uart_port *p, int offset)
314 if (offset >= ARRAY_SIZE(au_io_in_map))
316 offset = au_io_in_map[offset];
319 return __raw_readl(p->membase + (offset << p->regshift));
322 static void au_serial_out(struct uart_port *p, int offset, int value)
324 if (offset >= ARRAY_SIZE(au_io_out_map))
326 offset = au_io_out_map[offset];
329 __raw_writel(value, p->membase + (offset << p->regshift));
332 /* Au1x00 haven't got a standard divisor latch */
333 static int au_serial_dl_read(struct uart_8250_port *up)
335 return __raw_readl(up->port.membase + 0x28);
338 static void au_serial_dl_write(struct uart_8250_port *up, int value)
340 __raw_writel(value, up->port.membase + 0x28);
345 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
347 offset = offset << p->regshift;
348 outb(p->hub6 - 1 + offset, p->iobase);
349 return inb(p->iobase + 1);
352 static void hub6_serial_out(struct uart_port *p, int offset, int value)
354 offset = offset << p->regshift;
355 outb(p->hub6 - 1 + offset, p->iobase);
356 outb(value, p->iobase + 1);
359 static unsigned int mem_serial_in(struct uart_port *p, int offset)
361 offset = offset << p->regshift;
362 return readb(p->membase + offset);
365 static void mem_serial_out(struct uart_port *p, int offset, int value)
367 offset = offset << p->regshift;
368 writeb(value, p->membase + offset);
371 static void mem32_serial_out(struct uart_port *p, int offset, int value)
373 offset = offset << p->regshift;
374 writel(value, p->membase + offset);
377 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
379 offset = offset << p->regshift;
380 return readl(p->membase + offset);
383 static void mem32be_serial_out(struct uart_port *p, int offset, int value)
385 offset = offset << p->regshift;
386 iowrite32be(value, p->membase + offset);
389 static unsigned int mem32be_serial_in(struct uart_port *p, int offset)
391 offset = offset << p->regshift;
392 return ioread32be(p->membase + offset);
395 static unsigned int io_serial_in(struct uart_port *p, int offset)
397 offset = offset << p->regshift;
398 return inb(p->iobase + offset);
401 static void io_serial_out(struct uart_port *p, int offset, int value)
403 offset = offset << p->regshift;
404 outb(value, p->iobase + offset);
407 static int serial8250_default_handle_irq(struct uart_port *port);
408 static int exar_handle_irq(struct uart_port *port);
410 static void set_io_from_upio(struct uart_port *p)
412 struct uart_8250_port *up = up_to_u8250p(p);
414 up->dl_read = default_serial_dl_read;
415 up->dl_write = default_serial_dl_write;
419 p->serial_in = hub6_serial_in;
420 p->serial_out = hub6_serial_out;
424 p->serial_in = mem_serial_in;
425 p->serial_out = mem_serial_out;
429 p->serial_in = mem32_serial_in;
430 p->serial_out = mem32_serial_out;
434 p->serial_in = mem32be_serial_in;
435 p->serial_out = mem32be_serial_out;
438 #ifdef CONFIG_SERIAL_8250_RT288X
440 p->serial_in = au_serial_in;
441 p->serial_out = au_serial_out;
442 up->dl_read = au_serial_dl_read;
443 up->dl_write = au_serial_dl_write;
448 p->serial_in = io_serial_in;
449 p->serial_out = io_serial_out;
452 /* Remember loaded iotype */
453 up->cur_iotype = p->iotype;
454 p->handle_irq = serial8250_default_handle_irq;
458 serial_port_out_sync(struct uart_port *p, int offset, int value)
465 p->serial_out(p, offset, value);
466 p->serial_in(p, UART_LCR); /* safe, no side-effects */
469 p->serial_out(p, offset, value);
476 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
478 serial_out(up, UART_SCR, offset);
479 serial_out(up, UART_ICR, value);
482 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
486 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
487 serial_out(up, UART_SCR, offset);
488 value = serial_in(up, UART_ICR);
489 serial_icr_write(up, UART_ACR, up->acr);
497 static void serial8250_clear_fifos(struct uart_8250_port *p)
499 if (p->capabilities & UART_CAP_FIFO) {
500 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
501 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
502 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
503 serial_out(p, UART_FCR, 0);
507 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
509 serial8250_clear_fifos(p);
510 serial_out(p, UART_FCR, p->fcr);
512 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
514 void serial8250_rpm_get(struct uart_8250_port *p)
516 if (!(p->capabilities & UART_CAP_RPM))
518 pm_runtime_get_sync(p->port.dev);
520 EXPORT_SYMBOL_GPL(serial8250_rpm_get);
522 void serial8250_rpm_put(struct uart_8250_port *p)
524 if (!(p->capabilities & UART_CAP_RPM))
526 pm_runtime_mark_last_busy(p->port.dev);
527 pm_runtime_put_autosuspend(p->port.dev);
529 EXPORT_SYMBOL_GPL(serial8250_rpm_put);
532 * These two wrappers ensure that enable_runtime_pm_tx() can be called more than
533 * once and disable_runtime_pm_tx() will still disable RPM because the fifo is
534 * empty and the HW can idle again.
536 static void serial8250_rpm_get_tx(struct uart_8250_port *p)
538 unsigned char rpm_active;
540 if (!(p->capabilities & UART_CAP_RPM))
543 rpm_active = xchg(&p->rpm_tx_active, 1);
546 pm_runtime_get_sync(p->port.dev);
549 static void serial8250_rpm_put_tx(struct uart_8250_port *p)
551 unsigned char rpm_active;
553 if (!(p->capabilities & UART_CAP_RPM))
556 rpm_active = xchg(&p->rpm_tx_active, 0);
559 pm_runtime_mark_last_busy(p->port.dev);
560 pm_runtime_put_autosuspend(p->port.dev);
564 * IER sleep support. UARTs which have EFRs need the "extended
565 * capability" bit enabled. Note that on XR16C850s, we need to
566 * reset LCR to write to IER.
568 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
570 unsigned char lcr = 0, efr = 0;
572 * Exar UARTs have a SLEEP register that enables or disables
573 * each UART to enter sleep mode separately. On the XR17V35x the
574 * register is accessible to each UART at the UART_EXAR_SLEEP
575 * offset but the UART channel may only write to the corresponding
578 serial8250_rpm_get(p);
579 if ((p->port.type == PORT_XR17V35X) ||
580 (p->port.type == PORT_XR17D15X)) {
581 serial_out(p, UART_EXAR_SLEEP, sleep ? 0xff : 0);
585 if (p->capabilities & UART_CAP_SLEEP) {
586 if (p->capabilities & UART_CAP_EFR) {
587 lcr = serial_in(p, UART_LCR);
588 efr = serial_in(p, UART_EFR);
589 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
590 serial_out(p, UART_EFR, UART_EFR_ECB);
591 serial_out(p, UART_LCR, 0);
593 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
594 if (p->capabilities & UART_CAP_EFR) {
595 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
596 serial_out(p, UART_EFR, efr);
597 serial_out(p, UART_LCR, lcr);
601 serial8250_rpm_put(p);
604 #ifdef CONFIG_SERIAL_8250_RSA
606 * Attempts to turn on the RSA FIFO. Returns zero on failure.
607 * We set the port uart clock rate if we succeed.
609 static int __enable_rsa(struct uart_8250_port *up)
614 mode = serial_in(up, UART_RSA_MSR);
615 result = mode & UART_RSA_MSR_FIFO;
618 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
619 mode = serial_in(up, UART_RSA_MSR);
620 result = mode & UART_RSA_MSR_FIFO;
624 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
629 static void enable_rsa(struct uart_8250_port *up)
631 if (up->port.type == PORT_RSA) {
632 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
633 spin_lock_irq(&up->port.lock);
635 spin_unlock_irq(&up->port.lock);
637 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
638 serial_out(up, UART_RSA_FRR, 0);
643 * Attempts to turn off the RSA FIFO. Returns zero on failure.
644 * It is unknown why interrupts were disabled in here. However,
645 * the caller is expected to preserve this behaviour by grabbing
646 * the spinlock before calling this function.
648 static void disable_rsa(struct uart_8250_port *up)
653 if (up->port.type == PORT_RSA &&
654 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
655 spin_lock_irq(&up->port.lock);
657 mode = serial_in(up, UART_RSA_MSR);
658 result = !(mode & UART_RSA_MSR_FIFO);
661 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
662 mode = serial_in(up, UART_RSA_MSR);
663 result = !(mode & UART_RSA_MSR_FIFO);
667 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
668 spin_unlock_irq(&up->port.lock);
671 #endif /* CONFIG_SERIAL_8250_RSA */
674 * This is a quickie test to see how big the FIFO is.
675 * It doesn't work at all the time, more's the pity.
677 static int size_fifo(struct uart_8250_port *up)
679 unsigned char old_fcr, old_mcr, old_lcr;
680 unsigned short old_dl;
683 old_lcr = serial_in(up, UART_LCR);
684 serial_out(up, UART_LCR, 0);
685 old_fcr = serial_in(up, UART_FCR);
686 old_mcr = serial_in(up, UART_MCR);
687 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
688 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
689 serial_out(up, UART_MCR, UART_MCR_LOOP);
690 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
691 old_dl = serial_dl_read(up);
692 serial_dl_write(up, 0x0001);
693 serial_out(up, UART_LCR, 0x03);
694 for (count = 0; count < 256; count++)
695 serial_out(up, UART_TX, count);
696 mdelay(20);/* FIXME - schedule_timeout */
697 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
698 (count < 256); count++)
699 serial_in(up, UART_RX);
700 serial_out(up, UART_FCR, old_fcr);
701 serial_out(up, UART_MCR, old_mcr);
702 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
703 serial_dl_write(up, old_dl);
704 serial_out(up, UART_LCR, old_lcr);
710 * Read UART ID using the divisor method - set DLL and DLM to zero
711 * and the revision will be in DLL and device type in DLM. We
712 * preserve the device state across this.
714 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
716 unsigned char old_dll, old_dlm, old_lcr;
719 old_lcr = serial_in(p, UART_LCR);
720 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
722 old_dll = serial_in(p, UART_DLL);
723 old_dlm = serial_in(p, UART_DLM);
725 serial_out(p, UART_DLL, 0);
726 serial_out(p, UART_DLM, 0);
728 id = serial_in(p, UART_DLL) | serial_in(p, UART_DLM) << 8;
730 serial_out(p, UART_DLL, old_dll);
731 serial_out(p, UART_DLM, old_dlm);
732 serial_out(p, UART_LCR, old_lcr);
738 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
739 * When this function is called we know it is at least a StarTech
740 * 16650 V2, but it might be one of several StarTech UARTs, or one of
741 * its clones. (We treat the broken original StarTech 16650 V1 as a
742 * 16550, and why not? Startech doesn't seem to even acknowledge its
745 * What evil have men's minds wrought...
747 static void autoconfig_has_efr(struct uart_8250_port *up)
749 unsigned int id1, id2, id3, rev;
752 * Everything with an EFR has SLEEP
754 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
757 * First we check to see if it's an Oxford Semiconductor UART.
759 * If we have to do this here because some non-National
760 * Semiconductor clone chips lock up if you try writing to the
761 * LSR register (which serial_icr_read does)
765 * Check for Oxford Semiconductor 16C950.
767 * EFR [4] must be set else this test fails.
769 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
770 * claims that it's needed for 952 dual UART's (which are not
771 * recommended for new designs).
774 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
775 serial_out(up, UART_EFR, UART_EFR_ECB);
776 serial_out(up, UART_LCR, 0x00);
777 id1 = serial_icr_read(up, UART_ID1);
778 id2 = serial_icr_read(up, UART_ID2);
779 id3 = serial_icr_read(up, UART_ID3);
780 rev = serial_icr_read(up, UART_REV);
782 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
784 if (id1 == 0x16 && id2 == 0xC9 &&
785 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
786 up->port.type = PORT_16C950;
789 * Enable work around for the Oxford Semiconductor 952 rev B
790 * chip which causes it to seriously miscalculate baud rates
793 if (id3 == 0x52 && rev == 0x01)
794 up->bugs |= UART_BUG_QUOT;
799 * We check for a XR16C850 by setting DLL and DLM to 0, and then
800 * reading back DLL and DLM. The chip type depends on the DLM
802 * 0x10 - XR16C850 and the DLL contains the chip revision.
806 id1 = autoconfig_read_divisor_id(up);
807 DEBUG_AUTOCONF("850id=%04x ", id1);
810 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
811 up->port.type = PORT_16850;
816 * It wasn't an XR16C850.
818 * We distinguish between the '654 and the '650 by counting
819 * how many bytes are in the FIFO. I'm using this for now,
820 * since that's the technique that was sent to me in the
821 * serial driver update, but I'm not convinced this works.
822 * I've had problems doing this in the past. -TYT
824 if (size_fifo(up) == 64)
825 up->port.type = PORT_16654;
827 up->port.type = PORT_16650V2;
831 * We detected a chip without a FIFO. Only two fall into
832 * this category - the original 8250 and the 16450. The
833 * 16450 has a scratch register (accessible with LCR=0)
835 static void autoconfig_8250(struct uart_8250_port *up)
837 unsigned char scratch, status1, status2;
839 up->port.type = PORT_8250;
841 scratch = serial_in(up, UART_SCR);
842 serial_out(up, UART_SCR, 0xa5);
843 status1 = serial_in(up, UART_SCR);
844 serial_out(up, UART_SCR, 0x5a);
845 status2 = serial_in(up, UART_SCR);
846 serial_out(up, UART_SCR, scratch);
848 if (status1 == 0xa5 && status2 == 0x5a)
849 up->port.type = PORT_16450;
852 static int broken_efr(struct uart_8250_port *up)
855 * Exar ST16C2550 "A2" devices incorrectly detect as
856 * having an EFR, and report an ID of 0x0201. See
857 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
859 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
866 * We know that the chip has FIFOs. Does it have an EFR? The
867 * EFR is located in the same register position as the IIR and
868 * we know the top two bits of the IIR are currently set. The
869 * EFR should contain zero. Try to read the EFR.
871 static void autoconfig_16550a(struct uart_8250_port *up)
873 unsigned char status1, status2;
874 unsigned int iersave;
876 up->port.type = PORT_16550A;
877 up->capabilities |= UART_CAP_FIFO;
880 * XR17V35x UARTs have an extra divisor register, DLD
881 * that gets enabled with when DLAB is set which will
882 * cause the device to incorrectly match and assign
883 * port type to PORT_16650. The EFR for this UART is
884 * found at offset 0x09. Instead check the Deice ID (DVID)
885 * register for a 2, 4 or 8 port UART.
887 if (up->port.flags & UPF_EXAR_EFR) {
888 status1 = serial_in(up, UART_EXAR_DVID);
889 if (status1 == 0x82 || status1 == 0x84 || status1 == 0x88) {
890 DEBUG_AUTOCONF("Exar XR17V35x ");
891 up->port.type = PORT_XR17V35X;
892 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
901 * Check for presence of the EFR when DLAB is set.
902 * Only ST16C650V1 UARTs pass this test.
904 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
905 if (serial_in(up, UART_EFR) == 0) {
906 serial_out(up, UART_EFR, 0xA8);
907 if (serial_in(up, UART_EFR) != 0) {
908 DEBUG_AUTOCONF("EFRv1 ");
909 up->port.type = PORT_16650;
910 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
912 serial_out(up, UART_LCR, 0);
913 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
915 status1 = serial_in(up, UART_IIR) >> 5;
916 serial_out(up, UART_FCR, 0);
917 serial_out(up, UART_LCR, 0);
920 up->port.type = PORT_16550A_FSL64;
922 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
924 serial_out(up, UART_EFR, 0);
929 * Maybe it requires 0xbf to be written to the LCR.
930 * (other ST16C650V2 UARTs, TI16C752A, etc)
932 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
933 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
934 DEBUG_AUTOCONF("EFRv2 ");
935 autoconfig_has_efr(up);
940 * Check for a National Semiconductor SuperIO chip.
941 * Attempt to switch to bank 2, read the value of the LOOP bit
942 * from EXCR1. Switch back to bank 0, change it in MCR. Then
943 * switch back to bank 2, read it from EXCR1 again and check
944 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
946 serial_out(up, UART_LCR, 0);
947 status1 = serial_in(up, UART_MCR);
948 serial_out(up, UART_LCR, 0xE0);
949 status2 = serial_in(up, 0x02); /* EXCR1 */
951 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
952 serial_out(up, UART_LCR, 0);
953 serial_out(up, UART_MCR, status1 ^ UART_MCR_LOOP);
954 serial_out(up, UART_LCR, 0xE0);
955 status2 = serial_in(up, 0x02); /* EXCR1 */
956 serial_out(up, UART_LCR, 0);
957 serial_out(up, UART_MCR, status1);
959 if ((status2 ^ status1) & UART_MCR_LOOP) {
962 serial_out(up, UART_LCR, 0xE0);
964 quot = serial_dl_read(up);
967 if (ns16550a_goto_highspeed(up))
968 serial_dl_write(up, quot);
970 serial_out(up, UART_LCR, 0);
972 up->port.uartclk = 921600*16;
973 up->port.type = PORT_NS16550A;
974 up->capabilities |= UART_NATSEMI;
980 * No EFR. Try to detect a TI16750, which only sets bit 5 of
981 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
982 * Try setting it with and without DLAB set. Cheap clones
983 * set bit 5 without DLAB set.
985 serial_out(up, UART_LCR, 0);
986 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
987 status1 = serial_in(up, UART_IIR) >> 5;
988 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
989 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
990 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
991 status2 = serial_in(up, UART_IIR) >> 5;
992 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
993 serial_out(up, UART_LCR, 0);
995 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
997 if (status1 == 6 && status2 == 7) {
998 up->port.type = PORT_16750;
999 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1004 * Try writing and reading the UART_IER_UUE bit (b6).
1005 * If it works, this is probably one of the Xscale platform's
1007 * We're going to explicitly set the UUE bit to 0 before
1008 * trying to write and read a 1 just to make sure it's not
1009 * already a 1 and maybe locked there before we even start start.
1011 iersave = serial_in(up, UART_IER);
1012 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1013 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1015 * OK it's in a known zero state, try writing and reading
1016 * without disturbing the current state of the other bits.
1018 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1019 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1022 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1024 DEBUG_AUTOCONF("Xscale ");
1025 up->port.type = PORT_XSCALE;
1026 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1031 * If we got here we couldn't force the IER_UUE bit to 0.
1032 * Log it and continue.
1034 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1036 serial_out(up, UART_IER, iersave);
1039 * Exar uarts have EFR in a weird location
1041 if (up->port.flags & UPF_EXAR_EFR) {
1042 DEBUG_AUTOCONF("Exar XR17D15x ");
1043 up->port.type = PORT_XR17D15X;
1044 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
1051 * We distinguish between 16550A and U6 16550A by counting
1052 * how many bytes are in the FIFO.
1054 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1055 up->port.type = PORT_U6_16550A;
1056 up->capabilities |= UART_CAP_AFE;
1061 * This routine is called by rs_init() to initialize a specific serial
1062 * port. It determines what type of UART chip this serial port is
1063 * using: 8250, 16450, 16550, 16550A. The important question is
1064 * whether or not this UART is a 16550A or not, since this will
1065 * determine whether or not we can use its FIFO features or not.
1067 static void autoconfig(struct uart_8250_port *up)
1069 unsigned char status1, scratch, scratch2, scratch3;
1070 unsigned char save_lcr, save_mcr;
1071 struct uart_port *port = &up->port;
1072 unsigned long flags;
1073 unsigned int old_capabilities;
1075 if (!port->iobase && !port->mapbase && !port->membase)
1078 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1079 serial_index(port), port->iobase, port->membase);
1082 * We really do need global IRQs disabled here - we're going to
1083 * be frobbing the chips IRQ enable register to see if it exists.
1085 spin_lock_irqsave(&port->lock, flags);
1087 up->capabilities = 0;
1090 if (!(port->flags & UPF_BUGGY_UART)) {
1092 * Do a simple existence test first; if we fail this,
1093 * there's no point trying anything else.
1095 * 0x80 is used as a nonsense port to prevent against
1096 * false positives due to ISA bus float. The
1097 * assumption is that 0x80 is a non-existent port;
1098 * which should be safe since include/asm/io.h also
1099 * makes this assumption.
1101 * Note: this is safe as long as MCR bit 4 is clear
1102 * and the device is in "PC" mode.
1104 scratch = serial_in(up, UART_IER);
1105 serial_out(up, UART_IER, 0);
1110 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1111 * 16C754B) allow only to modify them if an EFR bit is set.
1113 scratch2 = serial_in(up, UART_IER) & 0x0f;
1114 serial_out(up, UART_IER, 0x0F);
1118 scratch3 = serial_in(up, UART_IER) & 0x0f;
1119 serial_out(up, UART_IER, scratch);
1120 if (scratch2 != 0 || scratch3 != 0x0F) {
1122 * We failed; there's nothing here
1124 spin_unlock_irqrestore(&port->lock, flags);
1125 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1126 scratch2, scratch3);
1131 save_mcr = serial_in(up, UART_MCR);
1132 save_lcr = serial_in(up, UART_LCR);
1135 * Check to see if a UART is really there. Certain broken
1136 * internal modems based on the Rockwell chipset fail this
1137 * test, because they apparently don't implement the loopback
1138 * test mode. So this test is skipped on the COM 1 through
1139 * COM 4 ports. This *should* be safe, since no board
1140 * manufacturer would be stupid enough to design a board
1141 * that conflicts with COM 1-4 --- we hope!
1143 if (!(port->flags & UPF_SKIP_TEST)) {
1144 serial_out(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1145 status1 = serial_in(up, UART_MSR) & 0xF0;
1146 serial_out(up, UART_MCR, save_mcr);
1147 if (status1 != 0x90) {
1148 spin_unlock_irqrestore(&port->lock, flags);
1149 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1156 * We're pretty sure there's a port here. Lets find out what
1157 * type of port it is. The IIR top two bits allows us to find
1158 * out if it's 8250 or 16450, 16550, 16550A or later. This
1159 * determines what we test for next.
1161 * We also initialise the EFR (if any) to zero for later. The
1162 * EFR occupies the same register location as the FCR and IIR.
1164 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1165 serial_out(up, UART_EFR, 0);
1166 serial_out(up, UART_LCR, 0);
1168 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1169 scratch = serial_in(up, UART_IIR) >> 6;
1173 autoconfig_8250(up);
1176 port->type = PORT_UNKNOWN;
1179 port->type = PORT_16550;
1182 autoconfig_16550a(up);
1186 #ifdef CONFIG_SERIAL_8250_RSA
1188 * Only probe for RSA ports if we got the region.
1190 if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA &&
1192 port->type = PORT_RSA;
1195 serial_out(up, UART_LCR, save_lcr);
1197 port->fifosize = uart_config[up->port.type].fifo_size;
1198 old_capabilities = up->capabilities;
1199 up->capabilities = uart_config[port->type].flags;
1200 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1202 if (port->type == PORT_UNKNOWN)
1208 #ifdef CONFIG_SERIAL_8250_RSA
1209 if (port->type == PORT_RSA)
1210 serial_out(up, UART_RSA_FRR, 0);
1212 serial_out(up, UART_MCR, save_mcr);
1213 serial8250_clear_fifos(up);
1214 serial_in(up, UART_RX);
1215 if (up->capabilities & UART_CAP_UUE)
1216 serial_out(up, UART_IER, UART_IER_UUE);
1218 serial_out(up, UART_IER, 0);
1221 spin_unlock_irqrestore(&port->lock, flags);
1222 if (up->capabilities != old_capabilities) {
1224 "ttyS%d: detected caps %08x should be %08x\n",
1225 serial_index(port), old_capabilities,
1229 DEBUG_AUTOCONF("iir=%d ", scratch);
1230 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1233 static void autoconfig_irq(struct uart_8250_port *up)
1235 struct uart_port *port = &up->port;
1236 unsigned char save_mcr, save_ier;
1237 unsigned char save_ICP = 0;
1238 unsigned int ICP = 0;
1242 if (port->flags & UPF_FOURPORT) {
1243 ICP = (port->iobase & 0xfe0) | 0x1f;
1244 save_ICP = inb_p(ICP);
1249 if (uart_console(port))
1252 /* forget possible initially masked and pending IRQ */
1253 probe_irq_off(probe_irq_on());
1254 save_mcr = serial_in(up, UART_MCR);
1255 save_ier = serial_in(up, UART_IER);
1256 serial_out(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1258 irqs = probe_irq_on();
1259 serial_out(up, UART_MCR, 0);
1261 if (port->flags & UPF_FOURPORT) {
1262 serial_out(up, UART_MCR,
1263 UART_MCR_DTR | UART_MCR_RTS);
1265 serial_out(up, UART_MCR,
1266 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1268 serial_out(up, UART_IER, 0x0f); /* enable all intrs */
1269 serial_in(up, UART_LSR);
1270 serial_in(up, UART_RX);
1271 serial_in(up, UART_IIR);
1272 serial_in(up, UART_MSR);
1273 serial_out(up, UART_TX, 0xFF);
1275 irq = probe_irq_off(irqs);
1277 serial_out(up, UART_MCR, save_mcr);
1278 serial_out(up, UART_IER, save_ier);
1280 if (port->flags & UPF_FOURPORT)
1281 outb_p(save_ICP, ICP);
1283 if (uart_console(port))
1286 port->irq = (irq > 0) ? irq : 0;
1289 static inline void __stop_tx(struct uart_8250_port *p)
1291 if (p->ier & UART_IER_THRI) {
1292 p->ier &= ~UART_IER_THRI;
1293 serial_out(p, UART_IER, p->ier);
1294 serial8250_rpm_put_tx(p);
1298 static void serial8250_stop_tx(struct uart_port *port)
1300 struct uart_8250_port *up = up_to_u8250p(port);
1302 serial8250_rpm_get(up);
1306 * We really want to stop the transmitter from sending.
1308 if (port->type == PORT_16C950) {
1309 up->acr |= UART_ACR_TXDIS;
1310 serial_icr_write(up, UART_ACR, up->acr);
1312 serial8250_rpm_put(up);
1315 static void serial8250_start_tx(struct uart_port *port)
1317 struct uart_8250_port *up = up_to_u8250p(port);
1319 serial8250_rpm_get_tx(up);
1321 if (up->dma && !up->dma->tx_dma(up))
1324 if (!(up->ier & UART_IER_THRI)) {
1325 up->ier |= UART_IER_THRI;
1326 serial_port_out(port, UART_IER, up->ier);
1328 if (up->bugs & UART_BUG_TXEN) {
1330 lsr = serial_in(up, UART_LSR);
1331 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1332 if (lsr & UART_LSR_THRE)
1333 serial8250_tx_chars(up);
1338 * Re-enable the transmitter if we disabled it.
1340 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1341 up->acr &= ~UART_ACR_TXDIS;
1342 serial_icr_write(up, UART_ACR, up->acr);
1346 static void serial8250_throttle(struct uart_port *port)
1348 port->throttle(port);
1351 static void serial8250_unthrottle(struct uart_port *port)
1353 port->unthrottle(port);
1356 static void serial8250_stop_rx(struct uart_port *port)
1358 struct uart_8250_port *up = up_to_u8250p(port);
1360 serial8250_rpm_get(up);
1362 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1363 up->port.read_status_mask &= ~UART_LSR_DR;
1364 serial_port_out(port, UART_IER, up->ier);
1366 serial8250_rpm_put(up);
1369 static void serial8250_disable_ms(struct uart_port *port)
1371 struct uart_8250_port *up =
1372 container_of(port, struct uart_8250_port, port);
1374 /* no MSR capabilities */
1375 if (up->bugs & UART_BUG_NOMSR)
1378 up->ier &= ~UART_IER_MSI;
1379 serial_port_out(port, UART_IER, up->ier);
1382 static void serial8250_enable_ms(struct uart_port *port)
1384 struct uart_8250_port *up = up_to_u8250p(port);
1386 /* no MSR capabilities */
1387 if (up->bugs & UART_BUG_NOMSR)
1390 up->ier |= UART_IER_MSI;
1392 serial8250_rpm_get(up);
1393 serial_port_out(port, UART_IER, up->ier);
1394 serial8250_rpm_put(up);
1398 * serial8250_rx_chars: processes according to the passed in LSR
1399 * value, and returns the remaining LSR bits not handled
1400 * by this Rx routine.
1403 serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1405 struct uart_port *port = &up->port;
1407 int max_count = 256;
1411 if (likely(lsr & UART_LSR_DR))
1412 ch = serial_in(up, UART_RX);
1415 * Intel 82571 has a Serial Over Lan device that will
1416 * set UART_LSR_BI without setting UART_LSR_DR when
1417 * it receives a break. To avoid reading from the
1418 * receive buffer without UART_LSR_DR bit set, we
1419 * just force the read character to be 0
1426 lsr |= up->lsr_saved_flags;
1427 up->lsr_saved_flags = 0;
1429 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1430 if (lsr & UART_LSR_BI) {
1431 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1434 * We do the SysRQ and SAK checking
1435 * here because otherwise the break
1436 * may get masked by ignore_status_mask
1437 * or read_status_mask.
1439 if (uart_handle_break(port))
1441 } else if (lsr & UART_LSR_PE)
1442 port->icount.parity++;
1443 else if (lsr & UART_LSR_FE)
1444 port->icount.frame++;
1445 if (lsr & UART_LSR_OE)
1446 port->icount.overrun++;
1449 * Mask off conditions which should be ignored.
1451 lsr &= port->read_status_mask;
1453 if (lsr & UART_LSR_BI) {
1454 DEBUG_INTR("handling break....");
1456 } else if (lsr & UART_LSR_PE)
1458 else if (lsr & UART_LSR_FE)
1461 if (uart_handle_sysrq_char(port, ch))
1464 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1467 lsr = serial_in(up, UART_LSR);
1468 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (--max_count > 0));
1469 spin_unlock(&port->lock);
1470 tty_flip_buffer_push(&port->state->port);
1471 spin_lock(&port->lock);
1474 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1476 void serial8250_tx_chars(struct uart_8250_port *up)
1478 struct uart_port *port = &up->port;
1479 struct circ_buf *xmit = &port->state->xmit;
1483 serial_out(up, UART_TX, port->x_char);
1488 if (uart_tx_stopped(port)) {
1489 serial8250_stop_tx(port);
1492 if (uart_circ_empty(xmit)) {
1497 count = up->tx_loadsz;
1499 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1500 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1502 if (uart_circ_empty(xmit))
1504 if (up->capabilities & UART_CAP_HFIFO) {
1505 if ((serial_port_in(port, UART_LSR) & BOTH_EMPTY) !=
1509 } while (--count > 0);
1511 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1512 uart_write_wakeup(port);
1514 DEBUG_INTR("THRE...");
1517 * With RPM enabled, we have to wait until the FIFO is empty before the
1518 * HW can go idle. So we get here once again with empty FIFO and disable
1519 * the interrupt and RPM in __stop_tx()
1521 if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM))
1524 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1526 /* Caller holds uart port lock */
1527 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1529 struct uart_port *port = &up->port;
1530 unsigned int status = serial_in(up, UART_MSR);
1532 status |= up->msr_saved_flags;
1533 up->msr_saved_flags = 0;
1534 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1535 port->state != NULL) {
1536 if (status & UART_MSR_TERI)
1538 if (status & UART_MSR_DDSR)
1540 if (status & UART_MSR_DDCD)
1541 uart_handle_dcd_change(port, status & UART_MSR_DCD);
1542 if (status & UART_MSR_DCTS)
1543 uart_handle_cts_change(port, status & UART_MSR_CTS);
1545 wake_up_interruptible(&port->state->port.delta_msr_wait);
1550 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1553 * This handles the interrupt from one port.
1555 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1557 unsigned char status;
1558 unsigned long flags;
1559 struct uart_8250_port *up = up_to_u8250p(port);
1562 if (iir & UART_IIR_NO_INT)
1565 spin_lock_irqsave(&port->lock, flags);
1567 status = serial_port_in(port, UART_LSR);
1569 DEBUG_INTR("status = %x...", status);
1571 if (status & (UART_LSR_DR | UART_LSR_BI)) {
1573 dma_err = up->dma->rx_dma(up, iir);
1575 if (!up->dma || dma_err)
1576 status = serial8250_rx_chars(up, status);
1578 serial8250_modem_status(up);
1579 if ((!up->dma || (up->dma && up->dma->tx_err)) &&
1580 (status & UART_LSR_THRE))
1581 serial8250_tx_chars(up);
1583 spin_unlock_irqrestore(&port->lock, flags);
1586 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1588 static int serial8250_default_handle_irq(struct uart_port *port)
1590 struct uart_8250_port *up = up_to_u8250p(port);
1594 serial8250_rpm_get(up);
1596 iir = serial_port_in(port, UART_IIR);
1597 ret = serial8250_handle_irq(port, iir);
1599 serial8250_rpm_put(up);
1604 * These Exar UARTs have an extra interrupt indicator that could
1605 * fire for a few unimplemented interrupts. One of which is a
1606 * wakeup event when coming out of sleep. Put this here just
1607 * to be on the safe side that these interrupts don't go unhandled.
1609 static int exar_handle_irq(struct uart_port *port)
1611 unsigned char int0, int1, int2, int3;
1612 unsigned int iir = serial_port_in(port, UART_IIR);
1615 ret = serial8250_handle_irq(port, iir);
1617 if ((port->type == PORT_XR17V35X) ||
1618 (port->type == PORT_XR17D15X)) {
1619 int0 = serial_port_in(port, 0x80);
1620 int1 = serial_port_in(port, 0x81);
1621 int2 = serial_port_in(port, 0x82);
1622 int3 = serial_port_in(port, 0x83);
1628 static unsigned int serial8250_tx_empty(struct uart_port *port)
1630 struct uart_8250_port *up = up_to_u8250p(port);
1631 unsigned long flags;
1634 serial8250_rpm_get(up);
1636 spin_lock_irqsave(&port->lock, flags);
1637 lsr = serial_port_in(port, UART_LSR);
1638 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1639 spin_unlock_irqrestore(&port->lock, flags);
1641 serial8250_rpm_put(up);
1643 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1646 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1648 struct uart_8250_port *up = up_to_u8250p(port);
1649 unsigned int status;
1652 serial8250_rpm_get(up);
1653 status = serial8250_modem_status(up);
1654 serial8250_rpm_put(up);
1657 if (status & UART_MSR_DCD)
1659 if (status & UART_MSR_RI)
1661 if (status & UART_MSR_DSR)
1663 if (status & UART_MSR_CTS)
1668 void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl)
1670 struct uart_8250_port *up = up_to_u8250p(port);
1671 unsigned char mcr = 0;
1673 if (mctrl & TIOCM_RTS)
1674 mcr |= UART_MCR_RTS;
1675 if (mctrl & TIOCM_DTR)
1676 mcr |= UART_MCR_DTR;
1677 if (mctrl & TIOCM_OUT1)
1678 mcr |= UART_MCR_OUT1;
1679 if (mctrl & TIOCM_OUT2)
1680 mcr |= UART_MCR_OUT2;
1681 if (mctrl & TIOCM_LOOP)
1682 mcr |= UART_MCR_LOOP;
1684 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1686 serial_port_out(port, UART_MCR, mcr);
1688 EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl);
1690 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1692 if (port->set_mctrl)
1693 port->set_mctrl(port, mctrl);
1695 serial8250_do_set_mctrl(port, mctrl);
1698 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1700 struct uart_8250_port *up = up_to_u8250p(port);
1701 unsigned long flags;
1703 serial8250_rpm_get(up);
1704 spin_lock_irqsave(&port->lock, flags);
1705 if (break_state == -1)
1706 up->lcr |= UART_LCR_SBC;
1708 up->lcr &= ~UART_LCR_SBC;
1709 serial_port_out(port, UART_LCR, up->lcr);
1710 spin_unlock_irqrestore(&port->lock, flags);
1711 serial8250_rpm_put(up);
1715 * Wait for transmitter & holding register to empty
1717 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1719 unsigned int status, tmout = 10000;
1721 /* Wait up to 10ms for the character(s) to be sent. */
1723 status = serial_in(up, UART_LSR);
1725 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1727 if ((status & bits) == bits)
1734 /* Wait up to 1s for flow control if necessary */
1735 if (up->port.flags & UPF_CONS_FLOW) {
1737 for (tmout = 1000000; tmout; tmout--) {
1738 unsigned int msr = serial_in(up, UART_MSR);
1739 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1740 if (msr & UART_MSR_CTS)
1743 touch_nmi_watchdog();
1748 #ifdef CONFIG_CONSOLE_POLL
1750 * Console polling routines for writing and reading from the uart while
1751 * in an interrupt or debug context.
1754 static int serial8250_get_poll_char(struct uart_port *port)
1756 struct uart_8250_port *up = up_to_u8250p(port);
1760 serial8250_rpm_get(up);
1762 lsr = serial_port_in(port, UART_LSR);
1764 if (!(lsr & UART_LSR_DR)) {
1765 status = NO_POLL_CHAR;
1769 status = serial_port_in(port, UART_RX);
1771 serial8250_rpm_put(up);
1776 static void serial8250_put_poll_char(struct uart_port *port,
1780 struct uart_8250_port *up = up_to_u8250p(port);
1782 serial8250_rpm_get(up);
1784 * First save the IER then disable the interrupts
1786 ier = serial_port_in(port, UART_IER);
1787 if (up->capabilities & UART_CAP_UUE)
1788 serial_port_out(port, UART_IER, UART_IER_UUE);
1790 serial_port_out(port, UART_IER, 0);
1792 wait_for_xmitr(up, BOTH_EMPTY);
1794 * Send the character out.
1796 serial_port_out(port, UART_TX, c);
1799 * Finally, wait for transmitter to become empty
1800 * and restore the IER
1802 wait_for_xmitr(up, BOTH_EMPTY);
1803 serial_port_out(port, UART_IER, ier);
1804 serial8250_rpm_put(up);
1807 #endif /* CONFIG_CONSOLE_POLL */
1809 int serial8250_do_startup(struct uart_port *port)
1811 struct uart_8250_port *up = up_to_u8250p(port);
1812 unsigned long flags;
1813 unsigned char lsr, iir;
1816 if (!port->fifosize)
1817 port->fifosize = uart_config[port->type].fifo_size;
1819 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1820 if (!up->capabilities)
1821 up->capabilities = uart_config[port->type].flags;
1824 if (port->iotype != up->cur_iotype)
1825 set_io_from_upio(port);
1827 serial8250_rpm_get(up);
1828 if (port->type == PORT_16C950) {
1829 /* Wake up and initialize UART */
1831 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1832 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1833 serial_port_out(port, UART_IER, 0);
1834 serial_port_out(port, UART_LCR, 0);
1835 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1836 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1837 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1838 serial_port_out(port, UART_LCR, 0);
1841 #ifdef CONFIG_SERIAL_8250_RSA
1843 * If this is an RSA port, see if we can kick it up to the
1844 * higher speed clock.
1849 if (port->type == PORT_XR17V35X) {
1851 * First enable access to IER [7:5], ISR [5:4], FCR [5:4],
1852 * MCR [7:5] and MSR [7:0]
1854 serial_port_out(port, UART_XR_EFR, UART_EFR_ECB);
1857 * Make sure all interrups are masked until initialization is
1858 * complete and the FIFOs are cleared
1860 serial_port_out(port, UART_IER, 0);
1864 * Clear the FIFO buffers and disable them.
1865 * (they will be reenabled in set_termios())
1867 serial8250_clear_fifos(up);
1870 * Clear the interrupt registers.
1872 serial_port_in(port, UART_LSR);
1873 serial_port_in(port, UART_RX);
1874 serial_port_in(port, UART_IIR);
1875 serial_port_in(port, UART_MSR);
1878 * At this point, there's no way the LSR could still be 0xff;
1879 * if it is, then bail out, because there's likely no UART
1882 if (!(port->flags & UPF_BUGGY_UART) &&
1883 (serial_port_in(port, UART_LSR) == 0xff)) {
1884 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
1885 serial_index(port));
1891 * For a XR16C850, we need to set the trigger levels
1893 if (port->type == PORT_16850) {
1896 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1898 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
1899 serial_port_out(port, UART_FCTR,
1900 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
1901 serial_port_out(port, UART_TRG, UART_TRG_96);
1902 serial_port_out(port, UART_FCTR,
1903 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
1904 serial_port_out(port, UART_TRG, UART_TRG_96);
1906 serial_port_out(port, UART_LCR, 0);
1912 * Test for UARTs that do not reassert THRE when the
1913 * transmitter is idle and the interrupt has already
1914 * been cleared. Real 16550s should always reassert
1915 * this interrupt whenever the transmitter is idle and
1916 * the interrupt is enabled. Delays are necessary to
1917 * allow register changes to become visible.
1919 spin_lock_irqsave(&port->lock, flags);
1920 if (up->port.irqflags & IRQF_SHARED)
1921 disable_irq_nosync(port->irq);
1923 wait_for_xmitr(up, UART_LSR_THRE);
1924 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
1925 udelay(1); /* allow THRE to set */
1926 iir1 = serial_port_in(port, UART_IIR);
1927 serial_port_out(port, UART_IER, 0);
1928 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
1929 udelay(1); /* allow a working UART time to re-assert THRE */
1930 iir = serial_port_in(port, UART_IIR);
1931 serial_port_out(port, UART_IER, 0);
1933 if (port->irqflags & IRQF_SHARED)
1934 enable_irq(port->irq);
1935 spin_unlock_irqrestore(&port->lock, flags);
1938 * If the interrupt is not reasserted, or we otherwise
1939 * don't trust the iir, setup a timer to kick the UART
1940 * on a regular basis.
1942 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
1943 up->port.flags & UPF_BUG_THRE) {
1944 up->bugs |= UART_BUG_THRE;
1948 retval = up->ops->setup_irq(up);
1953 * Now, initialize the UART
1955 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
1957 spin_lock_irqsave(&port->lock, flags);
1958 if (up->port.flags & UPF_FOURPORT) {
1960 up->port.mctrl |= TIOCM_OUT1;
1963 * Most PC uarts need OUT2 raised to enable interrupts.
1966 up->port.mctrl |= TIOCM_OUT2;
1968 serial8250_set_mctrl(port, port->mctrl);
1970 /* Serial over Lan (SoL) hack:
1971 Intel 8257x Gigabit ethernet chips have a
1972 16550 emulation, to be used for Serial Over Lan.
1973 Those chips take a longer time than a normal
1974 serial device to signalize that a transmission
1975 data was queued. Due to that, the above test generally
1976 fails. One solution would be to delay the reading of
1977 iir. However, this is not reliable, since the timeout
1978 is variable. So, let's just don't test if we receive
1979 TX irq. This way, we'll never enable UART_BUG_TXEN.
1981 if (up->port.flags & UPF_NO_TXEN_TEST)
1982 goto dont_test_tx_en;
1985 * Do a quick test to see if we receive an
1986 * interrupt when we enable the TX irq.
1988 serial_port_out(port, UART_IER, UART_IER_THRI);
1989 lsr = serial_port_in(port, UART_LSR);
1990 iir = serial_port_in(port, UART_IIR);
1991 serial_port_out(port, UART_IER, 0);
1993 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
1994 if (!(up->bugs & UART_BUG_TXEN)) {
1995 up->bugs |= UART_BUG_TXEN;
1996 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
1997 serial_index(port));
2000 up->bugs &= ~UART_BUG_TXEN;
2004 spin_unlock_irqrestore(&port->lock, flags);
2007 * Clear the interrupt registers again for luck, and clear the
2008 * saved flags to avoid getting false values from polling
2009 * routines or the previous session.
2011 serial_port_in(port, UART_LSR);
2012 serial_port_in(port, UART_RX);
2013 serial_port_in(port, UART_IIR);
2014 serial_port_in(port, UART_MSR);
2015 up->lsr_saved_flags = 0;
2016 up->msr_saved_flags = 0;
2019 * Request DMA channels for both RX and TX.
2022 retval = serial8250_request_dma(up);
2024 pr_warn_ratelimited("ttyS%d - failed to request DMA\n",
2025 serial_index(port));
2031 * Set the IER shadow for rx interrupts but defer actual interrupt
2032 * enable until after the FIFOs are enabled; otherwise, an already-
2033 * active sender can swamp the interrupt handler with "too much work".
2035 up->ier = UART_IER_RLSI | UART_IER_RDI;
2037 if (port->flags & UPF_FOURPORT) {
2040 * Enable interrupts on the AST Fourport board
2042 icp = (port->iobase & 0xfe0) | 0x01f;
2048 serial8250_rpm_put(up);
2051 EXPORT_SYMBOL_GPL(serial8250_do_startup);
2053 static int serial8250_startup(struct uart_port *port)
2056 return port->startup(port);
2057 return serial8250_do_startup(port);
2060 void serial8250_do_shutdown(struct uart_port *port)
2062 struct uart_8250_port *up = up_to_u8250p(port);
2063 unsigned long flags;
2065 serial8250_rpm_get(up);
2067 * Disable interrupts from this port
2070 serial_port_out(port, UART_IER, 0);
2073 serial8250_release_dma(up);
2075 spin_lock_irqsave(&port->lock, flags);
2076 if (port->flags & UPF_FOURPORT) {
2077 /* reset interrupts on the AST Fourport board */
2078 inb((port->iobase & 0xfe0) | 0x1f);
2079 port->mctrl |= TIOCM_OUT1;
2081 port->mctrl &= ~TIOCM_OUT2;
2083 serial8250_set_mctrl(port, port->mctrl);
2084 spin_unlock_irqrestore(&port->lock, flags);
2087 * Disable break condition and FIFOs
2089 serial_port_out(port, UART_LCR,
2090 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2091 serial8250_clear_fifos(up);
2093 #ifdef CONFIG_SERIAL_8250_RSA
2095 * Reset the RSA board back to 115kbps compat mode.
2101 * Read data port to reset things, and then unlink from
2104 serial_port_in(port, UART_RX);
2105 serial8250_rpm_put(up);
2107 up->ops->release_irq(up);
2109 EXPORT_SYMBOL_GPL(serial8250_do_shutdown);
2111 static void serial8250_shutdown(struct uart_port *port)
2114 port->shutdown(port);
2116 serial8250_do_shutdown(port);
2120 * XR17V35x UARTs have an extra fractional divisor register (DLD)
2121 * Calculate divisor with extra 4-bit fractional portion
2123 static unsigned int xr17v35x_get_divisor(struct uart_8250_port *up,
2127 struct uart_port *port = &up->port;
2128 unsigned int quot_16;
2130 quot_16 = DIV_ROUND_CLOSEST(port->uartclk, baud);
2131 *frac = quot_16 & 0x0f;
2133 return quot_16 >> 4;
2136 static unsigned int serial8250_get_divisor(struct uart_8250_port *up,
2140 struct uart_port *port = &up->port;
2144 * Handle magic divisors for baud rates above baud_base on
2145 * SMSC SuperIO chips.
2148 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2149 baud == (port->uartclk/4))
2151 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2152 baud == (port->uartclk/8))
2154 else if (up->port.type == PORT_XR17V35X)
2155 quot = xr17v35x_get_divisor(up, baud, frac);
2157 quot = uart_get_divisor(port, baud);
2160 * Oxford Semi 952 rev B workaround
2162 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2168 static unsigned char serial8250_compute_lcr(struct uart_8250_port *up,
2173 switch (c_cflag & CSIZE) {
2175 cval = UART_LCR_WLEN5;
2178 cval = UART_LCR_WLEN6;
2181 cval = UART_LCR_WLEN7;
2185 cval = UART_LCR_WLEN8;
2189 if (c_cflag & CSTOPB)
2190 cval |= UART_LCR_STOP;
2191 if (c_cflag & PARENB) {
2192 cval |= UART_LCR_PARITY;
2193 if (up->bugs & UART_BUG_PARITY)
2194 up->fifo_bug = true;
2196 if (!(c_cflag & PARODD))
2197 cval |= UART_LCR_EPAR;
2199 if (c_cflag & CMSPAR)
2200 cval |= UART_LCR_SPAR;
2206 static void serial8250_set_divisor(struct uart_port *port, unsigned int baud,
2207 unsigned int quot, unsigned int quot_frac)
2209 struct uart_8250_port *up = up_to_u8250p(port);
2211 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2212 if (is_omap1510_8250(up)) {
2213 if (baud == 115200) {
2215 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2217 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2221 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2222 * otherwise just set DLAB
2224 if (up->capabilities & UART_NATSEMI)
2225 serial_port_out(port, UART_LCR, 0xe0);
2227 serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
2229 serial_dl_write(up, quot);
2231 /* XR17V35x UARTs have an extra fractional divisor register (DLD) */
2232 if (up->port.type == PORT_XR17V35X)
2233 serial_port_out(port, 0x2, quot_frac);
2237 serial8250_get_baud_rate(struct uart_port *port, struct ktermios *termios,
2238 struct ktermios *old)
2240 unsigned int tolerance = port->uartclk / 100;
2243 * Ask the core to calculate the divisor for us.
2244 * Allow 1% tolerance at the upper limit so uart clks marginally
2245 * slower than nominal still match standard baud rates without
2246 * causing transmission errors.
2248 return uart_get_baud_rate(port, termios, old,
2249 port->uartclk / 16 / 0xffff,
2250 (port->uartclk + tolerance) / 16);
2254 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2255 struct ktermios *old)
2257 struct uart_8250_port *up = up_to_u8250p(port);
2259 unsigned long flags;
2260 unsigned int baud, quot, frac = 0;
2262 cval = serial8250_compute_lcr(up, termios->c_cflag);
2264 baud = serial8250_get_baud_rate(port, termios, old);
2265 quot = serial8250_get_divisor(up, baud, &frac);
2268 * Ok, we're now changing the port state. Do it with
2269 * interrupts disabled.
2271 serial8250_rpm_get(up);
2272 spin_lock_irqsave(&port->lock, flags);
2274 up->lcr = cval; /* Save computed LCR */
2276 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2277 /* NOTE: If fifo_bug is not set, a user can set RX_trigger. */
2278 if ((baud < 2400 && !up->dma) || up->fifo_bug) {
2279 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2280 up->fcr |= UART_FCR_TRIGGER_1;
2285 * MCR-based auto flow control. When AFE is enabled, RTS will be
2286 * deasserted when the receive FIFO contains more characters than
2287 * the trigger, or the MCR RTS bit is cleared. In the case where
2288 * the remote UART is not using CTS auto flow control, we must
2289 * have sufficient FIFO entries for the latency of the remote
2290 * UART to respond. IOW, at least 32 bytes of FIFO.
2292 if (up->capabilities & UART_CAP_AFE && port->fifosize >= 32) {
2293 up->mcr &= ~UART_MCR_AFE;
2294 if (termios->c_cflag & CRTSCTS)
2295 up->mcr |= UART_MCR_AFE;
2299 * Update the per-port timeout.
2301 uart_update_timeout(port, termios->c_cflag, baud);
2303 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2304 if (termios->c_iflag & INPCK)
2305 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2306 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2307 port->read_status_mask |= UART_LSR_BI;
2310 * Characteres to ignore
2312 port->ignore_status_mask = 0;
2313 if (termios->c_iflag & IGNPAR)
2314 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2315 if (termios->c_iflag & IGNBRK) {
2316 port->ignore_status_mask |= UART_LSR_BI;
2318 * If we're ignoring parity and break indicators,
2319 * ignore overruns too (for real raw support).
2321 if (termios->c_iflag & IGNPAR)
2322 port->ignore_status_mask |= UART_LSR_OE;
2326 * ignore all characters if CREAD is not set
2328 if ((termios->c_cflag & CREAD) == 0)
2329 port->ignore_status_mask |= UART_LSR_DR;
2332 * CTS flow control flag and modem status interrupts
2334 up->ier &= ~UART_IER_MSI;
2335 if (!(up->bugs & UART_BUG_NOMSR) &&
2336 UART_ENABLE_MS(&up->port, termios->c_cflag))
2337 up->ier |= UART_IER_MSI;
2338 if (up->capabilities & UART_CAP_UUE)
2339 up->ier |= UART_IER_UUE;
2340 if (up->capabilities & UART_CAP_RTOIE)
2341 up->ier |= UART_IER_RTOIE;
2343 serial_port_out(port, UART_IER, up->ier);
2345 if (up->capabilities & UART_CAP_EFR) {
2346 unsigned char efr = 0;
2348 * TI16C752/Startech hardware flow control. FIXME:
2349 * - TI16C752 requires control thresholds to be set.
2350 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2352 if (termios->c_cflag & CRTSCTS)
2353 efr |= UART_EFR_CTS;
2355 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2356 if (port->flags & UPF_EXAR_EFR)
2357 serial_port_out(port, UART_XR_EFR, efr);
2359 serial_port_out(port, UART_EFR, efr);
2362 serial8250_set_divisor(port, baud, quot, frac);
2365 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2366 * is written without DLAB set, this mode will be disabled.
2368 if (port->type == PORT_16750)
2369 serial_port_out(port, UART_FCR, up->fcr);
2371 serial_port_out(port, UART_LCR, up->lcr); /* reset DLAB */
2372 if (port->type != PORT_16750) {
2373 /* emulated UARTs (Lucent Venus 167x) need two steps */
2374 if (up->fcr & UART_FCR_ENABLE_FIFO)
2375 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2376 serial_port_out(port, UART_FCR, up->fcr); /* set fcr */
2378 serial8250_set_mctrl(port, port->mctrl);
2379 spin_unlock_irqrestore(&port->lock, flags);
2380 serial8250_rpm_put(up);
2382 /* Don't rewrite B0 */
2383 if (tty_termios_baud_rate(termios))
2384 tty_termios_encode_baud_rate(termios, baud, baud);
2386 EXPORT_SYMBOL(serial8250_do_set_termios);
2389 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2390 struct ktermios *old)
2392 if (port->set_termios)
2393 port->set_termios(port, termios, old);
2395 serial8250_do_set_termios(port, termios, old);
2399 serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios)
2401 if (termios->c_line == N_PPS) {
2402 port->flags |= UPF_HARDPPS_CD;
2403 spin_lock_irq(&port->lock);
2404 serial8250_enable_ms(port);
2405 spin_unlock_irq(&port->lock);
2407 port->flags &= ~UPF_HARDPPS_CD;
2408 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2409 spin_lock_irq(&port->lock);
2410 serial8250_disable_ms(port);
2411 spin_unlock_irq(&port->lock);
2417 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2418 unsigned int oldstate)
2420 struct uart_8250_port *p = up_to_u8250p(port);
2422 serial8250_set_sleep(p, state != 0);
2424 EXPORT_SYMBOL(serial8250_do_pm);
2427 serial8250_pm(struct uart_port *port, unsigned int state,
2428 unsigned int oldstate)
2431 port->pm(port, state, oldstate);
2433 serial8250_do_pm(port, state, oldstate);
2436 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2438 if (pt->port.mapsize)
2439 return pt->port.mapsize;
2440 if (pt->port.iotype == UPIO_AU) {
2441 if (pt->port.type == PORT_RT2880)
2445 if (is_omap1_8250(pt))
2446 return 0x16 << pt->port.regshift;
2448 return 8 << pt->port.regshift;
2452 * Resource handling.
2454 static int serial8250_request_std_resource(struct uart_8250_port *up)
2456 unsigned int size = serial8250_port_size(up);
2457 struct uart_port *port = &up->port;
2460 switch (port->iotype) {
2469 if (!request_mem_region(port->mapbase, size, "serial")) {
2474 if (port->flags & UPF_IOREMAP) {
2475 port->membase = ioremap_nocache(port->mapbase, size);
2476 if (!port->membase) {
2477 release_mem_region(port->mapbase, size);
2485 if (!request_region(port->iobase, size, "serial"))
2492 static void serial8250_release_std_resource(struct uart_8250_port *up)
2494 unsigned int size = serial8250_port_size(up);
2495 struct uart_port *port = &up->port;
2497 switch (port->iotype) {
2506 if (port->flags & UPF_IOREMAP) {
2507 iounmap(port->membase);
2508 port->membase = NULL;
2511 release_mem_region(port->mapbase, size);
2516 release_region(port->iobase, size);
2521 static void serial8250_release_port(struct uart_port *port)
2523 struct uart_8250_port *up = up_to_u8250p(port);
2525 serial8250_release_std_resource(up);
2528 static int serial8250_request_port(struct uart_port *port)
2530 struct uart_8250_port *up = up_to_u8250p(port);
2532 return serial8250_request_std_resource(up);
2535 static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
2537 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2538 unsigned char bytes;
2540 bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
2542 return bytes ? bytes : -EOPNOTSUPP;
2545 static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
2547 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2550 if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)])
2553 for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) {
2554 if (bytes < conf_type->rxtrig_bytes[i])
2555 /* Use the nearest lower value */
2556 return (--i) << UART_FCR_R_TRIG_SHIFT;
2559 return UART_FCR_R_TRIG_11;
2562 static int do_get_rxtrig(struct tty_port *port)
2564 struct uart_state *state = container_of(port, struct uart_state, port);
2565 struct uart_port *uport = state->uart_port;
2566 struct uart_8250_port *up =
2567 container_of(uport, struct uart_8250_port, port);
2569 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
2572 return fcr_get_rxtrig_bytes(up);
2575 static int do_serial8250_get_rxtrig(struct tty_port *port)
2579 mutex_lock(&port->mutex);
2580 rxtrig_bytes = do_get_rxtrig(port);
2581 mutex_unlock(&port->mutex);
2583 return rxtrig_bytes;
2586 static ssize_t serial8250_get_attr_rx_trig_bytes(struct device *dev,
2587 struct device_attribute *attr, char *buf)
2589 struct tty_port *port = dev_get_drvdata(dev);
2592 rxtrig_bytes = do_serial8250_get_rxtrig(port);
2593 if (rxtrig_bytes < 0)
2594 return rxtrig_bytes;
2596 return snprintf(buf, PAGE_SIZE, "%d\n", rxtrig_bytes);
2599 static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
2601 struct uart_state *state = container_of(port, struct uart_state, port);
2602 struct uart_port *uport = state->uart_port;
2603 struct uart_8250_port *up =
2604 container_of(uport, struct uart_8250_port, port);
2607 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1 ||
2611 rxtrig = bytes_to_fcr_rxtrig(up, bytes);
2615 serial8250_clear_fifos(up);
2616 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2617 up->fcr |= (unsigned char)rxtrig;
2618 serial_out(up, UART_FCR, up->fcr);
2622 static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes)
2626 mutex_lock(&port->mutex);
2627 ret = do_set_rxtrig(port, bytes);
2628 mutex_unlock(&port->mutex);
2633 static ssize_t serial8250_set_attr_rx_trig_bytes(struct device *dev,
2634 struct device_attribute *attr, const char *buf, size_t count)
2636 struct tty_port *port = dev_get_drvdata(dev);
2637 unsigned char bytes;
2643 ret = kstrtou8(buf, 10, &bytes);
2647 ret = do_serial8250_set_rxtrig(port, bytes);
2654 static DEVICE_ATTR(rx_trig_bytes, S_IRUSR | S_IWUSR | S_IRGRP,
2655 serial8250_get_attr_rx_trig_bytes,
2656 serial8250_set_attr_rx_trig_bytes);
2658 static struct attribute *serial8250_dev_attrs[] = {
2659 &dev_attr_rx_trig_bytes.attr,
2663 static struct attribute_group serial8250_dev_attr_group = {
2664 .attrs = serial8250_dev_attrs,
2667 static void register_dev_spec_attr_grp(struct uart_8250_port *up)
2669 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2671 if (conf_type->rxtrig_bytes[0])
2672 up->port.attr_group = &serial8250_dev_attr_group;
2675 static void serial8250_config_port(struct uart_port *port, int flags)
2677 struct uart_8250_port *up = up_to_u8250p(port);
2681 * Find the region that we can probe for. This in turn
2682 * tells us whether we can probe for the type of port.
2684 ret = serial8250_request_std_resource(up);
2688 if (port->iotype != up->cur_iotype)
2689 set_io_from_upio(port);
2691 if (flags & UART_CONFIG_TYPE)
2694 /* if access method is AU, it is a 16550 with a quirk */
2695 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
2696 up->bugs |= UART_BUG_NOMSR;
2698 /* HW bugs may trigger IRQ while IIR == NO_INT */
2699 if (port->type == PORT_TEGRA)
2700 up->bugs |= UART_BUG_NOMSR;
2702 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2705 if (port->type == PORT_UNKNOWN)
2706 serial8250_release_std_resource(up);
2708 /* Fixme: probably not the best place for this */
2709 if ((port->type == PORT_XR17V35X) ||
2710 (port->type == PORT_XR17D15X))
2711 port->handle_irq = exar_handle_irq;
2713 register_dev_spec_attr_grp(up);
2714 up->fcr = uart_config[up->port.type].fcr;
2718 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2720 if (ser->irq >= nr_irqs || ser->irq < 0 ||
2721 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2722 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2723 ser->type == PORT_STARTECH)
2729 serial8250_type(struct uart_port *port)
2731 int type = port->type;
2733 if (type >= ARRAY_SIZE(uart_config))
2735 return uart_config[type].name;
2738 static const struct uart_ops serial8250_pops = {
2739 .tx_empty = serial8250_tx_empty,
2740 .set_mctrl = serial8250_set_mctrl,
2741 .get_mctrl = serial8250_get_mctrl,
2742 .stop_tx = serial8250_stop_tx,
2743 .start_tx = serial8250_start_tx,
2744 .throttle = serial8250_throttle,
2745 .unthrottle = serial8250_unthrottle,
2746 .stop_rx = serial8250_stop_rx,
2747 .enable_ms = serial8250_enable_ms,
2748 .break_ctl = serial8250_break_ctl,
2749 .startup = serial8250_startup,
2750 .shutdown = serial8250_shutdown,
2751 .set_termios = serial8250_set_termios,
2752 .set_ldisc = serial8250_set_ldisc,
2753 .pm = serial8250_pm,
2754 .type = serial8250_type,
2755 .release_port = serial8250_release_port,
2756 .request_port = serial8250_request_port,
2757 .config_port = serial8250_config_port,
2758 .verify_port = serial8250_verify_port,
2759 #ifdef CONFIG_CONSOLE_POLL
2760 .poll_get_char = serial8250_get_poll_char,
2761 .poll_put_char = serial8250_put_poll_char,
2765 void serial8250_init_port(struct uart_8250_port *up)
2767 struct uart_port *port = &up->port;
2769 spin_lock_init(&port->lock);
2770 port->ops = &serial8250_pops;
2772 up->cur_iotype = 0xFF;
2774 EXPORT_SYMBOL_GPL(serial8250_init_port);
2776 void serial8250_set_defaults(struct uart_8250_port *up)
2778 struct uart_port *port = &up->port;
2780 if (up->port.flags & UPF_FIXED_TYPE) {
2781 unsigned int type = up->port.type;
2783 if (!up->port.fifosize)
2784 up->port.fifosize = uart_config[type].fifo_size;
2786 up->tx_loadsz = uart_config[type].tx_loadsz;
2787 if (!up->capabilities)
2788 up->capabilities = uart_config[type].flags;
2791 set_io_from_upio(port);
2793 /* default dma handlers */
2795 if (!up->dma->tx_dma)
2796 up->dma->tx_dma = serial8250_tx_dma;
2797 if (!up->dma->rx_dma)
2798 up->dma->rx_dma = serial8250_rx_dma;
2801 EXPORT_SYMBOL_GPL(serial8250_set_defaults);
2803 #ifdef CONFIG_SERIAL_8250_CONSOLE
2805 static void serial8250_console_putchar(struct uart_port *port, int ch)
2807 struct uart_8250_port *up = up_to_u8250p(port);
2809 wait_for_xmitr(up, UART_LSR_THRE);
2810 serial_port_out(port, UART_TX, ch);
2814 * Restore serial console when h/w power-off detected
2816 static void serial8250_console_restore(struct uart_8250_port *up)
2818 struct uart_port *port = &up->port;
2819 struct ktermios termios;
2820 unsigned int baud, quot, frac = 0;
2822 termios.c_cflag = port->cons->cflag;
2823 if (port->state->port.tty && termios.c_cflag == 0)
2824 termios.c_cflag = port->state->port.tty->termios.c_cflag;
2826 baud = serial8250_get_baud_rate(port, &termios, NULL);
2827 quot = serial8250_get_divisor(up, baud, &frac);
2829 serial8250_set_divisor(port, baud, quot, frac);
2830 serial_port_out(port, UART_LCR, up->lcr);
2831 serial_port_out(port, UART_MCR, UART_MCR_DTR | UART_MCR_RTS);
2835 * Print a string to the serial port trying not to disturb
2836 * any possible real use of the port...
2838 * The console_lock must be held when we get here.
2840 void serial8250_console_write(struct uart_8250_port *up, const char *s,
2843 struct uart_port *port = &up->port;
2844 unsigned long flags;
2848 touch_nmi_watchdog();
2850 serial8250_rpm_get(up);
2854 else if (oops_in_progress)
2855 locked = spin_trylock_irqsave(&port->lock, flags);
2857 spin_lock_irqsave(&port->lock, flags);
2860 * First save the IER then disable the interrupts
2862 ier = serial_port_in(port, UART_IER);
2864 if (up->capabilities & UART_CAP_UUE)
2865 serial_port_out(port, UART_IER, UART_IER_UUE);
2867 serial_port_out(port, UART_IER, 0);
2869 /* check scratch reg to see if port powered off during system sleep */
2870 if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) {
2871 serial8250_console_restore(up);
2875 uart_console_write(port, s, count, serial8250_console_putchar);
2878 * Finally, wait for transmitter to become empty
2879 * and restore the IER
2881 wait_for_xmitr(up, BOTH_EMPTY);
2882 serial_port_out(port, UART_IER, ier);
2885 * The receive handling will happen properly because the
2886 * receive ready bit will still be set; it is not cleared
2887 * on read. However, modem control will not, we must
2888 * call it if we have saved something in the saved flags
2889 * while processing with interrupts off.
2891 if (up->msr_saved_flags)
2892 serial8250_modem_status(up);
2895 spin_unlock_irqrestore(&port->lock, flags);
2896 serial8250_rpm_put(up);
2899 static unsigned int probe_baud(struct uart_port *port)
2901 unsigned char lcr, dll, dlm;
2904 lcr = serial_port_in(port, UART_LCR);
2905 serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB);
2906 dll = serial_port_in(port, UART_DLL);
2907 dlm = serial_port_in(port, UART_DLM);
2908 serial_port_out(port, UART_LCR, lcr);
2910 quot = (dlm << 8) | dll;
2911 return (port->uartclk / 16) / quot;
2914 int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
2921 if (!port->iobase && !port->membase)
2925 uart_parse_options(options, &baud, &parity, &bits, &flow);
2927 baud = probe_baud(port);
2929 return uart_set_options(port, port->cons, baud, parity, bits, flow);
2932 #endif /* CONFIG_SERIAL_8250_CONSOLE */
2934 MODULE_LICENSE("GPL");