2 * Driver for 8250/16550-type serial ports
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Copyright (C) 2001 Russell King.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * A note about mapbase / membase
15 * mapbase is the physical address of the IO port.
16 * membase is an 'ioremapped' cookie.
19 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
23 #include <linux/module.h>
24 #include <linux/moduleparam.h>
25 #include <linux/ioport.h>
26 #include <linux/init.h>
27 #include <linux/console.h>
28 #include <linux/sysrq.h>
29 #include <linux/delay.h>
30 #include <linux/platform_device.h>
31 #include <linux/tty.h>
32 #include <linux/ratelimit.h>
33 #include <linux/tty_flip.h>
34 #include <linux/serial_reg.h>
35 #include <linux/serial_core.h>
36 #include <linux/serial.h>
37 #include <linux/serial_8250.h>
38 #include <linux/nmi.h>
39 #include <linux/mutex.h>
40 #include <linux/slab.h>
53 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
54 * is unsafe when used on edge-triggered interrupts.
56 static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
58 static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
60 static struct uart_driver serial8250_reg;
62 static int serial_index(struct uart_port *port)
64 return (serial8250_reg.minor - 64) + port->line;
67 static unsigned int skip_txen_test; /* force skip of txen test at init time */
73 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
75 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
79 #define DEBUG_INTR(fmt...) printk(fmt)
81 #define DEBUG_INTR(fmt...) do { } while (0)
84 #define PASS_LIMIT 512
86 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
90 * We default to IRQ0 for the "no irq" hack. Some
91 * machine types want others as well - they're free
92 * to redefine this in their header file.
94 #define is_real_interrupt(irq) ((irq) != 0)
96 #ifdef CONFIG_SERIAL_8250_DETECT_IRQ
97 #define CONFIG_SERIAL_DETECT_IRQ 1
99 #ifdef CONFIG_SERIAL_8250_MANY_PORTS
100 #define CONFIG_SERIAL_MANY_PORTS 1
104 * HUB6 is always on. This will be removed once the header
105 * files have been cleaned.
107 #define CONFIG_HUB6 1
109 #include <asm/serial.h>
111 * SERIAL_PORT_DFNS tells us about built-in ports that have no
112 * standard enumeration mechanism. Platforms that can find all
113 * serial ports via mechanisms like ACPI or PCI need not supply it.
115 #ifndef SERIAL_PORT_DFNS
116 #define SERIAL_PORT_DFNS
119 static const struct old_serial_port old_serial_port[] = {
120 SERIAL_PORT_DFNS /* defined in asm/serial.h */
123 #define UART_NR CONFIG_SERIAL_8250_NR_UARTS
125 #ifdef CONFIG_SERIAL_8250_RSA
127 #define PORT_RSA_MAX 4
128 static unsigned long probe_rsa[PORT_RSA_MAX];
129 static unsigned int probe_rsa_count;
130 #endif /* CONFIG_SERIAL_8250_RSA */
132 struct uart_8250_port {
133 struct uart_port port;
134 struct timer_list timer; /* "no irq" timer */
135 struct list_head list; /* ports on this IRQ */
136 unsigned short capabilities; /* port capabilities */
137 unsigned short bugs; /* port bugs */
138 unsigned int tx_loadsz; /* transmit fifo load size */
143 unsigned char mcr_mask; /* mask of user bits */
144 unsigned char mcr_force; /* mask of forced bits */
145 unsigned char cur_iotype; /* Running I/O type */
148 * Some bits in registers are cleared on a read, so they must
149 * be saved whenever the register is read but the bits will not
150 * be immediately processed.
152 #define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS
153 unsigned char lsr_saved_flags;
154 #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
155 unsigned char msr_saved_flags;
159 struct hlist_node node;
161 spinlock_t lock; /* Protects list not the hash */
162 struct list_head *head;
165 #define NR_IRQ_HASH 32 /* Can be adjusted later */
166 static struct hlist_head irq_lists[NR_IRQ_HASH];
167 static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
170 * Here we define the default xmit fifo size used for each type of UART.
172 static const struct serial8250_config uart_config[] = {
197 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
198 .flags = UART_CAP_FIFO,
209 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
215 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
217 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
223 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
225 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
233 .name = "16C950/954",
236 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
237 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
238 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
244 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
246 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
252 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
253 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
259 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
260 .flags = UART_CAP_FIFO,
266 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
267 .flags = UART_CAP_FIFO | UART_NATSEMI,
273 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
274 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
280 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
281 .flags = UART_CAP_FIFO,
287 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
288 .flags = UART_CAP_FIFO,
294 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
295 .flags = UART_CAP_FIFO | UART_CAP_AFE,
301 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
302 .flags = UART_CAP_FIFO | UART_CAP_AFE,
308 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
310 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
316 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
317 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR,
321 #if defined(CONFIG_MIPS_ALCHEMY)
323 /* Au1x00 UART hardware has a weird register layout */
324 static const u8 au_io_in_map[] = {
334 static const u8 au_io_out_map[] = {
342 /* sane hardware needs no mapping */
343 static inline int map_8250_in_reg(struct uart_port *p, int offset)
345 if (p->iotype != UPIO_AU)
347 return au_io_in_map[offset];
350 static inline int map_8250_out_reg(struct uart_port *p, int offset)
352 if (p->iotype != UPIO_AU)
354 return au_io_out_map[offset];
357 #elif defined(CONFIG_SERIAL_8250_RM9K)
381 static inline int map_8250_in_reg(struct uart_port *p, int offset)
383 if (p->iotype != UPIO_RM9000)
385 return regmap_in[offset];
388 static inline int map_8250_out_reg(struct uart_port *p, int offset)
390 if (p->iotype != UPIO_RM9000)
392 return regmap_out[offset];
397 /* sane hardware needs no mapping */
398 #define map_8250_in_reg(up, offset) (offset)
399 #define map_8250_out_reg(up, offset) (offset)
403 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
405 offset = map_8250_in_reg(p, offset) << p->regshift;
406 outb(p->hub6 - 1 + offset, p->iobase);
407 return inb(p->iobase + 1);
410 static void hub6_serial_out(struct uart_port *p, int offset, int value)
412 offset = map_8250_out_reg(p, offset) << p->regshift;
413 outb(p->hub6 - 1 + offset, p->iobase);
414 outb(value, p->iobase + 1);
417 static unsigned int mem_serial_in(struct uart_port *p, int offset)
419 offset = map_8250_in_reg(p, offset) << p->regshift;
420 return readb(p->membase + offset);
423 static void mem_serial_out(struct uart_port *p, int offset, int value)
425 offset = map_8250_out_reg(p, offset) << p->regshift;
426 writeb(value, p->membase + offset);
429 static void mem32_serial_out(struct uart_port *p, int offset, int value)
431 offset = map_8250_out_reg(p, offset) << p->regshift;
432 writel(value, p->membase + offset);
435 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
437 offset = map_8250_in_reg(p, offset) << p->regshift;
438 return readl(p->membase + offset);
441 static unsigned int au_serial_in(struct uart_port *p, int offset)
443 offset = map_8250_in_reg(p, offset) << p->regshift;
444 return __raw_readl(p->membase + offset);
447 static void au_serial_out(struct uart_port *p, int offset, int value)
449 offset = map_8250_out_reg(p, offset) << p->regshift;
450 __raw_writel(value, p->membase + offset);
453 static unsigned int io_serial_in(struct uart_port *p, int offset)
455 offset = map_8250_in_reg(p, offset) << p->regshift;
456 return inb(p->iobase + offset);
459 static void io_serial_out(struct uart_port *p, int offset, int value)
461 offset = map_8250_out_reg(p, offset) << p->regshift;
462 outb(value, p->iobase + offset);
465 static int serial8250_default_handle_irq(struct uart_port *port);
467 static void set_io_from_upio(struct uart_port *p)
469 struct uart_8250_port *up =
470 container_of(p, struct uart_8250_port, port);
473 p->serial_in = hub6_serial_in;
474 p->serial_out = hub6_serial_out;
478 p->serial_in = mem_serial_in;
479 p->serial_out = mem_serial_out;
484 p->serial_in = mem32_serial_in;
485 p->serial_out = mem32_serial_out;
489 p->serial_in = au_serial_in;
490 p->serial_out = au_serial_out;
494 p->serial_in = io_serial_in;
495 p->serial_out = io_serial_out;
498 /* Remember loaded iotype */
499 up->cur_iotype = p->iotype;
500 p->handle_irq = serial8250_default_handle_irq;
504 serial_out_sync(struct uart_8250_port *up, int offset, int value)
506 struct uart_port *p = &up->port;
511 p->serial_out(p, offset, value);
512 p->serial_in(p, UART_LCR); /* safe, no side-effects */
515 p->serial_out(p, offset, value);
519 #define serial_in(up, offset) \
520 (up->port.serial_in(&(up)->port, (offset)))
521 #define serial_out(up, offset, value) \
522 (up->port.serial_out(&(up)->port, (offset), (value)))
524 * We used to support using pause I/O for certain machines. We
525 * haven't supported this for a while, but just in case it's badly
526 * needed for certain old 386 machines, I've left these #define's
529 #define serial_inp(up, offset) serial_in(up, offset)
530 #define serial_outp(up, offset, value) serial_out(up, offset, value)
532 /* Uart divisor latch read */
533 static inline int _serial_dl_read(struct uart_8250_port *up)
535 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
538 /* Uart divisor latch write */
539 static inline void _serial_dl_write(struct uart_8250_port *up, int value)
541 serial_outp(up, UART_DLL, value & 0xff);
542 serial_outp(up, UART_DLM, value >> 8 & 0xff);
545 #if defined(CONFIG_MIPS_ALCHEMY)
546 /* Au1x00 haven't got a standard divisor latch */
547 static int serial_dl_read(struct uart_8250_port *up)
549 if (up->port.iotype == UPIO_AU)
550 return __raw_readl(up->port.membase + 0x28);
552 return _serial_dl_read(up);
555 static void serial_dl_write(struct uart_8250_port *up, int value)
557 if (up->port.iotype == UPIO_AU)
558 __raw_writel(value, up->port.membase + 0x28);
560 _serial_dl_write(up, value);
562 #elif defined(CONFIG_SERIAL_8250_RM9K)
563 static int serial_dl_read(struct uart_8250_port *up)
565 return (up->port.iotype == UPIO_RM9000) ?
566 (((__raw_readl(up->port.membase + 0x10) << 8) |
567 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
571 static void serial_dl_write(struct uart_8250_port *up, int value)
573 if (up->port.iotype == UPIO_RM9000) {
574 __raw_writel(value, up->port.membase + 0x08);
575 __raw_writel(value >> 8, up->port.membase + 0x10);
577 _serial_dl_write(up, value);
581 #define serial_dl_read(up) _serial_dl_read(up)
582 #define serial_dl_write(up, value) _serial_dl_write(up, value)
588 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
590 serial_out(up, UART_SCR, offset);
591 serial_out(up, UART_ICR, value);
594 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
598 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
599 serial_out(up, UART_SCR, offset);
600 value = serial_in(up, UART_ICR);
601 serial_icr_write(up, UART_ACR, up->acr);
609 static void serial8250_clear_fifos(struct uart_8250_port *p)
611 if (p->capabilities & UART_CAP_FIFO) {
612 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
613 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
614 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
615 serial_outp(p, UART_FCR, 0);
620 * IER sleep support. UARTs which have EFRs need the "extended
621 * capability" bit enabled. Note that on XR16C850s, we need to
622 * reset LCR to write to IER.
624 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
626 if (p->capabilities & UART_CAP_SLEEP) {
627 if (p->capabilities & UART_CAP_EFR) {
628 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
629 serial_outp(p, UART_EFR, UART_EFR_ECB);
630 serial_outp(p, UART_LCR, 0);
632 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
633 if (p->capabilities & UART_CAP_EFR) {
634 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
635 serial_outp(p, UART_EFR, 0);
636 serial_outp(p, UART_LCR, 0);
641 #ifdef CONFIG_SERIAL_8250_RSA
643 * Attempts to turn on the RSA FIFO. Returns zero on failure.
644 * We set the port uart clock rate if we succeed.
646 static int __enable_rsa(struct uart_8250_port *up)
651 mode = serial_inp(up, UART_RSA_MSR);
652 result = mode & UART_RSA_MSR_FIFO;
655 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
656 mode = serial_inp(up, UART_RSA_MSR);
657 result = mode & UART_RSA_MSR_FIFO;
661 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
666 static void enable_rsa(struct uart_8250_port *up)
668 if (up->port.type == PORT_RSA) {
669 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
670 spin_lock_irq(&up->port.lock);
672 spin_unlock_irq(&up->port.lock);
674 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
675 serial_outp(up, UART_RSA_FRR, 0);
680 * Attempts to turn off the RSA FIFO. Returns zero on failure.
681 * It is unknown why interrupts were disabled in here. However,
682 * the caller is expected to preserve this behaviour by grabbing
683 * the spinlock before calling this function.
685 static void disable_rsa(struct uart_8250_port *up)
690 if (up->port.type == PORT_RSA &&
691 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
692 spin_lock_irq(&up->port.lock);
694 mode = serial_inp(up, UART_RSA_MSR);
695 result = !(mode & UART_RSA_MSR_FIFO);
698 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
699 mode = serial_inp(up, UART_RSA_MSR);
700 result = !(mode & UART_RSA_MSR_FIFO);
704 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
705 spin_unlock_irq(&up->port.lock);
708 #endif /* CONFIG_SERIAL_8250_RSA */
711 * This is a quickie test to see how big the FIFO is.
712 * It doesn't work at all the time, more's the pity.
714 static int size_fifo(struct uart_8250_port *up)
716 unsigned char old_fcr, old_mcr, old_lcr;
717 unsigned short old_dl;
720 old_lcr = serial_inp(up, UART_LCR);
721 serial_outp(up, UART_LCR, 0);
722 old_fcr = serial_inp(up, UART_FCR);
723 old_mcr = serial_inp(up, UART_MCR);
724 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
725 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
726 serial_outp(up, UART_MCR, UART_MCR_LOOP);
727 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
728 old_dl = serial_dl_read(up);
729 serial_dl_write(up, 0x0001);
730 serial_outp(up, UART_LCR, 0x03);
731 for (count = 0; count < 256; count++)
732 serial_outp(up, UART_TX, count);
733 mdelay(20);/* FIXME - schedule_timeout */
734 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
735 (count < 256); count++)
736 serial_inp(up, UART_RX);
737 serial_outp(up, UART_FCR, old_fcr);
738 serial_outp(up, UART_MCR, old_mcr);
739 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
740 serial_dl_write(up, old_dl);
741 serial_outp(up, UART_LCR, old_lcr);
747 * Read UART ID using the divisor method - set DLL and DLM to zero
748 * and the revision will be in DLL and device type in DLM. We
749 * preserve the device state across this.
751 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
753 unsigned char old_dll, old_dlm, old_lcr;
756 old_lcr = serial_inp(p, UART_LCR);
757 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_A);
759 old_dll = serial_inp(p, UART_DLL);
760 old_dlm = serial_inp(p, UART_DLM);
762 serial_outp(p, UART_DLL, 0);
763 serial_outp(p, UART_DLM, 0);
765 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
767 serial_outp(p, UART_DLL, old_dll);
768 serial_outp(p, UART_DLM, old_dlm);
769 serial_outp(p, UART_LCR, old_lcr);
775 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
776 * When this function is called we know it is at least a StarTech
777 * 16650 V2, but it might be one of several StarTech UARTs, or one of
778 * its clones. (We treat the broken original StarTech 16650 V1 as a
779 * 16550, and why not? Startech doesn't seem to even acknowledge its
782 * What evil have men's minds wrought...
784 static void autoconfig_has_efr(struct uart_8250_port *up)
786 unsigned int id1, id2, id3, rev;
789 * Everything with an EFR has SLEEP
791 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
794 * First we check to see if it's an Oxford Semiconductor UART.
796 * If we have to do this here because some non-National
797 * Semiconductor clone chips lock up if you try writing to the
798 * LSR register (which serial_icr_read does)
802 * Check for Oxford Semiconductor 16C950.
804 * EFR [4] must be set else this test fails.
806 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
807 * claims that it's needed for 952 dual UART's (which are not
808 * recommended for new designs).
811 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
812 serial_out(up, UART_EFR, UART_EFR_ECB);
813 serial_out(up, UART_LCR, 0x00);
814 id1 = serial_icr_read(up, UART_ID1);
815 id2 = serial_icr_read(up, UART_ID2);
816 id3 = serial_icr_read(up, UART_ID3);
817 rev = serial_icr_read(up, UART_REV);
819 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
821 if (id1 == 0x16 && id2 == 0xC9 &&
822 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
823 up->port.type = PORT_16C950;
826 * Enable work around for the Oxford Semiconductor 952 rev B
827 * chip which causes it to seriously miscalculate baud rates
830 if (id3 == 0x52 && rev == 0x01)
831 up->bugs |= UART_BUG_QUOT;
836 * We check for a XR16C850 by setting DLL and DLM to 0, and then
837 * reading back DLL and DLM. The chip type depends on the DLM
839 * 0x10 - XR16C850 and the DLL contains the chip revision.
843 id1 = autoconfig_read_divisor_id(up);
844 DEBUG_AUTOCONF("850id=%04x ", id1);
847 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
848 up->port.type = PORT_16850;
853 * It wasn't an XR16C850.
855 * We distinguish between the '654 and the '650 by counting
856 * how many bytes are in the FIFO. I'm using this for now,
857 * since that's the technique that was sent to me in the
858 * serial driver update, but I'm not convinced this works.
859 * I've had problems doing this in the past. -TYT
861 if (size_fifo(up) == 64)
862 up->port.type = PORT_16654;
864 up->port.type = PORT_16650V2;
868 * We detected a chip without a FIFO. Only two fall into
869 * this category - the original 8250 and the 16450. The
870 * 16450 has a scratch register (accessible with LCR=0)
872 static void autoconfig_8250(struct uart_8250_port *up)
874 unsigned char scratch, status1, status2;
876 up->port.type = PORT_8250;
878 scratch = serial_in(up, UART_SCR);
879 serial_outp(up, UART_SCR, 0xa5);
880 status1 = serial_in(up, UART_SCR);
881 serial_outp(up, UART_SCR, 0x5a);
882 status2 = serial_in(up, UART_SCR);
883 serial_outp(up, UART_SCR, scratch);
885 if (status1 == 0xa5 && status2 == 0x5a)
886 up->port.type = PORT_16450;
889 static int broken_efr(struct uart_8250_port *up)
892 * Exar ST16C2550 "A2" devices incorrectly detect as
893 * having an EFR, and report an ID of 0x0201. See
894 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
896 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
902 static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)
904 unsigned char status;
906 status = serial_in(up, 0x04); /* EXCR2 */
907 #define PRESL(x) ((x) & 0x30)
908 if (PRESL(status) == 0x10) {
909 /* already in high speed mode */
912 status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
913 status |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
914 serial_outp(up, 0x04, status);
920 * We know that the chip has FIFOs. Does it have an EFR? The
921 * EFR is located in the same register position as the IIR and
922 * we know the top two bits of the IIR are currently set. The
923 * EFR should contain zero. Try to read the EFR.
925 static void autoconfig_16550a(struct uart_8250_port *up)
927 unsigned char status1, status2;
928 unsigned int iersave;
930 up->port.type = PORT_16550A;
931 up->capabilities |= UART_CAP_FIFO;
934 * Check for presence of the EFR when DLAB is set.
935 * Only ST16C650V1 UARTs pass this test.
937 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
938 if (serial_in(up, UART_EFR) == 0) {
939 serial_outp(up, UART_EFR, 0xA8);
940 if (serial_in(up, UART_EFR) != 0) {
941 DEBUG_AUTOCONF("EFRv1 ");
942 up->port.type = PORT_16650;
943 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
945 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
947 serial_outp(up, UART_EFR, 0);
952 * Maybe it requires 0xbf to be written to the LCR.
953 * (other ST16C650V2 UARTs, TI16C752A, etc)
955 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
956 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
957 DEBUG_AUTOCONF("EFRv2 ");
958 autoconfig_has_efr(up);
963 * Check for a National Semiconductor SuperIO chip.
964 * Attempt to switch to bank 2, read the value of the LOOP bit
965 * from EXCR1. Switch back to bank 0, change it in MCR. Then
966 * switch back to bank 2, read it from EXCR1 again and check
967 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
969 serial_outp(up, UART_LCR, 0);
970 status1 = serial_in(up, UART_MCR);
971 serial_outp(up, UART_LCR, 0xE0);
972 status2 = serial_in(up, 0x02); /* EXCR1 */
974 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
975 serial_outp(up, UART_LCR, 0);
976 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
977 serial_outp(up, UART_LCR, 0xE0);
978 status2 = serial_in(up, 0x02); /* EXCR1 */
979 serial_outp(up, UART_LCR, 0);
980 serial_outp(up, UART_MCR, status1);
982 if ((status2 ^ status1) & UART_MCR_LOOP) {
985 serial_outp(up, UART_LCR, 0xE0);
987 quot = serial_dl_read(up);
990 if (ns16550a_goto_highspeed(up))
991 serial_dl_write(up, quot);
993 serial_outp(up, UART_LCR, 0);
995 up->port.uartclk = 921600*16;
996 up->port.type = PORT_NS16550A;
997 up->capabilities |= UART_NATSEMI;
1003 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1004 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1005 * Try setting it with and without DLAB set. Cheap clones
1006 * set bit 5 without DLAB set.
1008 serial_outp(up, UART_LCR, 0);
1009 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1010 status1 = serial_in(up, UART_IIR) >> 5;
1011 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1012 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
1013 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1014 status2 = serial_in(up, UART_IIR) >> 5;
1015 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1016 serial_outp(up, UART_LCR, 0);
1018 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1020 if (status1 == 6 && status2 == 7) {
1021 up->port.type = PORT_16750;
1022 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1027 * Try writing and reading the UART_IER_UUE bit (b6).
1028 * If it works, this is probably one of the Xscale platform's
1030 * We're going to explicitly set the UUE bit to 0 before
1031 * trying to write and read a 1 just to make sure it's not
1032 * already a 1 and maybe locked there before we even start start.
1034 iersave = serial_in(up, UART_IER);
1035 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
1036 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1038 * OK it's in a known zero state, try writing and reading
1039 * without disturbing the current state of the other bits.
1041 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
1042 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1045 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1047 DEBUG_AUTOCONF("Xscale ");
1048 up->port.type = PORT_XSCALE;
1049 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1054 * If we got here we couldn't force the IER_UUE bit to 0.
1055 * Log it and continue.
1057 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1059 serial_outp(up, UART_IER, iersave);
1062 * Exar uarts have EFR in a weird location
1064 if (up->port.flags & UPF_EXAR_EFR) {
1065 up->port.type = PORT_XR17D15X;
1066 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR;
1070 * We distinguish between 16550A and U6 16550A by counting
1071 * how many bytes are in the FIFO.
1073 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1074 up->port.type = PORT_U6_16550A;
1075 up->capabilities |= UART_CAP_AFE;
1080 * This routine is called by rs_init() to initialize a specific serial
1081 * port. It determines what type of UART chip this serial port is
1082 * using: 8250, 16450, 16550, 16550A. The important question is
1083 * whether or not this UART is a 16550A or not, since this will
1084 * determine whether or not we can use its FIFO features or not.
1086 static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1088 unsigned char status1, scratch, scratch2, scratch3;
1089 unsigned char save_lcr, save_mcr;
1090 unsigned long flags;
1092 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
1095 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1096 serial_index(&up->port), up->port.iobase, up->port.membase);
1099 * We really do need global IRQs disabled here - we're going to
1100 * be frobbing the chips IRQ enable register to see if it exists.
1102 spin_lock_irqsave(&up->port.lock, flags);
1104 up->capabilities = 0;
1107 if (!(up->port.flags & UPF_BUGGY_UART)) {
1109 * Do a simple existence test first; if we fail this,
1110 * there's no point trying anything else.
1112 * 0x80 is used as a nonsense port to prevent against
1113 * false positives due to ISA bus float. The
1114 * assumption is that 0x80 is a non-existent port;
1115 * which should be safe since include/asm/io.h also
1116 * makes this assumption.
1118 * Note: this is safe as long as MCR bit 4 is clear
1119 * and the device is in "PC" mode.
1121 scratch = serial_inp(up, UART_IER);
1122 serial_outp(up, UART_IER, 0);
1127 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1128 * 16C754B) allow only to modify them if an EFR bit is set.
1130 scratch2 = serial_inp(up, UART_IER) & 0x0f;
1131 serial_outp(up, UART_IER, 0x0F);
1135 scratch3 = serial_inp(up, UART_IER) & 0x0f;
1136 serial_outp(up, UART_IER, scratch);
1137 if (scratch2 != 0 || scratch3 != 0x0F) {
1139 * We failed; there's nothing here
1141 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1142 scratch2, scratch3);
1147 save_mcr = serial_in(up, UART_MCR);
1148 save_lcr = serial_in(up, UART_LCR);
1151 * Check to see if a UART is really there. Certain broken
1152 * internal modems based on the Rockwell chipset fail this
1153 * test, because they apparently don't implement the loopback
1154 * test mode. So this test is skipped on the COM 1 through
1155 * COM 4 ports. This *should* be safe, since no board
1156 * manufacturer would be stupid enough to design a board
1157 * that conflicts with COM 1-4 --- we hope!
1159 if (!(up->port.flags & UPF_SKIP_TEST)) {
1160 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1161 status1 = serial_inp(up, UART_MSR) & 0xF0;
1162 serial_outp(up, UART_MCR, save_mcr);
1163 if (status1 != 0x90) {
1164 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1171 * We're pretty sure there's a port here. Lets find out what
1172 * type of port it is. The IIR top two bits allows us to find
1173 * out if it's 8250 or 16450, 16550, 16550A or later. This
1174 * determines what we test for next.
1176 * We also initialise the EFR (if any) to zero for later. The
1177 * EFR occupies the same register location as the FCR and IIR.
1179 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1180 serial_outp(up, UART_EFR, 0);
1181 serial_outp(up, UART_LCR, 0);
1183 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1184 scratch = serial_in(up, UART_IIR) >> 6;
1186 DEBUG_AUTOCONF("iir=%d ", scratch);
1190 autoconfig_8250(up);
1193 up->port.type = PORT_UNKNOWN;
1196 up->port.type = PORT_16550;
1199 autoconfig_16550a(up);
1203 #ifdef CONFIG_SERIAL_8250_RSA
1205 * Only probe for RSA ports if we got the region.
1207 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1210 for (i = 0 ; i < probe_rsa_count; ++i) {
1211 if (probe_rsa[i] == up->port.iobase &&
1213 up->port.type = PORT_RSA;
1220 serial_outp(up, UART_LCR, save_lcr);
1222 if (up->capabilities != uart_config[up->port.type].flags) {
1224 "ttyS%d: detected caps %08x should be %08x\n",
1225 serial_index(&up->port), up->capabilities,
1226 uart_config[up->port.type].flags);
1229 up->port.fifosize = uart_config[up->port.type].fifo_size;
1230 up->capabilities = uart_config[up->port.type].flags;
1231 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1233 if (up->port.type == PORT_UNKNOWN)
1239 #ifdef CONFIG_SERIAL_8250_RSA
1240 if (up->port.type == PORT_RSA)
1241 serial_outp(up, UART_RSA_FRR, 0);
1243 serial_outp(up, UART_MCR, save_mcr);
1244 serial8250_clear_fifos(up);
1245 serial_in(up, UART_RX);
1246 if (up->capabilities & UART_CAP_UUE)
1247 serial_outp(up, UART_IER, UART_IER_UUE);
1249 serial_outp(up, UART_IER, 0);
1252 spin_unlock_irqrestore(&up->port.lock, flags);
1253 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1256 static void autoconfig_irq(struct uart_8250_port *up)
1258 unsigned char save_mcr, save_ier;
1259 unsigned char save_ICP = 0;
1260 unsigned int ICP = 0;
1264 if (up->port.flags & UPF_FOURPORT) {
1265 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1266 save_ICP = inb_p(ICP);
1271 /* forget possible initially masked and pending IRQ */
1272 probe_irq_off(probe_irq_on());
1273 save_mcr = serial_inp(up, UART_MCR);
1274 save_ier = serial_inp(up, UART_IER);
1275 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1277 irqs = probe_irq_on();
1278 serial_outp(up, UART_MCR, 0);
1280 if (up->port.flags & UPF_FOURPORT) {
1281 serial_outp(up, UART_MCR,
1282 UART_MCR_DTR | UART_MCR_RTS);
1284 serial_outp(up, UART_MCR,
1285 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1287 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1288 (void)serial_inp(up, UART_LSR);
1289 (void)serial_inp(up, UART_RX);
1290 (void)serial_inp(up, UART_IIR);
1291 (void)serial_inp(up, UART_MSR);
1292 serial_outp(up, UART_TX, 0xFF);
1294 irq = probe_irq_off(irqs);
1296 serial_outp(up, UART_MCR, save_mcr);
1297 serial_outp(up, UART_IER, save_ier);
1299 if (up->port.flags & UPF_FOURPORT)
1300 outb_p(save_ICP, ICP);
1302 up->port.irq = (irq > 0) ? irq : 0;
1305 static inline void __stop_tx(struct uart_8250_port *p)
1307 if (p->ier & UART_IER_THRI) {
1308 p->ier &= ~UART_IER_THRI;
1309 serial_out(p, UART_IER, p->ier);
1313 static void serial8250_stop_tx(struct uart_port *port)
1315 struct uart_8250_port *up =
1316 container_of(port, struct uart_8250_port, port);
1321 * We really want to stop the transmitter from sending.
1323 if (up->port.type == PORT_16C950) {
1324 up->acr |= UART_ACR_TXDIS;
1325 serial_icr_write(up, UART_ACR, up->acr);
1329 static void transmit_chars(struct uart_8250_port *up);
1331 static void serial8250_start_tx(struct uart_port *port)
1333 struct uart_8250_port *up =
1334 container_of(port, struct uart_8250_port, port);
1336 if (!(up->ier & UART_IER_THRI)) {
1337 up->ier |= UART_IER_THRI;
1338 serial_out(up, UART_IER, up->ier);
1340 if (up->bugs & UART_BUG_TXEN) {
1342 lsr = serial_in(up, UART_LSR);
1343 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1344 if ((up->port.type == PORT_RM9000) ?
1345 (lsr & UART_LSR_THRE) :
1346 (lsr & UART_LSR_TEMT))
1352 * Re-enable the transmitter if we disabled it.
1354 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1355 up->acr &= ~UART_ACR_TXDIS;
1356 serial_icr_write(up, UART_ACR, up->acr);
1360 static void serial8250_stop_rx(struct uart_port *port)
1362 struct uart_8250_port *up =
1363 container_of(port, struct uart_8250_port, port);
1365 up->ier &= ~UART_IER_RLSI;
1366 up->port.read_status_mask &= ~UART_LSR_DR;
1367 serial_out(up, UART_IER, up->ier);
1370 static void serial8250_enable_ms(struct uart_port *port)
1372 struct uart_8250_port *up =
1373 container_of(port, struct uart_8250_port, port);
1375 /* no MSR capabilities */
1376 if (up->bugs & UART_BUG_NOMSR)
1379 up->ier |= UART_IER_MSI;
1380 serial_out(up, UART_IER, up->ier);
1384 * Clear the Tegra rx fifo after a break
1386 * FIXME: This needs to become a port specific callback once we have a
1387 * framework for this
1389 static void clear_rx_fifo(struct uart_8250_port *up)
1391 unsigned int status, tmout = 10000;
1393 status = serial_in(up, UART_LSR);
1394 if (status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS))
1395 status = serial_in(up, UART_RX);
1405 receive_chars(struct uart_8250_port *up, unsigned int *status)
1407 struct tty_struct *tty = up->port.state->port.tty;
1408 unsigned char ch, lsr = *status;
1409 int max_count = 256;
1413 if (likely(lsr & UART_LSR_DR))
1414 ch = serial_inp(up, UART_RX);
1417 * Intel 82571 has a Serial Over Lan device that will
1418 * set UART_LSR_BI without setting UART_LSR_DR when
1419 * it receives a break. To avoid reading from the
1420 * receive buffer without UART_LSR_DR bit set, we
1421 * just force the read character to be 0
1426 up->port.icount.rx++;
1428 lsr |= up->lsr_saved_flags;
1429 up->lsr_saved_flags = 0;
1431 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1433 * For statistics only
1435 if (lsr & UART_LSR_BI) {
1436 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1437 up->port.icount.brk++;
1439 * If tegra port then clear the rx fifo to
1440 * accept another break/character.
1442 if (up->port.type == PORT_TEGRA)
1446 * We do the SysRQ and SAK checking
1447 * here because otherwise the break
1448 * may get masked by ignore_status_mask
1449 * or read_status_mask.
1451 if (uart_handle_break(&up->port))
1453 } else if (lsr & UART_LSR_PE)
1454 up->port.icount.parity++;
1455 else if (lsr & UART_LSR_FE)
1456 up->port.icount.frame++;
1457 if (lsr & UART_LSR_OE)
1458 up->port.icount.overrun++;
1461 * Mask off conditions which should be ignored.
1463 lsr &= up->port.read_status_mask;
1465 if (lsr & UART_LSR_BI) {
1466 DEBUG_INTR("handling break....");
1468 } else if (lsr & UART_LSR_PE)
1470 else if (lsr & UART_LSR_FE)
1473 if (uart_handle_sysrq_char(&up->port, ch))
1476 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1479 lsr = serial_inp(up, UART_LSR);
1480 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1481 spin_unlock(&up->port.lock);
1482 tty_flip_buffer_push(tty);
1483 spin_lock(&up->port.lock);
1487 static void transmit_chars(struct uart_8250_port *up)
1489 struct circ_buf *xmit = &up->port.state->xmit;
1492 if (up->port.x_char) {
1493 serial_outp(up, UART_TX, up->port.x_char);
1494 up->port.icount.tx++;
1495 up->port.x_char = 0;
1498 if (uart_tx_stopped(&up->port)) {
1499 serial8250_stop_tx(&up->port);
1502 if (uart_circ_empty(xmit)) {
1507 count = up->tx_loadsz;
1509 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1510 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1511 up->port.icount.tx++;
1512 if (uart_circ_empty(xmit))
1514 } while (--count > 0);
1516 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1517 uart_write_wakeup(&up->port);
1519 DEBUG_INTR("THRE...");
1521 if (uart_circ_empty(xmit))
1525 static unsigned int check_modem_status(struct uart_8250_port *up)
1527 unsigned int status = serial_in(up, UART_MSR);
1529 status |= up->msr_saved_flags;
1530 up->msr_saved_flags = 0;
1531 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1532 up->port.state != NULL) {
1533 if (status & UART_MSR_TERI)
1534 up->port.icount.rng++;
1535 if (status & UART_MSR_DDSR)
1536 up->port.icount.dsr++;
1537 if (status & UART_MSR_DDCD)
1538 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1539 if (status & UART_MSR_DCTS)
1540 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1542 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
1549 * This handles the interrupt from one port.
1551 static void serial8250_handle_port(struct uart_8250_port *up)
1553 unsigned int status;
1554 unsigned long flags;
1556 spin_lock_irqsave(&up->port.lock, flags);
1558 status = serial_inp(up, UART_LSR);
1560 DEBUG_INTR("status = %x...", status);
1562 if (status & (UART_LSR_DR | UART_LSR_BI))
1563 receive_chars(up, &status);
1564 check_modem_status(up);
1565 if (status & UART_LSR_THRE)
1568 spin_unlock_irqrestore(&up->port.lock, flags);
1571 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1573 struct uart_8250_port *up =
1574 container_of(port, struct uart_8250_port, port);
1576 if (!(iir & UART_IIR_NO_INT)) {
1577 serial8250_handle_port(up);
1583 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1585 static int serial8250_default_handle_irq(struct uart_port *port)
1587 struct uart_8250_port *up =
1588 container_of(port, struct uart_8250_port, port);
1589 unsigned int iir = serial_in(up, UART_IIR);
1591 return serial8250_handle_irq(port, iir);
1595 * This is the serial driver's interrupt routine.
1597 * Arjan thinks the old way was overly complex, so it got simplified.
1598 * Alan disagrees, saying that need the complexity to handle the weird
1599 * nature of ISA shared interrupts. (This is a special exception.)
1601 * In order to handle ISA shared interrupts properly, we need to check
1602 * that all ports have been serviced, and therefore the ISA interrupt
1603 * line has been de-asserted.
1605 * This means we need to loop through all ports. checking that they
1606 * don't have an interrupt pending.
1608 static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1610 struct irq_info *i = dev_id;
1611 struct list_head *l, *end = NULL;
1612 int pass_counter = 0, handled = 0;
1614 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1616 spin_lock(&i->lock);
1620 struct uart_8250_port *up;
1621 struct uart_port *port;
1624 up = list_entry(l, struct uart_8250_port, list);
1626 skip = pass_counter && up->port.flags & UPF_IIR_ONCE;
1628 if (!skip && port->handle_irq(port)) {
1631 } else if (end == NULL)
1636 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1637 /* If we hit this, we're dead. */
1638 printk_ratelimited(KERN_ERR
1639 "serial8250: too much work for irq%d\n", irq);
1644 spin_unlock(&i->lock);
1646 DEBUG_INTR("end.\n");
1648 return IRQ_RETVAL(handled);
1652 * To support ISA shared interrupts, we need to have one interrupt
1653 * handler that ensures that the IRQ line has been deasserted
1654 * before returning. Failing to do this will result in the IRQ
1655 * line being stuck active, and, since ISA irqs are edge triggered,
1656 * no more IRQs will be seen.
1658 static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1660 spin_lock_irq(&i->lock);
1662 if (!list_empty(i->head)) {
1663 if (i->head == &up->list)
1664 i->head = i->head->next;
1665 list_del(&up->list);
1667 BUG_ON(i->head != &up->list);
1670 spin_unlock_irq(&i->lock);
1671 /* List empty so throw away the hash node */
1672 if (i->head == NULL) {
1673 hlist_del(&i->node);
1678 static int serial_link_irq_chain(struct uart_8250_port *up)
1680 struct hlist_head *h;
1681 struct hlist_node *n;
1683 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1685 mutex_lock(&hash_mutex);
1687 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1689 hlist_for_each(n, h) {
1690 i = hlist_entry(n, struct irq_info, node);
1691 if (i->irq == up->port.irq)
1696 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1698 mutex_unlock(&hash_mutex);
1701 spin_lock_init(&i->lock);
1702 i->irq = up->port.irq;
1703 hlist_add_head(&i->node, h);
1705 mutex_unlock(&hash_mutex);
1707 spin_lock_irq(&i->lock);
1710 list_add(&up->list, i->head);
1711 spin_unlock_irq(&i->lock);
1715 INIT_LIST_HEAD(&up->list);
1716 i->head = &up->list;
1717 spin_unlock_irq(&i->lock);
1718 irq_flags |= up->port.irqflags;
1719 ret = request_irq(up->port.irq, serial8250_interrupt,
1720 irq_flags, "serial", i);
1722 serial_do_unlink(i, up);
1728 static void serial_unlink_irq_chain(struct uart_8250_port *up)
1731 struct hlist_node *n;
1732 struct hlist_head *h;
1734 mutex_lock(&hash_mutex);
1736 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1738 hlist_for_each(n, h) {
1739 i = hlist_entry(n, struct irq_info, node);
1740 if (i->irq == up->port.irq)
1745 BUG_ON(i->head == NULL);
1747 if (list_empty(i->head))
1748 free_irq(up->port.irq, i);
1750 serial_do_unlink(i, up);
1751 mutex_unlock(&hash_mutex);
1755 * This function is used to handle ports that do not have an
1756 * interrupt. This doesn't work very well for 16450's, but gives
1757 * barely passable results for a 16550A. (Although at the expense
1758 * of much CPU overhead).
1760 static void serial8250_timeout(unsigned long data)
1762 struct uart_8250_port *up = (struct uart_8250_port *)data;
1765 iir = serial_in(up, UART_IIR);
1766 if (!(iir & UART_IIR_NO_INT))
1767 serial8250_handle_port(up);
1768 mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
1771 static void serial8250_backup_timeout(unsigned long data)
1773 struct uart_8250_port *up = (struct uart_8250_port *)data;
1774 unsigned int iir, ier = 0, lsr;
1775 unsigned long flags;
1777 spin_lock_irqsave(&up->port.lock, flags);
1780 * Must disable interrupts or else we risk racing with the interrupt
1783 if (is_real_interrupt(up->port.irq)) {
1784 ier = serial_in(up, UART_IER);
1785 serial_out(up, UART_IER, 0);
1788 iir = serial_in(up, UART_IIR);
1791 * This should be a safe test for anyone who doesn't trust the
1792 * IIR bits on their UART, but it's specifically designed for
1793 * the "Diva" UART used on the management processor on many HP
1794 * ia64 and parisc boxes.
1796 lsr = serial_in(up, UART_LSR);
1797 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1798 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1799 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
1800 (lsr & UART_LSR_THRE)) {
1801 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1802 iir |= UART_IIR_THRI;
1805 if (!(iir & UART_IIR_NO_INT))
1808 if (is_real_interrupt(up->port.irq))
1809 serial_out(up, UART_IER, ier);
1811 spin_unlock_irqrestore(&up->port.lock, flags);
1813 /* Standard timer interval plus 0.2s to keep the port running */
1814 mod_timer(&up->timer,
1815 jiffies + uart_poll_timeout(&up->port) + HZ / 5);
1818 static unsigned int serial8250_tx_empty(struct uart_port *port)
1820 struct uart_8250_port *up =
1821 container_of(port, struct uart_8250_port, port);
1822 unsigned long flags;
1825 spin_lock_irqsave(&up->port.lock, flags);
1826 lsr = serial_in(up, UART_LSR);
1827 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1828 spin_unlock_irqrestore(&up->port.lock, flags);
1830 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1833 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1835 struct uart_8250_port *up =
1836 container_of(port, struct uart_8250_port, port);
1837 unsigned int status;
1840 status = check_modem_status(up);
1843 if (status & UART_MSR_DCD)
1845 if (status & UART_MSR_RI)
1847 if (status & UART_MSR_DSR)
1849 if (status & UART_MSR_CTS)
1854 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1856 struct uart_8250_port *up =
1857 container_of(port, struct uart_8250_port, port);
1858 unsigned char mcr = 0;
1860 if (mctrl & TIOCM_RTS)
1861 mcr |= UART_MCR_RTS;
1862 if (mctrl & TIOCM_DTR)
1863 mcr |= UART_MCR_DTR;
1864 if (mctrl & TIOCM_OUT1)
1865 mcr |= UART_MCR_OUT1;
1866 if (mctrl & TIOCM_OUT2)
1867 mcr |= UART_MCR_OUT2;
1868 if (mctrl & TIOCM_LOOP)
1869 mcr |= UART_MCR_LOOP;
1871 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1873 serial_out(up, UART_MCR, mcr);
1876 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1878 struct uart_8250_port *up =
1879 container_of(port, struct uart_8250_port, port);
1880 unsigned long flags;
1882 spin_lock_irqsave(&up->port.lock, flags);
1883 if (break_state == -1)
1884 up->lcr |= UART_LCR_SBC;
1886 up->lcr &= ~UART_LCR_SBC;
1887 serial_out(up, UART_LCR, up->lcr);
1888 spin_unlock_irqrestore(&up->port.lock, flags);
1892 * Wait for transmitter & holding register to empty
1894 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1896 unsigned int status, tmout = 10000;
1898 /* Wait up to 10ms for the character(s) to be sent. */
1900 status = serial_in(up, UART_LSR);
1902 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1904 if ((status & bits) == bits)
1911 /* Wait up to 1s for flow control if necessary */
1912 if (up->port.flags & UPF_CONS_FLOW) {
1914 for (tmout = 1000000; tmout; tmout--) {
1915 unsigned int msr = serial_in(up, UART_MSR);
1916 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1917 if (msr & UART_MSR_CTS)
1920 touch_nmi_watchdog();
1925 #ifdef CONFIG_CONSOLE_POLL
1927 * Console polling routines for writing and reading from the uart while
1928 * in an interrupt or debug context.
1931 static int serial8250_get_poll_char(struct uart_port *port)
1933 struct uart_8250_port *up =
1934 container_of(port, struct uart_8250_port, port);
1935 unsigned char lsr = serial_inp(up, UART_LSR);
1937 if (!(lsr & UART_LSR_DR))
1938 return NO_POLL_CHAR;
1940 return serial_inp(up, UART_RX);
1944 static void serial8250_put_poll_char(struct uart_port *port,
1948 struct uart_8250_port *up =
1949 container_of(port, struct uart_8250_port, port);
1952 * First save the IER then disable the interrupts
1954 ier = serial_in(up, UART_IER);
1955 if (up->capabilities & UART_CAP_UUE)
1956 serial_out(up, UART_IER, UART_IER_UUE);
1958 serial_out(up, UART_IER, 0);
1960 wait_for_xmitr(up, BOTH_EMPTY);
1962 * Send the character out.
1963 * If a LF, also do CR...
1965 serial_out(up, UART_TX, c);
1967 wait_for_xmitr(up, BOTH_EMPTY);
1968 serial_out(up, UART_TX, 13);
1972 * Finally, wait for transmitter to become empty
1973 * and restore the IER
1975 wait_for_xmitr(up, BOTH_EMPTY);
1976 serial_out(up, UART_IER, ier);
1979 #endif /* CONFIG_CONSOLE_POLL */
1981 static int serial8250_startup(struct uart_port *port)
1983 struct uart_8250_port *up =
1984 container_of(port, struct uart_8250_port, port);
1985 unsigned long flags;
1986 unsigned char lsr, iir;
1989 up->port.fifosize = uart_config[up->port.type].fifo_size;
1990 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1991 up->capabilities = uart_config[up->port.type].flags;
1994 if (up->port.iotype != up->cur_iotype)
1995 set_io_from_upio(port);
1997 if (up->port.type == PORT_16C950) {
1998 /* Wake up and initialize UART */
2000 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
2001 serial_outp(up, UART_EFR, UART_EFR_ECB);
2002 serial_outp(up, UART_IER, 0);
2003 serial_outp(up, UART_LCR, 0);
2004 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2005 serial_outp(up, UART_LCR, 0xBF);
2006 serial_outp(up, UART_EFR, UART_EFR_ECB);
2007 serial_outp(up, UART_LCR, 0);
2010 #ifdef CONFIG_SERIAL_8250_RSA
2012 * If this is an RSA port, see if we can kick it up to the
2013 * higher speed clock.
2019 * Clear the FIFO buffers and disable them.
2020 * (they will be reenabled in set_termios())
2022 serial8250_clear_fifos(up);
2025 * Clear the interrupt registers.
2027 (void) serial_inp(up, UART_LSR);
2028 (void) serial_inp(up, UART_RX);
2029 (void) serial_inp(up, UART_IIR);
2030 (void) serial_inp(up, UART_MSR);
2033 * At this point, there's no way the LSR could still be 0xff;
2034 * if it is, then bail out, because there's likely no UART
2037 if (!(up->port.flags & UPF_BUGGY_UART) &&
2038 (serial_inp(up, UART_LSR) == 0xff)) {
2039 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
2040 serial_index(&up->port));
2045 * For a XR16C850, we need to set the trigger levels
2047 if (up->port.type == PORT_16850) {
2050 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
2052 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2053 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2054 serial_outp(up, UART_TRG, UART_TRG_96);
2055 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2056 serial_outp(up, UART_TRG, UART_TRG_96);
2058 serial_outp(up, UART_LCR, 0);
2061 if (is_real_interrupt(up->port.irq)) {
2064 * Test for UARTs that do not reassert THRE when the
2065 * transmitter is idle and the interrupt has already
2066 * been cleared. Real 16550s should always reassert
2067 * this interrupt whenever the transmitter is idle and
2068 * the interrupt is enabled. Delays are necessary to
2069 * allow register changes to become visible.
2071 spin_lock_irqsave(&up->port.lock, flags);
2072 if (up->port.irqflags & IRQF_SHARED)
2073 disable_irq_nosync(up->port.irq);
2075 wait_for_xmitr(up, UART_LSR_THRE);
2076 serial_out_sync(up, UART_IER, UART_IER_THRI);
2077 udelay(1); /* allow THRE to set */
2078 iir1 = serial_in(up, UART_IIR);
2079 serial_out(up, UART_IER, 0);
2080 serial_out_sync(up, UART_IER, UART_IER_THRI);
2081 udelay(1); /* allow a working UART time to re-assert THRE */
2082 iir = serial_in(up, UART_IIR);
2083 serial_out(up, UART_IER, 0);
2085 if (up->port.irqflags & IRQF_SHARED)
2086 enable_irq(up->port.irq);
2087 spin_unlock_irqrestore(&up->port.lock, flags);
2090 * If the interrupt is not reasserted, setup a timer to
2091 * kick the UART on a regular basis.
2093 if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) {
2094 up->bugs |= UART_BUG_THRE;
2095 pr_debug("ttyS%d - using backup timer\n",
2096 serial_index(port));
2101 * The above check will only give an accurate result the first time
2102 * the port is opened so this value needs to be preserved.
2104 if (up->bugs & UART_BUG_THRE) {
2105 up->timer.function = serial8250_backup_timeout;
2106 up->timer.data = (unsigned long)up;
2107 mod_timer(&up->timer, jiffies +
2108 uart_poll_timeout(port) + HZ / 5);
2112 * If the "interrupt" for this port doesn't correspond with any
2113 * hardware interrupt, we use a timer-based system. The original
2114 * driver used to do this with IRQ0.
2116 if (!is_real_interrupt(up->port.irq)) {
2117 up->timer.data = (unsigned long)up;
2118 mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
2120 retval = serial_link_irq_chain(up);
2126 * Now, initialize the UART
2128 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
2130 spin_lock_irqsave(&up->port.lock, flags);
2131 if (up->port.flags & UPF_FOURPORT) {
2132 if (!is_real_interrupt(up->port.irq))
2133 up->port.mctrl |= TIOCM_OUT1;
2136 * Most PC uarts need OUT2 raised to enable interrupts.
2138 if (is_real_interrupt(up->port.irq))
2139 up->port.mctrl |= TIOCM_OUT2;
2141 serial8250_set_mctrl(&up->port, up->port.mctrl);
2143 /* Serial over Lan (SoL) hack:
2144 Intel 8257x Gigabit ethernet chips have a
2145 16550 emulation, to be used for Serial Over Lan.
2146 Those chips take a longer time than a normal
2147 serial device to signalize that a transmission
2148 data was queued. Due to that, the above test generally
2149 fails. One solution would be to delay the reading of
2150 iir. However, this is not reliable, since the timeout
2151 is variable. So, let's just don't test if we receive
2152 TX irq. This way, we'll never enable UART_BUG_TXEN.
2154 if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
2155 goto dont_test_tx_en;
2158 * Do a quick test to see if we receive an
2159 * interrupt when we enable the TX irq.
2161 serial_outp(up, UART_IER, UART_IER_THRI);
2162 lsr = serial_in(up, UART_LSR);
2163 iir = serial_in(up, UART_IIR);
2164 serial_outp(up, UART_IER, 0);
2166 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2167 if (!(up->bugs & UART_BUG_TXEN)) {
2168 up->bugs |= UART_BUG_TXEN;
2169 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2170 serial_index(port));
2173 up->bugs &= ~UART_BUG_TXEN;
2177 spin_unlock_irqrestore(&up->port.lock, flags);
2180 * Clear the interrupt registers again for luck, and clear the
2181 * saved flags to avoid getting false values from polling
2182 * routines or the previous session.
2184 serial_inp(up, UART_LSR);
2185 serial_inp(up, UART_RX);
2186 serial_inp(up, UART_IIR);
2187 serial_inp(up, UART_MSR);
2188 up->lsr_saved_flags = 0;
2189 up->msr_saved_flags = 0;
2192 * Finally, enable interrupts. Note: Modem status interrupts
2193 * are set via set_termios(), which will be occurring imminently
2194 * anyway, so we don't enable them here.
2196 up->ier = UART_IER_RLSI | UART_IER_RDI;
2197 serial_outp(up, UART_IER, up->ier);
2199 if (up->port.flags & UPF_FOURPORT) {
2202 * Enable interrupts on the AST Fourport board
2204 icp = (up->port.iobase & 0xfe0) | 0x01f;
2212 static void serial8250_shutdown(struct uart_port *port)
2214 struct uart_8250_port *up =
2215 container_of(port, struct uart_8250_port, port);
2216 unsigned long flags;
2219 * Disable interrupts from this port
2222 serial_outp(up, UART_IER, 0);
2224 spin_lock_irqsave(&up->port.lock, flags);
2225 if (up->port.flags & UPF_FOURPORT) {
2226 /* reset interrupts on the AST Fourport board */
2227 inb((up->port.iobase & 0xfe0) | 0x1f);
2228 up->port.mctrl |= TIOCM_OUT1;
2230 up->port.mctrl &= ~TIOCM_OUT2;
2232 serial8250_set_mctrl(&up->port, up->port.mctrl);
2233 spin_unlock_irqrestore(&up->port.lock, flags);
2236 * Disable break condition and FIFOs
2238 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
2239 serial8250_clear_fifos(up);
2241 #ifdef CONFIG_SERIAL_8250_RSA
2243 * Reset the RSA board back to 115kbps compat mode.
2249 * Read data port to reset things, and then unlink from
2252 (void) serial_in(up, UART_RX);
2254 del_timer_sync(&up->timer);
2255 up->timer.function = serial8250_timeout;
2256 if (is_real_interrupt(up->port.irq))
2257 serial_unlink_irq_chain(up);
2260 static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2265 * Handle magic divisors for baud rates above baud_base on
2266 * SMSC SuperIO chips.
2268 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2269 baud == (port->uartclk/4))
2271 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2272 baud == (port->uartclk/8))
2275 quot = uart_get_divisor(port, baud);
2281 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2282 struct ktermios *old)
2284 struct uart_8250_port *up =
2285 container_of(port, struct uart_8250_port, port);
2286 unsigned char cval, fcr = 0;
2287 unsigned long flags;
2288 unsigned int baud, quot;
2290 switch (termios->c_cflag & CSIZE) {
2292 cval = UART_LCR_WLEN5;
2295 cval = UART_LCR_WLEN6;
2298 cval = UART_LCR_WLEN7;
2302 cval = UART_LCR_WLEN8;
2306 if (termios->c_cflag & CSTOPB)
2307 cval |= UART_LCR_STOP;
2308 if (termios->c_cflag & PARENB)
2309 cval |= UART_LCR_PARITY;
2310 if (!(termios->c_cflag & PARODD))
2311 cval |= UART_LCR_EPAR;
2313 if (termios->c_cflag & CMSPAR)
2314 cval |= UART_LCR_SPAR;
2318 * Ask the core to calculate the divisor for us.
2320 baud = uart_get_baud_rate(port, termios, old,
2321 port->uartclk / 16 / 0xffff,
2322 port->uartclk / 16);
2323 quot = serial8250_get_divisor(port, baud);
2326 * Oxford Semi 952 rev B workaround
2328 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2331 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
2333 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
2335 fcr = uart_config[up->port.type].fcr;
2339 * MCR-based auto flow control. When AFE is enabled, RTS will be
2340 * deasserted when the receive FIFO contains more characters than
2341 * the trigger, or the MCR RTS bit is cleared. In the case where
2342 * the remote UART is not using CTS auto flow control, we must
2343 * have sufficient FIFO entries for the latency of the remote
2344 * UART to respond. IOW, at least 32 bytes of FIFO.
2346 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
2347 up->mcr &= ~UART_MCR_AFE;
2348 if (termios->c_cflag & CRTSCTS)
2349 up->mcr |= UART_MCR_AFE;
2353 * Ok, we're now changing the port state. Do it with
2354 * interrupts disabled.
2356 spin_lock_irqsave(&up->port.lock, flags);
2359 * Update the per-port timeout.
2361 uart_update_timeout(port, termios->c_cflag, baud);
2363 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2364 if (termios->c_iflag & INPCK)
2365 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2366 if (termios->c_iflag & (BRKINT | PARMRK))
2367 up->port.read_status_mask |= UART_LSR_BI;
2370 * Characteres to ignore
2372 up->port.ignore_status_mask = 0;
2373 if (termios->c_iflag & IGNPAR)
2374 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2375 if (termios->c_iflag & IGNBRK) {
2376 up->port.ignore_status_mask |= UART_LSR_BI;
2378 * If we're ignoring parity and break indicators,
2379 * ignore overruns too (for real raw support).
2381 if (termios->c_iflag & IGNPAR)
2382 up->port.ignore_status_mask |= UART_LSR_OE;
2386 * ignore all characters if CREAD is not set
2388 if ((termios->c_cflag & CREAD) == 0)
2389 up->port.ignore_status_mask |= UART_LSR_DR;
2392 * CTS flow control flag and modem status interrupts
2394 up->ier &= ~UART_IER_MSI;
2395 if (!(up->bugs & UART_BUG_NOMSR) &&
2396 UART_ENABLE_MS(&up->port, termios->c_cflag))
2397 up->ier |= UART_IER_MSI;
2398 if (up->capabilities & UART_CAP_UUE)
2399 up->ier |= UART_IER_UUE;
2400 if (up->capabilities & UART_CAP_RTOIE)
2401 up->ier |= UART_IER_RTOIE;
2403 serial_out(up, UART_IER, up->ier);
2405 if (up->capabilities & UART_CAP_EFR) {
2406 unsigned char efr = 0;
2408 * TI16C752/Startech hardware flow control. FIXME:
2409 * - TI16C752 requires control thresholds to be set.
2410 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2412 if (termios->c_cflag & CRTSCTS)
2413 efr |= UART_EFR_CTS;
2415 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
2416 if (up->port.flags & UPF_EXAR_EFR)
2417 serial_outp(up, UART_XR_EFR, efr);
2419 serial_outp(up, UART_EFR, efr);
2422 #ifdef CONFIG_ARCH_OMAP
2423 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2424 if (cpu_is_omap1510() && is_omap_port(up)) {
2425 if (baud == 115200) {
2427 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2429 serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2433 if (up->capabilities & UART_NATSEMI) {
2434 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2435 serial_outp(up, UART_LCR, 0xe0);
2437 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
2440 serial_dl_write(up, quot);
2443 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2444 * is written without DLAB set, this mode will be disabled.
2446 if (up->port.type == PORT_16750)
2447 serial_outp(up, UART_FCR, fcr);
2449 serial_outp(up, UART_LCR, cval); /* reset DLAB */
2450 up->lcr = cval; /* Save LCR */
2451 if (up->port.type != PORT_16750) {
2452 if (fcr & UART_FCR_ENABLE_FIFO) {
2453 /* emulated UARTs (Lucent Venus 167x) need two steps */
2454 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2456 serial_outp(up, UART_FCR, fcr); /* set fcr */
2458 serial8250_set_mctrl(&up->port, up->port.mctrl);
2459 spin_unlock_irqrestore(&up->port.lock, flags);
2460 /* Don't rewrite B0 */
2461 if (tty_termios_baud_rate(termios))
2462 tty_termios_encode_baud_rate(termios, baud, baud);
2464 EXPORT_SYMBOL(serial8250_do_set_termios);
2467 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2468 struct ktermios *old)
2470 if (port->set_termios)
2471 port->set_termios(port, termios, old);
2473 serial8250_do_set_termios(port, termios, old);
2477 serial8250_set_ldisc(struct uart_port *port, int new)
2480 port->flags |= UPF_HARDPPS_CD;
2481 serial8250_enable_ms(port);
2483 port->flags &= ~UPF_HARDPPS_CD;
2487 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2488 unsigned int oldstate)
2490 struct uart_8250_port *p =
2491 container_of(port, struct uart_8250_port, port);
2493 serial8250_set_sleep(p, state != 0);
2495 EXPORT_SYMBOL(serial8250_do_pm);
2498 serial8250_pm(struct uart_port *port, unsigned int state,
2499 unsigned int oldstate)
2502 port->pm(port, state, oldstate);
2504 serial8250_do_pm(port, state, oldstate);
2507 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2509 if (pt->port.iotype == UPIO_AU)
2511 #ifdef CONFIG_ARCH_OMAP
2512 if (is_omap_port(pt))
2513 return 0x16 << pt->port.regshift;
2515 return 8 << pt->port.regshift;
2519 * Resource handling.
2521 static int serial8250_request_std_resource(struct uart_8250_port *up)
2523 unsigned int size = serial8250_port_size(up);
2526 switch (up->port.iotype) {
2531 if (!up->port.mapbase)
2534 if (!request_mem_region(up->port.mapbase, size, "serial")) {
2539 if (up->port.flags & UPF_IOREMAP) {
2540 up->port.membase = ioremap_nocache(up->port.mapbase,
2542 if (!up->port.membase) {
2543 release_mem_region(up->port.mapbase, size);
2551 if (!request_region(up->port.iobase, size, "serial"))
2558 static void serial8250_release_std_resource(struct uart_8250_port *up)
2560 unsigned int size = serial8250_port_size(up);
2562 switch (up->port.iotype) {
2567 if (!up->port.mapbase)
2570 if (up->port.flags & UPF_IOREMAP) {
2571 iounmap(up->port.membase);
2572 up->port.membase = NULL;
2575 release_mem_region(up->port.mapbase, size);
2580 release_region(up->port.iobase, size);
2585 static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2587 unsigned long start = UART_RSA_BASE << up->port.regshift;
2588 unsigned int size = 8 << up->port.regshift;
2591 switch (up->port.iotype) {
2594 start += up->port.iobase;
2595 if (request_region(start, size, "serial-rsa"))
2605 static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2607 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2608 unsigned int size = 8 << up->port.regshift;
2610 switch (up->port.iotype) {
2613 release_region(up->port.iobase + offset, size);
2618 static void serial8250_release_port(struct uart_port *port)
2620 struct uart_8250_port *up =
2621 container_of(port, struct uart_8250_port, port);
2623 serial8250_release_std_resource(up);
2624 if (up->port.type == PORT_RSA)
2625 serial8250_release_rsa_resource(up);
2628 static int serial8250_request_port(struct uart_port *port)
2630 struct uart_8250_port *up =
2631 container_of(port, struct uart_8250_port, port);
2634 ret = serial8250_request_std_resource(up);
2635 if (ret == 0 && up->port.type == PORT_RSA) {
2636 ret = serial8250_request_rsa_resource(up);
2638 serial8250_release_std_resource(up);
2644 static void serial8250_config_port(struct uart_port *port, int flags)
2646 struct uart_8250_port *up =
2647 container_of(port, struct uart_8250_port, port);
2648 int probeflags = PROBE_ANY;
2652 * Find the region that we can probe for. This in turn
2653 * tells us whether we can probe for the type of port.
2655 ret = serial8250_request_std_resource(up);
2659 ret = serial8250_request_rsa_resource(up);
2661 probeflags &= ~PROBE_RSA;
2663 if (up->port.iotype != up->cur_iotype)
2664 set_io_from_upio(port);
2666 if (flags & UART_CONFIG_TYPE)
2667 autoconfig(up, probeflags);
2669 /* if access method is AU, it is a 16550 with a quirk */
2670 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
2671 up->bugs |= UART_BUG_NOMSR;
2673 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2676 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2677 serial8250_release_rsa_resource(up);
2678 if (up->port.type == PORT_UNKNOWN)
2679 serial8250_release_std_resource(up);
2683 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2685 if (ser->irq >= nr_irqs || ser->irq < 0 ||
2686 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2687 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2688 ser->type == PORT_STARTECH)
2694 serial8250_type(struct uart_port *port)
2696 int type = port->type;
2698 if (type >= ARRAY_SIZE(uart_config))
2700 return uart_config[type].name;
2703 static struct uart_ops serial8250_pops = {
2704 .tx_empty = serial8250_tx_empty,
2705 .set_mctrl = serial8250_set_mctrl,
2706 .get_mctrl = serial8250_get_mctrl,
2707 .stop_tx = serial8250_stop_tx,
2708 .start_tx = serial8250_start_tx,
2709 .stop_rx = serial8250_stop_rx,
2710 .enable_ms = serial8250_enable_ms,
2711 .break_ctl = serial8250_break_ctl,
2712 .startup = serial8250_startup,
2713 .shutdown = serial8250_shutdown,
2714 .set_termios = serial8250_set_termios,
2715 .set_ldisc = serial8250_set_ldisc,
2716 .pm = serial8250_pm,
2717 .type = serial8250_type,
2718 .release_port = serial8250_release_port,
2719 .request_port = serial8250_request_port,
2720 .config_port = serial8250_config_port,
2721 .verify_port = serial8250_verify_port,
2722 #ifdef CONFIG_CONSOLE_POLL
2723 .poll_get_char = serial8250_get_poll_char,
2724 .poll_put_char = serial8250_put_poll_char,
2728 static struct uart_8250_port serial8250_ports[UART_NR];
2730 static void (*serial8250_isa_config)(int port, struct uart_port *up,
2731 unsigned short *capabilities);
2733 void serial8250_set_isa_configurator(
2734 void (*v)(int port, struct uart_port *up, unsigned short *capabilities))
2736 serial8250_isa_config = v;
2738 EXPORT_SYMBOL(serial8250_set_isa_configurator);
2740 static void __init serial8250_isa_init_ports(void)
2742 struct uart_8250_port *up;
2743 static int first = 1;
2750 for (i = 0; i < nr_uarts; i++) {
2751 struct uart_8250_port *up = &serial8250_ports[i];
2754 spin_lock_init(&up->port.lock);
2756 init_timer(&up->timer);
2757 up->timer.function = serial8250_timeout;
2760 * ALPHA_KLUDGE_MCR needs to be killed.
2762 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2763 up->mcr_force = ALPHA_KLUDGE_MCR;
2765 up->port.ops = &serial8250_pops;
2769 irqflag = IRQF_SHARED;
2771 for (i = 0, up = serial8250_ports;
2772 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2774 up->port.iobase = old_serial_port[i].port;
2775 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2776 up->port.irqflags = old_serial_port[i].irqflags;
2777 up->port.uartclk = old_serial_port[i].baud_base * 16;
2778 up->port.flags = old_serial_port[i].flags;
2779 up->port.hub6 = old_serial_port[i].hub6;
2780 up->port.membase = old_serial_port[i].iomem_base;
2781 up->port.iotype = old_serial_port[i].io_type;
2782 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2783 set_io_from_upio(&up->port);
2784 up->port.irqflags |= irqflag;
2785 if (serial8250_isa_config != NULL)
2786 serial8250_isa_config(i, &up->port, &up->capabilities);
2792 serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2794 up->port.type = type;
2795 up->port.fifosize = uart_config[type].fifo_size;
2796 up->capabilities = uart_config[type].flags;
2797 up->tx_loadsz = uart_config[type].tx_loadsz;
2801 serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2805 for (i = 0; i < nr_uarts; i++) {
2806 struct uart_8250_port *up = &serial8250_ports[i];
2807 up->cur_iotype = 0xFF;
2810 serial8250_isa_init_ports();
2812 for (i = 0; i < nr_uarts; i++) {
2813 struct uart_8250_port *up = &serial8250_ports[i];
2817 if (up->port.flags & UPF_FIXED_TYPE)
2818 serial8250_init_fixed_type_port(up, up->port.type);
2820 uart_add_one_port(drv, &up->port);
2824 #ifdef CONFIG_SERIAL_8250_CONSOLE
2826 static void serial8250_console_putchar(struct uart_port *port, int ch)
2828 struct uart_8250_port *up =
2829 container_of(port, struct uart_8250_port, port);
2831 wait_for_xmitr(up, UART_LSR_THRE);
2832 serial_out(up, UART_TX, ch);
2836 * Print a string to the serial port trying not to disturb
2837 * any possible real use of the port...
2839 * The console_lock must be held when we get here.
2842 serial8250_console_write(struct console *co, const char *s, unsigned int count)
2844 struct uart_8250_port *up = &serial8250_ports[co->index];
2845 unsigned long flags;
2849 touch_nmi_watchdog();
2851 local_irq_save(flags);
2852 if (up->port.sysrq) {
2853 /* serial8250_handle_port() already took the lock */
2855 } else if (oops_in_progress) {
2856 locked = spin_trylock(&up->port.lock);
2858 spin_lock(&up->port.lock);
2861 * First save the IER then disable the interrupts
2863 ier = serial_in(up, UART_IER);
2865 if (up->capabilities & UART_CAP_UUE)
2866 serial_out(up, UART_IER, UART_IER_UUE);
2868 serial_out(up, UART_IER, 0);
2870 uart_console_write(&up->port, s, count, serial8250_console_putchar);
2873 * Finally, wait for transmitter to become empty
2874 * and restore the IER
2876 wait_for_xmitr(up, BOTH_EMPTY);
2877 serial_out(up, UART_IER, ier);
2880 * The receive handling will happen properly because the
2881 * receive ready bit will still be set; it is not cleared
2882 * on read. However, modem control will not, we must
2883 * call it if we have saved something in the saved flags
2884 * while processing with interrupts off.
2886 if (up->msr_saved_flags)
2887 check_modem_status(up);
2890 spin_unlock(&up->port.lock);
2891 local_irq_restore(flags);
2894 static int __init serial8250_console_setup(struct console *co, char *options)
2896 struct uart_port *port;
2903 * Check whether an invalid uart number has been specified, and
2904 * if so, search for the first available port that does have
2907 if (co->index >= nr_uarts)
2909 port = &serial8250_ports[co->index].port;
2910 if (!port->iobase && !port->membase)
2914 uart_parse_options(options, &baud, &parity, &bits, &flow);
2916 return uart_set_options(port, co, baud, parity, bits, flow);
2919 static int serial8250_console_early_setup(void)
2921 return serial8250_find_port_for_earlycon();
2924 static struct console serial8250_console = {
2926 .write = serial8250_console_write,
2927 .device = uart_console_device,
2928 .setup = serial8250_console_setup,
2929 .early_setup = serial8250_console_early_setup,
2930 .flags = CON_PRINTBUFFER | CON_ANYTIME,
2932 .data = &serial8250_reg,
2935 static int __init serial8250_console_init(void)
2937 if (nr_uarts > UART_NR)
2940 serial8250_isa_init_ports();
2941 register_console(&serial8250_console);
2944 console_initcall(serial8250_console_init);
2946 int serial8250_find_port(struct uart_port *p)
2949 struct uart_port *port;
2951 for (line = 0; line < nr_uarts; line++) {
2952 port = &serial8250_ports[line].port;
2953 if (uart_match_port(p, port))
2959 #define SERIAL8250_CONSOLE &serial8250_console
2961 #define SERIAL8250_CONSOLE NULL
2964 static struct uart_driver serial8250_reg = {
2965 .owner = THIS_MODULE,
2966 .driver_name = "serial",
2970 .cons = SERIAL8250_CONSOLE,
2974 * early_serial_setup - early registration for 8250 ports
2976 * Setup an 8250 port structure prior to console initialisation. Use
2977 * after console initialisation will cause undefined behaviour.
2979 int __init early_serial_setup(struct uart_port *port)
2981 struct uart_port *p;
2983 if (port->line >= ARRAY_SIZE(serial8250_ports))
2986 serial8250_isa_init_ports();
2987 p = &serial8250_ports[port->line].port;
2988 p->iobase = port->iobase;
2989 p->membase = port->membase;
2991 p->irqflags = port->irqflags;
2992 p->uartclk = port->uartclk;
2993 p->fifosize = port->fifosize;
2994 p->regshift = port->regshift;
2995 p->iotype = port->iotype;
2996 p->flags = port->flags;
2997 p->mapbase = port->mapbase;
2998 p->private_data = port->private_data;
2999 p->type = port->type;
3000 p->line = port->line;
3002 set_io_from_upio(p);
3003 if (port->serial_in)
3004 p->serial_in = port->serial_in;
3005 if (port->serial_out)
3006 p->serial_out = port->serial_out;
3007 if (port->handle_irq)
3008 p->handle_irq = port->handle_irq;
3010 p->handle_irq = serial8250_default_handle_irq;
3016 * serial8250_suspend_port - suspend one serial port
3017 * @line: serial line number
3019 * Suspend one serial port.
3021 void serial8250_suspend_port(int line)
3023 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
3027 * serial8250_resume_port - resume one serial port
3028 * @line: serial line number
3030 * Resume one serial port.
3032 void serial8250_resume_port(int line)
3034 struct uart_8250_port *up = &serial8250_ports[line];
3036 if (up->capabilities & UART_NATSEMI) {
3037 /* Ensure it's still in high speed mode */
3038 serial_outp(up, UART_LCR, 0xE0);
3040 ns16550a_goto_highspeed(up);
3042 serial_outp(up, UART_LCR, 0);
3043 up->port.uartclk = 921600*16;
3045 uart_resume_port(&serial8250_reg, &up->port);
3049 * Register a set of serial devices attached to a platform device. The
3050 * list is terminated with a zero flags entry, which means we expect
3051 * all entries to have at least UPF_BOOT_AUTOCONF set.
3053 static int __devinit serial8250_probe(struct platform_device *dev)
3055 struct plat_serial8250_port *p = dev->dev.platform_data;
3056 struct uart_port port;
3057 int ret, i, irqflag = 0;
3059 memset(&port, 0, sizeof(struct uart_port));
3062 irqflag = IRQF_SHARED;
3064 for (i = 0; p && p->flags != 0; p++, i++) {
3065 port.iobase = p->iobase;
3066 port.membase = p->membase;
3068 port.irqflags = p->irqflags;
3069 port.uartclk = p->uartclk;
3070 port.regshift = p->regshift;
3071 port.iotype = p->iotype;
3072 port.flags = p->flags;
3073 port.mapbase = p->mapbase;
3074 port.hub6 = p->hub6;
3075 port.private_data = p->private_data;
3076 port.type = p->type;
3077 port.serial_in = p->serial_in;
3078 port.serial_out = p->serial_out;
3079 port.handle_irq = p->handle_irq;
3080 port.set_termios = p->set_termios;
3082 port.dev = &dev->dev;
3083 port.irqflags |= irqflag;
3084 ret = serial8250_register_port(&port);
3086 dev_err(&dev->dev, "unable to register port at index %d "
3087 "(IO%lx MEM%llx IRQ%d): %d\n", i,
3088 p->iobase, (unsigned long long)p->mapbase,
3096 * Remove serial ports registered against a platform device.
3098 static int __devexit serial8250_remove(struct platform_device *dev)
3102 for (i = 0; i < nr_uarts; i++) {
3103 struct uart_8250_port *up = &serial8250_ports[i];
3105 if (up->port.dev == &dev->dev)
3106 serial8250_unregister_port(i);
3111 static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
3115 for (i = 0; i < UART_NR; i++) {
3116 struct uart_8250_port *up = &serial8250_ports[i];
3118 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3119 uart_suspend_port(&serial8250_reg, &up->port);
3125 static int serial8250_resume(struct platform_device *dev)
3129 for (i = 0; i < UART_NR; i++) {
3130 struct uart_8250_port *up = &serial8250_ports[i];
3132 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3133 serial8250_resume_port(i);
3139 static struct platform_driver serial8250_isa_driver = {
3140 .probe = serial8250_probe,
3141 .remove = __devexit_p(serial8250_remove),
3142 .suspend = serial8250_suspend,
3143 .resume = serial8250_resume,
3145 .name = "serial8250",
3146 .owner = THIS_MODULE,
3151 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3152 * in the table in include/asm/serial.h
3154 static struct platform_device *serial8250_isa_devs;
3157 * serial8250_register_port and serial8250_unregister_port allows for
3158 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3159 * modems and PCI multiport cards.
3161 static DEFINE_MUTEX(serial_mutex);
3163 static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3168 * First, find a port entry which matches.
3170 for (i = 0; i < nr_uarts; i++)
3171 if (uart_match_port(&serial8250_ports[i].port, port))
3172 return &serial8250_ports[i];
3175 * We didn't find a matching entry, so look for the first
3176 * free entry. We look for one which hasn't been previously
3177 * used (indicated by zero iobase).
3179 for (i = 0; i < nr_uarts; i++)
3180 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3181 serial8250_ports[i].port.iobase == 0)
3182 return &serial8250_ports[i];
3185 * That also failed. Last resort is to find any entry which
3186 * doesn't have a real port associated with it.
3188 for (i = 0; i < nr_uarts; i++)
3189 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3190 return &serial8250_ports[i];
3196 * serial8250_register_port - register a serial port
3197 * @port: serial port template
3199 * Configure the serial port specified by the request. If the
3200 * port exists and is in use, it is hung up and unregistered
3203 * The port is then probed and if necessary the IRQ is autodetected
3204 * If this fails an error is returned.
3206 * On success the port is ready to use and the line number is returned.
3208 int serial8250_register_port(struct uart_port *port)
3210 struct uart_8250_port *uart;
3213 if (port->uartclk == 0)
3216 mutex_lock(&serial_mutex);
3218 uart = serial8250_find_match_or_unused(port);
3220 uart_remove_one_port(&serial8250_reg, &uart->port);
3222 uart->port.iobase = port->iobase;
3223 uart->port.membase = port->membase;
3224 uart->port.irq = port->irq;
3225 uart->port.irqflags = port->irqflags;
3226 uart->port.uartclk = port->uartclk;
3227 uart->port.fifosize = port->fifosize;
3228 uart->port.regshift = port->regshift;
3229 uart->port.iotype = port->iotype;
3230 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
3231 uart->port.mapbase = port->mapbase;
3232 uart->port.private_data = port->private_data;
3234 uart->port.dev = port->dev;
3236 if (port->flags & UPF_FIXED_TYPE)
3237 serial8250_init_fixed_type_port(uart, port->type);
3239 set_io_from_upio(&uart->port);
3240 /* Possibly override default I/O functions. */
3241 if (port->serial_in)
3242 uart->port.serial_in = port->serial_in;
3243 if (port->serial_out)
3244 uart->port.serial_out = port->serial_out;
3245 if (port->handle_irq)
3246 uart->port.handle_irq = port->handle_irq;
3247 /* Possibly override set_termios call */
3248 if (port->set_termios)
3249 uart->port.set_termios = port->set_termios;
3251 uart->port.pm = port->pm;
3253 if (serial8250_isa_config != NULL)
3254 serial8250_isa_config(0, &uart->port,
3255 &uart->capabilities);
3257 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3259 ret = uart->port.line;
3261 mutex_unlock(&serial_mutex);
3265 EXPORT_SYMBOL(serial8250_register_port);
3268 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3269 * @line: serial line number
3271 * Remove one serial port. This may not be called from interrupt
3272 * context. We hand the port back to the our control.
3274 void serial8250_unregister_port(int line)
3276 struct uart_8250_port *uart = &serial8250_ports[line];
3278 mutex_lock(&serial_mutex);
3279 uart_remove_one_port(&serial8250_reg, &uart->port);
3280 if (serial8250_isa_devs) {
3281 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3282 uart->port.type = PORT_UNKNOWN;
3283 uart->port.dev = &serial8250_isa_devs->dev;
3284 uart->capabilities = uart_config[uart->port.type].flags;
3285 uart_add_one_port(&serial8250_reg, &uart->port);
3287 uart->port.dev = NULL;
3289 mutex_unlock(&serial_mutex);
3291 EXPORT_SYMBOL(serial8250_unregister_port);
3293 static int __init serial8250_init(void)
3297 if (nr_uarts > UART_NR)
3300 printk(KERN_INFO "Serial: 8250/16550 driver, "
3301 "%d ports, IRQ sharing %sabled\n", nr_uarts,
3302 share_irqs ? "en" : "dis");
3305 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3307 serial8250_reg.nr = UART_NR;
3308 ret = uart_register_driver(&serial8250_reg);
3313 serial8250_isa_devs = platform_device_alloc("serial8250",
3314 PLAT8250_DEV_LEGACY);
3315 if (!serial8250_isa_devs) {
3317 goto unreg_uart_drv;
3320 ret = platform_device_add(serial8250_isa_devs);
3324 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3326 ret = platform_driver_register(&serial8250_isa_driver);
3330 platform_device_del(serial8250_isa_devs);
3332 platform_device_put(serial8250_isa_devs);
3335 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3337 uart_unregister_driver(&serial8250_reg);
3343 static void __exit serial8250_exit(void)
3345 struct platform_device *isa_dev = serial8250_isa_devs;
3348 * This tells serial8250_unregister_port() not to re-register
3349 * the ports (thereby making serial8250_isa_driver permanently
3352 serial8250_isa_devs = NULL;
3354 platform_driver_unregister(&serial8250_isa_driver);
3355 platform_device_unregister(isa_dev);
3358 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3360 uart_unregister_driver(&serial8250_reg);
3364 module_init(serial8250_init);
3365 module_exit(serial8250_exit);
3367 EXPORT_SYMBOL(serial8250_suspend_port);
3368 EXPORT_SYMBOL(serial8250_resume_port);
3370 MODULE_LICENSE("GPL");
3371 MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
3373 module_param(share_irqs, uint, 0644);
3374 MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3377 module_param(nr_uarts, uint, 0644);
3378 MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3380 module_param(skip_txen_test, uint, 0644);
3381 MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3383 #ifdef CONFIG_SERIAL_8250_RSA
3384 module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3385 MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3387 MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);