1 #if defined(CONFIG_SERIAL_EFM32_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
5 #include <linux/kernel.h>
6 #include <linux/module.h>
8 #include <linux/platform_device.h>
9 #include <linux/console.h>
10 #include <linux/sysrq.h>
11 #include <linux/serial_core.h>
12 #include <linux/tty_flip.h>
13 #include <linux/slab.h>
14 #include <linux/clk.h>
16 #include <linux/of_device.h>
18 #include <linux/platform_data/efm32-uart.h>
20 #define DRIVER_NAME "efm32-uart"
21 #define DEV_NAME "ttyefm"
23 #define UARTn_CTRL 0x00
24 #define UARTn_CTRL_SYNC 0x0001
25 #define UARTn_CTRL_TXBIL 0x1000
27 #define UARTn_FRAME 0x04
28 #define UARTn_FRAME_DATABITS__MASK 0x000f
29 #define UARTn_FRAME_DATABITS(n) ((n) - 3)
30 #define UARTn_FRAME_PARITY_NONE 0x0000
31 #define UARTn_FRAME_PARITY_EVEN 0x0200
32 #define UARTn_FRAME_PARITY_ODD 0x0300
33 #define UARTn_FRAME_STOPBITS_HALF 0x0000
34 #define UARTn_FRAME_STOPBITS_ONE 0x1000
35 #define UARTn_FRAME_STOPBITS_TWO 0x3000
37 #define UARTn_CMD 0x0c
38 #define UARTn_CMD_RXEN 0x0001
39 #define UARTn_CMD_RXDIS 0x0002
40 #define UARTn_CMD_TXEN 0x0004
41 #define UARTn_CMD_TXDIS 0x0008
43 #define UARTn_STATUS 0x10
44 #define UARTn_STATUS_TXENS 0x0002
45 #define UARTn_STATUS_TXC 0x0020
46 #define UARTn_STATUS_TXBL 0x0040
47 #define UARTn_STATUS_RXDATAV 0x0080
49 #define UARTn_CLKDIV 0x14
51 #define UARTn_RXDATAX 0x18
52 #define UARTn_RXDATAX_RXDATA__MASK 0x01ff
53 #define UARTn_RXDATAX_PERR 0x4000
54 #define UARTn_RXDATAX_FERR 0x8000
56 * This is a software only flag used for ignore_status_mask and
57 * read_status_mask! It's used for breaks that the hardware doesn't report
60 #define SW_UARTn_RXDATAX_BERR 0x2000
62 #define UARTn_TXDATA 0x34
65 #define UARTn_IF_TXC 0x0001
66 #define UARTn_IF_TXBL 0x0002
67 #define UARTn_IF_RXDATAV 0x0004
68 #define UARTn_IF_RXOF 0x0010
70 #define UARTn_IFS 0x44
71 #define UARTn_IFC 0x48
72 #define UARTn_IEN 0x4c
74 #define UARTn_ROUTE 0x54
75 #define UARTn_ROUTE_LOCATION__MASK 0x0700
76 #define UARTn_ROUTE_LOCATION(n) (((n) << 8) & UARTn_ROUTE_LOCATION__MASK)
77 #define UARTn_ROUTE_RXPEN 0x0001
78 #define UARTn_ROUTE_TXPEN 0x0002
80 struct efm32_uart_port {
81 struct uart_port port;
85 #define to_efm_port(_port) container_of(_port, struct efm32_uart_port, port)
86 #define efm_debug(efm_port, format, arg...) \
87 dev_dbg(efm_port->port.dev, format, ##arg)
89 static void efm32_uart_write32(struct efm32_uart_port *efm_port,
90 u32 value, unsigned offset)
92 writel_relaxed(value, efm_port->port.membase + offset);
95 static u32 efm32_uart_read32(struct efm32_uart_port *efm_port,
98 return readl_relaxed(efm_port->port.membase + offset);
101 static unsigned int efm32_uart_tx_empty(struct uart_port *port)
103 struct efm32_uart_port *efm_port = to_efm_port(port);
104 u32 status = efm32_uart_read32(efm_port, UARTn_STATUS);
106 if (status & UARTn_STATUS_TXC)
112 static void efm32_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
114 /* sorry, neither handshaking lines nor loop functionallity */
117 static unsigned int efm32_uart_get_mctrl(struct uart_port *port)
119 /* sorry, no handshaking lines available */
120 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR;
123 static void efm32_uart_stop_tx(struct uart_port *port)
125 struct efm32_uart_port *efm_port = to_efm_port(port);
126 u32 ien = efm32_uart_read32(efm_port, UARTn_IEN);
128 efm32_uart_write32(efm_port, UARTn_CMD_TXDIS, UARTn_CMD);
129 ien &= ~(UARTn_IF_TXC | UARTn_IF_TXBL);
130 efm32_uart_write32(efm_port, ien, UARTn_IEN);
133 static void efm32_uart_tx_chars(struct efm32_uart_port *efm_port)
135 struct uart_port *port = &efm_port->port;
136 struct circ_buf *xmit = &port->state->xmit;
138 while (efm32_uart_read32(efm_port, UARTn_STATUS) &
142 efm32_uart_write32(efm_port, port->x_char,
147 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
149 efm32_uart_write32(efm_port, xmit->buf[xmit->tail],
151 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
156 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
157 uart_write_wakeup(port);
159 if (!port->x_char && uart_circ_empty(xmit) &&
160 efm32_uart_read32(efm_port, UARTn_STATUS) &
162 efm32_uart_stop_tx(port);
165 static void efm32_uart_start_tx(struct uart_port *port)
167 struct efm32_uart_port *efm_port = to_efm_port(port);
170 efm32_uart_write32(efm_port,
171 UARTn_IF_TXBL | UARTn_IF_TXC, UARTn_IFC);
172 ien = efm32_uart_read32(efm_port, UARTn_IEN);
173 efm32_uart_write32(efm_port,
174 ien | UARTn_IF_TXBL | UARTn_IF_TXC, UARTn_IEN);
175 efm32_uart_write32(efm_port, UARTn_CMD_TXEN, UARTn_CMD);
177 efm32_uart_tx_chars(efm_port);
180 static void efm32_uart_stop_rx(struct uart_port *port)
182 struct efm32_uart_port *efm_port = to_efm_port(port);
184 efm32_uart_write32(efm_port, UARTn_CMD_RXDIS, UARTn_CMD);
187 static void efm32_uart_enable_ms(struct uart_port *port)
189 /* no handshake lines, no modem status interrupts */
192 static void efm32_uart_break_ctl(struct uart_port *port, int ctl)
194 /* not possible without fiddling with gpios */
197 static void efm32_uart_rx_chars(struct efm32_uart_port *efm_port)
199 struct uart_port *port = &efm_port->port;
201 while (efm32_uart_read32(efm_port, UARTn_STATUS) &
202 UARTn_STATUS_RXDATAV) {
203 u32 rxdata = efm32_uart_read32(efm_port, UARTn_RXDATAX);
207 * This is a reserved bit and I only saw it read as 0. But to be
208 * sure not to be confused too much by new devices adhere to the
209 * warning in the reference manual that reserverd bits might
210 * read as 1 in the future.
212 rxdata &= ~SW_UARTn_RXDATAX_BERR;
216 if ((rxdata & UARTn_RXDATAX_FERR) &&
217 !(rxdata & UARTn_RXDATAX_RXDATA__MASK)) {
218 rxdata |= SW_UARTn_RXDATAX_BERR;
220 if (uart_handle_break(port))
222 } else if (rxdata & UARTn_RXDATAX_PERR)
223 port->icount.parity++;
224 else if (rxdata & UARTn_RXDATAX_FERR)
225 port->icount.frame++;
227 rxdata &= port->read_status_mask;
229 if (rxdata & SW_UARTn_RXDATAX_BERR)
231 else if (rxdata & UARTn_RXDATAX_PERR)
233 else if (rxdata & UARTn_RXDATAX_FERR)
235 else if (uart_handle_sysrq_char(port,
236 rxdata & UARTn_RXDATAX_RXDATA__MASK))
239 if ((rxdata & port->ignore_status_mask) == 0)
240 tty_insert_flip_char(&port->state->port,
241 rxdata & UARTn_RXDATAX_RXDATA__MASK, flag);
245 static irqreturn_t efm32_uart_rxirq(int irq, void *data)
247 struct efm32_uart_port *efm_port = data;
248 u32 irqflag = efm32_uart_read32(efm_port, UARTn_IF);
249 int handled = IRQ_NONE;
250 struct uart_port *port = &efm_port->port;
251 struct tty_port *tport = &port->state->port;
252 struct tty_struct *tty;
254 spin_lock(&port->lock);
256 tty = tty_kref_get(tport->tty);
258 if (irqflag & UARTn_IF_RXDATAV) {
259 efm32_uart_write32(efm_port, UARTn_IF_RXDATAV, UARTn_IFC);
260 efm32_uart_rx_chars(efm_port);
262 handled = IRQ_HANDLED;
265 if (irqflag & UARTn_IF_RXOF) {
266 efm32_uart_write32(efm_port, UARTn_IF_RXOF, UARTn_IFC);
267 port->icount.overrun++;
268 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
270 handled = IRQ_HANDLED;
274 tty_flip_buffer_push(tty);
278 spin_unlock(&port->lock);
283 static irqreturn_t efm32_uart_txirq(int irq, void *data)
285 struct efm32_uart_port *efm_port = data;
286 u32 irqflag = efm32_uart_read32(efm_port, UARTn_IF);
288 /* TXBL doesn't need to be cleared */
289 if (irqflag & UARTn_IF_TXC)
290 efm32_uart_write32(efm_port, UARTn_IF_TXC, UARTn_IFC);
292 if (irqflag & (UARTn_IF_TXC | UARTn_IF_TXBL)) {
293 efm32_uart_tx_chars(efm_port);
299 static int efm32_uart_startup(struct uart_port *port)
301 struct efm32_uart_port *efm_port = to_efm_port(port);
303 struct efm32_uart_pdata *pdata = dev_get_platdata(port->dev);
307 location = UARTn_ROUTE_LOCATION(pdata->location);
309 ret = clk_enable(efm_port->clk);
311 efm_debug(efm_port, "failed to enable clk\n");
314 port->uartclk = clk_get_rate(efm_port->clk);
316 /* Enable pins at configured location */
317 efm32_uart_write32(efm_port, location | UARTn_ROUTE_RXPEN | UARTn_ROUTE_TXPEN,
320 ret = request_irq(port->irq, efm32_uart_rxirq, 0,
321 DRIVER_NAME, efm_port);
323 efm_debug(efm_port, "failed to register rxirq\n");
324 goto err_request_irq_rx;
327 /* disable all irqs */
328 efm32_uart_write32(efm_port, 0, UARTn_IEN);
330 ret = request_irq(efm_port->txirq, efm32_uart_txirq, 0,
331 DRIVER_NAME, efm_port);
333 efm_debug(efm_port, "failed to register txirq\n");
334 free_irq(port->irq, efm_port);
337 clk_disable(efm_port->clk);
339 efm32_uart_write32(efm_port,
340 UARTn_IF_RXDATAV | UARTn_IF_RXOF, UARTn_IEN);
341 efm32_uart_write32(efm_port, UARTn_CMD_RXEN, UARTn_CMD);
348 static void efm32_uart_shutdown(struct uart_port *port)
350 struct efm32_uart_port *efm_port = to_efm_port(port);
352 efm32_uart_write32(efm_port, 0, UARTn_IEN);
353 free_irq(port->irq, efm_port);
355 clk_disable(efm_port->clk);
358 static void efm32_uart_set_termios(struct uart_port *port,
359 struct ktermios *new, struct ktermios *old)
361 struct efm32_uart_port *efm_port = to_efm_port(port);
367 /* no modem control lines */
368 new->c_cflag &= ~(CRTSCTS | CMSPAR);
370 baud = uart_get_baud_rate(port, new, old,
371 DIV_ROUND_CLOSEST(port->uartclk, 16 * 8192),
372 DIV_ROUND_CLOSEST(port->uartclk, 16));
374 switch (new->c_cflag & CSIZE) {
376 frame |= UARTn_FRAME_DATABITS(5);
379 frame |= UARTn_FRAME_DATABITS(6);
382 frame |= UARTn_FRAME_DATABITS(7);
385 frame |= UARTn_FRAME_DATABITS(8);
389 if (new->c_cflag & CSTOPB)
390 /* the receiver only verifies the first stop bit */
391 frame |= UARTn_FRAME_STOPBITS_TWO;
393 frame |= UARTn_FRAME_STOPBITS_ONE;
395 if (new->c_cflag & PARENB) {
396 if (new->c_cflag & PARODD)
397 frame |= UARTn_FRAME_PARITY_ODD;
399 frame |= UARTn_FRAME_PARITY_EVEN;
401 frame |= UARTn_FRAME_PARITY_NONE;
404 * the 6 lowest bits of CLKDIV are dc, bit 6 has value 0.25.
405 * port->uartclk <= 14e6, so 4 * port->uartclk doesn't overflow.
407 clkdiv = (DIV_ROUND_CLOSEST(4 * port->uartclk, 16 * baud) - 4) << 6;
409 spin_lock_irqsave(&port->lock, flags);
411 efm32_uart_write32(efm_port,
412 UARTn_CMD_TXDIS | UARTn_CMD_RXDIS, UARTn_CMD);
414 port->read_status_mask = UARTn_RXDATAX_RXDATA__MASK;
415 if (new->c_iflag & INPCK)
416 port->read_status_mask |=
417 UARTn_RXDATAX_FERR | UARTn_RXDATAX_PERR;
418 if (new->c_iflag & (BRKINT | PARMRK))
419 port->read_status_mask |= SW_UARTn_RXDATAX_BERR;
421 port->ignore_status_mask = 0;
422 if (new->c_iflag & IGNPAR)
423 port->ignore_status_mask |=
424 UARTn_RXDATAX_FERR | UARTn_RXDATAX_PERR;
425 if (new->c_iflag & IGNBRK)
426 port->ignore_status_mask |= SW_UARTn_RXDATAX_BERR;
428 uart_update_timeout(port, new->c_cflag, baud);
430 efm32_uart_write32(efm_port, UARTn_CTRL_TXBIL, UARTn_CTRL);
431 efm32_uart_write32(efm_port, frame, UARTn_FRAME);
432 efm32_uart_write32(efm_port, clkdiv, UARTn_CLKDIV);
434 efm32_uart_write32(efm_port, UARTn_CMD_TXEN | UARTn_CMD_RXEN,
437 spin_unlock_irqrestore(&port->lock, flags);
440 static const char *efm32_uart_type(struct uart_port *port)
442 return port->type == PORT_EFMUART ? "efm32-uart" : NULL;
445 static void efm32_uart_release_port(struct uart_port *port)
447 struct efm32_uart_port *efm_port = to_efm_port(port);
449 clk_unprepare(efm_port->clk);
450 clk_put(efm_port->clk);
451 iounmap(port->membase);
454 static int efm32_uart_request_port(struct uart_port *port)
456 struct efm32_uart_port *efm_port = to_efm_port(port);
459 port->membase = ioremap(port->mapbase, 60);
460 if (!efm_port->port.membase) {
462 efm_debug(efm_port, "failed to remap\n");
466 efm_port->clk = clk_get(port->dev, NULL);
467 if (IS_ERR(efm_port->clk)) {
468 ret = PTR_ERR(efm_port->clk);
469 efm_debug(efm_port, "failed to get clock\n");
473 ret = clk_prepare(efm_port->clk);
475 clk_put(efm_port->clk);
478 iounmap(port->membase);
485 static void efm32_uart_config_port(struct uart_port *port, int type)
487 if (type & UART_CONFIG_TYPE &&
488 !efm32_uart_request_port(port))
489 port->type = PORT_EFMUART;
492 static int efm32_uart_verify_port(struct uart_port *port,
493 struct serial_struct *serinfo)
497 if (serinfo->type != PORT_UNKNOWN && serinfo->type != PORT_EFMUART)
503 static struct uart_ops efm32_uart_pops = {
504 .tx_empty = efm32_uart_tx_empty,
505 .set_mctrl = efm32_uart_set_mctrl,
506 .get_mctrl = efm32_uart_get_mctrl,
507 .stop_tx = efm32_uart_stop_tx,
508 .start_tx = efm32_uart_start_tx,
509 .stop_rx = efm32_uart_stop_rx,
510 .enable_ms = efm32_uart_enable_ms,
511 .break_ctl = efm32_uart_break_ctl,
512 .startup = efm32_uart_startup,
513 .shutdown = efm32_uart_shutdown,
514 .set_termios = efm32_uart_set_termios,
515 .type = efm32_uart_type,
516 .release_port = efm32_uart_release_port,
517 .request_port = efm32_uart_request_port,
518 .config_port = efm32_uart_config_port,
519 .verify_port = efm32_uart_verify_port,
522 static struct efm32_uart_port *efm32_uart_ports[5];
524 #ifdef CONFIG_SERIAL_EFM32_UART_CONSOLE
525 static void efm32_uart_console_putchar(struct uart_port *port, int ch)
527 struct efm32_uart_port *efm_port = to_efm_port(port);
528 unsigned int timeout = 0x400;
532 status = efm32_uart_read32(efm_port, UARTn_STATUS);
534 if (status & UARTn_STATUS_TXBL)
539 efm32_uart_write32(efm_port, ch, UARTn_TXDATA);
542 static void efm32_uart_console_write(struct console *co, const char *s,
545 struct efm32_uart_port *efm_port = efm32_uart_ports[co->index];
546 u32 status = efm32_uart_read32(efm_port, UARTn_STATUS);
547 unsigned int timeout = 0x400;
549 if (!(status & UARTn_STATUS_TXENS))
550 efm32_uart_write32(efm_port, UARTn_CMD_TXEN, UARTn_CMD);
552 uart_console_write(&efm_port->port, s, count,
553 efm32_uart_console_putchar);
555 /* Wait for the transmitter to become empty */
557 u32 status = efm32_uart_read32(efm_port, UARTn_STATUS);
558 if (status & UARTn_STATUS_TXC)
564 if (!(status & UARTn_STATUS_TXENS))
565 efm32_uart_write32(efm_port, UARTn_CMD_TXDIS, UARTn_CMD);
568 static void efm32_uart_console_get_options(struct efm32_uart_port *efm_port,
569 int *baud, int *parity, int *bits)
571 u32 ctrl = efm32_uart_read32(efm_port, UARTn_CTRL);
572 u32 route, clkdiv, frame;
574 if (ctrl & UARTn_CTRL_SYNC)
575 /* not operating in async mode */
578 route = efm32_uart_read32(efm_port, UARTn_ROUTE);
579 if (!(route & UARTn_ROUTE_TXPEN))
580 /* tx pin not routed */
583 clkdiv = efm32_uart_read32(efm_port, UARTn_CLKDIV);
585 *baud = DIV_ROUND_CLOSEST(4 * efm_port->port.uartclk,
586 16 * (4 + (clkdiv >> 6)));
588 frame = efm32_uart_read32(efm_port, UARTn_FRAME);
589 if (frame & UARTn_FRAME_PARITY_ODD)
591 else if (frame & UARTn_FRAME_PARITY_EVEN)
596 *bits = (frame & UARTn_FRAME_DATABITS__MASK) -
597 UARTn_FRAME_DATABITS(4) + 4;
599 efm_debug(efm_port, "get_opts: options=%d%c%d\n",
600 *baud, *parity, *bits);
603 static int efm32_uart_console_setup(struct console *co, char *options)
605 struct efm32_uart_port *efm_port;
612 if (co->index < 0 || co->index >= ARRAY_SIZE(efm32_uart_ports)) {
614 for (i = 0; i < ARRAY_SIZE(efm32_uart_ports); ++i) {
615 if (efm32_uart_ports[i]) {
616 pr_warn("efm32-console: fall back to console index %u (from %hhi)\n",
624 efm_port = efm32_uart_ports[co->index];
626 pr_warn("efm32-console: No port at %d\n", co->index);
630 ret = clk_prepare(efm_port->clk);
632 dev_warn(efm_port->port.dev,
633 "console: clk_prepare failed: %d\n", ret);
637 efm_port->port.uartclk = clk_get_rate(efm_port->clk);
640 uart_parse_options(options, &baud, &parity, &bits, &flow);
642 efm32_uart_console_get_options(efm_port,
643 &baud, &parity, &bits);
645 return uart_set_options(&efm_port->port, co, baud, parity, bits, flow);
648 static struct uart_driver efm32_uart_reg;
650 static struct console efm32_uart_console = {
652 .write = efm32_uart_console_write,
653 .device = uart_console_device,
654 .setup = efm32_uart_console_setup,
655 .flags = CON_PRINTBUFFER,
657 .data = &efm32_uart_reg,
661 #define efm32_uart_console (*(struct console *)NULL)
662 #endif /* ifdef CONFIG_SERIAL_EFM32_UART_CONSOLE / else */
664 static struct uart_driver efm32_uart_reg = {
665 .owner = THIS_MODULE,
666 .driver_name = DRIVER_NAME,
667 .dev_name = DEV_NAME,
668 .nr = ARRAY_SIZE(efm32_uart_ports),
669 .cons = &efm32_uart_console,
672 static int efm32_uart_probe_dt(struct platform_device *pdev,
673 struct efm32_uart_port *efm_port)
675 struct device_node *np = pdev->dev.of_node;
681 ret = of_alias_get_id(np, "serial");
683 dev_err(&pdev->dev, "failed to get alias id: %d\n", ret);
686 efm_port->port.line = ret;
692 static int efm32_uart_probe(struct platform_device *pdev)
694 struct efm32_uart_port *efm_port;
695 struct resource *res;
698 efm_port = kzalloc(sizeof(*efm_port), GFP_KERNEL);
700 dev_dbg(&pdev->dev, "failed to allocate private data\n");
704 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
707 dev_dbg(&pdev->dev, "failed to determine base address\n");
711 if (resource_size(res) < 60) {
713 dev_dbg(&pdev->dev, "memory resource too small\n");
717 ret = platform_get_irq(pdev, 0);
719 dev_dbg(&pdev->dev, "failed to get rx irq\n");
723 efm_port->port.irq = ret;
725 ret = platform_get_irq(pdev, 1);
727 ret = efm_port->port.irq + 1;
729 efm_port->txirq = ret;
731 efm_port->port.dev = &pdev->dev;
732 efm_port->port.mapbase = res->start;
733 efm_port->port.type = PORT_EFMUART;
734 efm_port->port.iotype = UPIO_MEM32;
735 efm_port->port.fifosize = 2;
736 efm_port->port.ops = &efm32_uart_pops;
737 efm_port->port.flags = UPF_BOOT_AUTOCONF;
739 ret = efm32_uart_probe_dt(pdev, efm_port);
741 /* not created by device tree */
742 efm_port->port.line = pdev->id;
744 if (efm_port->port.line >= 0 &&
745 efm_port->port.line < ARRAY_SIZE(efm32_uart_ports))
746 efm32_uart_ports[efm_port->port.line] = efm_port;
748 ret = uart_add_one_port(&efm32_uart_reg, &efm_port->port);
750 dev_dbg(&pdev->dev, "failed to add port: %d\n", ret);
752 if (pdev->id >= 0 && pdev->id < ARRAY_SIZE(efm32_uart_ports))
753 efm32_uart_ports[pdev->id] = NULL;
759 platform_set_drvdata(pdev, efm_port);
760 dev_dbg(&pdev->dev, "\\o/\n");
766 static int efm32_uart_remove(struct platform_device *pdev)
768 struct efm32_uart_port *efm_port = platform_get_drvdata(pdev);
770 platform_set_drvdata(pdev, NULL);
772 uart_remove_one_port(&efm32_uart_reg, &efm_port->port);
774 if (pdev->id >= 0 && pdev->id < ARRAY_SIZE(efm32_uart_ports))
775 efm32_uart_ports[pdev->id] = NULL;
782 static struct of_device_id efm32_uart_dt_ids[] = {
784 .compatible = "efm32,uart",
789 MODULE_DEVICE_TABLE(of, efm32_uart_dt_ids);
791 static struct platform_driver efm32_uart_driver = {
792 .probe = efm32_uart_probe,
793 .remove = efm32_uart_remove,
797 .owner = THIS_MODULE,
798 .of_match_table = efm32_uart_dt_ids,
802 static int __init efm32_uart_init(void)
806 ret = uart_register_driver(&efm32_uart_reg);
810 ret = platform_driver_register(&efm32_uart_driver);
812 uart_unregister_driver(&efm32_uart_reg);
814 pr_info("EFM32 UART/USART driver\n");
818 module_init(efm32_uart_init);
820 static void __exit efm32_uart_exit(void)
822 platform_driver_unregister(&efm32_uart_driver);
823 uart_unregister_driver(&efm32_uart_reg);
826 MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>");
827 MODULE_DESCRIPTION("EFM32 UART/USART driver");
828 MODULE_LICENSE("GPL v2");
829 MODULE_ALIAS("platform:" DRIVER_NAME);