2 * Driver for Motorola IMX serial ports
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Author: Sascha Hauer <sascha@saschahauer.de>
7 * Copyright (C) 2004 Pengutronix
9 * Copyright (C) 2009 emlix GmbH
10 * Author: Fabian Godehardt (added IrDA support for iMX)
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 * [29-Mar-2005] Mike Lee
27 * Added hardware handshake
30 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
34 #include <linux/module.h>
35 #include <linux/ioport.h>
36 #include <linux/init.h>
37 #include <linux/console.h>
38 #include <linux/sysrq.h>
39 #include <linux/platform_device.h>
40 #include <linux/tty.h>
41 #include <linux/tty_flip.h>
42 #include <linux/serial_core.h>
43 #include <linux/serial.h>
44 #include <linux/clk.h>
45 #include <linux/delay.h>
46 #include <linux/rational.h>
47 #include <linux/slab.h>
49 #include <linux/of_device.h>
50 #include <linux/pinctrl/consumer.h>
54 #include <linux/platform_data/serial-imx.h>
56 /* Register definitions */
57 #define URXD0 0x0 /* Receiver Register */
58 #define URTX0 0x40 /* Transmitter Register */
59 #define UCR1 0x80 /* Control Register 1 */
60 #define UCR2 0x84 /* Control Register 2 */
61 #define UCR3 0x88 /* Control Register 3 */
62 #define UCR4 0x8c /* Control Register 4 */
63 #define UFCR 0x90 /* FIFO Control Register */
64 #define USR1 0x94 /* Status Register 1 */
65 #define USR2 0x98 /* Status Register 2 */
66 #define UESC 0x9c /* Escape Character Register */
67 #define UTIM 0xa0 /* Escape Timer Register */
68 #define UBIR 0xa4 /* BRM Incremental Register */
69 #define UBMR 0xa8 /* BRM Modulator Register */
70 #define UBRC 0xac /* Baud Rate Count Register */
71 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
72 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
73 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
75 /* UART Control Register Bit Fields.*/
76 #define URXD_CHARRDY (1<<15)
77 #define URXD_ERR (1<<14)
78 #define URXD_OVRRUN (1<<13)
79 #define URXD_FRMERR (1<<12)
80 #define URXD_BRK (1<<11)
81 #define URXD_PRERR (1<<10)
82 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */
83 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
84 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
85 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
86 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
87 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
88 #define UCR1_IREN (1<<7) /* Infrared interface enable */
89 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
90 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
91 #define UCR1_SNDBRK (1<<4) /* Send break */
92 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
93 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
94 #define UCR1_DOZE (1<<1) /* Doze */
95 #define UCR1_UARTEN (1<<0) /* UART enabled */
96 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
97 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
98 #define UCR2_CTSC (1<<13) /* CTS pin control */
99 #define UCR2_CTS (1<<12) /* Clear to send */
100 #define UCR2_ESCEN (1<<11) /* Escape enable */
101 #define UCR2_PREN (1<<8) /* Parity enable */
102 #define UCR2_PROE (1<<7) /* Parity odd/even */
103 #define UCR2_STPB (1<<6) /* Stop */
104 #define UCR2_WS (1<<5) /* Word size */
105 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
106 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */
107 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
108 #define UCR2_RXEN (1<<1) /* Receiver enabled */
109 #define UCR2_SRST (1<<0) /* SW reset */
110 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
111 #define UCR3_PARERREN (1<<12) /* Parity enable */
112 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
113 #define UCR3_DSR (1<<10) /* Data set ready */
114 #define UCR3_DCD (1<<9) /* Data carrier detect */
115 #define UCR3_RI (1<<8) /* Ring indicator */
116 #define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
117 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
118 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
119 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
120 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
121 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
122 #define UCR3_BPEN (1<<0) /* Preset registers enable */
123 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
124 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
125 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
126 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
127 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
128 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
129 #define UCR4_IRSC (1<<5) /* IR special case */
130 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
131 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
132 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
133 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
134 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
135 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
136 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
137 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
138 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
139 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
140 #define USR1_RTSS (1<<14) /* RTS pin status */
141 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
142 #define USR1_RTSD (1<<12) /* RTS delta */
143 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
144 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
145 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
146 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
147 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
148 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
149 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
150 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
151 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
152 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
153 #define USR2_IDLE (1<<12) /* Idle condition */
154 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
155 #define USR2_WAKE (1<<7) /* Wake */
156 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
157 #define USR2_TXDC (1<<3) /* Transmitter complete */
158 #define USR2_BRCD (1<<2) /* Break condition */
159 #define USR2_ORE (1<<1) /* Overrun error */
160 #define USR2_RDR (1<<0) /* Recv data ready */
161 #define UTS_FRCPERR (1<<13) /* Force parity error */
162 #define UTS_LOOP (1<<12) /* Loop tx and rx */
163 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
164 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
165 #define UTS_TXFULL (1<<4) /* TxFIFO full */
166 #define UTS_RXFULL (1<<3) /* RxFIFO full */
167 #define UTS_SOFTRST (1<<0) /* Software reset */
169 /* We've been assigned a range on the "Low-density serial ports" major */
170 #define SERIAL_IMX_MAJOR 207
171 #define MINOR_START 16
172 #define DEV_NAME "ttymxc"
175 * This determines how often we check the modem status signals
176 * for any change. They generally aren't connected to an IRQ
177 * so we have to poll them. We also check immediately before
178 * filling the TX fifo incase CTS has been dropped.
180 #define MCTRL_TIMEOUT (250*HZ/1000)
182 #define DRIVER_NAME "IMX-uart"
186 /* i.mx21 type uart runs on all i.mx except i.mx1 */
192 /* device type dependent stuff */
193 struct imx_uart_data {
195 enum imx_uart_type devtype;
199 struct uart_port port;
200 struct timer_list timer;
201 unsigned int old_status;
202 int txirq, rxirq, rtsirq;
203 unsigned int have_rtscts:1;
204 unsigned int use_irda:1;
205 unsigned int irda_inv_rx:1;
206 unsigned int irda_inv_tx:1;
207 unsigned short trcv_delay; /* transceiver delay */
210 const struct imx_uart_data *devdata;
213 struct imx_port_ucrs {
220 #define USE_IRDA(sport) ((sport)->use_irda)
222 #define USE_IRDA(sport) (0)
225 static struct imx_uart_data imx_uart_devdata[] = {
228 .devtype = IMX1_UART,
231 .uts_reg = IMX21_UTS,
232 .devtype = IMX21_UART,
236 static struct platform_device_id imx_uart_devtype[] = {
239 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
241 .name = "imx21-uart",
242 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
247 MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
249 static struct of_device_id imx_uart_dt_ids[] = {
250 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
251 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
254 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
256 static inline unsigned uts_reg(struct imx_port *sport)
258 return sport->devdata->uts_reg;
261 static inline int is_imx1_uart(struct imx_port *sport)
263 return sport->devdata->devtype == IMX1_UART;
266 static inline int is_imx21_uart(struct imx_port *sport)
268 return sport->devdata->devtype == IMX21_UART;
272 * Save and restore functions for UCR1, UCR2 and UCR3 registers
274 static void imx_port_ucrs_save(struct uart_port *port,
275 struct imx_port_ucrs *ucr)
277 /* save control registers */
278 ucr->ucr1 = readl(port->membase + UCR1);
279 ucr->ucr2 = readl(port->membase + UCR2);
280 ucr->ucr3 = readl(port->membase + UCR3);
283 static void imx_port_ucrs_restore(struct uart_port *port,
284 struct imx_port_ucrs *ucr)
286 /* restore control registers */
287 writel(ucr->ucr1, port->membase + UCR1);
288 writel(ucr->ucr2, port->membase + UCR2);
289 writel(ucr->ucr3, port->membase + UCR3);
293 * Handle any change of modem status signal since we were last called.
295 static void imx_mctrl_check(struct imx_port *sport)
297 unsigned int status, changed;
299 status = sport->port.ops->get_mctrl(&sport->port);
300 changed = status ^ sport->old_status;
305 sport->old_status = status;
307 if (changed & TIOCM_RI)
308 sport->port.icount.rng++;
309 if (changed & TIOCM_DSR)
310 sport->port.icount.dsr++;
311 if (changed & TIOCM_CAR)
312 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
313 if (changed & TIOCM_CTS)
314 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
316 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
320 * This is our per-port timeout handler, for checking the
321 * modem status signals.
323 static void imx_timeout(unsigned long data)
325 struct imx_port *sport = (struct imx_port *)data;
328 if (sport->port.state) {
329 spin_lock_irqsave(&sport->port.lock, flags);
330 imx_mctrl_check(sport);
331 spin_unlock_irqrestore(&sport->port.lock, flags);
333 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
338 * interrupts disabled on entry
340 static void imx_stop_tx(struct uart_port *port)
342 struct imx_port *sport = (struct imx_port *)port;
345 if (USE_IRDA(sport)) {
346 /* half duplex - wait for end of transmission */
349 !(readl(sport->port.membase + USR2) & USR2_TXDC)) {
354 * irda transceiver - wait a bit more to avoid
355 * cutoff, hardware dependent
357 udelay(sport->trcv_delay);
360 * half duplex - reactivate receive mode,
361 * flush receive pipe echo crap
363 if (readl(sport->port.membase + USR2) & USR2_TXDC) {
364 temp = readl(sport->port.membase + UCR1);
365 temp &= ~(UCR1_TXMPTYEN | UCR1_TRDYEN);
366 writel(temp, sport->port.membase + UCR1);
368 temp = readl(sport->port.membase + UCR4);
369 temp &= ~(UCR4_TCEN);
370 writel(temp, sport->port.membase + UCR4);
372 while (readl(sport->port.membase + URXD0) &
376 temp = readl(sport->port.membase + UCR1);
378 writel(temp, sport->port.membase + UCR1);
380 temp = readl(sport->port.membase + UCR4);
382 writel(temp, sport->port.membase + UCR4);
387 temp = readl(sport->port.membase + UCR1);
388 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
392 * interrupts disabled on entry
394 static void imx_stop_rx(struct uart_port *port)
396 struct imx_port *sport = (struct imx_port *)port;
399 temp = readl(sport->port.membase + UCR2);
400 writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2);
404 * Set the modem control timer to fire immediately.
406 static void imx_enable_ms(struct uart_port *port)
408 struct imx_port *sport = (struct imx_port *)port;
410 mod_timer(&sport->timer, jiffies);
413 static inline void imx_transmit_buffer(struct imx_port *sport)
415 struct circ_buf *xmit = &sport->port.state->xmit;
417 while (!uart_circ_empty(xmit) &&
418 !(readl(sport->port.membase + uts_reg(sport))
420 /* send xmit->buf[xmit->tail]
421 * out the port here */
422 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
423 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
424 sport->port.icount.tx++;
427 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
428 uart_write_wakeup(&sport->port);
430 if (uart_circ_empty(xmit))
431 imx_stop_tx(&sport->port);
435 * interrupts disabled on entry
437 static void imx_start_tx(struct uart_port *port)
439 struct imx_port *sport = (struct imx_port *)port;
442 if (USE_IRDA(sport)) {
443 /* half duplex in IrDA mode; have to disable receive mode */
444 temp = readl(sport->port.membase + UCR4);
445 temp &= ~(UCR4_DREN);
446 writel(temp, sport->port.membase + UCR4);
448 temp = readl(sport->port.membase + UCR1);
449 temp &= ~(UCR1_RRDYEN);
450 writel(temp, sport->port.membase + UCR1);
452 /* Clear any pending ORE flag before enabling interrupt */
453 temp = readl(sport->port.membase + USR2);
454 writel(temp | USR2_ORE, sport->port.membase + USR2);
456 temp = readl(sport->port.membase + UCR4);
458 writel(temp, sport->port.membase + UCR4);
460 temp = readl(sport->port.membase + UCR1);
461 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
463 if (USE_IRDA(sport)) {
464 temp = readl(sport->port.membase + UCR1);
466 writel(temp, sport->port.membase + UCR1);
468 temp = readl(sport->port.membase + UCR4);
470 writel(temp, sport->port.membase + UCR4);
473 if (readl(sport->port.membase + uts_reg(sport)) & UTS_TXEMPTY)
474 imx_transmit_buffer(sport);
477 static irqreturn_t imx_rtsint(int irq, void *dev_id)
479 struct imx_port *sport = dev_id;
483 spin_lock_irqsave(&sport->port.lock, flags);
485 writel(USR1_RTSD, sport->port.membase + USR1);
486 val = readl(sport->port.membase + USR1) & USR1_RTSS;
487 uart_handle_cts_change(&sport->port, !!val);
488 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
490 spin_unlock_irqrestore(&sport->port.lock, flags);
494 static irqreturn_t imx_txint(int irq, void *dev_id)
496 struct imx_port *sport = dev_id;
497 struct circ_buf *xmit = &sport->port.state->xmit;
500 spin_lock_irqsave(&sport->port.lock, flags);
501 if (sport->port.x_char) {
503 writel(sport->port.x_char, sport->port.membase + URTX0);
507 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
508 imx_stop_tx(&sport->port);
512 imx_transmit_buffer(sport);
514 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
515 uart_write_wakeup(&sport->port);
518 spin_unlock_irqrestore(&sport->port.lock, flags);
522 static irqreturn_t imx_rxint(int irq, void *dev_id)
524 struct imx_port *sport = dev_id;
525 unsigned int rx, flg, ignored = 0;
526 struct tty_port *port = &sport->port.state->port;
527 unsigned long flags, temp;
529 spin_lock_irqsave(&sport->port.lock, flags);
531 while (readl(sport->port.membase + USR2) & USR2_RDR) {
533 sport->port.icount.rx++;
535 rx = readl(sport->port.membase + URXD0);
537 temp = readl(sport->port.membase + USR2);
538 if (temp & USR2_BRCD) {
539 writel(USR2_BRCD, sport->port.membase + USR2);
540 if (uart_handle_break(&sport->port))
544 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
547 if (unlikely(rx & URXD_ERR)) {
549 sport->port.icount.brk++;
550 else if (rx & URXD_PRERR)
551 sport->port.icount.parity++;
552 else if (rx & URXD_FRMERR)
553 sport->port.icount.frame++;
554 if (rx & URXD_OVRRUN)
555 sport->port.icount.overrun++;
557 if (rx & sport->port.ignore_status_mask) {
563 rx &= sport->port.read_status_mask;
567 else if (rx & URXD_PRERR)
569 else if (rx & URXD_FRMERR)
571 if (rx & URXD_OVRRUN)
575 sport->port.sysrq = 0;
579 tty_insert_flip_char(port, rx, flg);
583 spin_unlock_irqrestore(&sport->port.lock, flags);
584 tty_flip_buffer_push(port);
588 static irqreturn_t imx_int(int irq, void *dev_id)
590 struct imx_port *sport = dev_id;
594 sts = readl(sport->port.membase + USR1);
597 imx_rxint(irq, dev_id);
599 if (sts & USR1_TRDY &&
600 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN)
601 imx_txint(irq, dev_id);
604 imx_rtsint(irq, dev_id);
606 if (sts & USR1_AWAKE)
607 writel(USR1_AWAKE, sport->port.membase + USR1);
609 sts2 = readl(sport->port.membase + USR2);
610 if (sts2 & USR2_ORE) {
611 dev_err(sport->port.dev, "Rx FIFO overrun\n");
612 sport->port.icount.overrun++;
613 writel(sts2 | USR2_ORE, sport->port.membase + USR2);
620 * Return TIOCSER_TEMT when transmitter is not busy.
622 static unsigned int imx_tx_empty(struct uart_port *port)
624 struct imx_port *sport = (struct imx_port *)port;
626 return (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
630 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
632 static unsigned int imx_get_mctrl(struct uart_port *port)
634 struct imx_port *sport = (struct imx_port *)port;
635 unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
637 if (readl(sport->port.membase + USR1) & USR1_RTSS)
640 if (readl(sport->port.membase + UCR2) & UCR2_CTS)
646 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
648 struct imx_port *sport = (struct imx_port *)port;
651 temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS;
653 if (mctrl & TIOCM_RTS)
656 writel(temp, sport->port.membase + UCR2);
660 * Interrupts always disabled.
662 static void imx_break_ctl(struct uart_port *port, int break_state)
664 struct imx_port *sport = (struct imx_port *)port;
665 unsigned long flags, temp;
667 spin_lock_irqsave(&sport->port.lock, flags);
669 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
671 if (break_state != 0)
674 writel(temp, sport->port.membase + UCR1);
676 spin_unlock_irqrestore(&sport->port.lock, flags);
679 #define TXTL 2 /* reset default */
680 #define RXTL 1 /* reset default */
682 static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
686 /* set receiver / transmitter trigger level */
687 val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
688 val |= TXTL << UFCR_TXTL_SHF | RXTL;
689 writel(val, sport->port.membase + UFCR);
693 /* half the RX buffer size */
696 static int imx_startup(struct uart_port *port)
698 struct imx_port *sport = (struct imx_port *)port;
700 unsigned long flags, temp;
702 imx_setup_ufcr(sport, 0);
704 /* disable the DREN bit (Data Ready interrupt enable) before
707 temp = readl(sport->port.membase + UCR4);
712 /* set the trigger level for CTS */
713 temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
714 temp |= CTSTL << UCR4_CTSTL_SHF;
716 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
718 if (USE_IRDA(sport)) {
719 /* reset fifo's and state machines */
721 temp = readl(sport->port.membase + UCR2);
723 writel(temp, sport->port.membase + UCR2);
724 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) &&
731 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
732 * chips only have one interrupt.
734 if (sport->txirq > 0) {
735 retval = request_irq(sport->rxirq, imx_rxint, 0,
740 retval = request_irq(sport->txirq, imx_txint, 0,
745 /* do not use RTS IRQ on IrDA */
746 if (!USE_IRDA(sport)) {
747 retval = request_irq(sport->rtsirq, imx_rtsint, 0,
753 retval = request_irq(sport->port.irq, imx_int, 0,
756 free_irq(sport->port.irq, sport);
761 spin_lock_irqsave(&sport->port.lock, flags);
763 * Finally, clear and enable interrupts
765 writel(USR1_RTSD, sport->port.membase + USR1);
767 temp = readl(sport->port.membase + UCR1);
768 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
770 if (USE_IRDA(sport)) {
772 temp &= ~(UCR1_RTSDEN);
775 writel(temp, sport->port.membase + UCR1);
777 temp = readl(sport->port.membase + UCR2);
778 temp |= (UCR2_RXEN | UCR2_TXEN);
779 writel(temp, sport->port.membase + UCR2);
781 if (USE_IRDA(sport)) {
785 (readl(sport->port.membase + URXD0) & URXD_CHARRDY)) {
790 if (is_imx21_uart(sport)) {
791 temp = readl(sport->port.membase + UCR3);
792 temp |= IMX21_UCR3_RXDMUXSEL;
793 writel(temp, sport->port.membase + UCR3);
796 if (USE_IRDA(sport)) {
797 temp = readl(sport->port.membase + UCR4);
798 if (sport->irda_inv_rx)
801 temp &= ~(UCR4_INVR);
802 writel(temp | UCR4_DREN, sport->port.membase + UCR4);
804 temp = readl(sport->port.membase + UCR3);
805 if (sport->irda_inv_tx)
808 temp &= ~(UCR3_INVT);
809 writel(temp, sport->port.membase + UCR3);
813 * Enable modem status interrupts
815 imx_enable_ms(&sport->port);
816 spin_unlock_irqrestore(&sport->port.lock, flags);
818 if (USE_IRDA(sport)) {
819 struct imxuart_platform_data *pdata;
820 pdata = sport->port.dev->platform_data;
821 sport->irda_inv_rx = pdata->irda_inv_rx;
822 sport->irda_inv_tx = pdata->irda_inv_tx;
823 sport->trcv_delay = pdata->transceiver_delay;
824 if (pdata->irda_enable)
825 pdata->irda_enable(1);
832 free_irq(sport->txirq, sport);
835 free_irq(sport->rxirq, sport);
840 static void imx_shutdown(struct uart_port *port)
842 struct imx_port *sport = (struct imx_port *)port;
846 spin_lock_irqsave(&sport->port.lock, flags);
847 temp = readl(sport->port.membase + UCR2);
848 temp &= ~(UCR2_TXEN);
849 writel(temp, sport->port.membase + UCR2);
850 spin_unlock_irqrestore(&sport->port.lock, flags);
852 if (USE_IRDA(sport)) {
853 struct imxuart_platform_data *pdata;
854 pdata = sport->port.dev->platform_data;
855 if (pdata->irda_enable)
856 pdata->irda_enable(0);
862 del_timer_sync(&sport->timer);
865 * Free the interrupts
867 if (sport->txirq > 0) {
868 if (!USE_IRDA(sport))
869 free_irq(sport->rtsirq, sport);
870 free_irq(sport->txirq, sport);
871 free_irq(sport->rxirq, sport);
873 free_irq(sport->port.irq, sport);
876 * Disable all interrupts, port and break condition.
879 spin_lock_irqsave(&sport->port.lock, flags);
880 temp = readl(sport->port.membase + UCR1);
881 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
883 temp &= ~(UCR1_IREN);
885 writel(temp, sport->port.membase + UCR1);
886 spin_unlock_irqrestore(&sport->port.lock, flags);
890 imx_set_termios(struct uart_port *port, struct ktermios *termios,
891 struct ktermios *old)
893 struct imx_port *sport = (struct imx_port *)port;
895 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
896 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
897 unsigned int div, ufcr;
898 unsigned long num, denom;
902 * If we don't support modem control lines, don't allow
906 termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
907 termios->c_cflag |= CLOCAL;
911 * We only support CS7 and CS8.
913 while ((termios->c_cflag & CSIZE) != CS7 &&
914 (termios->c_cflag & CSIZE) != CS8) {
915 termios->c_cflag &= ~CSIZE;
916 termios->c_cflag |= old_csize;
920 if ((termios->c_cflag & CSIZE) == CS8)
921 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
923 ucr2 = UCR2_SRST | UCR2_IRTS;
925 if (termios->c_cflag & CRTSCTS) {
926 if (sport->have_rtscts) {
930 termios->c_cflag &= ~CRTSCTS;
934 if (termios->c_cflag & CSTOPB)
936 if (termios->c_cflag & PARENB) {
938 if (termios->c_cflag & PARODD)
942 del_timer_sync(&sport->timer);
945 * Ask the core to calculate the divisor for us.
947 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
948 quot = uart_get_divisor(port, baud);
950 spin_lock_irqsave(&sport->port.lock, flags);
952 sport->port.read_status_mask = 0;
953 if (termios->c_iflag & INPCK)
954 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
955 if (termios->c_iflag & (BRKINT | PARMRK))
956 sport->port.read_status_mask |= URXD_BRK;
959 * Characters to ignore
961 sport->port.ignore_status_mask = 0;
962 if (termios->c_iflag & IGNPAR)
963 sport->port.ignore_status_mask |= URXD_PRERR;
964 if (termios->c_iflag & IGNBRK) {
965 sport->port.ignore_status_mask |= URXD_BRK;
967 * If we're ignoring parity and break indicators,
968 * ignore overruns too (for real raw support).
970 if (termios->c_iflag & IGNPAR)
971 sport->port.ignore_status_mask |= URXD_OVRRUN;
975 * Update the per-port timeout.
977 uart_update_timeout(port, termios->c_cflag, baud);
980 * disable interrupts and drain transmitter
982 old_ucr1 = readl(sport->port.membase + UCR1);
983 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
984 sport->port.membase + UCR1);
986 while (!(readl(sport->port.membase + USR2) & USR2_TXDC))
989 /* then, disable everything */
990 old_txrxen = readl(sport->port.membase + UCR2);
991 writel(old_txrxen & ~(UCR2_TXEN | UCR2_RXEN),
992 sport->port.membase + UCR2);
993 old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
995 if (USE_IRDA(sport)) {
997 * use maximum available submodule frequency to
998 * avoid missing short pulses due to low sampling rate
1002 div = sport->port.uartclk / (baud * 16);
1009 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1010 1 << 16, 1 << 16, &num, &denom);
1012 tdiv64 = sport->port.uartclk;
1014 do_div(tdiv64, denom * 16 * div);
1015 tty_termios_encode_baud_rate(termios,
1016 (speed_t)tdiv64, (speed_t)tdiv64);
1021 ufcr = readl(sport->port.membase + UFCR);
1022 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1023 writel(ufcr, sport->port.membase + UFCR);
1025 writel(num, sport->port.membase + UBIR);
1026 writel(denom, sport->port.membase + UBMR);
1028 if (is_imx21_uart(sport))
1029 writel(sport->port.uartclk / div / 1000,
1030 sport->port.membase + IMX21_ONEMS);
1032 writel(old_ucr1, sport->port.membase + UCR1);
1034 /* set the parity, stop bits and data size */
1035 writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
1037 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1038 imx_enable_ms(&sport->port);
1040 spin_unlock_irqrestore(&sport->port.lock, flags);
1043 static const char *imx_type(struct uart_port *port)
1045 struct imx_port *sport = (struct imx_port *)port;
1047 return sport->port.type == PORT_IMX ? "IMX" : NULL;
1051 * Release the memory region(s) being used by 'port'.
1053 static void imx_release_port(struct uart_port *port)
1055 struct platform_device *pdev = to_platform_device(port->dev);
1056 struct resource *mmres;
1058 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1059 release_mem_region(mmres->start, resource_size(mmres));
1063 * Request the memory region(s) being used by 'port'.
1065 static int imx_request_port(struct uart_port *port)
1067 struct platform_device *pdev = to_platform_device(port->dev);
1068 struct resource *mmres;
1071 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1075 ret = request_mem_region(mmres->start, resource_size(mmres), "imx-uart");
1077 return ret ? 0 : -EBUSY;
1081 * Configure/autoconfigure the port.
1083 static void imx_config_port(struct uart_port *port, int flags)
1085 struct imx_port *sport = (struct imx_port *)port;
1087 if (flags & UART_CONFIG_TYPE &&
1088 imx_request_port(&sport->port) == 0)
1089 sport->port.type = PORT_IMX;
1093 * Verify the new serial_struct (for TIOCSSERIAL).
1094 * The only change we allow are to the flags and type, and
1095 * even then only between PORT_IMX and PORT_UNKNOWN
1098 imx_verify_port(struct uart_port *port, struct serial_struct *ser)
1100 struct imx_port *sport = (struct imx_port *)port;
1103 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1105 if (sport->port.irq != ser->irq)
1107 if (ser->io_type != UPIO_MEM)
1109 if (sport->port.uartclk / 16 != ser->baud_base)
1111 if ((void *)sport->port.mapbase != ser->iomem_base)
1113 if (sport->port.iobase != ser->port)
1120 #if defined(CONFIG_CONSOLE_POLL)
1121 static int imx_poll_get_char(struct uart_port *port)
1123 struct imx_port_ucrs old_ucr;
1124 unsigned int status;
1127 /* save control registers */
1128 imx_port_ucrs_save(port, &old_ucr);
1130 /* disable interrupts */
1131 writel(UCR1_UARTEN, port->membase + UCR1);
1132 writel(old_ucr.ucr2 & ~(UCR2_ATEN | UCR2_RTSEN | UCR2_ESCI),
1133 port->membase + UCR2);
1134 writel(old_ucr.ucr3 & ~(UCR3_DCD | UCR3_RI | UCR3_DTREN),
1135 port->membase + UCR3);
1139 status = readl(port->membase + USR2);
1140 } while (~status & USR2_RDR);
1143 c = readl(port->membase + URXD0);
1145 /* restore control registers */
1146 imx_port_ucrs_restore(port, &old_ucr);
1151 static void imx_poll_put_char(struct uart_port *port, unsigned char c)
1153 struct imx_port_ucrs old_ucr;
1154 unsigned int status;
1156 /* save control registers */
1157 imx_port_ucrs_save(port, &old_ucr);
1159 /* disable interrupts */
1160 writel(UCR1_UARTEN, port->membase + UCR1);
1161 writel(old_ucr.ucr2 & ~(UCR2_ATEN | UCR2_RTSEN | UCR2_ESCI),
1162 port->membase + UCR2);
1163 writel(old_ucr.ucr3 & ~(UCR3_DCD | UCR3_RI | UCR3_DTREN),
1164 port->membase + UCR3);
1168 status = readl(port->membase + USR1);
1169 } while (~status & USR1_TRDY);
1172 writel(c, port->membase + URTX0);
1176 status = readl(port->membase + USR2);
1177 } while (~status & USR2_TXDC);
1179 /* restore control registers */
1180 imx_port_ucrs_restore(port, &old_ucr);
1184 static struct uart_ops imx_pops = {
1185 .tx_empty = imx_tx_empty,
1186 .set_mctrl = imx_set_mctrl,
1187 .get_mctrl = imx_get_mctrl,
1188 .stop_tx = imx_stop_tx,
1189 .start_tx = imx_start_tx,
1190 .stop_rx = imx_stop_rx,
1191 .enable_ms = imx_enable_ms,
1192 .break_ctl = imx_break_ctl,
1193 .startup = imx_startup,
1194 .shutdown = imx_shutdown,
1195 .set_termios = imx_set_termios,
1197 .release_port = imx_release_port,
1198 .request_port = imx_request_port,
1199 .config_port = imx_config_port,
1200 .verify_port = imx_verify_port,
1201 #if defined(CONFIG_CONSOLE_POLL)
1202 .poll_get_char = imx_poll_get_char,
1203 .poll_put_char = imx_poll_put_char,
1207 static struct imx_port *imx_ports[UART_NR];
1209 #ifdef CONFIG_SERIAL_IMX_CONSOLE
1210 static void imx_console_putchar(struct uart_port *port, int ch)
1212 struct imx_port *sport = (struct imx_port *)port;
1214 while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)
1217 writel(ch, sport->port.membase + URTX0);
1221 * Interrupts are disabled on entering
1224 imx_console_write(struct console *co, const char *s, unsigned int count)
1226 struct imx_port *sport = imx_ports[co->index];
1227 struct imx_port_ucrs old_ucr;
1229 unsigned long flags = 0;
1232 if (sport->port.sysrq)
1234 else if (oops_in_progress)
1235 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1237 spin_lock_irqsave(&sport->port.lock, flags);
1240 * First, save UCR1/2/3 and then disable interrupts
1242 imx_port_ucrs_save(&sport->port, &old_ucr);
1243 ucr1 = old_ucr.ucr1;
1245 if (is_imx1_uart(sport))
1246 ucr1 |= IMX1_UCR1_UARTCLKEN;
1247 ucr1 |= UCR1_UARTEN;
1248 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1250 writel(ucr1, sport->port.membase + UCR1);
1252 writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
1254 uart_console_write(&sport->port, s, count, imx_console_putchar);
1257 * Finally, wait for transmitter to become empty
1258 * and restore UCR1/2/3
1260 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
1262 imx_port_ucrs_restore(&sport->port, &old_ucr);
1265 spin_unlock_irqrestore(&sport->port.lock, flags);
1269 * If the port was already initialised (eg, by a boot loader),
1270 * try to determine the current setup.
1273 imx_console_get_options(struct imx_port *sport, int *baud,
1274 int *parity, int *bits)
1277 if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {
1278 /* ok, the port was enabled */
1279 unsigned int ucr2, ubir, ubmr, uartclk;
1280 unsigned int baud_raw;
1281 unsigned int ucfr_rfdiv;
1283 ucr2 = readl(sport->port.membase + UCR2);
1286 if (ucr2 & UCR2_PREN) {
1287 if (ucr2 & UCR2_PROE)
1298 ubir = readl(sport->port.membase + UBIR) & 0xffff;
1299 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
1301 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
1302 if (ucfr_rfdiv == 6)
1305 ucfr_rfdiv = 6 - ucfr_rfdiv;
1307 uartclk = clk_get_rate(sport->clk_per);
1308 uartclk /= ucfr_rfdiv;
1311 * The next code provides exact computation of
1312 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1313 * without need of float support or long long division,
1314 * which would be required to prevent 32bit arithmetic overflow
1316 unsigned int mul = ubir + 1;
1317 unsigned int div = 16 * (ubmr + 1);
1318 unsigned int rem = uartclk % div;
1320 baud_raw = (uartclk / div) * mul;
1321 baud_raw += (rem * mul + div / 2) / div;
1322 *baud = (baud_raw + 50) / 100 * 100;
1325 if (*baud != baud_raw)
1326 pr_info("Console IMX rounded baud rate from %d to %d\n",
1332 imx_console_setup(struct console *co, char *options)
1334 struct imx_port *sport;
1341 * Check whether an invalid uart number has been specified, and
1342 * if so, search for the first available port that does have
1345 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1347 sport = imx_ports[co->index];
1352 uart_parse_options(options, &baud, &parity, &bits, &flow);
1354 imx_console_get_options(sport, &baud, &parity, &bits);
1356 imx_setup_ufcr(sport, 0);
1358 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
1361 static struct uart_driver imx_reg;
1362 static struct console imx_console = {
1364 .write = imx_console_write,
1365 .device = uart_console_device,
1366 .setup = imx_console_setup,
1367 .flags = CON_PRINTBUFFER,
1372 #define IMX_CONSOLE &imx_console
1374 #define IMX_CONSOLE NULL
1377 static struct uart_driver imx_reg = {
1378 .owner = THIS_MODULE,
1379 .driver_name = DRIVER_NAME,
1380 .dev_name = DEV_NAME,
1381 .major = SERIAL_IMX_MAJOR,
1382 .minor = MINOR_START,
1383 .nr = ARRAY_SIZE(imx_ports),
1384 .cons = IMX_CONSOLE,
1387 static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)
1389 struct imx_port *sport = platform_get_drvdata(dev);
1392 /* enable wakeup from i.MX UART */
1393 val = readl(sport->port.membase + UCR3);
1395 writel(val, sport->port.membase + UCR3);
1397 uart_suspend_port(&imx_reg, &sport->port);
1402 static int serial_imx_resume(struct platform_device *dev)
1404 struct imx_port *sport = platform_get_drvdata(dev);
1407 /* disable wakeup from i.MX UART */
1408 val = readl(sport->port.membase + UCR3);
1409 val &= ~UCR3_AWAKEN;
1410 writel(val, sport->port.membase + UCR3);
1412 uart_resume_port(&imx_reg, &sport->port);
1419 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
1420 * could successfully get all information from dt or a negative errno.
1422 static int serial_imx_probe_dt(struct imx_port *sport,
1423 struct platform_device *pdev)
1425 struct device_node *np = pdev->dev.of_node;
1426 const struct of_device_id *of_id =
1427 of_match_device(imx_uart_dt_ids, &pdev->dev);
1431 /* no device tree device */
1434 ret = of_alias_get_id(np, "serial");
1436 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
1439 sport->port.line = ret;
1441 if (of_get_property(np, "fsl,uart-has-rtscts", NULL))
1442 sport->have_rtscts = 1;
1444 if (of_get_property(np, "fsl,irda-mode", NULL))
1445 sport->use_irda = 1;
1447 sport->devdata = of_id->data;
1452 static inline int serial_imx_probe_dt(struct imx_port *sport,
1453 struct platform_device *pdev)
1459 static void serial_imx_probe_pdata(struct imx_port *sport,
1460 struct platform_device *pdev)
1462 struct imxuart_platform_data *pdata = pdev->dev.platform_data;
1464 sport->port.line = pdev->id;
1465 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data;
1470 if (pdata->flags & IMXUART_HAVE_RTSCTS)
1471 sport->have_rtscts = 1;
1473 if (pdata->flags & IMXUART_IRDA)
1474 sport->use_irda = 1;
1477 static int serial_imx_probe(struct platform_device *pdev)
1479 struct imx_port *sport;
1480 struct imxuart_platform_data *pdata;
1483 struct resource *res;
1484 struct pinctrl *pinctrl;
1486 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
1490 ret = serial_imx_probe_dt(sport, pdev);
1492 serial_imx_probe_pdata(sport, pdev);
1496 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1500 base = devm_ioremap(&pdev->dev, res->start, PAGE_SIZE);
1504 sport->port.dev = &pdev->dev;
1505 sport->port.mapbase = res->start;
1506 sport->port.membase = base;
1507 sport->port.type = PORT_IMX,
1508 sport->port.iotype = UPIO_MEM;
1509 sport->port.irq = platform_get_irq(pdev, 0);
1510 sport->rxirq = platform_get_irq(pdev, 0);
1511 sport->txirq = platform_get_irq(pdev, 1);
1512 sport->rtsirq = platform_get_irq(pdev, 2);
1513 sport->port.fifosize = 32;
1514 sport->port.ops = &imx_pops;
1515 sport->port.flags = UPF_BOOT_AUTOCONF;
1516 init_timer(&sport->timer);
1517 sport->timer.function = imx_timeout;
1518 sport->timer.data = (unsigned long)sport;
1520 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1521 if (IS_ERR(pinctrl)) {
1522 ret = PTR_ERR(pinctrl);
1523 dev_err(&pdev->dev, "failed to get default pinctrl: %d\n", ret);
1527 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1528 if (IS_ERR(sport->clk_ipg)) {
1529 ret = PTR_ERR(sport->clk_ipg);
1530 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
1534 sport->clk_per = devm_clk_get(&pdev->dev, "per");
1535 if (IS_ERR(sport->clk_per)) {
1536 ret = PTR_ERR(sport->clk_per);
1537 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
1541 clk_prepare_enable(sport->clk_per);
1542 clk_prepare_enable(sport->clk_ipg);
1544 sport->port.uartclk = clk_get_rate(sport->clk_per);
1546 imx_ports[sport->port.line] = sport;
1548 pdata = pdev->dev.platform_data;
1549 if (pdata && pdata->init) {
1550 ret = pdata->init(pdev);
1555 ret = uart_add_one_port(&imx_reg, &sport->port);
1558 platform_set_drvdata(pdev, sport);
1562 if (pdata && pdata->exit)
1565 clk_disable_unprepare(sport->clk_per);
1566 clk_disable_unprepare(sport->clk_ipg);
1570 static int serial_imx_remove(struct platform_device *pdev)
1572 struct imxuart_platform_data *pdata;
1573 struct imx_port *sport = platform_get_drvdata(pdev);
1575 pdata = pdev->dev.platform_data;
1577 platform_set_drvdata(pdev, NULL);
1579 uart_remove_one_port(&imx_reg, &sport->port);
1581 clk_disable_unprepare(sport->clk_per);
1582 clk_disable_unprepare(sport->clk_ipg);
1584 if (pdata && pdata->exit)
1590 static struct platform_driver serial_imx_driver = {
1591 .probe = serial_imx_probe,
1592 .remove = serial_imx_remove,
1594 .suspend = serial_imx_suspend,
1595 .resume = serial_imx_resume,
1596 .id_table = imx_uart_devtype,
1599 .owner = THIS_MODULE,
1600 .of_match_table = imx_uart_dt_ids,
1604 static int __init imx_serial_init(void)
1608 pr_info("Serial: IMX driver\n");
1610 ret = uart_register_driver(&imx_reg);
1614 ret = platform_driver_register(&serial_imx_driver);
1616 uart_unregister_driver(&imx_reg);
1621 static void __exit imx_serial_exit(void)
1623 platform_driver_unregister(&serial_imx_driver);
1624 uart_unregister_driver(&imx_reg);
1627 module_init(imx_serial_init);
1628 module_exit(imx_serial_exit);
1630 MODULE_AUTHOR("Sascha Hauer");
1631 MODULE_DESCRIPTION("IMX generic serial port driver");
1632 MODULE_LICENSE("GPL");
1633 MODULE_ALIAS("platform:imx-uart");