2 * Driver for Motorola IMX serial ports
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Author: Sascha Hauer <sascha@saschahauer.de>
7 * Copyright (C) 2004 Pengutronix
9 * Copyright (C) 2009 emlix GmbH
10 * Author: Fabian Godehardt (added IrDA support for iMX)
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 * [29-Mar-2005] Mike Lee
27 * Added hardware handshake
30 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
34 #include <linux/module.h>
35 #include <linux/ioport.h>
36 #include <linux/init.h>
37 #include <linux/console.h>
38 #include <linux/sysrq.h>
39 #include <linux/platform_device.h>
40 #include <linux/tty.h>
41 #include <linux/tty_flip.h>
42 #include <linux/serial_core.h>
43 #include <linux/serial.h>
44 #include <linux/clk.h>
45 #include <linux/delay.h>
46 #include <linux/rational.h>
47 #include <linux/slab.h>
49 #include <linux/of_device.h>
51 #include <linux/dma-mapping.h>
54 #include <linux/platform_data/serial-imx.h>
55 #include <linux/platform_data/dma-imx.h>
57 /* Register definitions */
58 #define URXD0 0x0 /* Receiver Register */
59 #define URTX0 0x40 /* Transmitter Register */
60 #define UCR1 0x80 /* Control Register 1 */
61 #define UCR2 0x84 /* Control Register 2 */
62 #define UCR3 0x88 /* Control Register 3 */
63 #define UCR4 0x8c /* Control Register 4 */
64 #define UFCR 0x90 /* FIFO Control Register */
65 #define USR1 0x94 /* Status Register 1 */
66 #define USR2 0x98 /* Status Register 2 */
67 #define UESC 0x9c /* Escape Character Register */
68 #define UTIM 0xa0 /* Escape Timer Register */
69 #define UBIR 0xa4 /* BRM Incremental Register */
70 #define UBMR 0xa8 /* BRM Modulator Register */
71 #define UBRC 0xac /* Baud Rate Count Register */
72 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
73 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
74 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
76 /* UART Control Register Bit Fields.*/
77 #define URXD_DUMMY_READ (1<<16)
78 #define URXD_CHARRDY (1<<15)
79 #define URXD_ERR (1<<14)
80 #define URXD_OVRRUN (1<<13)
81 #define URXD_FRMERR (1<<12)
82 #define URXD_BRK (1<<11)
83 #define URXD_PRERR (1<<10)
84 #define URXD_RX_DATA (0xFF<<0)
85 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */
86 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
87 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
88 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
89 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
90 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
91 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
92 #define UCR1_IREN (1<<7) /* Infrared interface enable */
93 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
94 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
95 #define UCR1_SNDBRK (1<<4) /* Send break */
96 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
97 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
98 #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
99 #define UCR1_DOZE (1<<1) /* Doze */
100 #define UCR1_UARTEN (1<<0) /* UART enabled */
101 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
102 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
103 #define UCR2_CTSC (1<<13) /* CTS pin control */
104 #define UCR2_CTS (1<<12) /* Clear to send */
105 #define UCR2_ESCEN (1<<11) /* Escape enable */
106 #define UCR2_PREN (1<<8) /* Parity enable */
107 #define UCR2_PROE (1<<7) /* Parity odd/even */
108 #define UCR2_STPB (1<<6) /* Stop */
109 #define UCR2_WS (1<<5) /* Word size */
110 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
111 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */
112 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
113 #define UCR2_RXEN (1<<1) /* Receiver enabled */
114 #define UCR2_SRST (1<<0) /* SW reset */
115 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
116 #define UCR3_PARERREN (1<<12) /* Parity enable */
117 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
118 #define UCR3_DSR (1<<10) /* Data set ready */
119 #define UCR3_DCD (1<<9) /* Data carrier detect */
120 #define UCR3_RI (1<<8) /* Ring indicator */
121 #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
122 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
123 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
124 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
125 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
126 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
127 #define UCR3_BPEN (1<<0) /* Preset registers enable */
128 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
129 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
130 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
131 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
132 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
133 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
134 #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
135 #define UCR4_IRSC (1<<5) /* IR special case */
136 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
137 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
138 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
139 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
140 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
141 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
142 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
143 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
144 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
145 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
146 #define USR1_RTSS (1<<14) /* RTS pin status */
147 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
148 #define USR1_RTSD (1<<12) /* RTS delta */
149 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
150 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
151 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
152 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
153 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
154 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
155 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
156 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
157 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
158 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
159 #define USR2_IDLE (1<<12) /* Idle condition */
160 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
161 #define USR2_WAKE (1<<7) /* Wake */
162 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
163 #define USR2_TXDC (1<<3) /* Transmitter complete */
164 #define USR2_BRCD (1<<2) /* Break condition */
165 #define USR2_ORE (1<<1) /* Overrun error */
166 #define USR2_RDR (1<<0) /* Recv data ready */
167 #define UTS_FRCPERR (1<<13) /* Force parity error */
168 #define UTS_LOOP (1<<12) /* Loop tx and rx */
169 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
170 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
171 #define UTS_TXFULL (1<<4) /* TxFIFO full */
172 #define UTS_RXFULL (1<<3) /* RxFIFO full */
173 #define UTS_SOFTRST (1<<0) /* Software reset */
175 /* We've been assigned a range on the "Low-density serial ports" major */
176 #define SERIAL_IMX_MAJOR 207
177 #define MINOR_START 16
178 #define DEV_NAME "ttymxc"
181 * This determines how often we check the modem status signals
182 * for any change. They generally aren't connected to an IRQ
183 * so we have to poll them. We also check immediately before
184 * filling the TX fifo incase CTS has been dropped.
186 #define MCTRL_TIMEOUT (250*HZ/1000)
188 #define DRIVER_NAME "IMX-uart"
192 /* i.mx21 type uart runs on all i.mx except i.mx1 */
199 /* device type dependent stuff */
200 struct imx_uart_data {
202 enum imx_uart_type devtype;
206 struct uart_port port;
207 struct timer_list timer;
208 unsigned int old_status;
209 int txirq, rxirq, rtsirq;
210 unsigned int have_rtscts:1;
211 unsigned int dte_mode:1;
212 unsigned int use_irda:1;
213 unsigned int irda_inv_rx:1;
214 unsigned int irda_inv_tx:1;
215 unsigned short trcv_delay; /* transceiver delay */
218 const struct imx_uart_data *devdata;
221 unsigned int dma_is_inited:1;
222 unsigned int dma_is_enabled:1;
223 unsigned int dma_is_rxing:1;
224 unsigned int dma_is_txing:1;
225 struct dma_chan *dma_chan_rx, *dma_chan_tx;
226 struct scatterlist rx_sgl, tx_sgl[2];
228 unsigned int tx_bytes;
229 unsigned int dma_tx_nents;
230 wait_queue_head_t dma_wait;
233 struct imx_port_ucrs {
240 #define USE_IRDA(sport) ((sport)->use_irda)
242 #define USE_IRDA(sport) (0)
245 static struct imx_uart_data imx_uart_devdata[] = {
248 .devtype = IMX1_UART,
251 .uts_reg = IMX21_UTS,
252 .devtype = IMX21_UART,
255 .uts_reg = IMX21_UTS,
256 .devtype = IMX6Q_UART,
260 static struct platform_device_id imx_uart_devtype[] = {
263 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
265 .name = "imx21-uart",
266 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
268 .name = "imx6q-uart",
269 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART],
274 MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
276 static struct of_device_id imx_uart_dt_ids[] = {
277 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
278 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
279 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
282 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
284 static inline unsigned uts_reg(struct imx_port *sport)
286 return sport->devdata->uts_reg;
289 static inline int is_imx1_uart(struct imx_port *sport)
291 return sport->devdata->devtype == IMX1_UART;
294 static inline int is_imx21_uart(struct imx_port *sport)
296 return sport->devdata->devtype == IMX21_UART;
299 static inline int is_imx6q_uart(struct imx_port *sport)
301 return sport->devdata->devtype == IMX6Q_UART;
304 * Save and restore functions for UCR1, UCR2 and UCR3 registers
306 #if defined(CONFIG_SERIAL_IMX_CONSOLE)
307 static void imx_port_ucrs_save(struct uart_port *port,
308 struct imx_port_ucrs *ucr)
310 /* save control registers */
311 ucr->ucr1 = readl(port->membase + UCR1);
312 ucr->ucr2 = readl(port->membase + UCR2);
313 ucr->ucr3 = readl(port->membase + UCR3);
316 static void imx_port_ucrs_restore(struct uart_port *port,
317 struct imx_port_ucrs *ucr)
319 /* restore control registers */
320 writel(ucr->ucr1, port->membase + UCR1);
321 writel(ucr->ucr2, port->membase + UCR2);
322 writel(ucr->ucr3, port->membase + UCR3);
327 * Handle any change of modem status signal since we were last called.
329 static void imx_mctrl_check(struct imx_port *sport)
331 unsigned int status, changed;
333 status = sport->port.ops->get_mctrl(&sport->port);
334 changed = status ^ sport->old_status;
339 sport->old_status = status;
341 if (changed & TIOCM_RI)
342 sport->port.icount.rng++;
343 if (changed & TIOCM_DSR)
344 sport->port.icount.dsr++;
345 if (changed & TIOCM_CAR)
346 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
347 if (changed & TIOCM_CTS)
348 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
350 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
354 * This is our per-port timeout handler, for checking the
355 * modem status signals.
357 static void imx_timeout(unsigned long data)
359 struct imx_port *sport = (struct imx_port *)data;
362 if (sport->port.state) {
363 spin_lock_irqsave(&sport->port.lock, flags);
364 imx_mctrl_check(sport);
365 spin_unlock_irqrestore(&sport->port.lock, flags);
367 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
372 * interrupts disabled on entry
374 static void imx_stop_tx(struct uart_port *port)
376 struct imx_port *sport = (struct imx_port *)port;
379 if (USE_IRDA(sport)) {
380 /* half duplex - wait for end of transmission */
383 !(readl(sport->port.membase + USR2) & USR2_TXDC)) {
388 * irda transceiver - wait a bit more to avoid
389 * cutoff, hardware dependent
391 udelay(sport->trcv_delay);
394 * half duplex - reactivate receive mode,
395 * flush receive pipe echo crap
397 if (readl(sport->port.membase + USR2) & USR2_TXDC) {
398 temp = readl(sport->port.membase + UCR1);
399 temp &= ~(UCR1_TXMPTYEN | UCR1_TRDYEN);
400 writel(temp, sport->port.membase + UCR1);
402 temp = readl(sport->port.membase + UCR4);
403 temp &= ~(UCR4_TCEN);
404 writel(temp, sport->port.membase + UCR4);
406 while (readl(sport->port.membase + URXD0) &
410 temp = readl(sport->port.membase + UCR1);
412 writel(temp, sport->port.membase + UCR1);
414 temp = readl(sport->port.membase + UCR4);
416 writel(temp, sport->port.membase + UCR4);
422 * We are maybe in the SMP context, so if the DMA TX thread is running
423 * on other cpu, we have to wait for it to finish.
425 if (sport->dma_is_enabled && sport->dma_is_txing)
428 temp = readl(sport->port.membase + UCR1);
429 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
433 * interrupts disabled on entry
435 static void imx_stop_rx(struct uart_port *port)
437 struct imx_port *sport = (struct imx_port *)port;
440 if (sport->dma_is_enabled && sport->dma_is_rxing) {
441 if (sport->port.suspended) {
442 dmaengine_terminate_all(sport->dma_chan_rx);
443 sport->dma_is_rxing = 0;
449 temp = readl(sport->port.membase + UCR2);
450 writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2);
452 /* disable the `Receiver Ready Interrrupt` */
453 temp = readl(sport->port.membase + UCR1);
454 writel(temp & ~UCR1_RRDYEN, sport->port.membase + UCR1);
458 * Set the modem control timer to fire immediately.
460 static void imx_enable_ms(struct uart_port *port)
462 struct imx_port *sport = (struct imx_port *)port;
464 mod_timer(&sport->timer, jiffies);
467 static inline void imx_transmit_buffer(struct imx_port *sport)
469 struct circ_buf *xmit = &sport->port.state->xmit;
471 if (sport->port.x_char) {
473 writel(sport->port.x_char, sport->port.membase + URTX0);
477 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
478 imx_stop_tx(&sport->port);
482 while (!uart_circ_empty(xmit) &&
483 !(readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)) {
484 /* send xmit->buf[xmit->tail]
485 * out the port here */
486 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
487 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
488 sport->port.icount.tx++;
491 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
492 uart_write_wakeup(&sport->port);
494 if (uart_circ_empty(xmit))
495 imx_stop_tx(&sport->port);
498 static void dma_tx_callback(void *data)
500 struct imx_port *sport = data;
501 struct scatterlist *sgl = &sport->tx_sgl[0];
502 struct circ_buf *xmit = &sport->port.state->xmit;
505 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
507 sport->dma_is_txing = 0;
509 /* update the stat */
510 spin_lock_irqsave(&sport->port.lock, flags);
511 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
512 sport->port.icount.tx += sport->tx_bytes;
513 spin_unlock_irqrestore(&sport->port.lock, flags);
515 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
517 uart_write_wakeup(&sport->port);
519 if (waitqueue_active(&sport->dma_wait)) {
520 wake_up(&sport->dma_wait);
521 dev_dbg(sport->port.dev, "exit in %s.\n", __func__);
526 static void imx_dma_tx(struct imx_port *sport)
528 struct circ_buf *xmit = &sport->port.state->xmit;
529 struct scatterlist *sgl = sport->tx_sgl;
530 struct dma_async_tx_descriptor *desc;
531 struct dma_chan *chan = sport->dma_chan_tx;
532 struct device *dev = sport->port.dev;
533 enum dma_status status;
536 status = dmaengine_tx_status(chan, (dma_cookie_t)0, NULL);
537 if (DMA_IN_PROGRESS == status)
540 sport->tx_bytes = uart_circ_chars_pending(xmit);
542 if (xmit->tail > xmit->head && xmit->head > 0) {
543 sport->dma_tx_nents = 2;
544 sg_init_table(sgl, 2);
545 sg_set_buf(sgl, xmit->buf + xmit->tail,
546 UART_XMIT_SIZE - xmit->tail);
547 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
549 sport->dma_tx_nents = 1;
550 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
553 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
555 dev_err(dev, "DMA mapping error for TX.\n");
558 desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents,
559 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
561 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
564 desc->callback = dma_tx_callback;
565 desc->callback_param = sport;
567 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
568 uart_circ_chars_pending(xmit));
570 sport->dma_is_txing = 1;
571 dmaengine_submit(desc);
572 dma_async_issue_pending(chan);
577 * interrupts disabled on entry
579 static void imx_start_tx(struct uart_port *port)
581 struct imx_port *sport = (struct imx_port *)port;
584 if (USE_IRDA(sport)) {
585 /* half duplex in IrDA mode; have to disable receive mode */
586 temp = readl(sport->port.membase + UCR4);
587 temp &= ~(UCR4_DREN);
588 writel(temp, sport->port.membase + UCR4);
590 temp = readl(sport->port.membase + UCR1);
591 temp &= ~(UCR1_RRDYEN);
592 writel(temp, sport->port.membase + UCR1);
594 /* Clear any pending ORE flag before enabling interrupt */
595 temp = readl(sport->port.membase + USR2);
596 writel(temp | USR2_ORE, sport->port.membase + USR2);
598 temp = readl(sport->port.membase + UCR4);
600 writel(temp, sport->port.membase + UCR4);
602 if (!sport->dma_is_enabled) {
603 temp = readl(sport->port.membase + UCR1);
604 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
607 if (USE_IRDA(sport)) {
608 temp = readl(sport->port.membase + UCR1);
610 writel(temp, sport->port.membase + UCR1);
612 temp = readl(sport->port.membase + UCR4);
614 writel(temp, sport->port.membase + UCR4);
617 if (sport->dma_is_enabled) {
618 /* FIXME: port->x_char must be transmitted if != 0 */
619 if (!uart_circ_empty(&port->state->xmit) &&
620 !uart_tx_stopped(port))
625 if (readl(sport->port.membase + uts_reg(sport)) & UTS_TXEMPTY)
626 imx_transmit_buffer(sport);
629 static irqreturn_t imx_rtsint(int irq, void *dev_id)
631 struct imx_port *sport = dev_id;
635 spin_lock_irqsave(&sport->port.lock, flags);
637 writel(USR1_RTSD, sport->port.membase + USR1);
638 val = readl(sport->port.membase + USR1) & USR1_RTSS;
639 uart_handle_cts_change(&sport->port, !!val);
640 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
642 spin_unlock_irqrestore(&sport->port.lock, flags);
646 static irqreturn_t imx_txint(int irq, void *dev_id)
648 struct imx_port *sport = dev_id;
651 spin_lock_irqsave(&sport->port.lock, flags);
652 imx_transmit_buffer(sport);
653 spin_unlock_irqrestore(&sport->port.lock, flags);
657 static irqreturn_t imx_rxint(int irq, void *dev_id)
659 struct imx_port *sport = dev_id;
660 unsigned int rx, flg, ignored = 0;
661 struct tty_port *port = &sport->port.state->port;
662 unsigned long flags, temp;
664 spin_lock_irqsave(&sport->port.lock, flags);
666 while (readl(sport->port.membase + USR2) & USR2_RDR) {
668 sport->port.icount.rx++;
670 rx = readl(sport->port.membase + URXD0);
672 temp = readl(sport->port.membase + USR2);
673 if (temp & USR2_BRCD) {
674 writel(USR2_BRCD, sport->port.membase + USR2);
675 if (uart_handle_break(&sport->port))
679 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
682 if (unlikely(rx & URXD_ERR)) {
684 sport->port.icount.brk++;
685 else if (rx & URXD_PRERR)
686 sport->port.icount.parity++;
687 else if (rx & URXD_FRMERR)
688 sport->port.icount.frame++;
689 if (rx & URXD_OVRRUN)
690 sport->port.icount.overrun++;
692 if (rx & sport->port.ignore_status_mask) {
698 rx &= sport->port.read_status_mask;
702 else if (rx & URXD_PRERR)
704 else if (rx & URXD_FRMERR)
706 if (rx & URXD_OVRRUN)
710 sport->port.sysrq = 0;
714 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
717 tty_insert_flip_char(port, rx, flg);
721 spin_unlock_irqrestore(&sport->port.lock, flags);
722 tty_flip_buffer_push(port);
726 static int start_rx_dma(struct imx_port *sport);
728 * If the RXFIFO is filled with some data, and then we
729 * arise a DMA operation to receive them.
731 static void imx_dma_rxint(struct imx_port *sport)
736 spin_lock_irqsave(&sport->port.lock, flags);
738 temp = readl(sport->port.membase + USR2);
739 if ((temp & USR2_RDR) && !sport->dma_is_rxing) {
740 sport->dma_is_rxing = 1;
742 /* disable the `Recerver Ready Interrrupt` */
743 temp = readl(sport->port.membase + UCR1);
744 temp &= ~(UCR1_RRDYEN);
745 writel(temp, sport->port.membase + UCR1);
747 /* tell the DMA to receive the data. */
751 spin_unlock_irqrestore(&sport->port.lock, flags);
754 static irqreturn_t imx_int(int irq, void *dev_id)
756 struct imx_port *sport = dev_id;
760 sts = readl(sport->port.membase + USR1);
762 if (sts & USR1_RRDY) {
763 if (sport->dma_is_enabled)
764 imx_dma_rxint(sport);
766 imx_rxint(irq, dev_id);
769 if (sts & USR1_TRDY &&
770 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN)
771 imx_txint(irq, dev_id);
774 imx_rtsint(irq, dev_id);
776 if (sts & USR1_AWAKE)
777 writel(USR1_AWAKE, sport->port.membase + USR1);
779 sts2 = readl(sport->port.membase + USR2);
780 if (sts2 & USR2_ORE) {
781 dev_err(sport->port.dev, "Rx FIFO overrun\n");
782 sport->port.icount.overrun++;
783 writel(sts2 | USR2_ORE, sport->port.membase + USR2);
790 * Return TIOCSER_TEMT when transmitter is not busy.
792 static unsigned int imx_tx_empty(struct uart_port *port)
794 struct imx_port *sport = (struct imx_port *)port;
797 ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
799 /* If the TX DMA is working, return 0. */
800 if (sport->dma_is_enabled && sport->dma_is_txing)
807 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
809 static unsigned int imx_get_mctrl(struct uart_port *port)
811 struct imx_port *sport = (struct imx_port *)port;
812 unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
814 if (readl(sport->port.membase + USR1) & USR1_RTSS)
817 if (readl(sport->port.membase + UCR2) & UCR2_CTS)
820 if (readl(sport->port.membase + uts_reg(sport)) & UTS_LOOP)
826 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
828 struct imx_port *sport = (struct imx_port *)port;
831 temp = readl(sport->port.membase + UCR2) & ~(UCR2_CTS | UCR2_CTSC);
832 if (mctrl & TIOCM_RTS)
833 temp |= UCR2_CTS | UCR2_CTSC;
835 writel(temp, sport->port.membase + UCR2);
837 temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP;
838 if (mctrl & TIOCM_LOOP)
840 writel(temp, sport->port.membase + uts_reg(sport));
844 * Interrupts always disabled.
846 static void imx_break_ctl(struct uart_port *port, int break_state)
848 struct imx_port *sport = (struct imx_port *)port;
849 unsigned long flags, temp;
851 spin_lock_irqsave(&sport->port.lock, flags);
853 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
855 if (break_state != 0)
858 writel(temp, sport->port.membase + UCR1);
860 spin_unlock_irqrestore(&sport->port.lock, flags);
863 #define TXTL 2 /* reset default */
864 #define RXTL 1 /* reset default */
866 static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
870 /* set receiver / transmitter trigger level */
871 val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
872 val |= TXTL << UFCR_TXTL_SHF | RXTL;
873 writel(val, sport->port.membase + UFCR);
877 #define RX_BUF_SIZE (PAGE_SIZE)
878 static void imx_rx_dma_done(struct imx_port *sport)
883 spin_lock_irqsave(&sport->port.lock, flags);
885 /* Enable this interrupt when the RXFIFO is empty. */
886 temp = readl(sport->port.membase + UCR1);
888 writel(temp, sport->port.membase + UCR1);
890 sport->dma_is_rxing = 0;
892 /* Is the shutdown waiting for us? */
893 if (waitqueue_active(&sport->dma_wait))
894 wake_up(&sport->dma_wait);
896 spin_unlock_irqrestore(&sport->port.lock, flags);
900 * There are three kinds of RX DMA interrupts(such as in the MX6Q):
901 * [1] the RX DMA buffer is full.
902 * [2] the Aging timer expires(wait for 8 bytes long)
903 * [3] the Idle Condition Detect(enabled the UCR4_IDDMAEN).
905 * The [2] is trigger when a character was been sitting in the FIFO
906 * meanwhile [3] can wait for 32 bytes long when the RX line is
907 * on IDLE state and RxFIFO is empty.
909 static void dma_rx_callback(void *data)
911 struct imx_port *sport = data;
912 struct dma_chan *chan = sport->dma_chan_rx;
913 struct scatterlist *sgl = &sport->rx_sgl;
914 struct tty_port *port = &sport->port.state->port;
915 struct dma_tx_state state;
916 enum dma_status status;
920 dma_unmap_sg(sport->port.dev, sgl, 1, DMA_FROM_DEVICE);
922 status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state);
923 count = RX_BUF_SIZE - state.residue;
924 dev_dbg(sport->port.dev, "We get %d bytes.\n", count);
927 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ))
928 tty_insert_flip_string(port, sport->rx_buf, count);
929 tty_flip_buffer_push(port);
933 imx_rx_dma_done(sport);
936 static int start_rx_dma(struct imx_port *sport)
938 struct scatterlist *sgl = &sport->rx_sgl;
939 struct dma_chan *chan = sport->dma_chan_rx;
940 struct device *dev = sport->port.dev;
941 struct dma_async_tx_descriptor *desc;
944 sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE);
945 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
947 dev_err(dev, "DMA mapping error for RX.\n");
950 desc = dmaengine_prep_slave_sg(chan, sgl, 1, DMA_DEV_TO_MEM,
953 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
956 desc->callback = dma_rx_callback;
957 desc->callback_param = sport;
959 dev_dbg(dev, "RX: prepare for the DMA.\n");
960 dmaengine_submit(desc);
961 dma_async_issue_pending(chan);
965 static void imx_uart_dma_exit(struct imx_port *sport)
967 if (sport->dma_chan_rx) {
968 dma_release_channel(sport->dma_chan_rx);
969 sport->dma_chan_rx = NULL;
971 kfree(sport->rx_buf);
972 sport->rx_buf = NULL;
975 if (sport->dma_chan_tx) {
976 dma_release_channel(sport->dma_chan_tx);
977 sport->dma_chan_tx = NULL;
980 sport->dma_is_inited = 0;
983 static int imx_uart_dma_init(struct imx_port *sport)
985 struct dma_slave_config slave_config = {};
986 struct device *dev = sport->port.dev;
989 /* Prepare for RX : */
990 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
991 if (!sport->dma_chan_rx) {
992 dev_dbg(dev, "cannot get the DMA channel.\n");
997 slave_config.direction = DMA_DEV_TO_MEM;
998 slave_config.src_addr = sport->port.mapbase + URXD0;
999 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1000 slave_config.src_maxburst = RXTL;
1001 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1003 dev_err(dev, "error in RX dma configuration.\n");
1007 sport->rx_buf = kzalloc(PAGE_SIZE, GFP_KERNEL);
1008 if (!sport->rx_buf) {
1013 /* Prepare for TX : */
1014 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1015 if (!sport->dma_chan_tx) {
1016 dev_err(dev, "cannot get the TX DMA channel!\n");
1021 slave_config.direction = DMA_MEM_TO_DEV;
1022 slave_config.dst_addr = sport->port.mapbase + URTX0;
1023 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1024 slave_config.dst_maxburst = TXTL;
1025 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1027 dev_err(dev, "error in TX dma configuration.");
1031 sport->dma_is_inited = 1;
1035 imx_uart_dma_exit(sport);
1039 static void imx_enable_dma(struct imx_port *sport)
1043 init_waitqueue_head(&sport->dma_wait);
1046 temp = readl(sport->port.membase + UCR1);
1047 temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN |
1048 /* wait for 32 idle frames for IDDMA interrupt */
1050 writel(temp, sport->port.membase + UCR1);
1053 temp = readl(sport->port.membase + UCR4);
1054 temp |= UCR4_IDDMAEN;
1055 writel(temp, sport->port.membase + UCR4);
1057 sport->dma_is_enabled = 1;
1060 static void imx_disable_dma(struct imx_port *sport)
1065 temp = readl(sport->port.membase + UCR1);
1066 temp &= ~(UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN);
1067 writel(temp, sport->port.membase + UCR1);
1070 temp = readl(sport->port.membase + UCR2);
1071 temp &= ~(UCR2_CTSC | UCR2_CTS);
1072 writel(temp, sport->port.membase + UCR2);
1075 temp = readl(sport->port.membase + UCR4);
1076 temp &= ~UCR4_IDDMAEN;
1077 writel(temp, sport->port.membase + UCR4);
1079 sport->dma_is_enabled = 0;
1082 /* half the RX buffer size */
1085 static int imx_startup(struct uart_port *port)
1087 struct imx_port *sport = (struct imx_port *)port;
1089 unsigned long flags, temp;
1091 retval = clk_prepare_enable(sport->clk_per);
1094 retval = clk_prepare_enable(sport->clk_ipg);
1096 clk_disable_unprepare(sport->clk_per);
1100 imx_setup_ufcr(sport, 0);
1102 /* disable the DREN bit (Data Ready interrupt enable) before
1105 temp = readl(sport->port.membase + UCR4);
1107 if (USE_IRDA(sport))
1110 /* set the trigger level for CTS */
1111 temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1112 temp |= CTSTL << UCR4_CTSTL_SHF;
1114 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
1116 /* Reset fifo's and state machines */
1119 temp = readl(sport->port.membase + UCR2);
1121 writel(temp, sport->port.membase + UCR2);
1123 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))
1126 spin_lock_irqsave(&sport->port.lock, flags);
1128 * Finally, clear and enable interrupts
1130 writel(USR1_RTSD, sport->port.membase + USR1);
1132 temp = readl(sport->port.membase + UCR1);
1133 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
1135 if (USE_IRDA(sport)) {
1137 temp &= ~(UCR1_RTSDEN);
1140 writel(temp, sport->port.membase + UCR1);
1142 temp = readl(sport->port.membase + UCR2);
1143 temp |= (UCR2_RXEN | UCR2_TXEN);
1144 if (!sport->have_rtscts)
1146 writel(temp, sport->port.membase + UCR2);
1148 if (!is_imx1_uart(sport)) {
1149 temp = readl(sport->port.membase + UCR3);
1150 temp |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
1151 writel(temp, sport->port.membase + UCR3);
1154 if (USE_IRDA(sport)) {
1155 temp = readl(sport->port.membase + UCR4);
1156 if (sport->irda_inv_rx)
1159 temp &= ~(UCR4_INVR);
1160 writel(temp | UCR4_DREN, sport->port.membase + UCR4);
1162 temp = readl(sport->port.membase + UCR3);
1163 if (sport->irda_inv_tx)
1166 temp &= ~(UCR3_INVT);
1167 writel(temp, sport->port.membase + UCR3);
1171 * Enable modem status interrupts
1173 imx_enable_ms(&sport->port);
1174 spin_unlock_irqrestore(&sport->port.lock, flags);
1176 if (USE_IRDA(sport)) {
1177 struct imxuart_platform_data *pdata;
1178 pdata = dev_get_platdata(sport->port.dev);
1179 sport->irda_inv_rx = pdata->irda_inv_rx;
1180 sport->irda_inv_tx = pdata->irda_inv_tx;
1181 sport->trcv_delay = pdata->transceiver_delay;
1182 if (pdata->irda_enable)
1183 pdata->irda_enable(1);
1189 static void imx_shutdown(struct uart_port *port)
1191 struct imx_port *sport = (struct imx_port *)port;
1193 unsigned long flags;
1195 if (sport->dma_is_enabled) {
1198 /* We have to wait for the DMA to finish. */
1199 ret = wait_event_interruptible(sport->dma_wait,
1200 !sport->dma_is_rxing && !sport->dma_is_txing);
1202 sport->dma_is_rxing = 0;
1203 sport->dma_is_txing = 0;
1204 dmaengine_terminate_all(sport->dma_chan_tx);
1205 dmaengine_terminate_all(sport->dma_chan_rx);
1207 spin_lock_irqsave(&sport->port.lock, flags);
1210 imx_disable_dma(sport);
1211 spin_unlock_irqrestore(&sport->port.lock, flags);
1212 imx_uart_dma_exit(sport);
1215 spin_lock_irqsave(&sport->port.lock, flags);
1216 temp = readl(sport->port.membase + UCR2);
1217 temp &= ~(UCR2_TXEN);
1218 writel(temp, sport->port.membase + UCR2);
1219 spin_unlock_irqrestore(&sport->port.lock, flags);
1221 if (USE_IRDA(sport)) {
1222 struct imxuart_platform_data *pdata;
1223 pdata = dev_get_platdata(sport->port.dev);
1224 if (pdata->irda_enable)
1225 pdata->irda_enable(0);
1231 del_timer_sync(&sport->timer);
1234 * Disable all interrupts, port and break condition.
1237 spin_lock_irqsave(&sport->port.lock, flags);
1238 temp = readl(sport->port.membase + UCR1);
1239 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
1240 if (USE_IRDA(sport))
1241 temp &= ~(UCR1_IREN);
1243 writel(temp, sport->port.membase + UCR1);
1244 spin_unlock_irqrestore(&sport->port.lock, flags);
1246 clk_disable_unprepare(sport->clk_per);
1247 clk_disable_unprepare(sport->clk_ipg);
1250 static void imx_flush_buffer(struct uart_port *port)
1252 struct imx_port *sport = (struct imx_port *)port;
1254 if (sport->dma_is_enabled) {
1255 sport->tx_bytes = 0;
1256 dmaengine_terminate_all(sport->dma_chan_tx);
1261 imx_set_termios(struct uart_port *port, struct ktermios *termios,
1262 struct ktermios *old)
1264 struct imx_port *sport = (struct imx_port *)port;
1265 unsigned long flags;
1266 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
1267 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1268 unsigned int div, ufcr;
1269 unsigned long num, denom;
1273 * If we don't support modem control lines, don't allow
1277 termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
1278 termios->c_cflag |= CLOCAL;
1282 * We only support CS7 and CS8.
1284 while ((termios->c_cflag & CSIZE) != CS7 &&
1285 (termios->c_cflag & CSIZE) != CS8) {
1286 termios->c_cflag &= ~CSIZE;
1287 termios->c_cflag |= old_csize;
1291 if ((termios->c_cflag & CSIZE) == CS8)
1292 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
1294 ucr2 = UCR2_SRST | UCR2_IRTS;
1296 if (termios->c_cflag & CRTSCTS) {
1297 if (sport->have_rtscts) {
1301 /* Can we enable the DMA support? */
1302 if (is_imx6q_uart(sport) && !uart_console(port)
1303 && !sport->dma_is_inited)
1304 imx_uart_dma_init(sport);
1306 termios->c_cflag &= ~CRTSCTS;
1310 if (termios->c_cflag & CSTOPB)
1312 if (termios->c_cflag & PARENB) {
1314 if (termios->c_cflag & PARODD)
1318 del_timer_sync(&sport->timer);
1321 * Ask the core to calculate the divisor for us.
1323 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1324 quot = uart_get_divisor(port, baud);
1326 spin_lock_irqsave(&sport->port.lock, flags);
1328 sport->port.read_status_mask = 0;
1329 if (termios->c_iflag & INPCK)
1330 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1331 if (termios->c_iflag & (BRKINT | PARMRK))
1332 sport->port.read_status_mask |= URXD_BRK;
1335 * Characters to ignore
1337 sport->port.ignore_status_mask = 0;
1338 if (termios->c_iflag & IGNPAR)
1339 sport->port.ignore_status_mask |= URXD_PRERR;
1340 if (termios->c_iflag & IGNBRK) {
1341 sport->port.ignore_status_mask |= URXD_BRK;
1343 * If we're ignoring parity and break indicators,
1344 * ignore overruns too (for real raw support).
1346 if (termios->c_iflag & IGNPAR)
1347 sport->port.ignore_status_mask |= URXD_OVRRUN;
1350 if ((termios->c_cflag & CREAD) == 0)
1351 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1354 * Update the per-port timeout.
1356 uart_update_timeout(port, termios->c_cflag, baud);
1359 * disable interrupts and drain transmitter
1361 old_ucr1 = readl(sport->port.membase + UCR1);
1362 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
1363 sport->port.membase + UCR1);
1365 while (!(readl(sport->port.membase + USR2) & USR2_TXDC))
1368 /* then, disable everything */
1369 old_txrxen = readl(sport->port.membase + UCR2);
1370 writel(old_txrxen & ~(UCR2_TXEN | UCR2_RXEN),
1371 sport->port.membase + UCR2);
1372 old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
1374 if (USE_IRDA(sport)) {
1376 * use maximum available submodule frequency to
1377 * avoid missing short pulses due to low sampling rate
1381 /* custom-baudrate handling */
1382 div = sport->port.uartclk / (baud * 16);
1383 if (baud == 38400 && quot != div)
1384 baud = sport->port.uartclk / (quot * 16);
1386 div = sport->port.uartclk / (baud * 16);
1393 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1394 1 << 16, 1 << 16, &num, &denom);
1396 tdiv64 = sport->port.uartclk;
1398 do_div(tdiv64, denom * 16 * div);
1399 tty_termios_encode_baud_rate(termios,
1400 (speed_t)tdiv64, (speed_t)tdiv64);
1405 ufcr = readl(sport->port.membase + UFCR);
1406 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1407 if (sport->dte_mode)
1408 ufcr |= UFCR_DCEDTE;
1409 writel(ufcr, sport->port.membase + UFCR);
1411 writel(num, sport->port.membase + UBIR);
1412 writel(denom, sport->port.membase + UBMR);
1414 if (!is_imx1_uart(sport))
1415 writel(sport->port.uartclk / div / 1000,
1416 sport->port.membase + IMX21_ONEMS);
1418 writel(old_ucr1, sport->port.membase + UCR1);
1420 /* set the parity, stop bits and data size */
1421 writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
1423 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1424 imx_enable_ms(&sport->port);
1426 if (sport->dma_is_inited && !sport->dma_is_enabled)
1427 imx_enable_dma(sport);
1428 spin_unlock_irqrestore(&sport->port.lock, flags);
1431 static const char *imx_type(struct uart_port *port)
1433 struct imx_port *sport = (struct imx_port *)port;
1435 return sport->port.type == PORT_IMX ? "IMX" : NULL;
1439 * Configure/autoconfigure the port.
1441 static void imx_config_port(struct uart_port *port, int flags)
1443 struct imx_port *sport = (struct imx_port *)port;
1445 if (flags & UART_CONFIG_TYPE)
1446 sport->port.type = PORT_IMX;
1450 * Verify the new serial_struct (for TIOCSSERIAL).
1451 * The only change we allow are to the flags and type, and
1452 * even then only between PORT_IMX and PORT_UNKNOWN
1455 imx_verify_port(struct uart_port *port, struct serial_struct *ser)
1457 struct imx_port *sport = (struct imx_port *)port;
1460 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1462 if (sport->port.irq != ser->irq)
1464 if (ser->io_type != UPIO_MEM)
1466 if (sport->port.uartclk / 16 != ser->baud_base)
1468 if (sport->port.mapbase != (unsigned long)ser->iomem_base)
1470 if (sport->port.iobase != ser->port)
1477 #if defined(CONFIG_CONSOLE_POLL)
1479 static int imx_poll_init(struct uart_port *port)
1481 struct imx_port *sport = (struct imx_port *)port;
1482 unsigned long flags;
1486 retval = clk_prepare_enable(sport->clk_ipg);
1489 retval = clk_prepare_enable(sport->clk_per);
1491 clk_disable_unprepare(sport->clk_ipg);
1493 imx_setup_ufcr(sport, 0);
1495 spin_lock_irqsave(&sport->port.lock, flags);
1497 temp = readl(sport->port.membase + UCR1);
1498 if (is_imx1_uart(sport))
1499 temp |= IMX1_UCR1_UARTCLKEN;
1500 temp |= UCR1_UARTEN | UCR1_RRDYEN;
1501 temp &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN);
1502 writel(temp, sport->port.membase + UCR1);
1504 temp = readl(sport->port.membase + UCR2);
1506 writel(temp, sport->port.membase + UCR2);
1508 spin_unlock_irqrestore(&sport->port.lock, flags);
1513 static int imx_poll_get_char(struct uart_port *port)
1515 if (!(readl_relaxed(port->membase + USR2) & USR2_RDR))
1516 return NO_POLL_CHAR;
1518 return readl_relaxed(port->membase + URXD0) & URXD_RX_DATA;
1521 static void imx_poll_put_char(struct uart_port *port, unsigned char c)
1523 unsigned int status;
1527 status = readl_relaxed(port->membase + USR1);
1528 } while (~status & USR1_TRDY);
1531 writel_relaxed(c, port->membase + URTX0);
1535 status = readl_relaxed(port->membase + USR2);
1536 } while (~status & USR2_TXDC);
1540 static struct uart_ops imx_pops = {
1541 .tx_empty = imx_tx_empty,
1542 .set_mctrl = imx_set_mctrl,
1543 .get_mctrl = imx_get_mctrl,
1544 .stop_tx = imx_stop_tx,
1545 .start_tx = imx_start_tx,
1546 .stop_rx = imx_stop_rx,
1547 .enable_ms = imx_enable_ms,
1548 .break_ctl = imx_break_ctl,
1549 .startup = imx_startup,
1550 .shutdown = imx_shutdown,
1551 .flush_buffer = imx_flush_buffer,
1552 .set_termios = imx_set_termios,
1554 .config_port = imx_config_port,
1555 .verify_port = imx_verify_port,
1556 #if defined(CONFIG_CONSOLE_POLL)
1557 .poll_init = imx_poll_init,
1558 .poll_get_char = imx_poll_get_char,
1559 .poll_put_char = imx_poll_put_char,
1563 static struct imx_port *imx_ports[UART_NR];
1565 #ifdef CONFIG_SERIAL_IMX_CONSOLE
1566 static void imx_console_putchar(struct uart_port *port, int ch)
1568 struct imx_port *sport = (struct imx_port *)port;
1570 while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)
1573 writel(ch, sport->port.membase + URTX0);
1577 * Interrupts are disabled on entering
1580 imx_console_write(struct console *co, const char *s, unsigned int count)
1582 struct imx_port *sport = imx_ports[co->index];
1583 struct imx_port_ucrs old_ucr;
1585 unsigned long flags = 0;
1589 retval = clk_enable(sport->clk_per);
1592 retval = clk_enable(sport->clk_ipg);
1594 clk_disable(sport->clk_per);
1598 if (sport->port.sysrq)
1600 else if (oops_in_progress)
1601 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1603 spin_lock_irqsave(&sport->port.lock, flags);
1606 * First, save UCR1/2/3 and then disable interrupts
1608 imx_port_ucrs_save(&sport->port, &old_ucr);
1609 ucr1 = old_ucr.ucr1;
1611 if (is_imx1_uart(sport))
1612 ucr1 |= IMX1_UCR1_UARTCLKEN;
1613 ucr1 |= UCR1_UARTEN;
1614 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1616 writel(ucr1, sport->port.membase + UCR1);
1618 writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
1620 uart_console_write(&sport->port, s, count, imx_console_putchar);
1623 * Finally, wait for transmitter to become empty
1624 * and restore UCR1/2/3
1626 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
1628 imx_port_ucrs_restore(&sport->port, &old_ucr);
1631 spin_unlock_irqrestore(&sport->port.lock, flags);
1633 clk_disable(sport->clk_ipg);
1634 clk_disable(sport->clk_per);
1638 * If the port was already initialised (eg, by a boot loader),
1639 * try to determine the current setup.
1642 imx_console_get_options(struct imx_port *sport, int *baud,
1643 int *parity, int *bits)
1646 if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {
1647 /* ok, the port was enabled */
1648 unsigned int ucr2, ubir, ubmr, uartclk;
1649 unsigned int baud_raw;
1650 unsigned int ucfr_rfdiv;
1652 ucr2 = readl(sport->port.membase + UCR2);
1655 if (ucr2 & UCR2_PREN) {
1656 if (ucr2 & UCR2_PROE)
1667 ubir = readl(sport->port.membase + UBIR) & 0xffff;
1668 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
1670 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
1671 if (ucfr_rfdiv == 6)
1674 ucfr_rfdiv = 6 - ucfr_rfdiv;
1676 uartclk = clk_get_rate(sport->clk_per);
1677 uartclk /= ucfr_rfdiv;
1680 * The next code provides exact computation of
1681 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1682 * without need of float support or long long division,
1683 * which would be required to prevent 32bit arithmetic overflow
1685 unsigned int mul = ubir + 1;
1686 unsigned int div = 16 * (ubmr + 1);
1687 unsigned int rem = uartclk % div;
1689 baud_raw = (uartclk / div) * mul;
1690 baud_raw += (rem * mul + div / 2) / div;
1691 *baud = (baud_raw + 50) / 100 * 100;
1694 if (*baud != baud_raw)
1695 pr_info("Console IMX rounded baud rate from %d to %d\n",
1701 imx_console_setup(struct console *co, char *options)
1703 struct imx_port *sport;
1711 * Check whether an invalid uart number has been specified, and
1712 * if so, search for the first available port that does have
1715 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1717 sport = imx_ports[co->index];
1721 /* For setting the registers, we only need to enable the ipg clock. */
1722 retval = clk_prepare_enable(sport->clk_ipg);
1727 uart_parse_options(options, &baud, &parity, &bits, &flow);
1729 imx_console_get_options(sport, &baud, &parity, &bits);
1731 imx_setup_ufcr(sport, 0);
1733 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
1735 clk_disable(sport->clk_ipg);
1737 clk_unprepare(sport->clk_ipg);
1741 retval = clk_prepare(sport->clk_per);
1743 clk_disable_unprepare(sport->clk_ipg);
1749 static struct uart_driver imx_reg;
1750 static struct console imx_console = {
1752 .write = imx_console_write,
1753 .device = uart_console_device,
1754 .setup = imx_console_setup,
1755 .flags = CON_PRINTBUFFER,
1760 #define IMX_CONSOLE &imx_console
1762 #define IMX_CONSOLE NULL
1765 static struct uart_driver imx_reg = {
1766 .owner = THIS_MODULE,
1767 .driver_name = DRIVER_NAME,
1768 .dev_name = DEV_NAME,
1769 .major = SERIAL_IMX_MAJOR,
1770 .minor = MINOR_START,
1771 .nr = ARRAY_SIZE(imx_ports),
1772 .cons = IMX_CONSOLE,
1775 static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)
1777 struct imx_port *sport = platform_get_drvdata(dev);
1780 /* enable wakeup from i.MX UART */
1781 val = readl(sport->port.membase + UCR3);
1783 writel(val, sport->port.membase + UCR3);
1785 uart_suspend_port(&imx_reg, &sport->port);
1790 static int serial_imx_resume(struct platform_device *dev)
1792 struct imx_port *sport = platform_get_drvdata(dev);
1795 /* disable wakeup from i.MX UART */
1796 val = readl(sport->port.membase + UCR3);
1797 val &= ~UCR3_AWAKEN;
1798 writel(val, sport->port.membase + UCR3);
1800 uart_resume_port(&imx_reg, &sport->port);
1807 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
1808 * could successfully get all information from dt or a negative errno.
1810 static int serial_imx_probe_dt(struct imx_port *sport,
1811 struct platform_device *pdev)
1813 struct device_node *np = pdev->dev.of_node;
1814 const struct of_device_id *of_id =
1815 of_match_device(imx_uart_dt_ids, &pdev->dev);
1819 /* no device tree device */
1822 ret = of_alias_get_id(np, "serial");
1824 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
1827 sport->port.line = ret;
1829 if (of_get_property(np, "fsl,uart-has-rtscts", NULL))
1830 sport->have_rtscts = 1;
1832 if (of_get_property(np, "fsl,irda-mode", NULL))
1833 sport->use_irda = 1;
1835 if (of_get_property(np, "fsl,dte-mode", NULL))
1836 sport->dte_mode = 1;
1838 sport->devdata = of_id->data;
1843 static inline int serial_imx_probe_dt(struct imx_port *sport,
1844 struct platform_device *pdev)
1850 static void serial_imx_probe_pdata(struct imx_port *sport,
1851 struct platform_device *pdev)
1853 struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev);
1855 sport->port.line = pdev->id;
1856 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data;
1861 if (pdata->flags & IMXUART_HAVE_RTSCTS)
1862 sport->have_rtscts = 1;
1864 if (pdata->flags & IMXUART_IRDA)
1865 sport->use_irda = 1;
1868 static int serial_imx_probe(struct platform_device *pdev)
1870 struct imx_port *sport;
1873 struct resource *res;
1875 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
1879 ret = serial_imx_probe_dt(sport, pdev);
1881 serial_imx_probe_pdata(sport, pdev);
1885 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1886 base = devm_ioremap_resource(&pdev->dev, res);
1888 return PTR_ERR(base);
1890 sport->port.dev = &pdev->dev;
1891 sport->port.mapbase = res->start;
1892 sport->port.membase = base;
1893 sport->port.type = PORT_IMX,
1894 sport->port.iotype = UPIO_MEM;
1895 sport->port.irq = platform_get_irq(pdev, 0);
1896 sport->rxirq = platform_get_irq(pdev, 0);
1897 sport->txirq = platform_get_irq(pdev, 1);
1898 sport->rtsirq = platform_get_irq(pdev, 2);
1899 sport->port.fifosize = 32;
1900 sport->port.ops = &imx_pops;
1901 sport->port.flags = UPF_BOOT_AUTOCONF;
1902 init_timer(&sport->timer);
1903 sport->timer.function = imx_timeout;
1904 sport->timer.data = (unsigned long)sport;
1906 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1907 if (IS_ERR(sport->clk_ipg)) {
1908 ret = PTR_ERR(sport->clk_ipg);
1909 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
1913 sport->clk_per = devm_clk_get(&pdev->dev, "per");
1914 if (IS_ERR(sport->clk_per)) {
1915 ret = PTR_ERR(sport->clk_per);
1916 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
1920 sport->port.uartclk = clk_get_rate(sport->clk_per);
1923 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
1924 * chips only have one interrupt.
1926 if (sport->txirq > 0) {
1927 ret = devm_request_irq(&pdev->dev, sport->rxirq, imx_rxint, 0,
1928 dev_name(&pdev->dev), sport);
1932 ret = devm_request_irq(&pdev->dev, sport->txirq, imx_txint, 0,
1933 dev_name(&pdev->dev), sport);
1937 /* do not use RTS IRQ on IrDA */
1938 if (!USE_IRDA(sport)) {
1939 ret = devm_request_irq(&pdev->dev, sport->rtsirq,
1941 dev_name(&pdev->dev), sport);
1946 ret = devm_request_irq(&pdev->dev, sport->port.irq, imx_int, 0,
1947 dev_name(&pdev->dev), sport);
1952 imx_ports[sport->port.line] = sport;
1954 platform_set_drvdata(pdev, sport);
1956 return uart_add_one_port(&imx_reg, &sport->port);
1959 static int serial_imx_remove(struct platform_device *pdev)
1961 struct imx_port *sport = platform_get_drvdata(pdev);
1963 return uart_remove_one_port(&imx_reg, &sport->port);
1966 static struct platform_driver serial_imx_driver = {
1967 .probe = serial_imx_probe,
1968 .remove = serial_imx_remove,
1970 .suspend = serial_imx_suspend,
1971 .resume = serial_imx_resume,
1972 .id_table = imx_uart_devtype,
1975 .of_match_table = imx_uart_dt_ids,
1979 static int __init imx_serial_init(void)
1981 int ret = uart_register_driver(&imx_reg);
1986 ret = platform_driver_register(&serial_imx_driver);
1988 uart_unregister_driver(&imx_reg);
1993 static void __exit imx_serial_exit(void)
1995 platform_driver_unregister(&serial_imx_driver);
1996 uart_unregister_driver(&imx_reg);
1999 module_init(imx_serial_init);
2000 module_exit(imx_serial_exit);
2002 MODULE_AUTHOR("Sascha Hauer");
2003 MODULE_DESCRIPTION("IMX generic serial port driver");
2004 MODULE_LICENSE("GPL");
2005 MODULE_ALIAS("platform:imx-uart");