2 * High Speed Serial Ports on NXP LPC32xx SoC
4 * Authors: Kevin Wells <kevin.wells@nxp.com>
5 * Roland Stigge <stigge@antcom.de>
7 * Copyright (C) 2010 NXP Semiconductors
8 * Copyright (C) 2012 Roland Stigge
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
21 #include <linux/module.h>
22 #include <linux/ioport.h>
23 #include <linux/init.h>
24 #include <linux/console.h>
25 #include <linux/sysrq.h>
26 #include <linux/tty.h>
27 #include <linux/tty_flip.h>
28 #include <linux/serial_core.h>
29 #include <linux/serial.h>
30 #include <linux/platform_device.h>
31 #include <linux/delay.h>
32 #include <linux/nmi.h>
34 #include <linux/irq.h>
35 #include <linux/gpio.h>
37 #include <mach/platform.h>
38 #include <mach/hardware.h>
41 * High Speed UART register offsets
43 #define LPC32XX_HSUART_FIFO(x) ((x) + 0x00)
44 #define LPC32XX_HSUART_LEVEL(x) ((x) + 0x04)
45 #define LPC32XX_HSUART_IIR(x) ((x) + 0x08)
46 #define LPC32XX_HSUART_CTRL(x) ((x) + 0x0C)
47 #define LPC32XX_HSUART_RATE(x) ((x) + 0x10)
49 #define LPC32XX_HSU_BREAK_DATA (1 << 10)
50 #define LPC32XX_HSU_ERROR_DATA (1 << 9)
51 #define LPC32XX_HSU_RX_EMPTY (1 << 8)
53 #define LPC32XX_HSU_TX_LEV(n) (((n) >> 8) & 0xFF)
54 #define LPC32XX_HSU_RX_LEV(n) ((n) & 0xFF)
56 #define LPC32XX_HSU_TX_INT_SET (1 << 6)
57 #define LPC32XX_HSU_RX_OE_INT (1 << 5)
58 #define LPC32XX_HSU_BRK_INT (1 << 4)
59 #define LPC32XX_HSU_FE_INT (1 << 3)
60 #define LPC32XX_HSU_RX_TIMEOUT_INT (1 << 2)
61 #define LPC32XX_HSU_RX_TRIG_INT (1 << 1)
62 #define LPC32XX_HSU_TX_INT (1 << 0)
64 #define LPC32XX_HSU_HRTS_INV (1 << 21)
65 #define LPC32XX_HSU_HRTS_TRIG_8B (0x0 << 19)
66 #define LPC32XX_HSU_HRTS_TRIG_16B (0x1 << 19)
67 #define LPC32XX_HSU_HRTS_TRIG_32B (0x2 << 19)
68 #define LPC32XX_HSU_HRTS_TRIG_48B (0x3 << 19)
69 #define LPC32XX_HSU_HRTS_EN (1 << 18)
70 #define LPC32XX_HSU_TMO_DISABLED (0x0 << 16)
71 #define LPC32XX_HSU_TMO_INACT_4B (0x1 << 16)
72 #define LPC32XX_HSU_TMO_INACT_8B (0x2 << 16)
73 #define LPC32XX_HSU_TMO_INACT_16B (0x3 << 16)
74 #define LPC32XX_HSU_HCTS_INV (1 << 15)
75 #define LPC32XX_HSU_HCTS_EN (1 << 14)
76 #define LPC32XX_HSU_OFFSET(n) ((n) << 9)
77 #define LPC32XX_HSU_BREAK (1 << 8)
78 #define LPC32XX_HSU_ERR_INT_EN (1 << 7)
79 #define LPC32XX_HSU_RX_INT_EN (1 << 6)
80 #define LPC32XX_HSU_TX_INT_EN (1 << 5)
81 #define LPC32XX_HSU_RX_TL1B (0x0 << 2)
82 #define LPC32XX_HSU_RX_TL4B (0x1 << 2)
83 #define LPC32XX_HSU_RX_TL8B (0x2 << 2)
84 #define LPC32XX_HSU_RX_TL16B (0x3 << 2)
85 #define LPC32XX_HSU_RX_TL32B (0x4 << 2)
86 #define LPC32XX_HSU_RX_TL48B (0x5 << 2)
87 #define LPC32XX_HSU_TX_TLEMPTY (0x0 << 0)
88 #define LPC32XX_HSU_TX_TL0B (0x0 << 0)
89 #define LPC32XX_HSU_TX_TL4B (0x1 << 0)
90 #define LPC32XX_HSU_TX_TL8B (0x2 << 0)
91 #define LPC32XX_HSU_TX_TL16B (0x3 << 0)
93 #define MODNAME "lpc32xx_hsuart"
95 struct lpc32xx_hsuart_port {
96 struct uart_port port;
99 #define FIFO_READ_LIMIT 128
101 #define LPC32XX_TTY_NAME "ttyTX"
102 static struct lpc32xx_hsuart_port lpc32xx_hs_ports[MAX_PORTS];
104 #ifdef CONFIG_SERIAL_HS_LPC32XX_CONSOLE
105 static void wait_for_xmit_empty(struct uart_port *port)
107 unsigned int timeout = 10000;
110 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(
111 port->membase))) == 0)
119 static void wait_for_xmit_ready(struct uart_port *port)
121 unsigned int timeout = 10000;
124 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(
125 port->membase))) < 32)
133 static void lpc32xx_hsuart_console_putchar(struct uart_port *port, int ch)
135 wait_for_xmit_ready(port);
136 writel((u32)ch, LPC32XX_HSUART_FIFO(port->membase));
139 static void lpc32xx_hsuart_console_write(struct console *co, const char *s,
142 struct lpc32xx_hsuart_port *up = &lpc32xx_hs_ports[co->index];
146 touch_nmi_watchdog();
147 local_irq_save(flags);
150 else if (oops_in_progress)
151 locked = spin_trylock(&up->port.lock);
153 spin_lock(&up->port.lock);
155 uart_console_write(&up->port, s, count, lpc32xx_hsuart_console_putchar);
156 wait_for_xmit_empty(&up->port);
159 spin_unlock(&up->port.lock);
160 local_irq_restore(flags);
163 static int __init lpc32xx_hsuart_console_setup(struct console *co,
166 struct uart_port *port;
172 if (co->index >= MAX_PORTS)
175 port = &lpc32xx_hs_ports[co->index].port;
180 uart_parse_options(options, &baud, &parity, &bits, &flow);
182 return uart_set_options(port, co, baud, parity, bits, flow);
185 static struct uart_driver lpc32xx_hsuart_reg;
186 static struct console lpc32xx_hsuart_console = {
187 .name = LPC32XX_TTY_NAME,
188 .write = lpc32xx_hsuart_console_write,
189 .device = uart_console_device,
190 .setup = lpc32xx_hsuart_console_setup,
191 .flags = CON_PRINTBUFFER,
193 .data = &lpc32xx_hsuart_reg,
196 static int __init lpc32xx_hsuart_console_init(void)
198 register_console(&lpc32xx_hsuart_console);
201 console_initcall(lpc32xx_hsuart_console_init);
203 #define LPC32XX_HSUART_CONSOLE (&lpc32xx_hsuart_console)
205 #define LPC32XX_HSUART_CONSOLE NULL
208 static struct uart_driver lpc32xx_hs_reg = {
209 .owner = THIS_MODULE,
210 .driver_name = MODNAME,
211 .dev_name = LPC32XX_TTY_NAME,
213 .cons = LPC32XX_HSUART_CONSOLE,
215 static int uarts_registered;
217 static unsigned int __serial_get_clock_div(unsigned long uartclk,
220 u32 div, goodrate, hsu_rate, l_hsu_rate, comprate;
223 /* Find the closest divider to get the desired clock rate */
224 div = uartclk / rate;
225 goodrate = hsu_rate = (div / 14) - 1;
230 l_hsu_rate = hsu_rate + 3;
231 rate_diff = 0xFFFFFFFF;
233 while (hsu_rate < l_hsu_rate) {
234 comprate = uartclk / ((hsu_rate + 1) * 14);
235 if (abs(comprate - rate) < rate_diff) {
237 rate_diff = abs(comprate - rate);
248 static void __serial_uart_flush(struct uart_port *port)
253 while ((readl(LPC32XX_HSUART_LEVEL(port->membase)) > 0) &&
254 (cnt++ < FIFO_READ_LIMIT))
255 tmp = readl(LPC32XX_HSUART_FIFO(port->membase));
258 static void __serial_lpc32xx_rx(struct uart_port *port)
260 unsigned int tmp, flag;
261 struct tty_struct *tty = tty_port_tty_get(&port->state->port);
264 /* Discard data: no tty available */
265 while (!(readl(LPC32XX_HSUART_FIFO(port->membase)) &
266 LPC32XX_HSU_RX_EMPTY))
272 /* Read data from FIFO and push into terminal */
273 tmp = readl(LPC32XX_HSUART_FIFO(port->membase));
274 while (!(tmp & LPC32XX_HSU_RX_EMPTY)) {
278 if (tmp & LPC32XX_HSU_ERROR_DATA) {
280 writel(LPC32XX_HSU_FE_INT,
281 LPC32XX_HSUART_IIR(port->membase));
282 port->icount.frame++;
284 tty_insert_flip_char(tty, 0, TTY_FRAME);
287 tty_insert_flip_char(tty, (tmp & 0xFF), flag);
289 tmp = readl(LPC32XX_HSUART_FIFO(port->membase));
291 tty_flip_buffer_push(tty);
295 static void __serial_lpc32xx_tx(struct uart_port *port)
297 struct circ_buf *xmit = &port->state->xmit;
301 writel((u32)port->x_char, LPC32XX_HSUART_FIFO(port->membase));
307 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
311 while (LPC32XX_HSU_TX_LEV(readl(
312 LPC32XX_HSUART_LEVEL(port->membase))) < 64) {
313 writel((u32) xmit->buf[xmit->tail],
314 LPC32XX_HSUART_FIFO(port->membase));
315 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
317 if (uart_circ_empty(xmit))
321 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
322 uart_write_wakeup(port);
325 if (uart_circ_empty(xmit)) {
326 tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
327 tmp &= ~LPC32XX_HSU_TX_INT_EN;
328 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
332 static irqreturn_t serial_lpc32xx_interrupt(int irq, void *dev_id)
334 struct uart_port *port = dev_id;
335 struct tty_struct *tty = tty_port_tty_get(&port->state->port);
338 spin_lock(&port->lock);
340 /* Read UART status and clear latched interrupts */
341 status = readl(LPC32XX_HSUART_IIR(port->membase));
343 if (status & LPC32XX_HSU_BRK_INT) {
345 writel(LPC32XX_HSU_BRK_INT, LPC32XX_HSUART_IIR(port->membase));
347 uart_handle_break(port);
351 if (status & LPC32XX_HSU_FE_INT)
352 writel(LPC32XX_HSU_FE_INT, LPC32XX_HSUART_IIR(port->membase));
354 if (status & LPC32XX_HSU_RX_OE_INT) {
355 /* Receive FIFO overrun */
356 writel(LPC32XX_HSU_RX_OE_INT,
357 LPC32XX_HSUART_IIR(port->membase));
358 port->icount.overrun++;
360 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
361 tty_schedule_flip(tty);
366 if (status & (LPC32XX_HSU_RX_TIMEOUT_INT | LPC32XX_HSU_RX_TRIG_INT)) {
367 __serial_lpc32xx_rx(port);
369 tty_flip_buffer_push(tty);
372 /* Transmit data request? */
373 if ((status & LPC32XX_HSU_TX_INT) && (!uart_tx_stopped(port))) {
374 writel(LPC32XX_HSU_TX_INT, LPC32XX_HSUART_IIR(port->membase));
375 __serial_lpc32xx_tx(port);
378 spin_unlock(&port->lock);
384 /* port->lock is not held. */
385 static unsigned int serial_lpc32xx_tx_empty(struct uart_port *port)
387 unsigned int ret = 0;
389 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(port->membase))) == 0)
395 /* port->lock held by caller. */
396 static void serial_lpc32xx_set_mctrl(struct uart_port *port,
399 /* No signals are supported on HS UARTs */
402 /* port->lock is held by caller and interrupts are disabled. */
403 static unsigned int serial_lpc32xx_get_mctrl(struct uart_port *port)
405 /* No signals are supported on HS UARTs */
406 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
409 /* port->lock held by caller. */
410 static void serial_lpc32xx_stop_tx(struct uart_port *port)
414 tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
415 tmp &= ~LPC32XX_HSU_TX_INT_EN;
416 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
419 /* port->lock held by caller. */
420 static void serial_lpc32xx_start_tx(struct uart_port *port)
424 __serial_lpc32xx_tx(port);
425 tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
426 tmp |= LPC32XX_HSU_TX_INT_EN;
427 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
430 /* port->lock held by caller. */
431 static void serial_lpc32xx_stop_rx(struct uart_port *port)
435 tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
436 tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN);
437 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
439 writel((LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT |
440 LPC32XX_HSU_FE_INT), LPC32XX_HSUART_IIR(port->membase));
443 /* port->lock held by caller. */
444 static void serial_lpc32xx_enable_ms(struct uart_port *port)
446 /* Modem status is not supported */
449 /* port->lock is not held. */
450 static void serial_lpc32xx_break_ctl(struct uart_port *port,
456 spin_lock_irqsave(&port->lock, flags);
457 tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
458 if (break_state != 0)
459 tmp |= LPC32XX_HSU_BREAK;
461 tmp &= ~LPC32XX_HSU_BREAK;
462 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
463 spin_unlock_irqrestore(&port->lock, flags);
466 /* LPC3250 Errata HSUART.1: Hang workaround via loopback mode on inactivity */
467 static void lpc32xx_loopback_set(resource_size_t mapbase, int state)
473 case LPC32XX_HS_UART1_BASE:
476 case LPC32XX_HS_UART2_BASE:
479 case LPC32XX_HS_UART7_BASE:
483 WARN(1, "lpc32xx_hs: Warning: Unknown port at %08x\n", mapbase);
487 tmp = readl(LPC32XX_UARTCTL_CLOOP);
492 writel(tmp, LPC32XX_UARTCTL_CLOOP);
495 /* port->lock is not held. */
496 static int serial_lpc32xx_startup(struct uart_port *port)
502 spin_lock_irqsave(&port->lock, flags);
504 __serial_uart_flush(port);
506 writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT |
507 LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT),
508 LPC32XX_HSUART_IIR(port->membase));
510 writel(0xFF, LPC32XX_HSUART_RATE(port->membase));
513 * Set receiver timeout, HSU offset of 20, no break, no interrupts,
514 * and default FIFO trigger levels
516 tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
517 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B;
518 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
520 lpc32xx_loopback_set(port->mapbase, 0); /* get out of loopback mode */
522 spin_unlock_irqrestore(&port->lock, flags);
524 retval = request_irq(port->irq, serial_lpc32xx_interrupt,
527 writel((tmp | LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN),
528 LPC32XX_HSUART_CTRL(port->membase));
533 /* port->lock is not held. */
534 static void serial_lpc32xx_shutdown(struct uart_port *port)
539 spin_lock_irqsave(&port->lock, flags);
541 tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
542 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B;
543 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
545 lpc32xx_loopback_set(port->mapbase, 1); /* go to loopback mode */
547 spin_unlock_irqrestore(&port->lock, flags);
549 free_irq(port->irq, port);
552 /* port->lock is not held. */
553 static void serial_lpc32xx_set_termios(struct uart_port *port,
554 struct ktermios *termios,
555 struct ktermios *old)
558 unsigned int baud, quot;
561 /* Always 8-bit, no parity, 1 stop bit */
562 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD);
563 termios->c_cflag |= CS8;
565 termios->c_cflag &= ~(HUPCL | CMSPAR | CLOCAL | CRTSCTS);
567 baud = uart_get_baud_rate(port, termios, old, 0,
570 quot = __serial_get_clock_div(port->uartclk, baud);
572 spin_lock_irqsave(&port->lock, flags);
574 /* Ignore characters? */
575 tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
576 if ((termios->c_cflag & CREAD) == 0)
577 tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN);
579 tmp |= LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN;
580 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
582 writel(quot, LPC32XX_HSUART_RATE(port->membase));
584 uart_update_timeout(port, termios->c_cflag, baud);
586 spin_unlock_irqrestore(&port->lock, flags);
588 /* Don't rewrite B0 */
589 if (tty_termios_baud_rate(termios))
590 tty_termios_encode_baud_rate(termios, baud, baud);
593 static const char *serial_lpc32xx_type(struct uart_port *port)
598 static void serial_lpc32xx_release_port(struct uart_port *port)
600 if ((port->iotype == UPIO_MEM32) && (port->mapbase)) {
601 if (port->flags & UPF_IOREMAP) {
602 iounmap(port->membase);
603 port->membase = NULL;
606 release_mem_region(port->mapbase, SZ_4K);
610 static int serial_lpc32xx_request_port(struct uart_port *port)
614 if ((port->iotype == UPIO_MEM32) && (port->mapbase)) {
617 if (!request_mem_region(port->mapbase, SZ_4K, MODNAME))
619 else if (port->flags & UPF_IOREMAP) {
620 port->membase = ioremap(port->mapbase, SZ_4K);
621 if (!port->membase) {
622 release_mem_region(port->mapbase, SZ_4K);
631 static void serial_lpc32xx_config_port(struct uart_port *port, int uflags)
635 ret = serial_lpc32xx_request_port(port);
638 port->type = PORT_UART00;
641 __serial_uart_flush(port);
643 writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT |
644 LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT),
645 LPC32XX_HSUART_IIR(port->membase));
647 writel(0xFF, LPC32XX_HSUART_RATE(port->membase));
649 /* Set receiver timeout, HSU offset of 20, no break, no interrupts,
650 and default FIFO trigger levels */
651 writel(LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
652 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B,
653 LPC32XX_HSUART_CTRL(port->membase));
656 static int serial_lpc32xx_verify_port(struct uart_port *port,
657 struct serial_struct *ser)
661 if (ser->type != PORT_UART00)
667 static struct uart_ops serial_lpc32xx_pops = {
668 .tx_empty = serial_lpc32xx_tx_empty,
669 .set_mctrl = serial_lpc32xx_set_mctrl,
670 .get_mctrl = serial_lpc32xx_get_mctrl,
671 .stop_tx = serial_lpc32xx_stop_tx,
672 .start_tx = serial_lpc32xx_start_tx,
673 .stop_rx = serial_lpc32xx_stop_rx,
674 .enable_ms = serial_lpc32xx_enable_ms,
675 .break_ctl = serial_lpc32xx_break_ctl,
676 .startup = serial_lpc32xx_startup,
677 .shutdown = serial_lpc32xx_shutdown,
678 .set_termios = serial_lpc32xx_set_termios,
679 .type = serial_lpc32xx_type,
680 .release_port = serial_lpc32xx_release_port,
681 .request_port = serial_lpc32xx_request_port,
682 .config_port = serial_lpc32xx_config_port,
683 .verify_port = serial_lpc32xx_verify_port,
687 * Register a set of serial devices attached to a platform device
689 static int serial_hs_lpc32xx_probe(struct platform_device *pdev)
691 struct lpc32xx_hsuart_port *p = &lpc32xx_hs_ports[uarts_registered];
693 struct resource *res;
695 if (uarts_registered >= MAX_PORTS) {
697 "Error: Number of possible ports exceeded (%d)!\n",
698 uarts_registered + 1);
702 memset(p, 0, sizeof(*p));
704 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
707 "Error getting mem resource for HS UART port %d\n",
711 p->port.mapbase = res->start;
712 p->port.membase = NULL;
714 p->port.irq = platform_get_irq(pdev, 0);
715 if (p->port.irq < 0) {
716 dev_err(&pdev->dev, "Error getting irq for HS UART port %d\n",
721 p->port.iotype = UPIO_MEM32;
722 p->port.uartclk = LPC32XX_MAIN_OSC_FREQ;
723 p->port.regshift = 2;
724 p->port.flags = UPF_BOOT_AUTOCONF | UPF_FIXED_PORT | UPF_IOREMAP;
725 p->port.dev = &pdev->dev;
726 p->port.ops = &serial_lpc32xx_pops;
727 p->port.line = uarts_registered++;
728 spin_lock_init(&p->port.lock);
730 /* send port to loopback mode by default */
731 lpc32xx_loopback_set(p->port.mapbase, 1);
733 ret = uart_add_one_port(&lpc32xx_hs_reg, &p->port);
735 platform_set_drvdata(pdev, p);
741 * Remove serial ports registered against a platform device.
743 static int serial_hs_lpc32xx_remove(struct platform_device *pdev)
745 struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev);
747 uart_remove_one_port(&lpc32xx_hs_reg, &p->port);
754 static int serial_hs_lpc32xx_suspend(struct platform_device *pdev,
757 struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev);
759 uart_suspend_port(&lpc32xx_hs_reg, &p->port);
764 static int serial_hs_lpc32xx_resume(struct platform_device *pdev)
766 struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev);
768 uart_resume_port(&lpc32xx_hs_reg, &p->port);
773 #define serial_hs_lpc32xx_suspend NULL
774 #define serial_hs_lpc32xx_resume NULL
777 static const struct of_device_id serial_hs_lpc32xx_dt_ids[] = {
778 { .compatible = "nxp,lpc3220-hsuart" },
782 MODULE_DEVICE_TABLE(of, serial_hs_lpc32xx_dt_ids);
784 static struct platform_driver serial_hs_lpc32xx_driver = {
785 .probe = serial_hs_lpc32xx_probe,
786 .remove = serial_hs_lpc32xx_remove,
787 .suspend = serial_hs_lpc32xx_suspend,
788 .resume = serial_hs_lpc32xx_resume,
791 .owner = THIS_MODULE,
792 .of_match_table = serial_hs_lpc32xx_dt_ids,
796 static int __init lpc32xx_hsuart_init(void)
800 ret = uart_register_driver(&lpc32xx_hs_reg);
804 ret = platform_driver_register(&serial_hs_lpc32xx_driver);
806 uart_unregister_driver(&lpc32xx_hs_reg);
811 static void __exit lpc32xx_hsuart_exit(void)
813 platform_driver_unregister(&serial_hs_lpc32xx_driver);
814 uart_unregister_driver(&lpc32xx_hs_reg);
817 module_init(lpc32xx_hsuart_init);
818 module_exit(lpc32xx_hsuart_exit);
820 MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
821 MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
822 MODULE_DESCRIPTION("NXP LPC32XX High Speed UART driver");
823 MODULE_LICENSE("GPL");