2 * max3107.c - spi uart protocol driver for Maxim 3107
4 * by Christian Pellegrin <chripell@evolware.org>
6 * by Feng Tang <feng.tang@intel.com>
8 * Copyright (C) Aavamobile 2009
10 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
30 #include <linux/delay.h>
31 #include <linux/device.h>
32 #include <linux/serial_core.h>
33 #include <linux/serial.h>
34 #include <linux/tty.h>
35 #include <linux/tty_flip.h>
36 #include <linux/gpio.h>
37 #include <linux/spi/spi.h>
38 #include <linux/freezer.h>
39 #include <linux/module.h>
42 static const struct baud_table brg26_ext[] = {
43 { 300, MAX3107_BRG26_B300 },
44 { 600, MAX3107_BRG26_B600 },
45 { 1200, MAX3107_BRG26_B1200 },
46 { 2400, MAX3107_BRG26_B2400 },
47 { 4800, MAX3107_BRG26_B4800 },
48 { 9600, MAX3107_BRG26_B9600 },
49 { 19200, MAX3107_BRG26_B19200 },
50 { 57600, MAX3107_BRG26_B57600 },
51 { 115200, MAX3107_BRG26_B115200 },
52 { 230400, MAX3107_BRG26_B230400 },
53 { 460800, MAX3107_BRG26_B460800 },
54 { 921600, MAX3107_BRG26_B921600 },
58 static const struct baud_table brg13_int[] = {
59 { 300, MAX3107_BRG13_IB300 },
60 { 600, MAX3107_BRG13_IB600 },
61 { 1200, MAX3107_BRG13_IB1200 },
62 { 2400, MAX3107_BRG13_IB2400 },
63 { 4800, MAX3107_BRG13_IB4800 },
64 { 9600, MAX3107_BRG13_IB9600 },
65 { 19200, MAX3107_BRG13_IB19200 },
66 { 57600, MAX3107_BRG13_IB57600 },
67 { 115200, MAX3107_BRG13_IB115200 },
68 { 230400, MAX3107_BRG13_IB230400 },
69 { 460800, MAX3107_BRG13_IB460800 },
70 { 921600, MAX3107_BRG13_IB921600 },
74 static u32 get_new_brg(int baud, struct max3107_port *s)
77 const struct baud_table *baud_tbl = s->baud_tbl;
79 for (i = 0; i < 13; i++) {
80 if (baud == baud_tbl[i].baud)
81 return baud_tbl[i].new_brg;
87 /* Perform SPI transfer for write/read of device register(s) */
88 int max3107_rw(struct max3107_port *s, u8 *tx, u8 *rx, int len)
90 struct spi_message spi_msg;
91 struct spi_transfer spi_xfer;
93 /* Initialize SPI ,message */
94 spi_message_init(&spi_msg);
96 /* Initialize SPI transfer */
97 memset(&spi_xfer, 0, sizeof spi_xfer);
100 spi_xfer.rx_buf = rx;
101 spi_xfer.speed_hz = MAX3107_SPI_SPEED;
103 /* Add SPI transfer to SPI message */
104 spi_message_add_tail(&spi_xfer, &spi_msg);
106 #ifdef DBG_TRACE_SPI_DATA
109 pr_info("tx len %d:\n", spi_xfer.len);
110 for (i = 0 ; i < spi_xfer.len && i < 32 ; i++)
111 pr_info(" %x", ((u8 *)spi_xfer.tx_buf)[i]);
116 /* Perform synchronous SPI transfer */
117 if (spi_sync(s->spi, &spi_msg)) {
118 dev_err(&s->spi->dev, "spi_sync failure\n");
122 #ifdef DBG_TRACE_SPI_DATA
123 if (spi_xfer.rx_buf) {
125 pr_info("rx len %d:\n", spi_xfer.len);
126 for (i = 0 ; i < spi_xfer.len && i < 32 ; i++)
127 pr_info(" %x", ((u8 *)spi_xfer.rx_buf)[i]);
133 EXPORT_SYMBOL_GPL(max3107_rw);
135 /* Puts received data to circular buffer */
136 static void put_data_to_circ_buf(struct max3107_port *s, unsigned char *data,
139 struct uart_port *port = &s->port;
140 struct tty_struct *tty;
145 tty = port->state->port.tty;
149 /* Insert received data */
150 tty_insert_flip_string(tty, data, len);
151 /* Update RX counter */
152 port->icount.rx += len;
155 /* Handle data receiving */
156 static void max3107_handlerx(struct max3107_port *s, u16 rxlvl)
160 int len; /* SPI transfer buffer length */
169 /* RX fifo is empty */
171 } else if (rxlvl >= MAX3107_RX_FIFO_SIZE) {
172 dev_warn(&s->spi->dev, "Possible RX FIFO overrun %d\n", rxlvl);
173 /* Ensure sanity of RX level */
174 rxlvl = MAX3107_RX_FIFO_SIZE;
176 if ((s->rxbuf == 0) || (s->rxstr == 0)) {
177 dev_warn(&s->spi->dev, "Rx buffer/str isn't ready\n");
181 valid_str = s->rxstr;
183 pr_debug("rxlvl %d\n", rxlvl);
185 memset(buf, 0, sizeof(u16) * (MAX3107_RX_FIFO_SIZE + 2));
187 if (s->irqen_reg & MAX3107_IRQ_RXFIFO_BIT) {
188 /* First disable RX FIFO interrupt */
189 pr_debug("Disabling RX INT\n");
190 buf[0] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
191 s->irqen_reg &= ~MAX3107_IRQ_RXFIFO_BIT;
192 buf[0] |= s->irqen_reg;
195 /* Just increase the length by amount of words in FIFO since
196 * buffer was zeroed and SPI transfer of 0x0000 means reading
200 /* Append RX level query */
201 buf[len] = MAX3107_RXFIFOLVL_REG;
204 /* Perform the SPI transfer */
205 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, len * 2)) {
206 dev_err(&s->spi->dev, "SPI transfer for RX h failed\n");
210 /* Skip RX FIFO interrupt disabling word if it was added */
211 j = ((len - 1) - rxlvl);
212 /* Read received words */
213 for (i = 0; i < rxlvl; i++, j++)
214 valid_str[i] = (u8)buf[j];
215 put_data_to_circ_buf(s, valid_str, rxlvl);
216 /* Get new RX level */
217 rxlvl = (buf[len - 1] & MAX3107_SPI_RX_DATA_MASK);
221 /* RX still enabled, re-enable RX FIFO interrupt */
222 pr_debug("Enabling RX INT\n");
223 buf[0] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
224 s->irqen_reg |= MAX3107_IRQ_RXFIFO_BIT;
225 buf[0] |= s->irqen_reg;
226 if (max3107_rw(s, (u8 *)buf, NULL, 2))
227 dev_err(&s->spi->dev, "RX FIFO INT enabling failed\n");
230 /* Push the received data to receivers */
231 if (s->port.state->port.tty)
232 tty_flip_buffer_push(s->port.state->port.tty);
236 /* Handle data sending */
237 static void max3107_handletx(struct max3107_port *s)
239 struct circ_buf *xmit = &s->port.state->xmit;
242 int len; /* SPI transfer buffer length */
245 if (!s->tx_fifo_empty)
246 /* Don't send more data before previous data is sent */
249 if (uart_circ_empty(xmit) || uart_tx_stopped(&s->port))
250 /* No data to send or TX is stopped */
254 dev_warn(&s->spi->dev, "Txbuf isn't ready\n");
258 /* Get length of data pending in circular buffer */
259 len = uart_circ_chars_pending(xmit);
261 /* Limit to size of TX FIFO */
262 if (len > MAX3107_TX_FIFO_SIZE)
263 len = MAX3107_TX_FIFO_SIZE;
265 pr_debug("txlen %d\n", len);
267 /* Update TX counter */
268 s->port.icount.tx += len;
270 /* TX FIFO will no longer be empty */
271 s->tx_fifo_empty = 0;
274 if (s->irqen_reg & MAX3107_IRQ_TXEMPTY_BIT) {
275 /* First disable TX empty interrupt */
276 pr_debug("Disabling TE INT\n");
277 buf[i] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
278 s->irqen_reg &= ~MAX3107_IRQ_TXEMPTY_BIT;
279 buf[i] |= s->irqen_reg;
283 /* Add data to send */
284 spin_lock_irqsave(&s->port.lock, flags);
285 for ( ; i < len ; i++) {
286 buf[i] = (MAX3107_WRITE_BIT | MAX3107_THR_REG);
287 buf[i] |= ((u16)xmit->buf[xmit->tail] &
288 MAX3107_SPI_TX_DATA_MASK);
289 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
291 spin_unlock_irqrestore(&s->port.lock, flags);
292 if (!(s->irqen_reg & MAX3107_IRQ_TXEMPTY_BIT)) {
293 /* Enable TX empty interrupt */
294 pr_debug("Enabling TE INT\n");
295 buf[i] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
296 s->irqen_reg |= MAX3107_IRQ_TXEMPTY_BIT;
297 buf[i] |= s->irqen_reg;
301 if (!s->tx_enabled) {
303 pr_debug("Enable TX\n");
304 buf[i] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG);
305 spin_lock_irqsave(&s->data_lock, flags);
306 s->mode1_reg &= ~MAX3107_MODE1_TXDIS_BIT;
307 buf[i] |= s->mode1_reg;
308 spin_unlock_irqrestore(&s->data_lock, flags);
314 /* Perform the SPI transfer */
315 if (max3107_rw(s, (u8 *)buf, NULL, len*2)) {
316 dev_err(&s->spi->dev,
317 "SPI transfer TX handling failed\n");
322 /* Indicate wake up if circular buffer is getting low on data */
323 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
324 uart_write_wakeup(&s->port);
329 * Also reads and returns current RX FIFO level
331 static u16 handle_interrupt(struct max3107_port *s)
333 u16 buf[4]; /* Buffer for SPI transfers */
338 /* Read IRQ status register */
339 buf[0] = MAX3107_IRQSTS_REG;
340 /* Read status IRQ status register */
341 buf[1] = MAX3107_STS_IRQSTS_REG;
342 /* Read LSR IRQ status register */
343 buf[2] = MAX3107_LSR_IRQSTS_REG;
345 buf[3] = MAX3107_RXFIFOLVL_REG;
347 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 8)) {
348 dev_err(&s->spi->dev,
349 "SPI transfer for INTR handling failed\n");
353 irq_status = (u8)buf[0];
354 pr_debug("IRQSTS %x\n", irq_status);
355 rx_level = (buf[3] & MAX3107_SPI_RX_DATA_MASK);
357 if (irq_status & MAX3107_IRQ_LSR_BIT) {
359 if (buf[2] & MAX3107_LSR_RXTO_BIT)
360 /* RX timeout interrupt,
361 * handled by normal RX handling
363 pr_debug("RX TO INT\n");
366 if (irq_status & MAX3107_IRQ_TXEMPTY_BIT) {
367 /* Tx empty interrupt,
368 * disable TX and set tx_fifo_empty flag
370 pr_debug("TE INT, disabling TX\n");
371 buf[0] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG);
372 spin_lock_irqsave(&s->data_lock, flags);
373 s->mode1_reg |= MAX3107_MODE1_TXDIS_BIT;
374 buf[0] |= s->mode1_reg;
375 spin_unlock_irqrestore(&s->data_lock, flags);
376 if (max3107_rw(s, (u8 *)buf, NULL, 2))
377 dev_err(&s->spi->dev, "SPI transfer TX dis failed\n");
379 s->tx_fifo_empty = 1;
382 if (irq_status & MAX3107_IRQ_RXFIFO_BIT)
383 /* RX FIFO interrupt,
384 * handled by normal RX handling
386 pr_debug("RFIFO INT\n");
388 /* Return RX level */
392 /* Trigger work thread*/
393 static void max3107_dowork(struct max3107_port *s)
395 if (!work_pending(&s->work) && !freezing(current) && !s->suspended)
396 queue_work(s->workqueue, &s->work);
398 dev_warn(&s->spi->dev, "interrup isn't serviced normally!\n");
402 static void max3107_work(struct work_struct *w)
404 struct max3107_port *s = container_of(w, struct max3107_port, work);
406 int len; /* SPI transfer buffer length */
407 u16 buf[5]; /* Buffer for SPI transfers */
410 /* Start by reading current RX FIFO level */
411 buf[0] = MAX3107_RXFIFOLVL_REG;
412 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 2)) {
413 dev_err(&s->spi->dev, "SPI transfer RX lev failed\n");
416 rxlvl = (buf[0] & MAX3107_SPI_RX_DATA_MASK);
420 pr_debug("rxlvl %d\n", rxlvl);
423 max3107_handlerx(s, rxlvl);
427 /* Handle pending interrupts
428 * We also get new RX FIFO level since new data may
429 * have been received while pushing received data to
433 rxlvl = handle_interrupt(s);
439 /* Handle configuration changes */
441 spin_lock_irqsave(&s->data_lock, flags);
442 if (s->mode1_commit) {
443 pr_debug("mode1_commit\n");
444 buf[len] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG);
445 buf[len++] |= s->mode1_reg;
449 pr_debug("lcr_commit\n");
450 buf[len] = (MAX3107_WRITE_BIT | MAX3107_LCR_REG);
451 buf[len++] |= s->lcr_reg;
455 pr_debug("brg_commit\n");
456 buf[len] = (MAX3107_WRITE_BIT | MAX3107_BRGDIVMSB_REG);
457 buf[len++] |= ((s->brg_cfg >> 16) &
458 MAX3107_SPI_TX_DATA_MASK);
459 buf[len] = (MAX3107_WRITE_BIT | MAX3107_BRGDIVLSB_REG);
460 buf[len++] |= ((s->brg_cfg >> 8) &
461 MAX3107_SPI_TX_DATA_MASK);
462 buf[len] = (MAX3107_WRITE_BIT | MAX3107_BRGCFG_REG);
463 buf[len++] |= ((s->brg_cfg) & 0xff);
466 spin_unlock_irqrestore(&s->data_lock, flags);
469 if (max3107_rw(s, (u8 *)buf, NULL, len * 2))
470 dev_err(&s->spi->dev,
471 "SPI transfer config failed\n");
474 /* Reloop if interrupt handling indicated data in RX FIFO */
480 static void max3107_set_sleep(struct max3107_port *s, int mode)
482 u16 buf[1]; /* Buffer for SPI transfer */
484 pr_debug("enter, mode %d\n", mode);
486 buf[0] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG);
487 spin_lock_irqsave(&s->data_lock, flags);
489 case MAX3107_DISABLE_FORCED_SLEEP:
490 s->mode1_reg &= ~MAX3107_MODE1_FORCESLEEP_BIT;
492 case MAX3107_ENABLE_FORCED_SLEEP:
493 s->mode1_reg |= MAX3107_MODE1_FORCESLEEP_BIT;
495 case MAX3107_DISABLE_AUTOSLEEP:
496 s->mode1_reg &= ~MAX3107_MODE1_AUTOSLEEP_BIT;
498 case MAX3107_ENABLE_AUTOSLEEP:
499 s->mode1_reg |= MAX3107_MODE1_AUTOSLEEP_BIT;
502 spin_unlock_irqrestore(&s->data_lock, flags);
503 dev_warn(&s->spi->dev, "invalid sleep mode\n");
506 buf[0] |= s->mode1_reg;
507 spin_unlock_irqrestore(&s->data_lock, flags);
509 if (max3107_rw(s, (u8 *)buf, NULL, 2))
510 dev_err(&s->spi->dev, "SPI transfer sleep mode failed\n");
512 if (mode == MAX3107_DISABLE_AUTOSLEEP ||
513 mode == MAX3107_DISABLE_FORCED_SLEEP)
514 msleep(MAX3107_WAKEUP_DELAY);
517 /* Perform full register initialization */
518 static void max3107_register_init(struct max3107_port *s)
520 u16 buf[11]; /* Buffer for SPI transfers */
522 /* 1. Configure baud rate, 9600 as default */
524 /* the below is default*/
526 s->brg_cfg = MAX3107_BRG26_B9600;
527 s->baud_tbl = (struct baud_table *)brg26_ext;
529 s->brg_cfg = MAX3107_BRG13_IB9600;
530 s->baud_tbl = (struct baud_table *)brg13_int;
536 buf[0] = (MAX3107_WRITE_BIT | MAX3107_BRGDIVMSB_REG)
537 | ((s->brg_cfg >> 16) & MAX3107_SPI_TX_DATA_MASK);
538 buf[1] = (MAX3107_WRITE_BIT | MAX3107_BRGDIVLSB_REG)
539 | ((s->brg_cfg >> 8) & MAX3107_SPI_TX_DATA_MASK);
540 buf[2] = (MAX3107_WRITE_BIT | MAX3107_BRGCFG_REG)
541 | ((s->brg_cfg) & 0xff);
543 /* 2. Configure LCR register, 8N1 mode by default */
544 s->lcr_reg = MAX3107_LCR_WORD_LEN_8;
545 buf[3] = (MAX3107_WRITE_BIT | MAX3107_LCR_REG)
548 /* 3. Configure MODE 1 register */
551 s->mode1_reg |= MAX3107_MODE1_IRQSEL_BIT;
553 s->mode1_reg |= MAX3107_MODE1_TXDIS_BIT;
557 buf[4] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG)
560 /* 4. Configure MODE 2 register */
561 buf[5] = (MAX3107_WRITE_BIT | MAX3107_MODE2_REG);
563 /* Enable loopback */
564 buf[5] |= MAX3107_MODE2_LOOPBACK_BIT;
567 buf[5] |= MAX3107_MODE2_FIFORST_BIT;
568 s->tx_fifo_empty = 1;
570 /* 5. Configure FIFO trigger level register */
571 buf[6] = (MAX3107_WRITE_BIT | MAX3107_FIFOTRIGLVL_REG);
572 /* RX FIFO trigger for 16 words, TX FIFO trigger not used */
573 buf[6] |= (MAX3107_FIFOTRIGLVL_RX(16) | MAX3107_FIFOTRIGLVL_TX(0));
575 /* 6. Configure flow control levels */
576 buf[7] = (MAX3107_WRITE_BIT | MAX3107_FLOWLVL_REG);
577 /* Flow control halt level 96, resume level 48 */
578 buf[7] |= (MAX3107_FLOWLVL_RES(48) | MAX3107_FLOWLVL_HALT(96));
580 /* 7. Configure flow control */
581 buf[8] = (MAX3107_WRITE_BIT | MAX3107_FLOWCTRL_REG);
582 /* Enable auto CTS and auto RTS flow control */
583 buf[8] |= (MAX3107_FLOWCTRL_AUTOCTS_BIT | MAX3107_FLOWCTRL_AUTORTS_BIT);
585 /* 8. Configure RX timeout register */
586 buf[9] = (MAX3107_WRITE_BIT | MAX3107_RXTO_REG);
587 /* Timeout after 48 character intervals */
590 /* 9. Configure LSR interrupt enable register */
591 buf[10] = (MAX3107_WRITE_BIT | MAX3107_LSR_IRQEN_REG);
592 /* Enable RX timeout interrupt */
593 buf[10] |= MAX3107_LSR_RXTO_BIT;
595 /* Perform SPI transfer */
596 if (max3107_rw(s, (u8 *)buf, NULL, 22))
597 dev_err(&s->spi->dev, "SPI transfer for init failed\n");
599 /* 10. Clear IRQ status register by reading it */
600 buf[0] = MAX3107_IRQSTS_REG;
602 /* 11. Configure interrupt enable register */
603 /* Enable LSR interrupt */
604 s->irqen_reg = MAX3107_IRQ_LSR_BIT;
605 /* Enable RX FIFO interrupt */
606 s->irqen_reg |= MAX3107_IRQ_RXFIFO_BIT;
607 buf[1] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG)
610 /* 12. Clear FIFO reset that was set in step 6 */
611 buf[2] = (MAX3107_WRITE_BIT | MAX3107_MODE2_REG);
613 /* Keep loopback enabled */
614 buf[2] |= MAX3107_MODE2_LOOPBACK_BIT;
617 /* Perform SPI transfer */
618 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 6))
619 dev_err(&s->spi->dev, "SPI transfer for init failed\n");
624 static irqreturn_t max3107_irq(int irqno, void *dev_id)
626 struct max3107_port *s = dev_id;
628 if (irqno != s->spi->irq) {
636 /* Trigger work thread */
642 /* HW suspension function
644 * Currently autosleep is used to decrease current consumption, alternative
645 * approach would be to set the chip to reset mode if UART is not being
646 * used but that would mess the GPIOs
649 void max3107_hw_susp(struct max3107_port *s, int suspend)
651 pr_debug("enter, suspend %d\n", suspend);
654 /* Suspend requested,
655 * enable autosleep to decrease current consumption
658 max3107_set_sleep(s, MAX3107_ENABLE_AUTOSLEEP);
664 max3107_set_sleep(s, MAX3107_DISABLE_AUTOSLEEP);
667 EXPORT_SYMBOL_GPL(max3107_hw_susp);
669 /* Modem status IRQ enabling */
670 static void max3107_enable_ms(struct uart_port *port)
672 /* Modem status not supported */
675 /* Data send function */
676 static void max3107_start_tx(struct uart_port *port)
678 struct max3107_port *s = container_of(port, struct max3107_port, port);
680 /* Trigger work thread for sending data */
684 /* Function for checking that there is no pending transfers */
685 static unsigned int max3107_tx_empty(struct uart_port *port)
687 struct max3107_port *s = container_of(port, struct max3107_port, port);
689 pr_debug("returning %d\n",
690 (s->tx_fifo_empty && uart_circ_empty(&s->port.state->xmit)));
691 return s->tx_fifo_empty && uart_circ_empty(&s->port.state->xmit);
694 /* Function for stopping RX */
695 static void max3107_stop_rx(struct uart_port *port)
697 struct max3107_port *s = container_of(port, struct max3107_port, port);
700 /* Set RX disabled in MODE 1 register */
701 spin_lock_irqsave(&s->data_lock, flags);
702 s->mode1_reg |= MAX3107_MODE1_RXDIS_BIT;
704 spin_unlock_irqrestore(&s->data_lock, flags);
705 /* Set RX disabled */
707 /* Trigger work thread for doing the actual configuration change */
711 /* Function for returning control pin states */
712 static unsigned int max3107_get_mctrl(struct uart_port *port)
714 /* DCD and DSR are not wired and CTS/RTS is handled automatically
715 * so just indicate DSR and CAR asserted
717 return TIOCM_DSR | TIOCM_CAR;
720 /* Function for setting control pin states */
721 static void max3107_set_mctrl(struct uart_port *port, unsigned int mctrl)
723 /* DCD and DSR are not wired and CTS/RTS is hadnled automatically
728 /* Function for configuring UART parameters */
729 static void max3107_set_termios(struct uart_port *port,
730 struct ktermios *termios,
731 struct ktermios *old)
733 struct max3107_port *s = container_of(port, struct max3107_port, port);
734 struct tty_struct *tty;
743 tty = port->state->port.tty;
747 /* Get new LCR register values */
749 if ((termios->c_cflag & CSIZE) == CS7)
750 new_lcr |= MAX3107_LCR_WORD_LEN_7;
752 new_lcr |= MAX3107_LCR_WORD_LEN_8;
755 if (termios->c_cflag & PARENB) {
756 new_lcr |= MAX3107_LCR_PARITY_BIT;
757 if (!(termios->c_cflag & PARODD))
758 new_lcr |= MAX3107_LCR_EVENPARITY_BIT;
762 if (termios->c_cflag & CSTOPB) {
764 new_lcr |= MAX3107_LCR_STOPLEN_BIT;
767 /* Mask termios capabilities we don't support */
768 termios->c_cflag &= ~CMSPAR;
770 /* Set status ignore mask */
771 s->port.ignore_status_mask = 0;
772 if (termios->c_iflag & IGNPAR)
773 s->port.ignore_status_mask |= MAX3107_ALL_ERRORS;
775 /* Set low latency to immediately handle pushed data */
776 s->port.state->port.tty->low_latency = 1;
778 /* Get new baud rate generator configuration */
779 baud = tty_get_baud_rate(tty);
781 spin_lock_irqsave(&s->data_lock, flags);
782 new_brg = get_new_brg(baud, s);
783 /* if can't find the corrent config, use previous */
786 new_brg = s->brg_cfg;
788 spin_unlock_irqrestore(&s->data_lock, flags);
789 tty_termios_encode_baud_rate(termios, baud, baud);
792 /* Update timeout according to new baud rate */
793 uart_update_timeout(port, termios->c_cflag, baud);
795 spin_lock_irqsave(&s->data_lock, flags);
796 if (s->lcr_reg != new_lcr) {
797 s->lcr_reg = new_lcr;
800 if (s->brg_cfg != new_brg) {
801 s->brg_cfg = new_brg;
804 spin_unlock_irqrestore(&s->data_lock, flags);
806 /* Trigger work thread for doing the actual configuration change */
810 /* Port shutdown function */
811 static void max3107_shutdown(struct uart_port *port)
813 struct max3107_port *s = container_of(port, struct max3107_port, port);
815 if (s->suspended && s->pdata->hw_suspend)
816 s->pdata->hw_suspend(s, 0);
818 /* Free the interrupt */
819 free_irq(s->spi->irq, s);
822 /* Flush and destroy work queue */
823 flush_workqueue(s->workqueue);
824 destroy_workqueue(s->workqueue);
829 if (s->pdata->hw_suspend)
830 s->pdata->hw_suspend(s, 1);
833 /* Port startup function */
834 static int max3107_startup(struct uart_port *port)
836 struct max3107_port *s = container_of(port, struct max3107_port, port);
838 /* Initialize work queue */
839 s->workqueue = create_freezable_workqueue("max3107");
841 dev_err(&s->spi->dev, "Workqueue creation failed\n");
844 INIT_WORK(&s->work, max3107_work);
847 if (request_irq(s->spi->irq, max3107_irq, IRQF_TRIGGER_FALLING,
849 dev_err(&s->spi->dev, "IRQ reguest failed\n");
850 destroy_workqueue(s->workqueue);
856 if (s->pdata->hw_suspend)
857 s->pdata->hw_suspend(s, 0);
860 max3107_register_init(s);
865 /* Port type function */
866 static const char *max3107_type(struct uart_port *port)
868 struct max3107_port *s = container_of(port, struct max3107_port, port);
869 return s->spi->modalias;
872 /* Port release function */
873 static void max3107_release_port(struct uart_port *port)
878 /* Port request function */
879 static int max3107_request_port(struct uart_port *port)
885 /* Port config function */
886 static void max3107_config_port(struct uart_port *port, int flags)
888 struct max3107_port *s = container_of(port, struct max3107_port, port);
889 s->port.type = PORT_MAX3107;
892 /* Port verify function */
893 static int max3107_verify_port(struct uart_port *port,
894 struct serial_struct *ser)
896 if (ser->type == PORT_UNKNOWN || ser->type == PORT_MAX3107)
902 /* Port stop TX function */
903 static void max3107_stop_tx(struct uart_port *port)
908 /* Port break control function */
909 static void max3107_break_ctl(struct uart_port *port, int break_state)
911 /* We don't support break control, do nothing */
916 static struct uart_ops max3107_ops = {
917 .tx_empty = max3107_tx_empty,
918 .set_mctrl = max3107_set_mctrl,
919 .get_mctrl = max3107_get_mctrl,
920 .stop_tx = max3107_stop_tx,
921 .start_tx = max3107_start_tx,
922 .stop_rx = max3107_stop_rx,
923 .enable_ms = max3107_enable_ms,
924 .break_ctl = max3107_break_ctl,
925 .startup = max3107_startup,
926 .shutdown = max3107_shutdown,
927 .set_termios = max3107_set_termios,
928 .type = max3107_type,
929 .release_port = max3107_release_port,
930 .request_port = max3107_request_port,
931 .config_port = max3107_config_port,
932 .verify_port = max3107_verify_port,
935 /* UART driver data */
936 static struct uart_driver max3107_uart_driver = {
937 .owner = THIS_MODULE,
938 .driver_name = "ttyMAX",
939 .dev_name = "ttyMAX",
943 static int driver_registered = 0;
947 /* 'Generic' platform data */
948 static struct max3107_plat generic_plat_data = {
951 .hw_suspend = max3107_hw_susp,
957 /*******************************************************************/
960 * max3107_probe - SPI bus probe entry point
961 * @spi: the spi device
963 * SPI wants us to probe this device and if appropriate claim it.
964 * Perform any platform specific requirements and then initialise
968 int max3107_probe(struct spi_device *spi, struct max3107_plat *pdata)
970 struct max3107_port *s;
971 u16 buf[2]; /* Buffer for SPI transfers */
974 pr_info("enter max3107 probe\n");
976 /* Allocate port structure */
977 s = kzalloc(sizeof(*s), GFP_KERNEL);
979 pr_err("Allocating port structure failed\n");
986 * +2 for RX FIFO interrupt
987 * disabling and RX level query
989 s->rxbuf = kzalloc(sizeof(u16) * (MAX3107_RX_FIFO_SIZE+2), GFP_KERNEL);
991 pr_err("Allocating RX buffer failed\n");
995 s->rxstr = kzalloc(sizeof(u8) * MAX3107_RX_FIFO_SIZE, GFP_KERNEL);
997 pr_err("Allocating RX buffer failed\n");
1002 * SPI transfer buffer
1003 * +3 for TX FIFO empty
1004 * interrupt disabling and
1005 * enabling and TX enabling
1007 s->txbuf = kzalloc(sizeof(u16) * MAX3107_TX_FIFO_SIZE + 3, GFP_KERNEL);
1009 pr_err("Allocating TX buffer failed\n");
1013 /* Initialize shared data lock */
1014 spin_lock_init(&s->data_lock);
1016 /* SPI intializations */
1017 dev_set_drvdata(&spi->dev, s);
1018 spi->mode = SPI_MODE_0;
1019 spi->dev.platform_data = pdata;
1020 spi->bits_per_word = 16;
1021 s->ext_clk = pdata->ext_clk;
1022 s->loopback = pdata->loopback;
1026 /* Check REV ID to ensure we are talking to what we expect */
1027 buf[0] = MAX3107_REVID_REG;
1028 if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 2)) {
1029 dev_err(&s->spi->dev, "SPI transfer for REVID read failed\n");
1033 if ((buf[0] & MAX3107_SPI_RX_DATA_MASK) != MAX3107_REVID1 &&
1034 (buf[0] & MAX3107_SPI_RX_DATA_MASK) != MAX3107_REVID2) {
1035 dev_err(&s->spi->dev, "REVID %x does not match\n",
1036 (buf[0] & MAX3107_SPI_RX_DATA_MASK));
1041 /* Disable all interrupts */
1042 buf[0] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG | 0x0000);
1045 /* Configure clock source */
1046 buf[1] = (MAX3107_WRITE_BIT | MAX3107_CLKSRC_REG);
1048 /* External clock */
1049 buf[1] |= MAX3107_CLKSRC_EXTCLK_BIT;
1053 buf[1] |= MAX3107_CLKSRC_PLLBYP_BIT;
1055 /* Perform SPI transfer */
1056 if (max3107_rw(s, (u8 *)buf, NULL, 4)) {
1057 dev_err(&s->spi->dev, "SPI transfer for init failed\n");
1062 /* Register UART driver */
1063 if (!driver_registered) {
1064 retval = uart_register_driver(&max3107_uart_driver);
1066 dev_err(&s->spi->dev, "Registering UART driver failed\n");
1069 driver_registered = 1;
1072 /* Initialize UART port data */
1073 s->port.fifosize = 128;
1074 s->port.ops = &max3107_ops;
1076 s->port.dev = &spi->dev;
1077 s->port.uartclk = 9600;
1078 s->port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF;
1079 s->port.irq = s->spi->irq;
1080 s->port.type = PORT_MAX3107;
1083 retval = uart_add_one_port(&max3107_uart_driver, &s->port);
1085 dev_err(&s->spi->dev, "Adding UART port failed\n");
1089 if (pdata->configure) {
1090 retval = pdata->configure(s);
1095 /* Go to suspend mode */
1096 if (pdata->hw_suspend)
1097 pdata->hw_suspend(s, 1);
1111 EXPORT_SYMBOL_GPL(max3107_probe);
1113 /* Driver remove function */
1114 int max3107_remove(struct spi_device *spi)
1116 struct max3107_port *s = dev_get_drvdata(&spi->dev);
1118 pr_info("enter max3107 remove\n");
1121 if (uart_remove_one_port(&max3107_uart_driver, &s->port))
1122 dev_warn(&s->spi->dev, "Removing UART port failed\n");
1125 /* Free TxRx buffer */
1130 /* Free port structure */
1135 EXPORT_SYMBOL_GPL(max3107_remove);
1137 /* Driver suspend function */
1138 int max3107_suspend(struct spi_device *spi, pm_message_t state)
1141 struct max3107_port *s = dev_get_drvdata(&spi->dev);
1143 pr_debug("enter suspend\n");
1145 /* Suspend UART port */
1146 uart_suspend_port(&max3107_uart_driver, &s->port);
1148 /* Go to suspend mode */
1149 if (s->pdata->hw_suspend)
1150 s->pdata->hw_suspend(s, 1);
1151 #endif /* CONFIG_PM */
1154 EXPORT_SYMBOL_GPL(max3107_suspend);
1156 /* Driver resume function */
1157 int max3107_resume(struct spi_device *spi)
1160 struct max3107_port *s = dev_get_drvdata(&spi->dev);
1162 pr_debug("enter resume\n");
1164 /* Resume from suspend */
1165 if (s->pdata->hw_suspend)
1166 s->pdata->hw_suspend(s, 0);
1168 /* Resume UART port */
1169 uart_resume_port(&max3107_uart_driver, &s->port);
1170 #endif /* CONFIG_PM */
1173 EXPORT_SYMBOL_GPL(max3107_resume);
1175 static int max3107_probe_generic(struct spi_device *spi)
1177 return max3107_probe(spi, &generic_plat_data);
1180 /* Spi driver data */
1181 static struct spi_driver max3107_driver = {
1184 .owner = THIS_MODULE,
1186 .probe = max3107_probe_generic,
1187 .remove = __devexit_p(max3107_remove),
1188 .suspend = max3107_suspend,
1189 .resume = max3107_resume,
1192 /* Driver init function */
1193 static int __init max3107_init(void)
1195 pr_info("enter max3107 init\n");
1196 return spi_register_driver(&max3107_driver);
1199 /* Driver exit function */
1200 static void __exit max3107_exit(void)
1202 pr_info("enter max3107 exit\n");
1203 /* Unregister UART driver */
1204 if (driver_registered)
1205 uart_unregister_driver(&max3107_uart_driver);
1206 spi_unregister_driver(&max3107_driver);
1209 module_init(max3107_init);
1210 module_exit(max3107_exit);
1212 MODULE_DESCRIPTION("MAX3107 driver");
1213 MODULE_AUTHOR("Aavamobile");
1214 MODULE_ALIAS("spi:max3107");
1215 MODULE_LICENSE("GPL v2");