2 * Maxim (Dallas) MAX3107/8 serial driver
4 * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
6 * Based on max3100.c, by Christian Pellegrin <chripell@evolware.org>
7 * Based on max3110.c, by Feng Tang <feng.tang@intel.com>
8 * Based on max3107.c, by Aavamobile
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
16 /* TODO: MAX3109 support (Dual) */
17 /* TODO: MAX14830 support (Quad) */
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/serial_core.h>
22 #include <linux/serial.h>
23 #include <linux/tty.h>
24 #include <linux/tty_flip.h>
25 #include <linux/regmap.h>
26 #include <linux/gpio.h>
27 #include <linux/spi/spi.h>
28 #include <linux/platform_data/max310x.h>
30 #define MAX310X_MAJOR 204
31 #define MAX310X_MINOR 209
33 /* MAX310X register definitions */
34 #define MAX310X_RHR_REG (0x00) /* RX FIFO */
35 #define MAX310X_THR_REG (0x00) /* TX FIFO */
36 #define MAX310X_IRQEN_REG (0x01) /* IRQ enable */
37 #define MAX310X_IRQSTS_REG (0x02) /* IRQ status */
38 #define MAX310X_LSR_IRQEN_REG (0x03) /* LSR IRQ enable */
39 #define MAX310X_LSR_IRQSTS_REG (0x04) /* LSR IRQ status */
40 #define MAX310X_SPCHR_IRQEN_REG (0x05) /* Special char IRQ enable */
41 #define MAX310X_SPCHR_IRQSTS_REG (0x06) /* Special char IRQ status */
42 #define MAX310X_STS_IRQEN_REG (0x07) /* Status IRQ enable */
43 #define MAX310X_STS_IRQSTS_REG (0x08) /* Status IRQ status */
44 #define MAX310X_MODE1_REG (0x09) /* MODE1 */
45 #define MAX310X_MODE2_REG (0x0a) /* MODE2 */
46 #define MAX310X_LCR_REG (0x0b) /* LCR */
47 #define MAX310X_RXTO_REG (0x0c) /* RX timeout */
48 #define MAX310X_HDPIXDELAY_REG (0x0d) /* Auto transceiver delays */
49 #define MAX310X_IRDA_REG (0x0e) /* IRDA settings */
50 #define MAX310X_FLOWLVL_REG (0x0f) /* Flow control levels */
51 #define MAX310X_FIFOTRIGLVL_REG (0x10) /* FIFO IRQ trigger levels */
52 #define MAX310X_TXFIFOLVL_REG (0x11) /* TX FIFO level */
53 #define MAX310X_RXFIFOLVL_REG (0x12) /* RX FIFO level */
54 #define MAX310X_FLOWCTRL_REG (0x13) /* Flow control */
55 #define MAX310X_XON1_REG (0x14) /* XON1 character */
56 #define MAX310X_XON2_REG (0x15) /* XON2 character */
57 #define MAX310X_XOFF1_REG (0x16) /* XOFF1 character */
58 #define MAX310X_XOFF2_REG (0x17) /* XOFF2 character */
59 #define MAX310X_GPIOCFG_REG (0x18) /* GPIO config */
60 #define MAX310X_GPIODATA_REG (0x19) /* GPIO data */
61 #define MAX310X_PLLCFG_REG (0x1a) /* PLL config */
62 #define MAX310X_BRGCFG_REG (0x1b) /* Baud rate generator conf */
63 #define MAX310X_BRGDIVLSB_REG (0x1c) /* Baud rate divisor LSB */
64 #define MAX310X_BRGDIVMSB_REG (0x1d) /* Baud rate divisor MSB */
65 #define MAX310X_CLKSRC_REG (0x1e) /* Clock source */
66 /* Only present in MAX3107 */
67 #define MAX3107_REVID_REG (0x1f) /* Revision identification */
69 /* IRQ register bits */
70 #define MAX310X_IRQ_LSR_BIT (1 << 0) /* LSR interrupt */
71 #define MAX310X_IRQ_SPCHR_BIT (1 << 1) /* Special char interrupt */
72 #define MAX310X_IRQ_STS_BIT (1 << 2) /* Status interrupt */
73 #define MAX310X_IRQ_RXFIFO_BIT (1 << 3) /* RX FIFO interrupt */
74 #define MAX310X_IRQ_TXFIFO_BIT (1 << 4) /* TX FIFO interrupt */
75 #define MAX310X_IRQ_TXEMPTY_BIT (1 << 5) /* TX FIFO empty interrupt */
76 #define MAX310X_IRQ_RXEMPTY_BIT (1 << 6) /* RX FIFO empty interrupt */
77 #define MAX310X_IRQ_CTS_BIT (1 << 7) /* CTS interrupt */
79 /* LSR register bits */
80 #define MAX310X_LSR_RXTO_BIT (1 << 0) /* RX timeout */
81 #define MAX310X_LSR_RXOVR_BIT (1 << 1) /* RX overrun */
82 #define MAX310X_LSR_RXPAR_BIT (1 << 2) /* RX parity error */
83 #define MAX310X_LSR_FRERR_BIT (1 << 3) /* Frame error */
84 #define MAX310X_LSR_RXBRK_BIT (1 << 4) /* RX break */
85 #define MAX310X_LSR_RXNOISE_BIT (1 << 5) /* RX noise */
86 #define MAX310X_LSR_CTS_BIT (1 << 7) /* CTS pin state */
88 /* Special character register bits */
89 #define MAX310X_SPCHR_XON1_BIT (1 << 0) /* XON1 character */
90 #define MAX310X_SPCHR_XON2_BIT (1 << 1) /* XON2 character */
91 #define MAX310X_SPCHR_XOFF1_BIT (1 << 2) /* XOFF1 character */
92 #define MAX310X_SPCHR_XOFF2_BIT (1 << 3) /* XOFF2 character */
93 #define MAX310X_SPCHR_BREAK_BIT (1 << 4) /* RX break */
94 #define MAX310X_SPCHR_MULTIDROP_BIT (1 << 5) /* 9-bit multidrop addr char */
96 /* Status register bits */
97 #define MAX310X_STS_GPIO0_BIT (1 << 0) /* GPIO 0 interrupt */
98 #define MAX310X_STS_GPIO1_BIT (1 << 1) /* GPIO 1 interrupt */
99 #define MAX310X_STS_GPIO2_BIT (1 << 2) /* GPIO 2 interrupt */
100 #define MAX310X_STS_GPIO3_BIT (1 << 3) /* GPIO 3 interrupt */
101 #define MAX310X_STS_CLKREADY_BIT (1 << 5) /* Clock ready */
102 #define MAX310X_STS_SLEEP_BIT (1 << 6) /* Sleep interrupt */
104 /* MODE1 register bits */
105 #define MAX310X_MODE1_RXDIS_BIT (1 << 0) /* RX disable */
106 #define MAX310X_MODE1_TXDIS_BIT (1 << 1) /* TX disable */
107 #define MAX310X_MODE1_TXHIZ_BIT (1 << 2) /* TX pin three-state */
108 #define MAX310X_MODE1_RTSHIZ_BIT (1 << 3) /* RTS pin three-state */
109 #define MAX310X_MODE1_TRNSCVCTRL_BIT (1 << 4) /* Transceiver ctrl enable */
110 #define MAX310X_MODE1_FORCESLEEP_BIT (1 << 5) /* Force sleep mode */
111 #define MAX310X_MODE1_AUTOSLEEP_BIT (1 << 6) /* Auto sleep enable */
112 #define MAX310X_MODE1_IRQSEL_BIT (1 << 7) /* IRQ pin enable */
114 /* MODE2 register bits */
115 #define MAX310X_MODE2_RST_BIT (1 << 0) /* Chip reset */
116 #define MAX310X_MODE2_FIFORST_BIT (1 << 1) /* FIFO reset */
117 #define MAX310X_MODE2_RXTRIGINV_BIT (1 << 2) /* RX FIFO INT invert */
118 #define MAX310X_MODE2_RXEMPTINV_BIT (1 << 3) /* RX FIFO empty INT invert */
119 #define MAX310X_MODE2_SPCHR_BIT (1 << 4) /* Special chr detect enable */
120 #define MAX310X_MODE2_LOOPBACK_BIT (1 << 5) /* Internal loopback enable */
121 #define MAX310X_MODE2_MULTIDROP_BIT (1 << 6) /* 9-bit multidrop enable */
122 #define MAX310X_MODE2_ECHOSUPR_BIT (1 << 7) /* ECHO suppression enable */
124 /* LCR register bits */
125 #define MAX310X_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */
126 #define MAX310X_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1
128 * Word length bits table:
134 #define MAX310X_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit
136 * STOP length bit table:
138 * 1 -> 1-1.5 stop bits if
140 * 2 stop bits otherwise
142 #define MAX310X_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */
143 #define MAX310X_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */
144 #define MAX310X_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */
145 #define MAX310X_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */
146 #define MAX310X_LCR_RTS_BIT (1 << 7) /* RTS pin control */
147 #define MAX310X_LCR_WORD_LEN_5 (0x00)
148 #define MAX310X_LCR_WORD_LEN_6 (0x01)
149 #define MAX310X_LCR_WORD_LEN_7 (0x02)
150 #define MAX310X_LCR_WORD_LEN_8 (0x03)
152 /* IRDA register bits */
153 #define MAX310X_IRDA_IRDAEN_BIT (1 << 0) /* IRDA mode enable */
154 #define MAX310X_IRDA_SIR_BIT (1 << 1) /* SIR mode enable */
155 #define MAX310X_IRDA_SHORTIR_BIT (1 << 2) /* Short SIR mode enable */
156 #define MAX310X_IRDA_MIR_BIT (1 << 3) /* MIR mode enable */
157 #define MAX310X_IRDA_RXINV_BIT (1 << 4) /* RX logic inversion enable */
158 #define MAX310X_IRDA_TXINV_BIT (1 << 5) /* TX logic inversion enable */
160 /* Flow control trigger level register masks */
161 #define MAX310X_FLOWLVL_HALT_MASK (0x000f) /* Flow control halt level */
162 #define MAX310X_FLOWLVL_RES_MASK (0x00f0) /* Flow control resume level */
163 #define MAX310X_FLOWLVL_HALT(words) ((words / 8) & 0x0f)
164 #define MAX310X_FLOWLVL_RES(words) (((words / 8) & 0x0f) << 4)
166 /* FIFO interrupt trigger level register masks */
167 #define MAX310X_FIFOTRIGLVL_TX_MASK (0x0f) /* TX FIFO trigger level */
168 #define MAX310X_FIFOTRIGLVL_RX_MASK (0xf0) /* RX FIFO trigger level */
169 #define MAX310X_FIFOTRIGLVL_TX(words) ((words / 8) & 0x0f)
170 #define MAX310X_FIFOTRIGLVL_RX(words) (((words / 8) & 0x0f) << 4)
172 /* Flow control register bits */
173 #define MAX310X_FLOWCTRL_AUTORTS_BIT (1 << 0) /* Auto RTS flow ctrl enable */
174 #define MAX310X_FLOWCTRL_AUTOCTS_BIT (1 << 1) /* Auto CTS flow ctrl enable */
175 #define MAX310X_FLOWCTRL_GPIADDR_BIT (1 << 2) /* Enables that GPIO inputs
176 * are used in conjunction with
177 * XOFF2 for definition of
178 * special character */
179 #define MAX310X_FLOWCTRL_SWFLOWEN_BIT (1 << 3) /* Auto SW flow ctrl enable */
180 #define MAX310X_FLOWCTRL_SWFLOW0_BIT (1 << 4) /* SWFLOW bit 0 */
181 #define MAX310X_FLOWCTRL_SWFLOW1_BIT (1 << 5) /* SWFLOW bit 1
183 * SWFLOW bits 1 & 0 table:
184 * 00 -> no transmitter flow
186 * 01 -> receiver compares
190 * 10 -> receiver compares
194 * 11 -> receiver compares
195 * XON1, XON2, XOFF1 and
199 #define MAX310X_FLOWCTRL_SWFLOW2_BIT (1 << 6) /* SWFLOW bit 2 */
200 #define MAX310X_FLOWCTRL_SWFLOW3_BIT (1 << 7) /* SWFLOW bit 3
202 * SWFLOW bits 3 & 2 table:
203 * 00 -> no received flow
205 * 01 -> transmitter generates
207 * 10 -> transmitter generates
209 * 11 -> transmitter generates
210 * XON1, XON2, XOFF1 and
214 /* GPIO configuration register bits */
215 #define MAX310X_GPIOCFG_GP0OUT_BIT (1 << 0) /* GPIO 0 output enable */
216 #define MAX310X_GPIOCFG_GP1OUT_BIT (1 << 1) /* GPIO 1 output enable */
217 #define MAX310X_GPIOCFG_GP2OUT_BIT (1 << 2) /* GPIO 2 output enable */
218 #define MAX310X_GPIOCFG_GP3OUT_BIT (1 << 3) /* GPIO 3 output enable */
219 #define MAX310X_GPIOCFG_GP0OD_BIT (1 << 4) /* GPIO 0 open-drain enable */
220 #define MAX310X_GPIOCFG_GP1OD_BIT (1 << 5) /* GPIO 1 open-drain enable */
221 #define MAX310X_GPIOCFG_GP2OD_BIT (1 << 6) /* GPIO 2 open-drain enable */
222 #define MAX310X_GPIOCFG_GP3OD_BIT (1 << 7) /* GPIO 3 open-drain enable */
224 /* GPIO DATA register bits */
225 #define MAX310X_GPIODATA_GP0OUT_BIT (1 << 0) /* GPIO 0 output value */
226 #define MAX310X_GPIODATA_GP1OUT_BIT (1 << 1) /* GPIO 1 output value */
227 #define MAX310X_GPIODATA_GP2OUT_BIT (1 << 2) /* GPIO 2 output value */
228 #define MAX310X_GPIODATA_GP3OUT_BIT (1 << 3) /* GPIO 3 output value */
229 #define MAX310X_GPIODATA_GP0IN_BIT (1 << 4) /* GPIO 0 input value */
230 #define MAX310X_GPIODATA_GP1IN_BIT (1 << 5) /* GPIO 1 input value */
231 #define MAX310X_GPIODATA_GP2IN_BIT (1 << 6) /* GPIO 2 input value */
232 #define MAX310X_GPIODATA_GP3IN_BIT (1 << 7) /* GPIO 3 input value */
234 /* PLL configuration register masks */
235 #define MAX310X_PLLCFG_PREDIV_MASK (0x3f) /* PLL predivision value */
236 #define MAX310X_PLLCFG_PLLFACTOR_MASK (0xc0) /* PLL multiplication factor */
238 /* Baud rate generator configuration register bits */
239 #define MAX310X_BRGCFG_2XMODE_BIT (1 << 4) /* Double baud rate */
240 #define MAX310X_BRGCFG_4XMODE_BIT (1 << 5) /* Quadruple baud rate */
242 /* Clock source register bits */
243 #define MAX310X_CLKSRC_CRYST_BIT (1 << 1) /* Crystal osc enable */
244 #define MAX310X_CLKSRC_PLL_BIT (1 << 2) /* PLL enable */
245 #define MAX310X_CLKSRC_PLLBYP_BIT (1 << 3) /* PLL bypass */
246 #define MAX310X_CLKSRC_EXTCLK_BIT (1 << 4) /* External clock enable */
247 #define MAX310X_CLKSRC_CLK2RTS_BIT (1 << 7) /* Baud clk to RTS pin */
249 /* Misc definitions */
250 #define MAX310X_FIFO_SIZE (128)
252 /* MAX3107 specific */
253 #define MAX3107_REV_ID (0xa0)
254 #define MAX3107_REV_MASK (0xfe)
256 /* IRQ status bits definitions */
257 #define MAX310X_IRQ_TX (MAX310X_IRQ_TXFIFO_BIT | \
258 MAX310X_IRQ_TXEMPTY_BIT)
259 #define MAX310X_IRQ_RX (MAX310X_IRQ_RXFIFO_BIT | \
260 MAX310X_IRQ_RXEMPTY_BIT)
262 /* Supported chip types */
264 MAX310X_TYPE_MAX3107 = 3107,
265 MAX310X_TYPE_MAX3108 = 3108,
268 struct max310x_port {
269 struct uart_driver uart;
270 struct uart_port port;
275 unsigned int nr_gpio;
276 #ifdef CONFIG_GPIOLIB
277 struct gpio_chip gpio;
280 struct regmap *regmap;
281 struct regmap_config regcfg;
283 struct workqueue_struct *wq;
284 struct work_struct tx_work;
286 struct mutex max310x_mutex;
288 struct max310x_pdata *pdata;
291 static bool max3107_8_reg_writeable(struct device *dev, unsigned int reg)
294 case MAX310X_IRQSTS_REG:
295 case MAX310X_LSR_IRQSTS_REG:
296 case MAX310X_SPCHR_IRQSTS_REG:
297 case MAX310X_STS_IRQSTS_REG:
298 case MAX310X_TXFIFOLVL_REG:
299 case MAX310X_RXFIFOLVL_REG:
300 case MAX3107_REVID_REG: /* Only available on MAX3107 */
309 static bool max310x_reg_volatile(struct device *dev, unsigned int reg)
312 case MAX310X_RHR_REG:
313 case MAX310X_IRQSTS_REG:
314 case MAX310X_LSR_IRQSTS_REG:
315 case MAX310X_SPCHR_IRQSTS_REG:
316 case MAX310X_STS_IRQSTS_REG:
317 case MAX310X_TXFIFOLVL_REG:
318 case MAX310X_RXFIFOLVL_REG:
319 case MAX310X_GPIODATA_REG:
328 static bool max310x_reg_precious(struct device *dev, unsigned int reg)
331 case MAX310X_RHR_REG:
332 case MAX310X_IRQSTS_REG:
333 case MAX310X_SPCHR_IRQSTS_REG:
334 case MAX310X_STS_IRQSTS_REG:
343 static void max310x_set_baud(struct max310x_port *s, int baud)
345 unsigned int mode = 0, div = s->uartclk / baud;
349 mode = MAX310X_BRGCFG_2XMODE_BIT;
350 div = (s->uartclk * 2) / baud;
355 mode = MAX310X_BRGCFG_4XMODE_BIT;
356 div = (s->uartclk * 4) / baud;
359 regmap_write(s->regmap, MAX310X_BRGDIVMSB_REG,
360 ((div / 16) >> 8) & 0xff);
361 regmap_write(s->regmap, MAX310X_BRGDIVLSB_REG, (div / 16) & 0xff);
362 regmap_write(s->regmap, MAX310X_BRGCFG_REG, (div % 16) | mode);
365 static void max310x_wait_pll(struct max310x_port *s)
369 /* Wait for PLL only if crystal is used */
370 if (!(s->pdata->driver_flags & MAX310X_EXT_CLK)) {
371 unsigned int sts = 0;
374 regmap_read(s->regmap, MAX310X_STS_IRQSTS_REG, &sts);
375 if (sts & MAX310X_STS_CLKREADY_BIT)
381 static int max310x_update_best_err(unsigned long f, long *besterr)
383 /* Use baudrate 115200 for calculate error */
384 long err = f % (115200 * 16);
386 if ((*besterr < 0) || (*besterr > err)) {
394 static int max310x_set_ref_clk(struct max310x_port *s)
396 unsigned int div, clksrc, pllcfg = 0;
398 unsigned long fdiv, fmul, bestfreq = s->pdata->frequency;
400 /* First, update error without PLL */
401 max310x_update_best_err(s->pdata->frequency, &besterr);
403 /* Try all possible PLL dividers */
404 for (div = 1; (div <= 63) && besterr; div++) {
405 fdiv = DIV_ROUND_CLOSEST(s->pdata->frequency, div);
407 /* Try multiplier 6 */
409 if ((fdiv >= 500000) && (fdiv <= 800000))
410 if (!max310x_update_best_err(fmul, &besterr)) {
411 pllcfg = (0 << 6) | div;
414 /* Try multiplier 48 */
416 if ((fdiv >= 850000) && (fdiv <= 1200000))
417 if (!max310x_update_best_err(fmul, &besterr)) {
418 pllcfg = (1 << 6) | div;
421 /* Try multiplier 96 */
423 if ((fdiv >= 425000) && (fdiv <= 1000000))
424 if (!max310x_update_best_err(fmul, &besterr)) {
425 pllcfg = (2 << 6) | div;
428 /* Try multiplier 144 */
430 if ((fdiv >= 390000) && (fdiv <= 667000))
431 if (!max310x_update_best_err(fmul, &besterr)) {
432 pllcfg = (3 << 6) | div;
437 /* Configure clock source */
438 if (s->pdata->driver_flags & MAX310X_EXT_CLK)
439 clksrc = MAX310X_CLKSRC_EXTCLK_BIT;
441 clksrc = MAX310X_CLKSRC_CRYST_BIT;
445 clksrc |= MAX310X_CLKSRC_PLL_BIT;
446 regmap_write(s->regmap, MAX310X_PLLCFG_REG, pllcfg);
448 clksrc |= MAX310X_CLKSRC_PLLBYP_BIT;
450 regmap_write(s->regmap, MAX310X_CLKSRC_REG, clksrc);
455 dev_dbg(s->port.dev, "Reference clock set to %lu Hz\n", bestfreq);
457 return (int)bestfreq;
460 static void max310x_handle_rx(struct max310x_port *s, unsigned int rxlen)
462 unsigned int sts = 0, ch = 0, flag;
464 if (unlikely(rxlen >= MAX310X_FIFO_SIZE)) {
465 dev_warn(s->port.dev, "Possible RX FIFO overrun %d\n", rxlen);
466 /* Ensure sanity of RX level */
467 rxlen = MAX310X_FIFO_SIZE;
470 dev_dbg(s->port.dev, "RX Len = %u\n", rxlen);
473 regmap_read(s->regmap, MAX310X_RHR_REG, &ch);
474 regmap_read(s->regmap, MAX310X_LSR_IRQSTS_REG, &sts);
476 sts &= MAX310X_LSR_RXPAR_BIT | MAX310X_LSR_FRERR_BIT |
477 MAX310X_LSR_RXOVR_BIT | MAX310X_LSR_RXBRK_BIT;
483 if (sts & MAX310X_LSR_RXBRK_BIT) {
484 s->port.icount.brk++;
485 if (uart_handle_break(&s->port))
487 } else if (sts & MAX310X_LSR_RXPAR_BIT)
488 s->port.icount.parity++;
489 else if (sts & MAX310X_LSR_FRERR_BIT)
490 s->port.icount.frame++;
491 else if (sts & MAX310X_LSR_RXOVR_BIT)
492 s->port.icount.overrun++;
494 sts &= s->port.read_status_mask;
495 if (sts & MAX310X_LSR_RXBRK_BIT)
497 else if (sts & MAX310X_LSR_RXPAR_BIT)
499 else if (sts & MAX310X_LSR_FRERR_BIT)
501 else if (sts & MAX310X_LSR_RXOVR_BIT)
505 if (uart_handle_sysrq_char(s->port, ch))
508 if (sts & s->port.ignore_status_mask)
511 uart_insert_char(&s->port, sts, MAX310X_LSR_RXOVR_BIT,
515 tty_flip_buffer_push(&s->port.state->port);
518 static void max310x_handle_tx(struct max310x_port *s)
520 struct circ_buf *xmit = &s->port.state->xmit;
521 unsigned int txlen = 0, to_send;
523 if (unlikely(s->port.x_char)) {
524 regmap_write(s->regmap, MAX310X_THR_REG, s->port.x_char);
530 if (uart_circ_empty(xmit) || uart_tx_stopped(&s->port))
533 /* Get length of data pending in circular buffer */
534 to_send = uart_circ_chars_pending(xmit);
535 if (likely(to_send)) {
536 /* Limit to size of TX FIFO */
537 regmap_read(s->regmap, MAX310X_TXFIFOLVL_REG, &txlen);
538 txlen = MAX310X_FIFO_SIZE - txlen;
539 to_send = (to_send > txlen) ? txlen : to_send;
541 dev_dbg(s->port.dev, "TX Len = %u\n", to_send);
543 /* Add data to send */
544 s->port.icount.tx += to_send;
546 regmap_write(s->regmap, MAX310X_THR_REG,
547 xmit->buf[xmit->tail]);
548 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
552 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
553 uart_write_wakeup(&s->port);
556 static irqreturn_t max310x_ist(int irq, void *dev_id)
558 struct max310x_port *s = (struct max310x_port *)dev_id;
559 unsigned int ists = 0, lsr = 0, rxlen = 0;
561 mutex_lock(&s->max310x_mutex);
564 /* Read IRQ status & RX FIFO level */
565 regmap_read(s->regmap, MAX310X_IRQSTS_REG, &ists);
566 regmap_read(s->regmap, MAX310X_LSR_IRQSTS_REG, &lsr);
567 regmap_read(s->regmap, MAX310X_RXFIFOLVL_REG, &rxlen);
568 if (!ists && !(lsr & MAX310X_LSR_RXTO_BIT) && !rxlen)
571 dev_dbg(s->port.dev, "IRQ status: 0x%02x\n", ists);
574 max310x_handle_rx(s, rxlen);
575 if (ists & MAX310X_IRQ_TX)
576 max310x_handle_tx(s);
577 if (ists & MAX310X_IRQ_CTS_BIT)
578 uart_handle_cts_change(&s->port,
579 !!(lsr & MAX310X_LSR_CTS_BIT));
582 mutex_unlock(&s->max310x_mutex);
587 static void max310x_wq_proc(struct work_struct *ws)
589 struct max310x_port *s = container_of(ws, struct max310x_port, tx_work);
591 mutex_lock(&s->max310x_mutex);
592 max310x_handle_tx(s);
593 mutex_unlock(&s->max310x_mutex);
596 static void max310x_start_tx(struct uart_port *port)
598 struct max310x_port *s = container_of(port, struct max310x_port, port);
600 queue_work(s->wq, &s->tx_work);
603 static void max310x_stop_tx(struct uart_port *port)
608 static void max310x_stop_rx(struct uart_port *port)
613 static unsigned int max310x_tx_empty(struct uart_port *port)
615 unsigned int val = 0;
616 struct max310x_port *s = container_of(port, struct max310x_port, port);
618 mutex_lock(&s->max310x_mutex);
619 regmap_read(s->regmap, MAX310X_TXFIFOLVL_REG, &val);
620 mutex_unlock(&s->max310x_mutex);
622 return val ? 0 : TIOCSER_TEMT;
625 static void max310x_enable_ms(struct uart_port *port)
627 /* Modem status not supported */
630 static unsigned int max310x_get_mctrl(struct uart_port *port)
632 /* DCD and DSR are not wired and CTS/RTS is handled automatically
633 * so just indicate DSR and CAR asserted
635 return TIOCM_DSR | TIOCM_CAR;
638 static void max310x_set_mctrl(struct uart_port *port, unsigned int mctrl)
640 /* DCD and DSR are not wired and CTS/RTS is hadnled automatically
645 static void max310x_break_ctl(struct uart_port *port, int break_state)
647 struct max310x_port *s = container_of(port, struct max310x_port, port);
649 mutex_lock(&s->max310x_mutex);
650 regmap_update_bits(s->regmap, MAX310X_LCR_REG,
651 MAX310X_LCR_TXBREAK_BIT,
652 break_state ? MAX310X_LCR_TXBREAK_BIT : 0);
653 mutex_unlock(&s->max310x_mutex);
656 static void max310x_set_termios(struct uart_port *port,
657 struct ktermios *termios,
658 struct ktermios *old)
660 struct max310x_port *s = container_of(port, struct max310x_port, port);
661 unsigned int lcr, flow = 0;
664 mutex_lock(&s->max310x_mutex);
666 /* Mask termios capabilities we don't support */
667 termios->c_cflag &= ~CMSPAR;
668 termios->c_iflag &= ~IXANY;
671 switch (termios->c_cflag & CSIZE) {
673 lcr = MAX310X_LCR_WORD_LEN_5;
676 lcr = MAX310X_LCR_WORD_LEN_6;
679 lcr = MAX310X_LCR_WORD_LEN_7;
683 lcr = MAX310X_LCR_WORD_LEN_8;
688 if (termios->c_cflag & PARENB) {
689 lcr |= MAX310X_LCR_PARITY_BIT;
690 if (!(termios->c_cflag & PARODD))
691 lcr |= MAX310X_LCR_EVENPARITY_BIT;
695 if (termios->c_cflag & CSTOPB)
696 lcr |= MAX310X_LCR_STOPLEN_BIT; /* 2 stops */
698 /* Update LCR register */
699 regmap_write(s->regmap, MAX310X_LCR_REG, lcr);
701 /* Set read status mask */
702 port->read_status_mask = MAX310X_LSR_RXOVR_BIT;
703 if (termios->c_iflag & INPCK)
704 port->read_status_mask |= MAX310X_LSR_RXPAR_BIT |
705 MAX310X_LSR_FRERR_BIT;
706 if (termios->c_iflag & (BRKINT | PARMRK))
707 port->read_status_mask |= MAX310X_LSR_RXBRK_BIT;
709 /* Set status ignore mask */
710 port->ignore_status_mask = 0;
711 if (termios->c_iflag & IGNBRK)
712 port->ignore_status_mask |= MAX310X_LSR_RXBRK_BIT;
713 if (!(termios->c_cflag & CREAD))
714 port->ignore_status_mask |= MAX310X_LSR_RXPAR_BIT |
715 MAX310X_LSR_RXOVR_BIT |
716 MAX310X_LSR_FRERR_BIT |
717 MAX310X_LSR_RXBRK_BIT;
719 /* Configure flow control */
720 regmap_write(s->regmap, MAX310X_XON1_REG, termios->c_cc[VSTART]);
721 regmap_write(s->regmap, MAX310X_XOFF1_REG, termios->c_cc[VSTOP]);
722 if (termios->c_cflag & CRTSCTS)
723 flow |= MAX310X_FLOWCTRL_AUTOCTS_BIT |
724 MAX310X_FLOWCTRL_AUTORTS_BIT;
725 if (termios->c_iflag & IXON)
726 flow |= MAX310X_FLOWCTRL_SWFLOW3_BIT |
727 MAX310X_FLOWCTRL_SWFLOWEN_BIT;
728 if (termios->c_iflag & IXOFF)
729 flow |= MAX310X_FLOWCTRL_SWFLOW1_BIT |
730 MAX310X_FLOWCTRL_SWFLOWEN_BIT;
731 regmap_write(s->regmap, MAX310X_FLOWCTRL_REG, flow);
733 /* Get baud rate generator configuration */
734 baud = uart_get_baud_rate(port, termios, old,
735 port->uartclk / 16 / 0xffff,
738 /* Setup baudrate generator */
739 max310x_set_baud(s, baud);
741 /* Update timeout according to new baud rate */
742 uart_update_timeout(port, termios->c_cflag, baud);
744 mutex_unlock(&s->max310x_mutex);
747 static int max310x_startup(struct uart_port *port)
749 unsigned int val, line = port->line;
750 struct max310x_port *s = container_of(port, struct max310x_port, port);
752 if (s->pdata->suspend)
753 s->pdata->suspend(0);
755 mutex_lock(&s->max310x_mutex);
757 /* Configure baud rate, 9600 as default */
758 max310x_set_baud(s, 9600);
760 /* Configure LCR register, 8N1 mode by default */
761 val = MAX310X_LCR_WORD_LEN_8;
762 regmap_write(s->regmap, MAX310X_LCR_REG, val);
764 /* Configure MODE1 register */
765 regmap_update_bits(s->regmap, MAX310X_MODE1_REG,
766 MAX310X_MODE1_TRNSCVCTRL_BIT,
767 (s->pdata->uart_flags[line] & MAX310X_AUTO_DIR_CTRL)
768 ? MAX310X_MODE1_TRNSCVCTRL_BIT : 0);
770 /* Configure MODE2 register */
771 val = MAX310X_MODE2_RXEMPTINV_BIT;
772 if (s->pdata->uart_flags[line] & MAX310X_LOOPBACK)
773 val |= MAX310X_MODE2_LOOPBACK_BIT;
774 if (s->pdata->uart_flags[line] & MAX310X_ECHO_SUPRESS)
775 val |= MAX310X_MODE2_ECHOSUPR_BIT;
778 val |= MAX310X_MODE2_FIFORST_BIT;
779 regmap_write(s->regmap, MAX310X_MODE2_REG, val);
781 /* Configure FIFO trigger level register */
782 /* RX FIFO trigger for 16 words, TX FIFO trigger for 64 words */
783 val = MAX310X_FIFOTRIGLVL_RX(16) | MAX310X_FIFOTRIGLVL_TX(64);
784 regmap_write(s->regmap, MAX310X_FIFOTRIGLVL_REG, val);
786 /* Configure flow control levels */
787 /* Flow control halt level 96, resume level 48 */
788 val = MAX310X_FLOWLVL_RES(48) | MAX310X_FLOWLVL_HALT(96);
789 regmap_write(s->regmap, MAX310X_FLOWLVL_REG, val);
791 /* Clear timeout register */
792 regmap_write(s->regmap, MAX310X_RXTO_REG, 0);
794 /* Configure LSR interrupt enable register */
795 /* Enable RX timeout interrupt */
796 val = MAX310X_LSR_RXTO_BIT;
797 regmap_write(s->regmap, MAX310X_LSR_IRQEN_REG, val);
799 /* Clear FIFO reset */
800 regmap_update_bits(s->regmap, MAX310X_MODE2_REG,
801 MAX310X_MODE2_FIFORST_BIT, 0);
803 /* Clear IRQ status register by reading it */
804 regmap_read(s->regmap, MAX310X_IRQSTS_REG, &val);
806 /* Configure interrupt enable register */
807 /* Enable CTS change interrupt */
808 val = MAX310X_IRQ_CTS_BIT;
809 /* Enable RX, TX interrupts */
810 val |= MAX310X_IRQ_RX | MAX310X_IRQ_TX;
811 regmap_write(s->regmap, MAX310X_IRQEN_REG, val);
813 mutex_unlock(&s->max310x_mutex);
818 static void max310x_shutdown(struct uart_port *port)
820 struct max310x_port *s = container_of(port, struct max310x_port, port);
822 /* Disable all interrupts */
823 mutex_lock(&s->max310x_mutex);
824 regmap_write(s->regmap, MAX310X_IRQEN_REG, 0);
825 mutex_unlock(&s->max310x_mutex);
827 if (s->pdata->suspend)
828 s->pdata->suspend(1);
831 static const char *max310x_type(struct uart_port *port)
833 struct max310x_port *s = container_of(port, struct max310x_port, port);
835 return (port->type == PORT_MAX310X) ? s->name : NULL;
838 static int max310x_request_port(struct uart_port *port)
844 static void max310x_release_port(struct uart_port *port)
849 static void max310x_config_port(struct uart_port *port, int flags)
851 if (flags & UART_CONFIG_TYPE)
852 port->type = PORT_MAX310X;
855 static int max310x_verify_port(struct uart_port *port, struct serial_struct *ser)
857 if ((ser->type == PORT_UNKNOWN) || (ser->type == PORT_MAX310X))
859 if (ser->irq == port->irq)
865 static struct uart_ops max310x_ops = {
866 .tx_empty = max310x_tx_empty,
867 .set_mctrl = max310x_set_mctrl,
868 .get_mctrl = max310x_get_mctrl,
869 .stop_tx = max310x_stop_tx,
870 .start_tx = max310x_start_tx,
871 .stop_rx = max310x_stop_rx,
872 .enable_ms = max310x_enable_ms,
873 .break_ctl = max310x_break_ctl,
874 .startup = max310x_startup,
875 .shutdown = max310x_shutdown,
876 .set_termios = max310x_set_termios,
877 .type = max310x_type,
878 .request_port = max310x_request_port,
879 .release_port = max310x_release_port,
880 .config_port = max310x_config_port,
881 .verify_port = max310x_verify_port,
884 #ifdef CONFIG_PM_SLEEP
886 static int max310x_suspend(struct device *dev)
889 struct max310x_port *s = dev_get_drvdata(dev);
891 dev_dbg(dev, "Suspend\n");
893 ret = uart_suspend_port(&s->uart, &s->port);
895 mutex_lock(&s->max310x_mutex);
897 /* Enable sleep mode */
898 regmap_update_bits(s->regmap, MAX310X_MODE1_REG,
899 MAX310X_MODE1_FORCESLEEP_BIT,
900 MAX310X_MODE1_FORCESLEEP_BIT);
902 mutex_unlock(&s->max310x_mutex);
904 if (s->pdata->suspend)
905 s->pdata->suspend(1);
910 static int max310x_resume(struct device *dev)
912 struct max310x_port *s = dev_get_drvdata(dev);
914 dev_dbg(dev, "Resume\n");
916 if (s->pdata->suspend)
917 s->pdata->suspend(0);
919 mutex_lock(&s->max310x_mutex);
921 /* Disable sleep mode */
922 regmap_update_bits(s->regmap, MAX310X_MODE1_REG,
923 MAX310X_MODE1_FORCESLEEP_BIT,
928 mutex_unlock(&s->max310x_mutex);
930 return uart_resume_port(&s->uart, &s->port);
933 static SIMPLE_DEV_PM_OPS(max310x_pm_ops, max310x_suspend, max310x_resume);
934 #define MAX310X_PM_OPS (&max310x_pm_ops)
937 #define MAX310X_PM_OPS NULL
940 #ifdef CONFIG_GPIOLIB
941 static int max310x_gpio_get(struct gpio_chip *chip, unsigned offset)
943 unsigned int val = 0;
944 struct max310x_port *s = container_of(chip, struct max310x_port, gpio);
946 mutex_lock(&s->max310x_mutex);
947 regmap_read(s->regmap, MAX310X_GPIODATA_REG, &val);
948 mutex_unlock(&s->max310x_mutex);
950 return !!((val >> 4) & (1 << offset));
953 static void max310x_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
955 struct max310x_port *s = container_of(chip, struct max310x_port, gpio);
957 mutex_lock(&s->max310x_mutex);
958 regmap_update_bits(s->regmap, MAX310X_GPIODATA_REG, 1 << offset, value ?
960 mutex_unlock(&s->max310x_mutex);
963 static int max310x_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
965 struct max310x_port *s = container_of(chip, struct max310x_port, gpio);
967 mutex_lock(&s->max310x_mutex);
969 regmap_update_bits(s->regmap, MAX310X_GPIOCFG_REG, 1 << offset, 0);
971 mutex_unlock(&s->max310x_mutex);
976 static int max310x_gpio_direction_output(struct gpio_chip *chip,
977 unsigned offset, int value)
979 struct max310x_port *s = container_of(chip, struct max310x_port, gpio);
981 mutex_lock(&s->max310x_mutex);
983 regmap_update_bits(s->regmap, MAX310X_GPIOCFG_REG, 1 << offset,
985 regmap_update_bits(s->regmap, MAX310X_GPIODATA_REG, 1 << offset, value ?
988 mutex_unlock(&s->max310x_mutex);
994 /* Generic platform data */
995 static struct max310x_pdata generic_plat_data = {
996 .driver_flags = MAX310X_EXT_CLK,
997 .uart_flags[0] = MAX310X_ECHO_SUPRESS,
998 .frequency = 26000000,
1001 static int max310x_probe(struct spi_device *spi)
1003 struct max310x_port *s;
1004 struct device *dev = &spi->dev;
1005 int chiptype = spi_get_device_id(spi)->driver_data;
1006 struct max310x_pdata *pdata = dev->platform_data;
1007 unsigned int val = 0;
1011 if (spi->irq <= 0) {
1012 dev_err(dev, "No IRQ specified\n");
1016 /* Alloc port structure */
1017 s = devm_kzalloc(dev, sizeof(struct max310x_port), GFP_KERNEL);
1019 dev_err(dev, "Error allocating port structure\n");
1022 dev_set_drvdata(dev, s);
1025 dev_warn(dev, "No platform data supplied, using defaults\n");
1026 pdata = &generic_plat_data;
1030 /* Individual chip settings */
1032 case MAX310X_TYPE_MAX3107:
1033 s->name = "MAX3107";
1036 s->regcfg.max_register = 0x1f;
1038 case MAX310X_TYPE_MAX3108:
1039 s->name = "MAX3108";
1042 s->regcfg.max_register = 0x1e;
1045 dev_err(dev, "Unsupported chip type %i\n", chiptype);
1049 /* Check input frequency */
1050 if ((pdata->driver_flags & MAX310X_EXT_CLK) &&
1051 ((pdata->frequency < 500000) || (pdata->frequency > 35000000)))
1053 /* Check frequency for quartz */
1054 if (!(pdata->driver_flags & MAX310X_EXT_CLK) &&
1055 ((pdata->frequency < 1000000) || (pdata->frequency > 4000000)))
1058 mutex_init(&s->max310x_mutex);
1061 spi->mode = SPI_MODE_0;
1062 spi->bits_per_word = 8;
1063 spi->max_speed_hz = 26000000;
1067 s->regcfg.reg_bits = 8;
1068 s->regcfg.val_bits = 8;
1069 s->regcfg.read_flag_mask = 0x00;
1070 s->regcfg.write_flag_mask = 0x80;
1071 s->regcfg.cache_type = REGCACHE_RBTREE;
1072 s->regcfg.writeable_reg = max3107_8_reg_writeable;
1073 s->regcfg.volatile_reg = max310x_reg_volatile;
1074 s->regcfg.precious_reg = max310x_reg_precious;
1075 s->regmap = devm_regmap_init_spi(spi, &s->regcfg);
1076 if (IS_ERR(s->regmap)) {
1077 ret = PTR_ERR(s->regmap);
1078 dev_err(dev, "Failed to initialize register map\n");
1082 /* Reset chip & check SPI function */
1083 ret = regmap_write(s->regmap, MAX310X_MODE2_REG, MAX310X_MODE2_RST_BIT);
1085 dev_err(dev, "SPI transfer failed\n");
1088 /* Clear chip reset */
1089 regmap_write(s->regmap, MAX310X_MODE2_REG, 0);
1092 case MAX310X_TYPE_MAX3107:
1093 /* Check REV ID to ensure we are talking to what we expect */
1094 regmap_read(s->regmap, MAX3107_REVID_REG, &val);
1095 if (((val & MAX3107_REV_MASK) != MAX3107_REV_ID)) {
1096 dev_err(dev, "%s ID 0x%02x does not match\n",
1102 case MAX310X_TYPE_MAX3108:
1103 /* MAX3108 have not REV ID register, we just check default value
1104 * from clocksource register to make sure everything works.
1106 regmap_read(s->regmap, MAX310X_CLKSRC_REG, &val);
1107 if (val != (MAX310X_CLKSRC_EXTCLK_BIT |
1108 MAX310X_CLKSRC_PLLBYP_BIT)) {
1109 dev_err(dev, "%s not present\n", s->name);
1116 /* Board specific configure */
1122 /* Calculate referecne clock */
1123 s->uartclk = max310x_set_ref_clk(s);
1125 /* Disable all interrupts */
1126 regmap_write(s->regmap, MAX310X_IRQEN_REG, 0);
1128 /* Setup MODE1 register */
1129 val = MAX310X_MODE1_IRQSEL_BIT; /* Enable IRQ pin */
1130 if (pdata->driver_flags & MAX310X_AUTOSLEEP)
1131 val = MAX310X_MODE1_AUTOSLEEP_BIT;
1132 regmap_write(s->regmap, MAX310X_MODE1_REG, val);
1134 /* Setup interrupt */
1135 ret = devm_request_threaded_irq(dev, spi->irq, NULL, max310x_ist,
1136 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1139 dev_err(dev, "Unable to reguest IRQ %i\n", spi->irq);
1143 /* Register UART driver */
1144 s->uart.owner = THIS_MODULE;
1145 s->uart.driver_name = dev_name(dev);
1146 s->uart.dev_name = "ttyMAX";
1147 s->uart.major = MAX310X_MAJOR;
1148 s->uart.minor = MAX310X_MINOR;
1149 ret = uart_register_driver(&s->uart);
1151 dev_err(dev, "Registering UART driver failed\n");
1155 /* Initialize workqueue for start TX */
1156 s->wq = create_freezable_workqueue(dev_name(dev));
1157 INIT_WORK(&s->tx_work, max310x_wq_proc);
1159 /* Initialize UART port data */
1162 s->port.irq = spi->irq;
1163 s->port.type = PORT_MAX310X;
1164 s->port.fifosize = MAX310X_FIFO_SIZE;
1165 s->port.flags = UPF_SKIP_TEST | UPF_FIXED_TYPE;
1166 s->port.iotype = UPIO_PORT;
1167 s->port.membase = (void __iomem *)0xffffffff; /* Bogus value */
1168 s->port.uartclk = s->uartclk;
1169 s->port.ops = &max310x_ops;
1170 uart_add_one_port(&s->uart, &s->port);
1172 #ifdef CONFIG_GPIOLIB
1173 /* Setup GPIO cotroller */
1174 if (pdata->gpio_base) {
1175 s->gpio.owner = THIS_MODULE;
1177 s->gpio.label = dev_name(dev);
1178 s->gpio.direction_input = max310x_gpio_direction_input;
1179 s->gpio.get = max310x_gpio_get;
1180 s->gpio.direction_output= max310x_gpio_direction_output;
1181 s->gpio.set = max310x_gpio_set;
1182 s->gpio.base = pdata->gpio_base;
1183 s->gpio.ngpio = s->nr_gpio;
1184 s->gpio.can_sleep = 1;
1185 if (gpiochip_add(&s->gpio)) {
1186 /* Indicate that we should not call gpiochip_remove */
1190 dev_info(dev, "GPIO support not enabled\n");
1193 /* Go to suspend mode */
1200 dev_err(dev, "Frequency parameter incorrect\n");
1204 dev_set_drvdata(dev, NULL);
1209 static int max310x_remove(struct spi_device *spi)
1211 struct device *dev = &spi->dev;
1212 struct max310x_port *s = dev_get_drvdata(dev);
1215 dev_dbg(dev, "Removing port\n");
1217 devm_free_irq(dev, s->port.irq, s);
1219 destroy_workqueue(s->wq);
1221 uart_remove_one_port(&s->uart, &s->port);
1223 uart_unregister_driver(&s->uart);
1225 #ifdef CONFIG_GPIOLIB
1226 if (s->pdata->gpio_base) {
1227 ret = gpiochip_remove(&s->gpio);
1229 dev_err(dev, "Failed to remove gpio chip: %d\n", ret);
1233 dev_set_drvdata(dev, NULL);
1235 if (s->pdata->suspend)
1236 s->pdata->suspend(1);
1243 static const struct spi_device_id max310x_id_table[] = {
1244 { "max3107", MAX310X_TYPE_MAX3107 },
1245 { "max3108", MAX310X_TYPE_MAX3108 },
1248 MODULE_DEVICE_TABLE(spi, max310x_id_table);
1250 static struct spi_driver max310x_driver = {
1253 .owner = THIS_MODULE,
1254 .pm = MAX310X_PM_OPS,
1256 .probe = max310x_probe,
1257 .remove = max310x_remove,
1258 .id_table = max310x_id_table,
1260 module_spi_driver(max310x_driver);
1262 MODULE_LICENSE("GPL v2");
1263 MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
1264 MODULE_DESCRIPTION("MAX310X serial driver");