1 /****************************************************************************/
4 * mcf.c -- Freescale ColdFire UART driver
6 * (C) Copyright 2003-2007, Greg Ungerer <gerg@snapgear.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 /****************************************************************************/
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/interrupt.h>
19 #include <linux/module.h>
20 #include <linux/console.h>
21 #include <linux/tty.h>
22 #include <linux/tty_flip.h>
23 #include <linux/serial.h>
24 #include <linux/serial_core.h>
26 #include <linux/uaccess.h>
27 #include <linux/platform_device.h>
28 #include <asm/coldfire.h>
29 #include <asm/mcfsim.h>
30 #include <asm/mcfuart.h>
31 #include <asm/nettel.h>
33 /****************************************************************************/
36 * Some boards implement the DTR/DCD lines using GPIO lines, most
37 * don't. Dummy out the access macros for those that don't. Those
38 * that do should define these macros somewhere in there board
39 * specific inlude files.
41 #if !defined(mcf_getppdcd)
42 #define mcf_getppdcd(p) (1)
44 #if !defined(mcf_getppdtr)
45 #define mcf_getppdtr(p) (1)
47 #if !defined(mcf_setppdtr)
48 #define mcf_setppdtr(p, v) do { } while (0)
51 /****************************************************************************/
54 * Local per-uart structure.
57 struct uart_port port;
58 unsigned int sigs; /* Local copy of line sigs */
59 unsigned char imr; /* Local IMR mirror */
62 /****************************************************************************/
64 static unsigned int mcf_tx_empty(struct uart_port *port)
66 return (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXEMPTY) ?
70 /****************************************************************************/
72 static unsigned int mcf_get_mctrl(struct uart_port *port)
74 struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
77 sigs = (readb(port->membase + MCFUART_UIPR) & MCFUART_UIPR_CTS) ?
79 sigs |= (pp->sigs & TIOCM_RTS);
80 sigs |= (mcf_getppdcd(port->line) ? TIOCM_CD : 0);
81 sigs |= (mcf_getppdtr(port->line) ? TIOCM_DTR : 0);
86 /****************************************************************************/
88 static void mcf_set_mctrl(struct uart_port *port, unsigned int sigs)
90 struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
93 mcf_setppdtr(port->line, (sigs & TIOCM_DTR));
95 writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP1);
97 writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP0);
100 /****************************************************************************/
102 static void mcf_start_tx(struct uart_port *port)
104 struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
106 if (port->rs485.flags & SER_RS485_ENABLED) {
107 /* Enable Transmitter */
108 writeb(MCFUART_UCR_TXENABLE, port->membase + MCFUART_UCR);
109 /* Manually assert RTS */
110 writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP1);
112 pp->imr |= MCFUART_UIR_TXREADY;
113 writeb(pp->imr, port->membase + MCFUART_UIMR);
116 /****************************************************************************/
118 static void mcf_stop_tx(struct uart_port *port)
120 struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
122 pp->imr &= ~MCFUART_UIR_TXREADY;
123 writeb(pp->imr, port->membase + MCFUART_UIMR);
126 /****************************************************************************/
128 static void mcf_stop_rx(struct uart_port *port)
130 struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
132 pp->imr &= ~MCFUART_UIR_RXREADY;
133 writeb(pp->imr, port->membase + MCFUART_UIMR);
136 /****************************************************************************/
138 static void mcf_break_ctl(struct uart_port *port, int break_state)
142 spin_lock_irqsave(&port->lock, flags);
143 if (break_state == -1)
144 writeb(MCFUART_UCR_CMDBREAKSTART, port->membase + MCFUART_UCR);
146 writeb(MCFUART_UCR_CMDBREAKSTOP, port->membase + MCFUART_UCR);
147 spin_unlock_irqrestore(&port->lock, flags);
150 /****************************************************************************/
152 static int mcf_startup(struct uart_port *port)
154 struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
157 spin_lock_irqsave(&port->lock, flags);
159 /* Reset UART, get it into known state... */
160 writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR);
161 writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR);
163 /* Enable the UART transmitter and receiver */
164 writeb(MCFUART_UCR_RXENABLE | MCFUART_UCR_TXENABLE,
165 port->membase + MCFUART_UCR);
167 /* Enable RX interrupts now */
168 pp->imr = MCFUART_UIR_RXREADY;
169 writeb(pp->imr, port->membase + MCFUART_UIMR);
171 spin_unlock_irqrestore(&port->lock, flags);
176 /****************************************************************************/
178 static void mcf_shutdown(struct uart_port *port)
180 struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
183 spin_lock_irqsave(&port->lock, flags);
185 /* Disable all interrupts now */
187 writeb(pp->imr, port->membase + MCFUART_UIMR);
189 /* Disable UART transmitter and receiver */
190 writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR);
191 writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR);
193 spin_unlock_irqrestore(&port->lock, flags);
196 /****************************************************************************/
198 static void mcf_set_termios(struct uart_port *port, struct ktermios *termios,
199 struct ktermios *old)
201 struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
203 unsigned int baud, baudclk;
204 #if defined(CONFIG_M5272)
207 unsigned char mr1, mr2;
209 baud = uart_get_baud_rate(port, termios, old, 0, 230400);
210 #if defined(CONFIG_M5272)
211 baudclk = (MCF_BUSCLK / baud) / 32;
212 baudfr = (((MCF_BUSCLK / baud) + 1) / 2) % 16;
214 baudclk = ((MCF_BUSCLK / baud) + 16) / 32;
217 mr1 = MCFUART_MR1_RXIRQRDY | MCFUART_MR1_RXERRCHAR;
220 switch (termios->c_cflag & CSIZE) {
221 case CS5: mr1 |= MCFUART_MR1_CS5; break;
222 case CS6: mr1 |= MCFUART_MR1_CS6; break;
223 case CS7: mr1 |= MCFUART_MR1_CS7; break;
225 default: mr1 |= MCFUART_MR1_CS8; break;
228 if (termios->c_cflag & PARENB) {
229 if (termios->c_cflag & CMSPAR) {
230 if (termios->c_cflag & PARODD)
231 mr1 |= MCFUART_MR1_PARITYMARK;
233 mr1 |= MCFUART_MR1_PARITYSPACE;
235 if (termios->c_cflag & PARODD)
236 mr1 |= MCFUART_MR1_PARITYODD;
238 mr1 |= MCFUART_MR1_PARITYEVEN;
241 mr1 |= MCFUART_MR1_PARITYNONE;
245 * FIXME: port->read_status_mask and port->ignore_status_mask
246 * need to be initialized based on termios settings for
247 * INPCK, IGNBRK, IGNPAR, PARMRK, BRKINT
250 if (termios->c_cflag & CSTOPB)
251 mr2 |= MCFUART_MR2_STOP2;
253 mr2 |= MCFUART_MR2_STOP1;
255 if (termios->c_cflag & CRTSCTS) {
256 mr1 |= MCFUART_MR1_RXRTS;
257 mr2 |= MCFUART_MR2_TXCTS;
260 spin_lock_irqsave(&port->lock, flags);
261 if (port->rs485.flags & SER_RS485_ENABLED) {
262 dev_dbg(port->dev, "Setting UART to RS485\n");
263 mr2 |= MCFUART_MR2_TXRTS;
266 uart_update_timeout(port, termios->c_cflag, baud);
267 writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR);
268 writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR);
269 writeb(MCFUART_UCR_CMDRESETMRPTR, port->membase + MCFUART_UCR);
270 writeb(mr1, port->membase + MCFUART_UMR);
271 writeb(mr2, port->membase + MCFUART_UMR);
272 writeb((baudclk & 0xff00) >> 8, port->membase + MCFUART_UBG1);
273 writeb((baudclk & 0xff), port->membase + MCFUART_UBG2);
274 #if defined(CONFIG_M5272)
275 writeb((baudfr & 0x0f), port->membase + MCFUART_UFPD);
277 writeb(MCFUART_UCSR_RXCLKTIMER | MCFUART_UCSR_TXCLKTIMER,
278 port->membase + MCFUART_UCSR);
279 writeb(MCFUART_UCR_RXENABLE | MCFUART_UCR_TXENABLE,
280 port->membase + MCFUART_UCR);
281 spin_unlock_irqrestore(&port->lock, flags);
284 /****************************************************************************/
286 static void mcf_rx_chars(struct mcf_uart *pp)
288 struct uart_port *port = &pp->port;
289 unsigned char status, ch, flag;
291 while ((status = readb(port->membase + MCFUART_USR)) & MCFUART_USR_RXREADY) {
292 ch = readb(port->membase + MCFUART_URB);
296 if (status & MCFUART_USR_RXERR) {
297 writeb(MCFUART_UCR_CMDRESETERR,
298 port->membase + MCFUART_UCR);
300 if (status & MCFUART_USR_RXBREAK) {
302 if (uart_handle_break(port))
304 } else if (status & MCFUART_USR_RXPARITY) {
305 port->icount.parity++;
306 } else if (status & MCFUART_USR_RXOVERRUN) {
307 port->icount.overrun++;
308 } else if (status & MCFUART_USR_RXFRAMING) {
309 port->icount.frame++;
312 status &= port->read_status_mask;
314 if (status & MCFUART_USR_RXBREAK)
316 else if (status & MCFUART_USR_RXPARITY)
318 else if (status & MCFUART_USR_RXFRAMING)
322 if (uart_handle_sysrq_char(port, ch))
324 uart_insert_char(port, status, MCFUART_USR_RXOVERRUN, ch, flag);
327 spin_unlock(&port->lock);
328 tty_flip_buffer_push(&port->state->port);
329 spin_lock(&port->lock);
332 /****************************************************************************/
334 static void mcf_tx_chars(struct mcf_uart *pp)
336 struct uart_port *port = &pp->port;
337 struct circ_buf *xmit = &port->state->xmit;
340 /* Send special char - probably flow control */
341 writeb(port->x_char, port->membase + MCFUART_UTB);
347 while (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXREADY) {
348 if (xmit->head == xmit->tail)
350 writeb(xmit->buf[xmit->tail], port->membase + MCFUART_UTB);
351 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE -1);
355 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
356 uart_write_wakeup(port);
358 if (xmit->head == xmit->tail) {
359 pp->imr &= ~MCFUART_UIR_TXREADY;
360 writeb(pp->imr, port->membase + MCFUART_UIMR);
361 /* Disable TX to negate RTS automatically */
362 if (port->rs485.flags & SER_RS485_ENABLED)
363 writeb(MCFUART_UCR_TXDISABLE,
364 port->membase + MCFUART_UCR);
368 /****************************************************************************/
370 static irqreturn_t mcf_interrupt(int irq, void *data)
372 struct uart_port *port = data;
373 struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
375 irqreturn_t ret = IRQ_NONE;
377 isr = readb(port->membase + MCFUART_UISR) & pp->imr;
379 spin_lock(&port->lock);
380 if (isr & MCFUART_UIR_RXREADY) {
384 if (isr & MCFUART_UIR_TXREADY) {
388 spin_unlock(&port->lock);
393 /****************************************************************************/
395 static void mcf_config_port(struct uart_port *port, int flags)
397 port->type = PORT_MCF;
398 port->fifosize = MCFUART_TXFIFOSIZE;
400 /* Clear mask, so no surprise interrupts. */
401 writeb(0, port->membase + MCFUART_UIMR);
403 if (request_irq(port->irq, mcf_interrupt, 0, "UART", port))
404 printk(KERN_ERR "MCF: unable to attach ColdFire UART %d "
405 "interrupt vector=%d\n", port->line, port->irq);
408 /****************************************************************************/
410 static const char *mcf_type(struct uart_port *port)
412 return (port->type == PORT_MCF) ? "ColdFire UART" : NULL;
415 /****************************************************************************/
417 static int mcf_request_port(struct uart_port *port)
419 /* UARTs always present */
423 /****************************************************************************/
425 static void mcf_release_port(struct uart_port *port)
427 /* Nothing to release... */
430 /****************************************************************************/
432 static int mcf_verify_port(struct uart_port *port, struct serial_struct *ser)
434 if ((ser->type != PORT_UNKNOWN) && (ser->type != PORT_MCF))
439 /****************************************************************************/
441 /* Enable or disable the RS485 support */
442 static int mcf_config_rs485(struct uart_port *port, struct serial_rs485 *rs485)
444 struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
445 unsigned char mr1, mr2;
447 /* Get mode registers */
448 mr1 = readb(port->membase + MCFUART_UMR);
449 mr2 = readb(port->membase + MCFUART_UMR);
450 if (rs485->flags & SER_RS485_ENABLED) {
451 dev_dbg(port->dev, "Setting UART to RS485\n");
452 /* Automatically negate RTS after TX completes */
453 mr2 |= MCFUART_MR2_TXRTS;
455 dev_dbg(port->dev, "Setting UART to RS232\n");
456 mr2 &= ~MCFUART_MR2_TXRTS;
458 writeb(mr1, port->membase + MCFUART_UMR);
459 writeb(mr2, port->membase + MCFUART_UMR);
460 port->rs485 = *rs485;
465 /****************************************************************************/
468 * Define the basic serial functions we support.
470 static const struct uart_ops mcf_uart_ops = {
471 .tx_empty = mcf_tx_empty,
472 .get_mctrl = mcf_get_mctrl,
473 .set_mctrl = mcf_set_mctrl,
474 .start_tx = mcf_start_tx,
475 .stop_tx = mcf_stop_tx,
476 .stop_rx = mcf_stop_rx,
477 .break_ctl = mcf_break_ctl,
478 .startup = mcf_startup,
479 .shutdown = mcf_shutdown,
480 .set_termios = mcf_set_termios,
482 .request_port = mcf_request_port,
483 .release_port = mcf_release_port,
484 .config_port = mcf_config_port,
485 .verify_port = mcf_verify_port,
488 static struct mcf_uart mcf_ports[4];
490 #define MCF_MAXPORTS ARRAY_SIZE(mcf_ports)
492 /****************************************************************************/
493 #if defined(CONFIG_SERIAL_MCF_CONSOLE)
494 /****************************************************************************/
496 int __init early_mcf_setup(struct mcf_platform_uart *platp)
498 struct uart_port *port;
501 for (i = 0; ((i < MCF_MAXPORTS) && (platp[i].mapbase)); i++) {
502 port = &mcf_ports[i].port;
505 port->type = PORT_MCF;
506 port->mapbase = platp[i].mapbase;
507 port->membase = (platp[i].membase) ? platp[i].membase :
508 (unsigned char __iomem *) port->mapbase;
509 port->iotype = SERIAL_IO_MEM;
510 port->irq = platp[i].irq;
511 port->uartclk = MCF_BUSCLK;
512 port->flags = UPF_BOOT_AUTOCONF;
513 port->rs485_config = mcf_config_rs485;
514 port->ops = &mcf_uart_ops;
520 /****************************************************************************/
522 static void mcf_console_putc(struct console *co, const char c)
524 struct uart_port *port = &(mcf_ports + co->index)->port;
527 for (i = 0; (i < 0x10000); i++) {
528 if (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXREADY)
531 writeb(c, port->membase + MCFUART_UTB);
532 for (i = 0; (i < 0x10000); i++) {
533 if (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXREADY)
538 /****************************************************************************/
540 static void mcf_console_write(struct console *co, const char *s, unsigned int count)
542 for (; (count); count--, s++) {
543 mcf_console_putc(co, *s);
545 mcf_console_putc(co, '\r');
549 /****************************************************************************/
551 static int __init mcf_console_setup(struct console *co, char *options)
553 struct uart_port *port;
554 int baud = CONFIG_SERIAL_MCF_BAUDRATE;
559 if ((co->index < 0) || (co->index >= MCF_MAXPORTS))
561 port = &mcf_ports[co->index].port;
562 if (port->membase == 0)
566 uart_parse_options(options, &baud, &parity, &bits, &flow);
568 return uart_set_options(port, co, baud, parity, bits, flow);
571 /****************************************************************************/
573 static struct uart_driver mcf_driver;
575 static struct console mcf_console = {
577 .write = mcf_console_write,
578 .device = uart_console_device,
579 .setup = mcf_console_setup,
580 .flags = CON_PRINTBUFFER,
585 static int __init mcf_console_init(void)
587 register_console(&mcf_console);
591 console_initcall(mcf_console_init);
593 #define MCF_CONSOLE &mcf_console
595 /****************************************************************************/
597 /****************************************************************************/
599 #define MCF_CONSOLE NULL
601 /****************************************************************************/
602 #endif /* CONFIG_MCF_CONSOLE */
603 /****************************************************************************/
606 * Define the mcf UART driver structure.
608 static struct uart_driver mcf_driver = {
609 .owner = THIS_MODULE,
610 .driver_name = "mcf",
618 /****************************************************************************/
620 static int mcf_probe(struct platform_device *pdev)
622 struct mcf_platform_uart *platp = dev_get_platdata(&pdev->dev);
623 struct uart_port *port;
626 for (i = 0; ((i < MCF_MAXPORTS) && (platp[i].mapbase)); i++) {
627 port = &mcf_ports[i].port;
630 port->type = PORT_MCF;
631 port->mapbase = platp[i].mapbase;
632 port->membase = (platp[i].membase) ? platp[i].membase :
633 (unsigned char __iomem *) platp[i].mapbase;
634 port->iotype = SERIAL_IO_MEM;
635 port->irq = platp[i].irq;
636 port->uartclk = MCF_BUSCLK;
637 port->ops = &mcf_uart_ops;
638 port->flags = UPF_BOOT_AUTOCONF;
639 port->rs485_config = mcf_config_rs485;
641 uart_add_one_port(&mcf_driver, port);
647 /****************************************************************************/
649 static int mcf_remove(struct platform_device *pdev)
651 struct uart_port *port;
654 for (i = 0; (i < MCF_MAXPORTS); i++) {
655 port = &mcf_ports[i].port;
657 uart_remove_one_port(&mcf_driver, port);
663 /****************************************************************************/
665 static struct platform_driver mcf_platform_driver = {
667 .remove = mcf_remove,
673 /****************************************************************************/
675 static int __init mcf_init(void)
679 printk("ColdFire internal UART serial driver\n");
681 rc = uart_register_driver(&mcf_driver);
684 rc = platform_driver_register(&mcf_platform_driver);
686 uart_unregister_driver(&mcf_driver);
692 /****************************************************************************/
694 static void __exit mcf_exit(void)
696 platform_driver_unregister(&mcf_platform_driver);
697 uart_unregister_driver(&mcf_driver);
700 /****************************************************************************/
702 module_init(mcf_init);
703 module_exit(mcf_exit);
705 MODULE_AUTHOR("Greg Ungerer <gerg@snapgear.com>");
706 MODULE_DESCRIPTION("Freescale ColdFire UART driver");
707 MODULE_LICENSE("GPL");
708 MODULE_ALIAS("platform:mcfuart");
710 /****************************************************************************/