drivers/tty/serial/mfd.c

   1 /*
   2  * mfd.c: driver for High Speed UART device of Intel Medfield platform
   3  *
   4  * Refer pxa.c, 8250.c and some other drivers in drivers/serial/
   5  *
   6  * (C) Copyright 2010 Intel Corporation
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * as published by the Free Software Foundation; version 2
  11  * of the License.
  12  */
  13
  14 /* Notes:
  15  * 1. DMA channel allocation: 0/1 channel are assigned to port 0,
  16  *    2/3 chan to port 1, 4/5 chan to port 3. Even number chans
  17  *    are used for RX, odd chans for TX
  18  *
  19  * 2. The RI/DSR/DCD/DTR are not pinned out, DCD & DSR are always
  20  *    asserted, only when the HW is reset the DDCD and DDSR will
  21  *    be triggered
  22  */
  23
  24 #include <linux/module.h>
  25 #include <linux/init.h>
  26 #include <linux/console.h>
  27 #include <linux/sysrq.h>
  28 #include <linux/slab.h>
  29 #include <linux/serial_reg.h>
  30 #include <linux/circ_buf.h>
  31 #include <linux/delay.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/tty.h>
  34 #include <linux/tty_flip.h>
  35 #include <linux/serial_core.h>
  36 #include <linux/serial_mfd.h>
  37 #include <linux/dma-mapping.h>
  38 #include <linux/pci.h>
  39 #include <linux/nmi.h>
  40 #include <linux/io.h>
  41 #include <linux/debugfs.h>
  42 #include <linux/pm_runtime.h>
  43
  44 #define HSU_DMA_BUF_SIZE        2048
  45
  46 #define chan_readl(chan, offset)        readl(chan->reg + offset)
  47 #define chan_writel(chan, offset, val)  writel(val, chan->reg + offset)
  48
  49 #define mfd_readl(obj, offset)          readl(obj->reg + offset)
  50 #define mfd_writel(obj, offset, val)    writel(val, obj->reg + offset)
  51
  52 static int hsu_dma_enable;
  53 module_param(hsu_dma_enable, int, 0);
  54 MODULE_PARM_DESC(hsu_dma_enable,
  55                  "It is a bitmap to set working mode, if bit[x] is 1, then port[x] will work in DMA mode, otherwise in PIO mode.");
  56
  57 struct hsu_dma_buffer {
  58         u8              *buf;
  59         dma_addr_t      dma_addr;
  60         u32             dma_size;
  61         u32             ofs;
  62 };
  63
  64 struct hsu_dma_chan {
  65         u32     id;
  66         enum dma_data_direction dirt;
  67         struct uart_hsu_port    *uport;
  68         void __iomem            *reg;
  69 };
  70
  71 struct uart_hsu_port {
  72         struct uart_port        port;
  73         unsigned char           ier;
  74         unsigned char           lcr;
  75         unsigned char           mcr;
  76         unsigned int            lsr_break_flag;
  77         char                    name[12];
  78         int                     index;
  79         struct device           *dev;
  80
  81         struct hsu_dma_chan     *txc;
  82         struct hsu_dma_chan     *rxc;
  83         struct hsu_dma_buffer   txbuf;
  84         struct hsu_dma_buffer   rxbuf;
  85         int                     use_dma;        /* flag for DMA/PIO */
  86         int                     running;
  87         int                     dma_tx_on;
  88 };
  89
  90 /* Top level data structure of HSU */
  91 struct hsu_port {
  92         void __iomem    *reg;
  93         unsigned long   paddr;
  94         unsigned long   iolen;
  95         u32             irq;
  96
  97         struct uart_hsu_port    port[3];
  98         struct hsu_dma_chan     chans[10];
  99
 100         struct dentry *debugfs;
 101 };
 102
 103 static inline unsigned int serial_in(struct uart_hsu_port *up, int offset)
 104 {
 105         unsigned int val;
 106
 107         if (offset > UART_MSR) {
 108                 offset <<= 2;
 109                 val = readl(up->port.membase + offset);
 110         } else
 111                 val = (unsigned int)readb(up->port.membase + offset);
 112
 113         return val;
 114 }
 115
 116 static inline void serial_out(struct uart_hsu_port *up, int offset, int value)
 117 {
 118         if (offset > UART_MSR) {
 119                 offset <<= 2;
 120                 writel(value, up->port.membase + offset);
 121         } else {
 122                 unsigned char val = value & 0xff;
 123                 writeb(val, up->port.membase + offset);
 124         }
 125 }
 126
 127 #ifdef CONFIG_DEBUG_FS
 128
 129 #define HSU_REGS_BUFSIZE        1024
 130
 131
 132 static ssize_t port_show_regs(struct file *file, char __user *user_buf,
 133                                 size_t count, loff_t *ppos)
 134 {
 135         struct uart_hsu_port *up = file->private_data;
 136         char *buf;
 137         u32 len = 0;
 138         ssize_t ret;
 139
 140         buf = kzalloc(HSU_REGS_BUFSIZE, GFP_KERNEL);
 141         if (!buf)
 142                 return 0;
 143
 144         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 145                         "MFD HSU port[%d] regs:\n", up->index);
 146
 147         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 148                         "=================================\n");
 149         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 150                         "IER: \t\t0x%08x\n", serial_in(up, UART_IER));
 151         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 152                         "IIR: \t\t0x%08x\n", serial_in(up, UART_IIR));
 153         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 154                         "LCR: \t\t0x%08x\n", serial_in(up, UART_LCR));
 155         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 156                         "MCR: \t\t0x%08x\n", serial_in(up, UART_MCR));
 157         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 158                         "LSR: \t\t0x%08x\n", serial_in(up, UART_LSR));
 159         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 160                         "MSR: \t\t0x%08x\n", serial_in(up, UART_MSR));
 161         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 162                         "FOR: \t\t0x%08x\n", serial_in(up, UART_FOR));
 163         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 164                         "PS: \t\t0x%08x\n", serial_in(up, UART_PS));
 165         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 166                         "MUL: \t\t0x%08x\n", serial_in(up, UART_MUL));
 167         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 168                         "DIV: \t\t0x%08x\n", serial_in(up, UART_DIV));
 169
 170         if (len > HSU_REGS_BUFSIZE)
 171                 len = HSU_REGS_BUFSIZE;
 172
 173         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);
 174         kfree(buf);
 175         return ret;
 176 }
 177
 178 static ssize_t dma_show_regs(struct file *file, char __user *user_buf,
 179                                 size_t count, loff_t *ppos)
 180 {
 181         struct hsu_dma_chan *chan = file->private_data;
 182         char *buf;
 183         u32 len = 0;
 184         ssize_t ret;
 185
 186         buf = kzalloc(HSU_REGS_BUFSIZE, GFP_KERNEL);
 187         if (!buf)
 188                 return 0;
 189
 190         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 191                         "MFD HSU DMA channel [%d] regs:\n", chan->id);
 192
 193         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 194                         "=================================\n");
 195         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 196                         "CR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_CR));
 197         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 198                         "DCR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_DCR));
 199         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 200                         "BSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_BSR));
 201         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 202                         "MOTSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_MOTSR));
 203         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 204                         "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D0SAR));
 205         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 206                         "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D0TSR));
 207         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 208                         "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D1SAR));
 209         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 210                         "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D1TSR));
 211         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 212                         "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D2SAR));
 213         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 214                         "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D2TSR));
 215         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 216                         "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D3SAR));
 217         len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
 218                         "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D3TSR));
 219
 220         if (len > HSU_REGS_BUFSIZE)
 221                 len = HSU_REGS_BUFSIZE;
 222
 223         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);
 224         kfree(buf);
 225         return ret;
 226 }
 227
 228 static const struct file_operations port_regs_ops = {
 229         .owner          = THIS_MODULE,
 230         .open           = simple_open,
 231         .read           = port_show_regs,
 232         .llseek         = default_llseek,
 233 };
 234
 235 static const struct file_operations dma_regs_ops = {
 236         .owner          = THIS_MODULE,
 237         .open           = simple_open,
 238         .read           = dma_show_regs,
 239         .llseek         = default_llseek,
 240 };
 241
 242 static int hsu_debugfs_init(struct hsu_port *hsu)
 243 {
 244         int i;
 245         char name[32];
 246
 247         hsu->debugfs = debugfs_create_dir("hsu", NULL);
 248         if (!hsu->debugfs)
 249                 return -ENOMEM;
 250
 251         for (i = 0; i < 3; i++) {
 252                 snprintf(name, sizeof(name), "port_%d_regs", i);
 253                 debugfs_create_file(name, S_IFREG | S_IRUGO,
 254                         hsu->debugfs, (void *)(&hsu->port[i]), &port_regs_ops);
 255         }
 256
 257         for (i = 0; i < 6; i++) {
 258                 snprintf(name, sizeof(name), "dma_chan_%d_regs", i);
 259                 debugfs_create_file(name, S_IFREG | S_IRUGO,
 260                         hsu->debugfs, (void *)&hsu->chans[i], &dma_regs_ops);
 261         }
 262
 263         return 0;
 264 }
 265
 266 static void hsu_debugfs_remove(struct hsu_port *hsu)
 267 {
 268         if (hsu->debugfs)
 269                 debugfs_remove_recursive(hsu->debugfs);
 270 }
 271
 272 #else
 273 static inline int hsu_debugfs_init(struct hsu_port *hsu)
 274 {
 275         return 0;
 276 }
 277
 278 static inline void hsu_debugfs_remove(struct hsu_port *hsu)
 279 {
 280 }
 281 #endif /* CONFIG_DEBUG_FS */
 282
 283 static void serial_hsu_enable_ms(struct uart_port *port)
 284 {
 285         struct uart_hsu_port *up =
 286                 container_of(port, struct uart_hsu_port, port);
 287
 288         up->ier |= UART_IER_MSI;
 289         serial_out(up, UART_IER, up->ier);
 290 }
 291
 292 void hsu_dma_tx(struct uart_hsu_port *up)
 293 {
 294         struct circ_buf *xmit = &up->port.state->xmit;
 295         struct hsu_dma_buffer *dbuf = &up->txbuf;
 296         int count;
 297
 298         /* test_and_set_bit may be better, but anyway it's in lock protected mode */
 299         if (up->dma_tx_on)
 300                 return;
 301
 302         /* Update the circ buf info */
 303         xmit->tail += dbuf->ofs;
 304         xmit->tail &= UART_XMIT_SIZE - 1;
 305
 306         up->port.icount.tx += dbuf->ofs;
 307         dbuf->ofs = 0;
 308
 309         /* Disable the channel */
 310         chan_writel(up->txc, HSU_CH_CR, 0x0);
 311
 312         if (!uart_circ_empty(xmit) && !uart_tx_stopped(&up->port)) {
 313                 dma_sync_single_for_device(up->port.dev,
 314                                            dbuf->dma_addr,
 315                                            dbuf->dma_size,
 316                                            DMA_TO_DEVICE);
 317
 318                 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 319                 dbuf->ofs = count;
 320
 321                 /* Reprogram the channel */
 322                 chan_writel(up->txc, HSU_CH_D0SAR, dbuf->dma_addr + xmit->tail);
 323                 chan_writel(up->txc, HSU_CH_D0TSR, count);
 324
 325                 /* Reenable the channel */
 326                 chan_writel(up->txc, HSU_CH_DCR, 0x1
 327                                                  | (0x1 << 8)
 328                                                  | (0x1 << 16)
 329                                                  | (0x1 << 24));
 330                 up->dma_tx_on = 1;
 331                 chan_writel(up->txc, HSU_CH_CR, 0x1);
 332         }
 333
 334         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 335                 uart_write_wakeup(&up->port);
 336 }
 337
 338 /* The buffer is already cache coherent */
 339 void hsu_dma_start_rx_chan(struct hsu_dma_chan *rxc, struct hsu_dma_buffer *dbuf)
 340 {
 341         dbuf->ofs = 0;
 342
 343         chan_writel(rxc, HSU_CH_BSR, 32);
 344         chan_writel(rxc, HSU_CH_MOTSR, 4);
 345
 346         chan_writel(rxc, HSU_CH_D0SAR, dbuf->dma_addr);
 347         chan_writel(rxc, HSU_CH_D0TSR, dbuf->dma_size);
 348         chan_writel(rxc, HSU_CH_DCR, 0x1 | (0x1 << 8)
 349                                          | (0x1 << 16)
 350                                          | (0x1 << 24)  /* timeout bit, see HSU Errata 1 */
 351                                          );
 352         chan_writel(rxc, HSU_CH_CR, 0x3);
 353 }
 354
 355 /* Protected by spin_lock_irqsave(port->lock) */
 356 static void serial_hsu_start_tx(struct uart_port *port)
 357 {
 358         struct uart_hsu_port *up =
 359                 container_of(port, struct uart_hsu_port, port);
 360
 361         if (up->use_dma) {
 362                 hsu_dma_tx(up);
 363         } else if (!(up->ier & UART_IER_THRI)) {
 364                 up->ier |= UART_IER_THRI;
 365                 serial_out(up, UART_IER, up->ier);
 366         }
 367 }
 368
 369 static void serial_hsu_stop_tx(struct uart_port *port)
 370 {
 371         struct uart_hsu_port *up =
 372                 container_of(port, struct uart_hsu_port, port);
 373         struct hsu_dma_chan *txc = up->txc;
 374
 375         if (up->use_dma)
 376                 chan_writel(txc, HSU_CH_CR, 0x0);
 377         else if (up->ier & UART_IER_THRI) {
 378                 up->ier &= ~UART_IER_THRI;
 379                 serial_out(up, UART_IER, up->ier);
 380         }
 381 }
 382
 383 /* This is always called in spinlock protected mode, so
 384  * modify timeout timer is safe here */
 385 void hsu_dma_rx(struct uart_hsu_port *up, u32 int_sts)
 386 {
 387         struct hsu_dma_buffer *dbuf = &up->rxbuf;
 388         struct hsu_dma_chan *chan = up->rxc;
 389         struct uart_port *port = &up->port;
 390         struct tty_struct *tty = port->state->port.tty;
 391         int count;
 392
 393         if (!tty)
 394                 return;
 395
 396         /*
 397          * First need to know how many is already transferred,
 398          * then check if its a timeout DMA irq, and return
 399          * the trail bytes out, push them up and reenable the
 400          * channel
 401          */
 402
 403         /* Timeout IRQ, need wait some time, see Errata 2 */
 404         if (int_sts & 0xf00)
 405                 udelay(2);
 406
 407         /* Stop the channel */
 408         chan_writel(chan, HSU_CH_CR, 0x0);
 409
 410         count = chan_readl(chan, HSU_CH_D0SAR) - dbuf->dma_addr;
 411         if (!count) {
 412                 /* Restart the channel before we leave */
 413                 chan_writel(chan, HSU_CH_CR, 0x3);
 414                 return;
 415         }
 416
 417         dma_sync_single_for_cpu(port->dev, dbuf->dma_addr,
 418                         dbuf->dma_size, DMA_FROM_DEVICE);
 419
 420         /*
 421          * Head will only wrap around when we recycle
 422          * the DMA buffer, and when that happens, we
 423          * explicitly set tail to 0. So head will
 424          * always be greater than tail.
 425          */
 426         tty_insert_flip_string(tty, dbuf->buf, count);
 427         port->icount.rx += count;
 428
 429         dma_sync_single_for_device(up->port.dev, dbuf->dma_addr,
 430                         dbuf->dma_size, DMA_FROM_DEVICE);
 431
 432         /* Reprogram the channel */
 433         chan_writel(chan, HSU_CH_D0SAR, dbuf->dma_addr);
 434         chan_writel(chan, HSU_CH_D0TSR, dbuf->dma_size);
 435         chan_writel(chan, HSU_CH_DCR, 0x1
 436                                          | (0x1 << 8)
 437                                          | (0x1 << 16)
 438                                          | (0x1 << 24)  /* timeout bit, see HSU Errata 1 */
 439                                          );
 440         tty_flip_buffer_push(tty);
 441
 442         chan_writel(chan, HSU_CH_CR, 0x3);
 443
 444 }
 445
 446 static void serial_hsu_stop_rx(struct uart_port *port)
 447 {
 448         struct uart_hsu_port *up =
 449                 container_of(port, struct uart_hsu_port, port);
 450         struct hsu_dma_chan *chan = up->rxc;
 451
 452         if (up->use_dma)
 453                 chan_writel(chan, HSU_CH_CR, 0x2);
 454         else {
 455                 up->ier &= ~UART_IER_RLSI;
 456                 up->port.read_status_mask &= ~UART_LSR_DR;
 457                 serial_out(up, UART_IER, up->ier);
 458         }
 459 }
 460
 461 static inline void receive_chars(struct uart_hsu_port *up, int *status)
 462 {
 463         struct tty_struct *tty = up->port.state->port.tty;
 464         unsigned int ch, flag;
 465         unsigned int max_count = 256;
 466
 467         if (!tty)
 468                 return;
 469
 470         do {
 471                 ch = serial_in(up, UART_RX);
 472                 flag = TTY_NORMAL;
 473                 up->port.icount.rx++;
 474
 475                 if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE |
 476                                        UART_LSR_FE | UART_LSR_OE))) {
 477
 478                         dev_warn(up->dev, "We really rush into ERR/BI case"
 479                                 "status = 0x%02x", *status);
 480                         /* For statistics only */
 481                         if (*status & UART_LSR_BI) {
 482                                 *status &= ~(UART_LSR_FE | UART_LSR_PE);
 483                                 up->port.icount.brk++;
 484                                 /*
 485                                  * We do the SysRQ and SAK checking
 486                                  * here because otherwise the break
 487                                  * may get masked by ignore_status_mask
 488                                  * or read_status_mask.
 489                                  */
 490                                 if (uart_handle_break(&up->port))
 491                                         goto ignore_char;
 492                         } else if (*status & UART_LSR_PE)
 493                                 up->port.icount.parity++;
 494                         else if (*status & UART_LSR_FE)
 495                                 up->port.icount.frame++;
 496                         if (*status & UART_LSR_OE)
 497                                 up->port.icount.overrun++;
 498
 499                         /* Mask off conditions which should be ignored. */
 500                         *status &= up->port.read_status_mask;
 501
 502 #ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
 503                         if (up->port.cons &&
 504                                 up->port.cons->index == up->port.line) {
 505                                 /* Recover the break flag from console xmit */
 506                                 *status |= up->lsr_break_flag;
 507                                 up->lsr_break_flag = 0;
 508                         }
 509 #endif
 510                         if (*status & UART_LSR_BI) {
 511                                 flag = TTY_BREAK;
 512                         } else if (*status & UART_LSR_PE)
 513                                 flag = TTY_PARITY;
 514                         else if (*status & UART_LSR_FE)
 515                                 flag = TTY_FRAME;
 516                 }
 517
 518                 if (uart_handle_sysrq_char(&up->port, ch))
 519                         goto ignore_char;
 520
 521                 uart_insert_char(&up->port, *status, UART_LSR_OE, ch, flag);
 522         ignore_char:
 523                 *status = serial_in(up, UART_LSR);
 524         } while ((*status & UART_LSR_DR) && max_count--);
 525         tty_flip_buffer_push(tty);
 526 }
 527
 528 static void transmit_chars(struct uart_hsu_port *up)
 529 {
 530         struct circ_buf *xmit = &up->port.state->xmit;
 531         int count;
 532
 533         if (up->port.x_char) {
 534                 serial_out(up, UART_TX, up->port.x_char);
 535                 up->port.icount.tx++;
 536                 up->port.x_char = 0;
 537                 return;
 538         }
 539         if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
 540                 serial_hsu_stop_tx(&up->port);
 541                 return;
 542         }
 543
 544         /* The IRQ is for TX FIFO half-empty */
 545         count = up->port.fifosize / 2;
 546
 547         do {
 548                 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
 549                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 550
 551                 up->port.icount.tx++;
 552                 if (uart_circ_empty(xmit))
 553                         break;
 554         } while (--count > 0);
 555
 556         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 557                 uart_write_wakeup(&up->port);
 558
 559         if (uart_circ_empty(xmit))
 560                 serial_hsu_stop_tx(&up->port);
 561 }
 562
 563 static inline void check_modem_status(struct uart_hsu_port *up)
 564 {
 565         int status;
 566
 567         status = serial_in(up, UART_MSR);
 568
 569         if ((status & UART_MSR_ANY_DELTA) == 0)
 570                 return;
 571
 572         if (status & UART_MSR_TERI)
 573                 up->port.icount.rng++;
 574         if (status & UART_MSR_DDSR)
 575                 up->port.icount.dsr++;
 576         /* We may only get DDCD when HW init and reset */
 577         if (status & UART_MSR_DDCD)
 578                 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
 579         /* Will start/stop_tx accordingly */
 580         if (status & UART_MSR_DCTS)
 581                 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
 582
 583         wake_up_interruptible(&up->port.state->port.delta_msr_wait);
 584 }
 585
 586 /*
 587  * This handles the interrupt from one port.
 588  */
 589 static irqreturn_t port_irq(int irq, void *dev_id)
 590 {
 591         struct uart_hsu_port *up = dev_id;
 592         unsigned int iir, lsr;
 593         unsigned long flags;
 594
 595         if (unlikely(!up->running))
 596                 return IRQ_NONE;
 597
 598         spin_lock_irqsave(&up->port.lock, flags);
 599         if (up->use_dma) {
 600                 lsr = serial_in(up, UART_LSR);
 601                 if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE |
 602                                        UART_LSR_FE | UART_LSR_OE)))
 603                         dev_warn(up->dev,
 604                                 "Got lsr irq while using DMA, lsr = 0x%2x\n",
 605                                 lsr);
 606                 check_modem_status(up);
 607                 spin_unlock_irqrestore(&up->port.lock, flags);
 608                 return IRQ_HANDLED;
 609         }
 610
 611         iir = serial_in(up, UART_IIR);
 612         if (iir & UART_IIR_NO_INT) {
 613                 spin_unlock_irqrestore(&up->port.lock, flags);
 614                 return IRQ_NONE;
 615         }
 616
 617         lsr = serial_in(up, UART_LSR);
 618         if (lsr & UART_LSR_DR)
 619                 receive_chars(up, &lsr);
 620         check_modem_status(up);
 621
 622         /* lsr will be renewed during the receive_chars */
 623         if (lsr & UART_LSR_THRE)
 624                 transmit_chars(up);
 625
 626         spin_unlock_irqrestore(&up->port.lock, flags);
 627         return IRQ_HANDLED;
 628 }
 629
 630 static inline void dma_chan_irq(struct hsu_dma_chan *chan)
 631 {
 632         struct uart_hsu_port *up = chan->uport;
 633         unsigned long flags;
 634         u32 int_sts;
 635
 636         spin_lock_irqsave(&up->port.lock, flags);
 637
 638         if (!up->use_dma || !up->running)
 639                 goto exit;
 640
 641         /*
 642          * No matter what situation, need read clear the IRQ status
 643          * There is a bug, see Errata 5, HSD 2900918
 644          */
 645         int_sts = chan_readl(chan, HSU_CH_SR);
 646
 647         /* Rx channel */
 648         if (chan->dirt == DMA_FROM_DEVICE)
 649                 hsu_dma_rx(up, int_sts);
 650
 651         /* Tx channel */
 652         if (chan->dirt == DMA_TO_DEVICE) {
 653                 chan_writel(chan, HSU_CH_CR, 0x0);
 654                 up->dma_tx_on = 0;
 655                 hsu_dma_tx(up);
 656         }
 657
 658 exit:
 659         spin_unlock_irqrestore(&up->port.lock, flags);
 660         return;
 661 }
 662
 663 static irqreturn_t dma_irq(int irq, void *dev_id)
 664 {
 665         struct hsu_port *hsu = dev_id;
 666         u32 int_sts, i;
 667
 668         int_sts = mfd_readl(hsu, HSU_GBL_DMAISR);
 669
 670         /* Currently we only have 6 channels may be used */
 671         for (i = 0; i < 6; i++) {
 672                 if (int_sts & 0x1)
 673                         dma_chan_irq(&hsu->chans[i]);
 674                 int_sts >>= 1;
 675         }
 676
 677         return IRQ_HANDLED;
 678 }
 679
 680 static unsigned int serial_hsu_tx_empty(struct uart_port *port)
 681 {
 682         struct uart_hsu_port *up =
 683                 container_of(port, struct uart_hsu_port, port);
 684         unsigned long flags;
 685         unsigned int ret;
 686
 687         spin_lock_irqsave(&up->port.lock, flags);
 688         ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
 689         spin_unlock_irqrestore(&up->port.lock, flags);
 690
 691         return ret;
 692 }
 693
 694 static unsigned int serial_hsu_get_mctrl(struct uart_port *port)
 695 {
 696         struct uart_hsu_port *up =
 697                 container_of(port, struct uart_hsu_port, port);
 698         unsigned char status;
 699         unsigned int ret;
 700
 701         status = serial_in(up, UART_MSR);
 702
 703         ret = 0;
 704         if (status & UART_MSR_DCD)
 705                 ret |= TIOCM_CAR;
 706         if (status & UART_MSR_RI)
 707                 ret |= TIOCM_RNG;
 708         if (status & UART_MSR_DSR)
 709                 ret |= TIOCM_DSR;
 710         if (status & UART_MSR_CTS)
 711                 ret |= TIOCM_CTS;
 712         return ret;
 713 }
 714
 715 static void serial_hsu_set_mctrl(struct uart_port *port, unsigned int mctrl)
 716 {
 717         struct uart_hsu_port *up =
 718                 container_of(port, struct uart_hsu_port, port);
 719         unsigned char mcr = 0;
 720
 721         if (mctrl & TIOCM_RTS)
 722                 mcr |= UART_MCR_RTS;
 723         if (mctrl & TIOCM_DTR)
 724                 mcr |= UART_MCR_DTR;
 725         if (mctrl & TIOCM_OUT1)
 726                 mcr |= UART_MCR_OUT1;
 727         if (mctrl & TIOCM_OUT2)
 728                 mcr |= UART_MCR_OUT2;
 729         if (mctrl & TIOCM_LOOP)
 730                 mcr |= UART_MCR_LOOP;
 731
 732         mcr |= up->mcr;
 733
 734         serial_out(up, UART_MCR, mcr);
 735 }
 736
 737 static void serial_hsu_break_ctl(struct uart_port *port, int break_state)
 738 {
 739         struct uart_hsu_port *up =
 740                 container_of(port, struct uart_hsu_port, port);
 741         unsigned long flags;
 742
 743         spin_lock_irqsave(&up->port.lock, flags);
 744         if (break_state == -1)
 745                 up->lcr |= UART_LCR_SBC;
 746         else
 747                 up->lcr &= ~UART_LCR_SBC;
 748         serial_out(up, UART_LCR, up->lcr);
 749         spin_unlock_irqrestore(&up->port.lock, flags);
 750 }
 751
 752 /*
 753  * What special to do:
 754  * 1. chose the 64B fifo mode
 755  * 2. start dma or pio depends on configuration
 756  * 3. we only allocate dma memory when needed
 757  */
 758 static int serial_hsu_startup(struct uart_port *port)
 759 {
 760         struct uart_hsu_port *up =
 761                 container_of(port, struct uart_hsu_port, port);
 762         unsigned long flags;
 763
 764         pm_runtime_get_sync(up->dev);
 765
 766         /*
 767          * Clear the FIFO buffers and disable them.
 768          * (they will be reenabled in set_termios())
 769          */
 770         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
 771         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
 772                         UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
 773         serial_out(up, UART_FCR, 0);
 774
 775         /* Clear the interrupt registers. */
 776         (void) serial_in(up, UART_LSR);
 777         (void) serial_in(up, UART_RX);
 778         (void) serial_in(up, UART_IIR);
 779         (void) serial_in(up, UART_MSR);
 780
 781         /* Now, initialize the UART, default is 8n1 */
 782         serial_out(up, UART_LCR, UART_LCR_WLEN8);
 783
 784         spin_lock_irqsave(&up->port.lock, flags);
 785
 786         up->port.mctrl |= TIOCM_OUT2;
 787         serial_hsu_set_mctrl(&up->port, up->port.mctrl);
 788
 789         /*
 790          * Finally, enable interrupts.  Note: Modem status interrupts
 791          * are set via set_termios(), which will be occurring imminently
 792          * anyway, so we don't enable them here.
 793          */
 794         if (!up->use_dma)
 795                 up->ier = UART_IER_RLSI | UART_IER_RDI | UART_IER_RTOIE;
 796         else
 797                 up->ier = 0;
 798         serial_out(up, UART_IER, up->ier);
 799
 800         spin_unlock_irqrestore(&up->port.lock, flags);
 801
 802         /* DMA init */
 803         if (up->use_dma) {
 804                 struct hsu_dma_buffer *dbuf;
 805                 struct circ_buf *xmit = &port->state->xmit;
 806
 807                 up->dma_tx_on = 0;
 808
 809                 /* First allocate the RX buffer */
 810                 dbuf = &up->rxbuf;
 811                 dbuf->buf = kzalloc(HSU_DMA_BUF_SIZE, GFP_KERNEL);
 812                 if (!dbuf->buf) {
 813                         up->use_dma = 0;
 814                         goto exit;
 815                 }
 816                 dbuf->dma_addr = dma_map_single(port->dev,
 817                                                 dbuf->buf,
 818                                                 HSU_DMA_BUF_SIZE,
 819                                                 DMA_FROM_DEVICE);
 820                 dbuf->dma_size = HSU_DMA_BUF_SIZE;
 821
 822                 /* Start the RX channel right now */
 823                 hsu_dma_start_rx_chan(up->rxc, dbuf);
 824
 825                 /* Next init the TX DMA */
 826                 dbuf = &up->txbuf;
 827                 dbuf->buf = xmit->buf;
 828                 dbuf->dma_addr = dma_map_single(port->dev,
 829                                                dbuf->buf,
 830                                                UART_XMIT_SIZE,
 831                                                DMA_TO_DEVICE);
 832                 dbuf->dma_size = UART_XMIT_SIZE;
 833
 834                 /* This should not be changed all around */
 835                 chan_writel(up->txc, HSU_CH_BSR, 32);
 836                 chan_writel(up->txc, HSU_CH_MOTSR, 4);
 837                 dbuf->ofs = 0;
 838         }
 839
 840 exit:
 841          /* And clear the interrupt registers again for luck. */
 842         (void) serial_in(up, UART_LSR);
 843         (void) serial_in(up, UART_RX);
 844         (void) serial_in(up, UART_IIR);
 845         (void) serial_in(up, UART_MSR);
 846
 847         up->running = 1;
 848         return 0;
 849 }
 850
 851 static void serial_hsu_shutdown(struct uart_port *port)
 852 {
 853         struct uart_hsu_port *up =
 854                 container_of(port, struct uart_hsu_port, port);
 855         unsigned long flags;
 856
 857         /* Disable interrupts from this port */
 858         up->ier = 0;
 859         serial_out(up, UART_IER, 0);
 860         up->running = 0;
 861
 862         spin_lock_irqsave(&up->port.lock, flags);
 863         up->port.mctrl &= ~TIOCM_OUT2;
 864         serial_hsu_set_mctrl(&up->port, up->port.mctrl);
 865         spin_unlock_irqrestore(&up->port.lock, flags);
 866
 867         /* Disable break condition and FIFOs */
 868         serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
 869         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
 870                                   UART_FCR_CLEAR_RCVR |
 871                                   UART_FCR_CLEAR_XMIT);
 872         serial_out(up, UART_FCR, 0);
 873
 874         pm_runtime_put(up->dev);
 875 }
 876
 877 static void
 878 serial_hsu_set_termios(struct uart_port *port, struct ktermios *termios,
 879                        struct ktermios *old)
 880 {
 881         struct uart_hsu_port *up =
 882                         container_of(port, struct uart_hsu_port, port);
 883         unsigned char cval, fcr = 0;
 884         unsigned long flags;
 885         unsigned int baud, quot;
 886         u32 ps, mul;
 887
 888         switch (termios->c_cflag & CSIZE) {
 889         case CS5:
 890                 cval = UART_LCR_WLEN5;
 891                 break;
 892         case CS6:
 893                 cval = UART_LCR_WLEN6;
 894                 break;
 895         case CS7:
 896                 cval = UART_LCR_WLEN7;
 897                 break;
 898         default:
 899         case CS8:
 900                 cval = UART_LCR_WLEN8;
 901                 break;
 902         }
 903
 904         /* CMSPAR isn't supported by this driver */
 905         termios->c_cflag &= ~CMSPAR;
 906
 907         if (termios->c_cflag & CSTOPB)
 908                 cval |= UART_LCR_STOP;
 909         if (termios->c_cflag & PARENB)
 910                 cval |= UART_LCR_PARITY;
 911         if (!(termios->c_cflag & PARODD))
 912                 cval |= UART_LCR_EPAR;
 913
 914         /*
 915          * The base clk is 50Mhz, and the baud rate come from:
 916          *      baud = 50M * MUL / (DIV * PS * DLAB)
 917          *
 918          * For those basic low baud rate we can get the direct
 919          * scalar from 2746800, like 115200 = 2746800/24. For those
 920          * higher baud rate, we handle them case by case, mainly by
 921          * adjusting the MUL/PS registers, and DIV register is kept
 922          * as default value 0x3d09 to make things simple
 923          */
 924         baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
 925
 926         quot = 1;
 927         ps = 0x10;
 928         mul = 0x3600;
 929         switch (baud) {
 930         case 3500000:
 931                 mul = 0x3345;
 932                 ps = 0xC;
 933                 break;
 934         case 1843200:
 935                 mul = 0x2400;
 936                 break;
 937         case 3000000:
 938         case 2500000:
 939         case 2000000:
 940         case 1500000:
 941         case 1000000:
 942         case 500000:
 943                 /* mul/ps/quot = 0x9C4/0x10/0x1 will make a 500000 bps */
 944                 mul = baud / 500000 * 0x9C4;
 945                 break;
 946         default:
 947                 /* Use uart_get_divisor to get quot for other baud rates */
 948                 quot = 0;
 949         }
 950
 951         if (!quot)
 952                 quot = uart_get_divisor(port, baud);
 953
 954         if ((up->port.uartclk / quot) < (2400 * 16))
 955                 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_1B;
 956         else if ((up->port.uartclk / quot) < (230400 * 16))
 957                 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_16B;
 958         else
 959                 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_32B;
 960
 961         fcr |= UART_FCR_HSU_64B_FIFO;
 962
 963         /*
 964          * Ok, we're now changing the port state.  Do it with
 965          * interrupts disabled.
 966          */
 967         spin_lock_irqsave(&up->port.lock, flags);
 968
 969         /* Update the per-port timeout */
 970         uart_update_timeout(port, termios->c_cflag, baud);
 971
 972         up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
 973         if (termios->c_iflag & INPCK)
 974                 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
 975         if (termios->c_iflag & (BRKINT | PARMRK))
 976                 up->port.read_status_mask |= UART_LSR_BI;
 977
 978         /* Characters to ignore */
 979         up->port.ignore_status_mask = 0;
 980         if (termios->c_iflag & IGNPAR)
 981                 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
 982         if (termios->c_iflag & IGNBRK) {
 983                 up->port.ignore_status_mask |= UART_LSR_BI;
 984                 /*
 985                  * If we're ignoring parity and break indicators,
 986                  * ignore overruns too (for real raw support).
 987                  */
 988                 if (termios->c_iflag & IGNPAR)
 989                         up->port.ignore_status_mask |= UART_LSR_OE;
 990         }
 991
 992         /* Ignore all characters if CREAD is not set */
 993         if ((termios->c_cflag & CREAD) == 0)
 994                 up->port.ignore_status_mask |= UART_LSR_DR;
 995
 996         /*
 997          * CTS flow control flag and modem status interrupts, disable
 998          * MSI by default
 999          */
1000         up->ier &= ~UART_IER_MSI;
1001         if (UART_ENABLE_MS(&up->port, termios->c_cflag))
1002                 up->ier |= UART_IER_MSI;
1003
1004         serial_out(up, UART_IER, up->ier);
1005
1006         if (termios->c_cflag & CRTSCTS)
1007                 up->mcr |= UART_MCR_AFE | UART_MCR_RTS;
1008         else
1009                 up->mcr &= ~UART_MCR_AFE;
1010
1011         serial_out(up, UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */
1012         serial_out(up, UART_DLL, quot & 0xff);          /* LS of divisor */
1013         serial_out(up, UART_DLM, quot >> 8);            /* MS of divisor */
1014         serial_out(up, UART_LCR, cval);                 /* reset DLAB */
1015         serial_out(up, UART_MUL, mul);                  /* set MUL */
1016         serial_out(up, UART_PS, ps);                    /* set PS */
1017         up->lcr = cval;                                 /* Save LCR */
1018         serial_hsu_set_mctrl(&up->port, up->port.mctrl);
1019         serial_out(up, UART_FCR, fcr);
1020         spin_unlock_irqrestore(&up->port.lock, flags);
1021 }
1022
1023 static void
1024 serial_hsu_pm(struct uart_port *port, unsigned int state,
1025               unsigned int oldstate)
1026 {
1027 }
1028
1029 static void serial_hsu_release_port(struct uart_port *port)
1030 {
1031 }
1032
1033 static int serial_hsu_request_port(struct uart_port *port)
1034 {
1035         return 0;
1036 }
1037
1038 static void serial_hsu_config_port(struct uart_port *port, int flags)
1039 {
1040         struct uart_hsu_port *up =
1041                 container_of(port, struct uart_hsu_port, port);
1042         up->port.type = PORT_MFD;
1043 }
1044
1045 static int
1046 serial_hsu_verify_port(struct uart_port *port, struct serial_struct *ser)
1047 {
1048         /* We don't want the core code to modify any port params */
1049         return -EINVAL;
1050 }
1051
1052 static const char *
1053 serial_hsu_type(struct uart_port *port)
1054 {
1055         struct uart_hsu_port *up =
1056                 container_of(port, struct uart_hsu_port, port);
1057         return up->name;
1058 }
1059
1060 /* Mainly for uart console use */
1061 static struct uart_hsu_port *serial_hsu_ports[3];
1062 static struct uart_driver serial_hsu_reg;
1063
1064 #ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
1065
1066 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1067
1068 /* Wait for transmitter & holding register to empty */
1069 static inline void wait_for_xmitr(struct uart_hsu_port *up)
1070 {
1071         unsigned int status, tmout = 1000;
1072
1073         /* Wait up to 1ms for the character to be sent. */
1074         do {
1075                 status = serial_in(up, UART_LSR);
1076
1077                 if (status & UART_LSR_BI)
1078                         up->lsr_break_flag = UART_LSR_BI;
1079
1080                 if (--tmout == 0)
1081                         break;
1082                 udelay(1);
1083         } while (!(status & BOTH_EMPTY));
1084
1085         /* Wait up to 1s for flow control if necessary */
1086         if (up->port.flags & UPF_CONS_FLOW) {
1087                 tmout = 1000000;
1088                 while (--tmout &&
1089                        ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
1090                         udelay(1);
1091         }
1092 }
1093
1094 static void serial_hsu_console_putchar(struct uart_port *port, int ch)
1095 {
1096         struct uart_hsu_port *up =
1097                 container_of(port, struct uart_hsu_port, port);
1098
1099         wait_for_xmitr(up);
1100         serial_out(up, UART_TX, ch);
1101 }
1102
1103 /*
1104  * Print a string to the serial port trying not to disturb
1105  * any possible real use of the port...
1106  *
1107  *      The console_lock must be held when we get here.
1108  */
1109 static void
1110 serial_hsu_console_write(struct console *co, const char *s, unsigned int count)
1111 {
1112         struct uart_hsu_port *up = serial_hsu_ports[co->index];
1113         unsigned long flags;
1114         unsigned int ier;
1115         int locked = 1;
1116
1117         touch_nmi_watchdog();
1118
1119         local_irq_save(flags);
1120         if (up->port.sysrq)
1121                 locked = 0;
1122         else if (oops_in_progress) {
1123                 locked = spin_trylock(&up->port.lock);
1124         } else
1125                 spin_lock(&up->port.lock);
1126
1127         /* First save the IER then disable the interrupts */
1128         ier = serial_in(up, UART_IER);
1129         serial_out(up, UART_IER, 0);
1130
1131         uart_console_write(&up->port, s, count, serial_hsu_console_putchar);
1132
1133         /*
1134          * Finally, wait for transmitter to become empty
1135          * and restore the IER
1136          */
1137         wait_for_xmitr(up);
1138         serial_out(up, UART_IER, ier);
1139
1140         if (locked)
1141                 spin_unlock(&up->port.lock);
1142         local_irq_restore(flags);
1143 }
1144
1145 static struct console serial_hsu_console;
1146
1147 static int __init
1148 serial_hsu_console_setup(struct console *co, char *options)
1149 {
1150         struct uart_hsu_port *up;
1151         int baud = 115200;
1152         int bits = 8;
1153         int parity = 'n';
1154         int flow = 'n';
1155
1156         if (co->index == -1 || co->index >= serial_hsu_reg.nr)
1157                 co->index = 0;
1158         up = serial_hsu_ports[co->index];
1159         if (!up)
1160                 return -ENODEV;
1161
1162         if (options)
1163                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1164
1165         return uart_set_options(&up->port, co, baud, parity, bits, flow);
1166 }
1167
1168 static struct console serial_hsu_console = {
1169         .name           = "ttyMFD",
1170         .write          = serial_hsu_console_write,
1171         .device         = uart_console_device,
1172         .setup          = serial_hsu_console_setup,
1173         .flags          = CON_PRINTBUFFER,
1174         .index          = -1,
1175         .data           = &serial_hsu_reg,
1176 };
1177
1178 #define SERIAL_HSU_CONSOLE      (&serial_hsu_console)
1179 #else
1180 #define SERIAL_HSU_CONSOLE      NULL
1181 #endif
1182
1183 struct uart_ops serial_hsu_pops = {
1184         .tx_empty       = serial_hsu_tx_empty,
1185         .set_mctrl      = serial_hsu_set_mctrl,
1186         .get_mctrl      = serial_hsu_get_mctrl,
1187         .stop_tx        = serial_hsu_stop_tx,
1188         .start_tx       = serial_hsu_start_tx,
1189         .stop_rx        = serial_hsu_stop_rx,
1190         .enable_ms      = serial_hsu_enable_ms,
1191         .break_ctl      = serial_hsu_break_ctl,
1192         .startup        = serial_hsu_startup,
1193         .shutdown       = serial_hsu_shutdown,
1194         .set_termios    = serial_hsu_set_termios,
1195         .pm             = serial_hsu_pm,
1196         .type           = serial_hsu_type,
1197         .release_port   = serial_hsu_release_port,
1198         .request_port   = serial_hsu_request_port,
1199         .config_port    = serial_hsu_config_port,
1200         .verify_port    = serial_hsu_verify_port,
1201 };
1202
1203 static struct uart_driver serial_hsu_reg = {
1204         .owner          = THIS_MODULE,
1205         .driver_name    = "MFD serial",
1206         .dev_name       = "ttyMFD",
1207         .major          = TTY_MAJOR,
1208         .minor          = 128,
1209         .nr             = 3,
1210         .cons           = SERIAL_HSU_CONSOLE,
1211 };
1212
1213 #ifdef CONFIG_PM
1214 static int serial_hsu_suspend(struct pci_dev *pdev, pm_message_t state)
1215 {
1216         void *priv = pci_get_drvdata(pdev);
1217         struct uart_hsu_port *up;
1218
1219         /* Make sure this is not the internal dma controller */
1220         if (priv && (pdev->device != 0x081E)) {
1221                 up = priv;
1222                 uart_suspend_port(&serial_hsu_reg, &up->port);
1223         }
1224
1225         pci_save_state(pdev);
1226         pci_set_power_state(pdev, pci_choose_state(pdev, state));
1227         return 0;
1228 }
1229
1230 static int serial_hsu_resume(struct pci_dev *pdev)
1231 {
1232         void *priv = pci_get_drvdata(pdev);
1233         struct uart_hsu_port *up;
1234         int ret;
1235
1236         pci_set_power_state(pdev, PCI_D0);
1237         pci_restore_state(pdev);
1238
1239         ret = pci_enable_device(pdev);
1240         if (ret)
1241                 dev_warn(&pdev->dev,
1242                         "HSU: can't re-enable device, try to continue\n");
1243
1244         if (priv && (pdev->device != 0x081E)) {
1245                 up = priv;
1246                 uart_resume_port(&serial_hsu_reg, &up->port);
1247         }
1248         return 0;
1249 }
1250 #else
1251 #define serial_hsu_suspend      NULL
1252 #define serial_hsu_resume       NULL
1253 #endif
1254
1255 #ifdef CONFIG_PM_RUNTIME
1256 static int serial_hsu_runtime_idle(struct device *dev)
1257 {
1258         int err;
1259
1260         err = pm_schedule_suspend(dev, 500);
1261         if (err)
1262                 return -EBUSY;
1263
1264         return 0;
1265 }
1266
1267 static int serial_hsu_runtime_suspend(struct device *dev)
1268 {
1269         return 0;
1270 }
1271
1272 static int serial_hsu_runtime_resume(struct device *dev)
1273 {
1274         return 0;
1275 }
1276 #else
1277 #define serial_hsu_runtime_idle         NULL
1278 #define serial_hsu_runtime_suspend      NULL
1279 #define serial_hsu_runtime_resume       NULL
1280 #endif
1281
1282 static const struct dev_pm_ops serial_hsu_pm_ops = {
1283         .runtime_suspend = serial_hsu_runtime_suspend,
1284         .runtime_resume = serial_hsu_runtime_resume,
1285         .runtime_idle = serial_hsu_runtime_idle,
1286 };
1287
1288 /* temp global pointer before we settle down on using one or four PCI dev */
1289 static struct hsu_port *phsu;
1290
1291 static int serial_hsu_probe(struct pci_dev *pdev,
1292                                 const struct pci_device_id *ent)
1293 {
1294         struct uart_hsu_port *uport;
1295         int index, ret;
1296
1297         printk(KERN_INFO "HSU: found PCI Serial controller(ID: %04x:%04x)\n",
1298                 pdev->vendor, pdev->device);
1299
1300         switch (pdev->device) {
1301         case 0x081B:
1302                 index = 0;
1303                 break;
1304         case 0x081C:
1305                 index = 1;
1306                 break;
1307         case 0x081D:
1308                 index = 2;
1309                 break;
1310         case 0x081E:
1311                 /* internal DMA controller */
1312                 index = 3;
1313                 break;
1314         default:
1315                 dev_err(&pdev->dev, "HSU: out of index!");
1316                 return -ENODEV;
1317         }
1318
1319         ret = pci_enable_device(pdev);
1320         if (ret)
1321                 return ret;
1322
1323         if (index == 3) {
1324                 /* DMA controller */
1325                 ret = request_irq(pdev->irq, dma_irq, 0, "hsu_dma", phsu);
1326                 if (ret) {
1327                         dev_err(&pdev->dev, "can not get IRQ\n");
1328                         goto err_disable;
1329                 }
1330                 pci_set_drvdata(pdev, phsu);
1331         } else {
1332                 /* UART port 0~2 */
1333                 uport = &phsu->port[index];
1334                 uport->port.irq = pdev->irq;
1335                 uport->port.dev = &pdev->dev;
1336                 uport->dev = &pdev->dev;
1337
1338                 ret = request_irq(pdev->irq, port_irq, 0, uport->name, uport);
1339                 if (ret) {
1340                         dev_err(&pdev->dev, "can not get IRQ\n");
1341                         goto err_disable;
1342                 }
1343                 uart_add_one_port(&serial_hsu_reg, &uport->port);
1344
1345                 pci_set_drvdata(pdev, uport);
1346         }
1347
1348         pm_runtime_put_noidle(&pdev->dev);
1349         pm_runtime_allow(&pdev->dev);
1350
1351         return 0;
1352
1353 err_disable:
1354         pci_disable_device(pdev);
1355         return ret;
1356 }
1357
1358 static void hsu_global_init(void)
1359 {
1360         struct hsu_port *hsu;
1361         struct uart_hsu_port *uport;
1362         struct hsu_dma_chan *dchan;
1363         int i, ret;
1364
1365         hsu = kzalloc(sizeof(struct hsu_port), GFP_KERNEL);
1366         if (!hsu)
1367                 return;
1368
1369         /* Get basic io resource and map it */
1370         hsu->paddr = 0xffa28000;
1371         hsu->iolen = 0x1000;
1372
1373         if (!(request_mem_region(hsu->paddr, hsu->iolen, "HSU global")))
1374                 pr_warning("HSU: error in request mem region\n");
1375
1376         hsu->reg = ioremap_nocache((unsigned long)hsu->paddr, hsu->iolen);
1377         if (!hsu->reg) {
1378                 pr_err("HSU: error in ioremap\n");
1379                 ret = -ENOMEM;
1380                 goto err_free_region;
1381         }
1382
1383         /* Initialise the 3 UART ports */
1384         uport = hsu->port;
1385         for (i = 0; i < 3; i++) {
1386                 uport->port.type = PORT_MFD;
1387                 uport->port.iotype = UPIO_MEM;
1388                 uport->port.mapbase = (resource_size_t)hsu->paddr
1389                                         + HSU_PORT_REG_OFFSET
1390                                         + i * HSU_PORT_REG_LENGTH;
1391                 uport->port.membase = hsu->reg + HSU_PORT_REG_OFFSET
1392                                         + i * HSU_PORT_REG_LENGTH;
1393
1394                 sprintf(uport->name, "hsu_port%d", i);
1395                 uport->port.fifosize = 64;
1396                 uport->port.ops = &serial_hsu_pops;
1397                 uport->port.line = i;
1398                 uport->port.flags = UPF_IOREMAP;
1399                 /* set the scalable maxim support rate to 2746800 bps */
1400                 uport->port.uartclk = 115200 * 24 * 16;
1401
1402                 uport->running = 0;
1403                 uport->txc = &hsu->chans[i * 2];
1404                 uport->rxc = &hsu->chans[i * 2 + 1];
1405
1406                 serial_hsu_ports[i] = uport;
1407                 uport->index = i;
1408
1409                 if (hsu_dma_enable & (1<<i))
1410                         uport->use_dma = 1;
1411                 else
1412                         uport->use_dma = 0;
1413
1414                 uport++;
1415         }
1416
1417         /* Initialise 6 dma channels */
1418         dchan = hsu->chans;
1419         for (i = 0; i < 6; i++) {
1420                 dchan->id = i;
1421                 dchan->dirt = (i & 0x1) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1422                 dchan->uport = &hsu->port[i/2];
1423                 dchan->reg = hsu->reg + HSU_DMA_CHANS_REG_OFFSET +
1424                                 i * HSU_DMA_CHANS_REG_LENGTH;
1425
1426                 dchan++;
1427         }
1428
1429         phsu = hsu;
1430         hsu_debugfs_init(hsu);
1431         return;
1432
1433 err_free_region:
1434         release_mem_region(hsu->paddr, hsu->iolen);
1435         kfree(hsu);
1436         return;
1437 }
1438
1439 static void serial_hsu_remove(struct pci_dev *pdev)
1440 {
1441         void *priv = pci_get_drvdata(pdev);
1442         struct uart_hsu_port *up;
1443
1444         if (!priv)
1445                 return;
1446
1447         pm_runtime_forbid(&pdev->dev);
1448         pm_runtime_get_noresume(&pdev->dev);
1449
1450         /* For port 0/1/2, priv is the address of uart_hsu_port */
1451         if (pdev->device != 0x081E) {
1452                 up = priv;
1453                 uart_remove_one_port(&serial_hsu_reg, &up->port);
1454         }
1455
1456         pci_set_drvdata(pdev, NULL);
1457         free_irq(pdev->irq, priv);
1458         pci_disable_device(pdev);
1459 }
1460
1461 /* First 3 are UART ports, and the 4th is the DMA */
1462 static const struct pci_device_id pci_ids[] = {
1463         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081B) },
1464         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081C) },
1465         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081D) },
1466         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081E) },
1467         {},
1468 };
1469
1470 static struct pci_driver hsu_pci_driver = {
1471         .name =         "HSU serial",
1472         .id_table =     pci_ids,
1473         .probe =        serial_hsu_probe,
1474         .remove =       serial_hsu_remove,
1475         .suspend =      serial_hsu_suspend,
1476         .resume =       serial_hsu_resume,
1477         .driver = {
1478                 .pm = &serial_hsu_pm_ops,
1479         },
1480 };
1481
1482 static int __init hsu_pci_init(void)
1483 {
1484         int ret;
1485
1486         hsu_global_init();
1487
1488         ret = uart_register_driver(&serial_hsu_reg);
1489         if (ret)
1490                 return ret;
1491
1492         return pci_register_driver(&hsu_pci_driver);
1493 }
1494
1495 static void __exit hsu_pci_exit(void)
1496 {
1497         pci_unregister_driver(&hsu_pci_driver);
1498         uart_unregister_driver(&serial_hsu_reg);
1499
1500         hsu_debugfs_remove(phsu);
1501
1502         kfree(phsu);
1503 }
1504
1505 module_init(hsu_pci_init);
1506 module_exit(hsu_pci_exit);
1507
1508 MODULE_LICENSE("GPL v2");
1509 MODULE_ALIAS("platform:medfield-hsu");