2 * Driver for the PSC of the Freescale MPC52xx PSCs configured as UARTs.
4 * FIXME According to the usermanual the status bits in the status register
5 * are only updated when the peripherals access the FIFO and not when the
6 * CPU access them. So since we use this bits to know when we stop writing
7 * and reading, they may not be updated in-time and a race condition may
8 * exists. But I haven't be able to prove this and I don't care. But if
9 * any problem arises, it might worth checking. The TX/RX FIFO Stats
10 * registers should be used in addition.
11 * Update: Actually, they seem updated ... At least the bits we use.
14 * Maintainer : Sylvain Munaut <tnt@246tNt.com>
16 * Some of the code has been inspired/copied from the 2.4 code written
17 * by Dale Farnsworth <dfarnsworth@mvista.com>.
19 * Copyright (C) 2008 Freescale Semiconductor Inc.
20 * John Rigby <jrigby@gmail.com>
21 * Added support for MPC5121
22 * Copyright (C) 2006 Secret Lab Technologies Ltd.
23 * Grant Likely <grant.likely@secretlab.ca>
24 * Copyright (C) 2004-2006 Sylvain Munaut <tnt@246tNt.com>
25 * Copyright (C) 2003 MontaVista, Software, Inc.
27 * This file is licensed under the terms of the GNU General Public License
28 * version 2. This program is licensed "as is" without any warranty of any
29 * kind, whether express or implied.
34 #include <linux/device.h>
35 #include <linux/module.h>
36 #include <linux/tty.h>
37 #include <linux/tty_flip.h>
38 #include <linux/serial.h>
39 #include <linux/sysrq.h>
40 #include <linux/console.h>
41 #include <linux/delay.h>
44 #include <linux/of_platform.h>
45 #include <linux/clk.h>
47 #include <asm/mpc52xx.h>
48 #include <asm/mpc52xx_psc.h>
50 #if defined(CONFIG_SERIAL_MPC52xx_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
54 #include <linux/serial_core.h>
57 /* We've been assigned a range on the "Low-density serial ports" major */
58 #define SERIAL_PSC_MAJOR 204
59 #define SERIAL_PSC_MINOR 148
62 #define ISR_PASS_LIMIT 256 /* Max number of iteration in the interrupt */
65 static struct uart_port mpc52xx_uart_ports[MPC52xx_PSC_MAXNUM];
66 /* Rem: - We use the read_status_mask as a shadow of
67 * psc->mpc52xx_psc_imr
68 * - It's important that is array is all zero on start as we
69 * use it to know if it's initialized or not ! If it's not sure
70 * it's cleared, then a memset(...,0,...) should be added to
74 /* lookup table for matching device nodes to index numbers */
75 static struct device_node *mpc52xx_uart_nodes[MPC52xx_PSC_MAXNUM];
77 static void mpc52xx_uart_of_enumerate(void);
80 #define PSC(port) ((struct mpc52xx_psc __iomem *)((port)->membase))
83 /* Forward declaration of the interruption handling routine */
84 static irqreturn_t mpc52xx_uart_int(int irq, void *dev_id);
85 static irqreturn_t mpc5xxx_uart_process_int(struct uart_port *port);
87 /* ======================================================================== */
88 /* PSC fifo operations for isolating differences between 52xx and 512x */
89 /* ======================================================================== */
92 void (*fifo_init)(struct uart_port *port);
93 int (*raw_rx_rdy)(struct uart_port *port);
94 int (*raw_tx_rdy)(struct uart_port *port);
95 int (*rx_rdy)(struct uart_port *port);
96 int (*tx_rdy)(struct uart_port *port);
97 int (*tx_empty)(struct uart_port *port);
98 void (*stop_rx)(struct uart_port *port);
99 void (*start_tx)(struct uart_port *port);
100 void (*stop_tx)(struct uart_port *port);
101 void (*rx_clr_irq)(struct uart_port *port);
102 void (*tx_clr_irq)(struct uart_port *port);
103 void (*write_char)(struct uart_port *port, unsigned char c);
104 unsigned char (*read_char)(struct uart_port *port);
105 void (*cw_disable_ints)(struct uart_port *port);
106 void (*cw_restore_ints)(struct uart_port *port);
107 unsigned int (*set_baudrate)(struct uart_port *port,
108 struct ktermios *new,
109 struct ktermios *old);
110 int (*clock_alloc)(struct uart_port *port);
111 void (*clock_relse)(struct uart_port *port);
112 int (*clock)(struct uart_port *port, int enable);
113 int (*fifoc_init)(void);
114 void (*fifoc_uninit)(void);
115 void (*get_irq)(struct uart_port *, struct device_node *);
116 irqreturn_t (*handle_irq)(struct uart_port *port);
117 u16 (*get_status)(struct uart_port *port);
118 u8 (*get_ipcr)(struct uart_port *port);
119 void (*command)(struct uart_port *port, u8 cmd);
120 void (*set_mode)(struct uart_port *port, u8 mr1, u8 mr2);
121 void (*set_rts)(struct uart_port *port, int state);
122 void (*enable_ms)(struct uart_port *port);
123 void (*set_sicr)(struct uart_port *port, u32 val);
124 void (*set_imr)(struct uart_port *port, u16 val);
125 u8 (*get_mr1)(struct uart_port *port);
128 /* setting the prescaler and divisor reg is common for all chips */
129 static inline void mpc52xx_set_divisor(struct mpc52xx_psc __iomem *psc,
130 u16 prescaler, unsigned int divisor)
132 /* select prescaler */
133 out_be16(&psc->mpc52xx_psc_clock_select, prescaler);
134 out_8(&psc->ctur, divisor >> 8);
135 out_8(&psc->ctlr, divisor & 0xff);
138 static u16 mpc52xx_psc_get_status(struct uart_port *port)
140 return in_be16(&PSC(port)->mpc52xx_psc_status);
143 static u8 mpc52xx_psc_get_ipcr(struct uart_port *port)
145 return in_8(&PSC(port)->mpc52xx_psc_ipcr);
148 static void mpc52xx_psc_command(struct uart_port *port, u8 cmd)
150 out_8(&PSC(port)->command, cmd);
153 static void mpc52xx_psc_set_mode(struct uart_port *port, u8 mr1, u8 mr2)
155 out_8(&PSC(port)->command, MPC52xx_PSC_SEL_MODE_REG_1);
156 out_8(&PSC(port)->mode, mr1);
157 out_8(&PSC(port)->mode, mr2);
160 static void mpc52xx_psc_set_rts(struct uart_port *port, int state)
163 out_8(&PSC(port)->op1, MPC52xx_PSC_OP_RTS);
165 out_8(&PSC(port)->op0, MPC52xx_PSC_OP_RTS);
168 static void mpc52xx_psc_enable_ms(struct uart_port *port)
170 struct mpc52xx_psc __iomem *psc = PSC(port);
172 /* clear D_*-bits by reading them */
173 in_8(&psc->mpc52xx_psc_ipcr);
174 /* enable CTS and DCD as IPC interrupts */
175 out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD);
177 port->read_status_mask |= MPC52xx_PSC_IMR_IPC;
178 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
181 static void mpc52xx_psc_set_sicr(struct uart_port *port, u32 val)
183 out_be32(&PSC(port)->sicr, val);
186 static void mpc52xx_psc_set_imr(struct uart_port *port, u16 val)
188 out_be16(&PSC(port)->mpc52xx_psc_imr, val);
191 static u8 mpc52xx_psc_get_mr1(struct uart_port *port)
193 out_8(&PSC(port)->command, MPC52xx_PSC_SEL_MODE_REG_1);
194 return in_8(&PSC(port)->mode);
197 #ifdef CONFIG_PPC_MPC52xx
198 #define FIFO_52xx(port) ((struct mpc52xx_psc_fifo __iomem *)(PSC(port)+1))
199 static void mpc52xx_psc_fifo_init(struct uart_port *port)
201 struct mpc52xx_psc __iomem *psc = PSC(port);
202 struct mpc52xx_psc_fifo __iomem *fifo = FIFO_52xx(port);
204 out_8(&fifo->rfcntl, 0x00);
205 out_be16(&fifo->rfalarm, 0x1ff);
206 out_8(&fifo->tfcntl, 0x07);
207 out_be16(&fifo->tfalarm, 0x80);
209 port->read_status_mask |= MPC52xx_PSC_IMR_RXRDY | MPC52xx_PSC_IMR_TXRDY;
210 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
213 static int mpc52xx_psc_raw_rx_rdy(struct uart_port *port)
215 return in_be16(&PSC(port)->mpc52xx_psc_status)
216 & MPC52xx_PSC_SR_RXRDY;
219 static int mpc52xx_psc_raw_tx_rdy(struct uart_port *port)
221 return in_be16(&PSC(port)->mpc52xx_psc_status)
222 & MPC52xx_PSC_SR_TXRDY;
226 static int mpc52xx_psc_rx_rdy(struct uart_port *port)
228 return in_be16(&PSC(port)->mpc52xx_psc_isr)
229 & port->read_status_mask
230 & MPC52xx_PSC_IMR_RXRDY;
233 static int mpc52xx_psc_tx_rdy(struct uart_port *port)
235 return in_be16(&PSC(port)->mpc52xx_psc_isr)
236 & port->read_status_mask
237 & MPC52xx_PSC_IMR_TXRDY;
240 static int mpc52xx_psc_tx_empty(struct uart_port *port)
242 u16 sts = in_be16(&PSC(port)->mpc52xx_psc_status);
244 return (sts & MPC52xx_PSC_SR_TXEMP) ? TIOCSER_TEMT : 0;
247 static void mpc52xx_psc_start_tx(struct uart_port *port)
249 port->read_status_mask |= MPC52xx_PSC_IMR_TXRDY;
250 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
253 static void mpc52xx_psc_stop_tx(struct uart_port *port)
255 port->read_status_mask &= ~MPC52xx_PSC_IMR_TXRDY;
256 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
259 static void mpc52xx_psc_stop_rx(struct uart_port *port)
261 port->read_status_mask &= ~MPC52xx_PSC_IMR_RXRDY;
262 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
265 static void mpc52xx_psc_rx_clr_irq(struct uart_port *port)
269 static void mpc52xx_psc_tx_clr_irq(struct uart_port *port)
273 static void mpc52xx_psc_write_char(struct uart_port *port, unsigned char c)
275 out_8(&PSC(port)->mpc52xx_psc_buffer_8, c);
278 static unsigned char mpc52xx_psc_read_char(struct uart_port *port)
280 return in_8(&PSC(port)->mpc52xx_psc_buffer_8);
283 static void mpc52xx_psc_cw_disable_ints(struct uart_port *port)
285 out_be16(&PSC(port)->mpc52xx_psc_imr, 0);
288 static void mpc52xx_psc_cw_restore_ints(struct uart_port *port)
290 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
293 static unsigned int mpc5200_psc_set_baudrate(struct uart_port *port,
294 struct ktermios *new,
295 struct ktermios *old)
298 unsigned int divisor;
300 /* The 5200 has a fixed /32 prescaler, uartclk contains the ipb freq */
301 baud = uart_get_baud_rate(port, new, old,
302 port->uartclk / (32 * 0xffff) + 1,
304 divisor = (port->uartclk + 16 * baud) / (32 * baud);
306 /* enable the /32 prescaler and set the divisor */
307 mpc52xx_set_divisor(PSC(port), 0xdd00, divisor);
311 static unsigned int mpc5200b_psc_set_baudrate(struct uart_port *port,
312 struct ktermios *new,
313 struct ktermios *old)
316 unsigned int divisor;
319 /* The 5200B has a selectable /4 or /32 prescaler, uartclk contains the
321 baud = uart_get_baud_rate(port, new, old,
322 port->uartclk / (32 * 0xffff) + 1,
324 divisor = (port->uartclk + 2 * baud) / (4 * baud);
326 /* select the proper prescaler and set the divisor
327 * prefer high prescaler for more tolerance on low baudrates */
328 if (divisor > 0xffff || baud <= 115200) {
329 divisor = (divisor + 4) / 8;
330 prescaler = 0xdd00; /* /32 */
332 prescaler = 0xff00; /* /4 */
333 mpc52xx_set_divisor(PSC(port), prescaler, divisor);
337 static void mpc52xx_psc_get_irq(struct uart_port *port, struct device_node *np)
340 port->irq = irq_of_parse_and_map(np, 0);
343 /* 52xx specific interrupt handler. The caller holds the port lock */
344 static irqreturn_t mpc52xx_psc_handle_irq(struct uart_port *port)
346 return mpc5xxx_uart_process_int(port);
349 static struct psc_ops mpc52xx_psc_ops = {
350 .fifo_init = mpc52xx_psc_fifo_init,
351 .raw_rx_rdy = mpc52xx_psc_raw_rx_rdy,
352 .raw_tx_rdy = mpc52xx_psc_raw_tx_rdy,
353 .rx_rdy = mpc52xx_psc_rx_rdy,
354 .tx_rdy = mpc52xx_psc_tx_rdy,
355 .tx_empty = mpc52xx_psc_tx_empty,
356 .stop_rx = mpc52xx_psc_stop_rx,
357 .start_tx = mpc52xx_psc_start_tx,
358 .stop_tx = mpc52xx_psc_stop_tx,
359 .rx_clr_irq = mpc52xx_psc_rx_clr_irq,
360 .tx_clr_irq = mpc52xx_psc_tx_clr_irq,
361 .write_char = mpc52xx_psc_write_char,
362 .read_char = mpc52xx_psc_read_char,
363 .cw_disable_ints = mpc52xx_psc_cw_disable_ints,
364 .cw_restore_ints = mpc52xx_psc_cw_restore_ints,
365 .set_baudrate = mpc5200_psc_set_baudrate,
366 .get_irq = mpc52xx_psc_get_irq,
367 .handle_irq = mpc52xx_psc_handle_irq,
368 .get_status = mpc52xx_psc_get_status,
369 .get_ipcr = mpc52xx_psc_get_ipcr,
370 .command = mpc52xx_psc_command,
371 .set_mode = mpc52xx_psc_set_mode,
372 .set_rts = mpc52xx_psc_set_rts,
373 .enable_ms = mpc52xx_psc_enable_ms,
374 .set_sicr = mpc52xx_psc_set_sicr,
375 .set_imr = mpc52xx_psc_set_imr,
376 .get_mr1 = mpc52xx_psc_get_mr1,
379 static struct psc_ops mpc5200b_psc_ops = {
380 .fifo_init = mpc52xx_psc_fifo_init,
381 .raw_rx_rdy = mpc52xx_psc_raw_rx_rdy,
382 .raw_tx_rdy = mpc52xx_psc_raw_tx_rdy,
383 .rx_rdy = mpc52xx_psc_rx_rdy,
384 .tx_rdy = mpc52xx_psc_tx_rdy,
385 .tx_empty = mpc52xx_psc_tx_empty,
386 .stop_rx = mpc52xx_psc_stop_rx,
387 .start_tx = mpc52xx_psc_start_tx,
388 .stop_tx = mpc52xx_psc_stop_tx,
389 .rx_clr_irq = mpc52xx_psc_rx_clr_irq,
390 .tx_clr_irq = mpc52xx_psc_tx_clr_irq,
391 .write_char = mpc52xx_psc_write_char,
392 .read_char = mpc52xx_psc_read_char,
393 .cw_disable_ints = mpc52xx_psc_cw_disable_ints,
394 .cw_restore_ints = mpc52xx_psc_cw_restore_ints,
395 .set_baudrate = mpc5200b_psc_set_baudrate,
396 .get_irq = mpc52xx_psc_get_irq,
397 .handle_irq = mpc52xx_psc_handle_irq,
398 .get_status = mpc52xx_psc_get_status,
399 .get_ipcr = mpc52xx_psc_get_ipcr,
400 .command = mpc52xx_psc_command,
401 .set_mode = mpc52xx_psc_set_mode,
402 .set_rts = mpc52xx_psc_set_rts,
403 .enable_ms = mpc52xx_psc_enable_ms,
404 .set_sicr = mpc52xx_psc_set_sicr,
405 .set_imr = mpc52xx_psc_set_imr,
406 .get_mr1 = mpc52xx_psc_get_mr1,
409 #endif /* CONFIG_PPC_MPC52xx */
411 #ifdef CONFIG_PPC_MPC512x
412 #define FIFO_512x(port) ((struct mpc512x_psc_fifo __iomem *)(PSC(port)+1))
414 /* PSC FIFO Controller for mpc512x */
423 static struct psc_fifoc __iomem *psc_fifoc;
424 static unsigned int psc_fifoc_irq;
425 static struct clk *psc_fifoc_clk;
427 static void mpc512x_psc_fifo_init(struct uart_port *port)
430 out_be16(&PSC(port)->mpc52xx_psc_clock_select, 0xdd00);
432 out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE);
433 out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
434 out_be32(&FIFO_512x(port)->txalarm, 1);
435 out_be32(&FIFO_512x(port)->tximr, 0);
437 out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE);
438 out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
439 out_be32(&FIFO_512x(port)->rxalarm, 1);
440 out_be32(&FIFO_512x(port)->rximr, 0);
442 out_be32(&FIFO_512x(port)->tximr, MPC512x_PSC_FIFO_ALARM);
443 out_be32(&FIFO_512x(port)->rximr, MPC512x_PSC_FIFO_ALARM);
446 static int mpc512x_psc_raw_rx_rdy(struct uart_port *port)
448 return !(in_be32(&FIFO_512x(port)->rxsr) & MPC512x_PSC_FIFO_EMPTY);
451 static int mpc512x_psc_raw_tx_rdy(struct uart_port *port)
453 return !(in_be32(&FIFO_512x(port)->txsr) & MPC512x_PSC_FIFO_FULL);
456 static int mpc512x_psc_rx_rdy(struct uart_port *port)
458 return in_be32(&FIFO_512x(port)->rxsr)
459 & in_be32(&FIFO_512x(port)->rximr)
460 & MPC512x_PSC_FIFO_ALARM;
463 static int mpc512x_psc_tx_rdy(struct uart_port *port)
465 return in_be32(&FIFO_512x(port)->txsr)
466 & in_be32(&FIFO_512x(port)->tximr)
467 & MPC512x_PSC_FIFO_ALARM;
470 static int mpc512x_psc_tx_empty(struct uart_port *port)
472 return in_be32(&FIFO_512x(port)->txsr)
473 & MPC512x_PSC_FIFO_EMPTY;
476 static void mpc512x_psc_stop_rx(struct uart_port *port)
478 unsigned long rx_fifo_imr;
480 rx_fifo_imr = in_be32(&FIFO_512x(port)->rximr);
481 rx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
482 out_be32(&FIFO_512x(port)->rximr, rx_fifo_imr);
485 static void mpc512x_psc_start_tx(struct uart_port *port)
487 unsigned long tx_fifo_imr;
489 tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr);
490 tx_fifo_imr |= MPC512x_PSC_FIFO_ALARM;
491 out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr);
494 static void mpc512x_psc_stop_tx(struct uart_port *port)
496 unsigned long tx_fifo_imr;
498 tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr);
499 tx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
500 out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr);
503 static void mpc512x_psc_rx_clr_irq(struct uart_port *port)
505 out_be32(&FIFO_512x(port)->rxisr, in_be32(&FIFO_512x(port)->rxisr));
508 static void mpc512x_psc_tx_clr_irq(struct uart_port *port)
510 out_be32(&FIFO_512x(port)->txisr, in_be32(&FIFO_512x(port)->txisr));
513 static void mpc512x_psc_write_char(struct uart_port *port, unsigned char c)
515 out_8(&FIFO_512x(port)->txdata_8, c);
518 static unsigned char mpc512x_psc_read_char(struct uart_port *port)
520 return in_8(&FIFO_512x(port)->rxdata_8);
523 static void mpc512x_psc_cw_disable_ints(struct uart_port *port)
525 port->read_status_mask =
526 in_be32(&FIFO_512x(port)->tximr) << 16 |
527 in_be32(&FIFO_512x(port)->rximr);
528 out_be32(&FIFO_512x(port)->tximr, 0);
529 out_be32(&FIFO_512x(port)->rximr, 0);
532 static void mpc512x_psc_cw_restore_ints(struct uart_port *port)
534 out_be32(&FIFO_512x(port)->tximr,
535 (port->read_status_mask >> 16) & 0x7f);
536 out_be32(&FIFO_512x(port)->rximr, port->read_status_mask & 0x7f);
539 static unsigned int mpc512x_psc_set_baudrate(struct uart_port *port,
540 struct ktermios *new,
541 struct ktermios *old)
544 unsigned int divisor;
547 * The "MPC5121e Microcontroller Reference Manual, Rev. 3" says on
548 * pg. 30-10 that the chip supports a /32 and a /10 prescaler.
549 * Furthermore, it states that "After reset, the prescaler by 10
550 * for the UART mode is selected", but the reset register value is
551 * 0x0000 which means a /32 prescaler. This is wrong.
553 * In reality using /32 prescaler doesn't work, as it is not supported!
554 * Use /16 or /10 prescaler, see "MPC5121e Hardware Design Guide",
555 * Chapter 4.1 PSC in UART Mode.
556 * Calculate with a /16 prescaler here.
559 /* uartclk contains the ips freq */
560 baud = uart_get_baud_rate(port, new, old,
561 port->uartclk / (16 * 0xffff) + 1,
563 divisor = (port->uartclk + 8 * baud) / (16 * baud);
565 /* enable the /16 prescaler and set the divisor */
566 mpc52xx_set_divisor(PSC(port), 0xdd00, divisor);
570 /* Init PSC FIFO Controller */
571 static int __init mpc512x_psc_fifoc_init(void)
574 struct device_node *np;
577 /* default error code, potentially overwritten by clock calls */
580 np = of_find_compatible_node(NULL, NULL,
581 "fsl,mpc5121-psc-fifo");
583 pr_err("%s: Can't find FIFOC node\n", __func__);
587 clk = of_clk_get(np, 0);
589 /* backwards compat with device trees that lack clock specs */
590 clk = clk_get_sys(np->name, "ipg");
593 pr_err("%s: Can't lookup FIFO clock\n", __func__);
597 if (clk_prepare_enable(clk)) {
598 pr_err("%s: Can't enable FIFO clock\n", __func__);
604 psc_fifoc = of_iomap(np, 0);
606 pr_err("%s: Can't map FIFOC\n", __func__);
607 goto out_clk_disable;
610 psc_fifoc_irq = irq_of_parse_and_map(np, 0);
611 if (psc_fifoc_irq == 0) {
612 pr_err("%s: Can't get FIFOC irq\n", __func__);
622 clk_disable_unprepare(psc_fifoc_clk);
623 clk_put(psc_fifoc_clk);
630 static void __exit mpc512x_psc_fifoc_uninit(void)
634 /* disable the clock, errors are not fatal */
636 clk_disable_unprepare(psc_fifoc_clk);
637 clk_put(psc_fifoc_clk);
638 psc_fifoc_clk = NULL;
642 /* 512x specific interrupt handler. The caller holds the port lock */
643 static irqreturn_t mpc512x_psc_handle_irq(struct uart_port *port)
645 unsigned long fifoc_int;
648 /* Read pending PSC FIFOC interrupts */
649 fifoc_int = in_be32(&psc_fifoc->fifoc_int);
651 /* Check if it is an interrupt for this port */
652 psc_num = (port->mapbase & 0xf00) >> 8;
653 if (test_bit(psc_num, &fifoc_int) ||
654 test_bit(psc_num + 16, &fifoc_int))
655 return mpc5xxx_uart_process_int(port);
660 static struct clk *psc_mclk_clk[MPC52xx_PSC_MAXNUM];
661 static struct clk *psc_ipg_clk[MPC52xx_PSC_MAXNUM];
663 /* called from within the .request_port() callback (allocation) */
664 static int mpc512x_psc_alloc_clock(struct uart_port *port)
670 psc_num = (port->mapbase & 0xf00) >> 8;
672 clk = devm_clk_get(port->dev, "mclk");
674 dev_err(port->dev, "Failed to get MCLK!\n");
678 err = clk_prepare_enable(clk);
680 dev_err(port->dev, "Failed to enable MCLK!\n");
683 psc_mclk_clk[psc_num] = clk;
685 clk = devm_clk_get(port->dev, "ipg");
687 dev_err(port->dev, "Failed to get IPG clock!\n");
691 err = clk_prepare_enable(clk);
693 dev_err(port->dev, "Failed to enable IPG clock!\n");
696 psc_ipg_clk[psc_num] = clk;
701 if (psc_mclk_clk[psc_num]) {
702 clk_disable_unprepare(psc_mclk_clk[psc_num]);
703 psc_mclk_clk[psc_num] = NULL;
705 if (psc_ipg_clk[psc_num]) {
706 clk_disable_unprepare(psc_ipg_clk[psc_num]);
707 psc_ipg_clk[psc_num] = NULL;
712 /* called from within the .release_port() callback (release) */
713 static void mpc512x_psc_relse_clock(struct uart_port *port)
718 psc_num = (port->mapbase & 0xf00) >> 8;
719 clk = psc_mclk_clk[psc_num];
721 clk_disable_unprepare(clk);
722 psc_mclk_clk[psc_num] = NULL;
724 if (psc_ipg_clk[psc_num]) {
725 clk_disable_unprepare(psc_ipg_clk[psc_num]);
726 psc_ipg_clk[psc_num] = NULL;
730 /* implementation of the .clock() callback (enable/disable) */
731 static int mpc512x_psc_endis_clock(struct uart_port *port, int enable)
737 if (uart_console(port))
740 psc_num = (port->mapbase & 0xf00) >> 8;
741 psc_clk = psc_mclk_clk[psc_num];
743 dev_err(port->dev, "Failed to get PSC clock entry!\n");
747 dev_dbg(port->dev, "mclk %sable\n", enable ? "en" : "dis");
749 ret = clk_enable(psc_clk);
751 dev_err(port->dev, "Failed to enable MCLK!\n");
754 clk_disable(psc_clk);
759 static void mpc512x_psc_get_irq(struct uart_port *port, struct device_node *np)
761 port->irqflags = IRQF_SHARED;
762 port->irq = psc_fifoc_irq;
766 #ifdef CONFIG_PPC_MPC512x
768 #define PSC_5125(port) ((struct mpc5125_psc __iomem *)((port)->membase))
769 #define FIFO_5125(port) ((struct mpc512x_psc_fifo __iomem *)(PSC_5125(port)+1))
771 static void mpc5125_psc_fifo_init(struct uart_port *port)
774 out_8(&PSC_5125(port)->mpc52xx_psc_clock_select, 0xdd);
776 out_be32(&FIFO_5125(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE);
777 out_be32(&FIFO_5125(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
778 out_be32(&FIFO_5125(port)->txalarm, 1);
779 out_be32(&FIFO_5125(port)->tximr, 0);
781 out_be32(&FIFO_5125(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE);
782 out_be32(&FIFO_5125(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
783 out_be32(&FIFO_5125(port)->rxalarm, 1);
784 out_be32(&FIFO_5125(port)->rximr, 0);
786 out_be32(&FIFO_5125(port)->tximr, MPC512x_PSC_FIFO_ALARM);
787 out_be32(&FIFO_5125(port)->rximr, MPC512x_PSC_FIFO_ALARM);
790 static int mpc5125_psc_raw_rx_rdy(struct uart_port *port)
792 return !(in_be32(&FIFO_5125(port)->rxsr) & MPC512x_PSC_FIFO_EMPTY);
795 static int mpc5125_psc_raw_tx_rdy(struct uart_port *port)
797 return !(in_be32(&FIFO_5125(port)->txsr) & MPC512x_PSC_FIFO_FULL);
800 static int mpc5125_psc_rx_rdy(struct uart_port *port)
802 return in_be32(&FIFO_5125(port)->rxsr) &
803 in_be32(&FIFO_5125(port)->rximr) & MPC512x_PSC_FIFO_ALARM;
806 static int mpc5125_psc_tx_rdy(struct uart_port *port)
808 return in_be32(&FIFO_5125(port)->txsr) &
809 in_be32(&FIFO_5125(port)->tximr) & MPC512x_PSC_FIFO_ALARM;
812 static int mpc5125_psc_tx_empty(struct uart_port *port)
814 return in_be32(&FIFO_5125(port)->txsr) & MPC512x_PSC_FIFO_EMPTY;
817 static void mpc5125_psc_stop_rx(struct uart_port *port)
819 unsigned long rx_fifo_imr;
821 rx_fifo_imr = in_be32(&FIFO_5125(port)->rximr);
822 rx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
823 out_be32(&FIFO_5125(port)->rximr, rx_fifo_imr);
826 static void mpc5125_psc_start_tx(struct uart_port *port)
828 unsigned long tx_fifo_imr;
830 tx_fifo_imr = in_be32(&FIFO_5125(port)->tximr);
831 tx_fifo_imr |= MPC512x_PSC_FIFO_ALARM;
832 out_be32(&FIFO_5125(port)->tximr, tx_fifo_imr);
835 static void mpc5125_psc_stop_tx(struct uart_port *port)
837 unsigned long tx_fifo_imr;
839 tx_fifo_imr = in_be32(&FIFO_5125(port)->tximr);
840 tx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
841 out_be32(&FIFO_5125(port)->tximr, tx_fifo_imr);
844 static void mpc5125_psc_rx_clr_irq(struct uart_port *port)
846 out_be32(&FIFO_5125(port)->rxisr, in_be32(&FIFO_5125(port)->rxisr));
849 static void mpc5125_psc_tx_clr_irq(struct uart_port *port)
851 out_be32(&FIFO_5125(port)->txisr, in_be32(&FIFO_5125(port)->txisr));
854 static void mpc5125_psc_write_char(struct uart_port *port, unsigned char c)
856 out_8(&FIFO_5125(port)->txdata_8, c);
859 static unsigned char mpc5125_psc_read_char(struct uart_port *port)
861 return in_8(&FIFO_5125(port)->rxdata_8);
864 static void mpc5125_psc_cw_disable_ints(struct uart_port *port)
866 port->read_status_mask =
867 in_be32(&FIFO_5125(port)->tximr) << 16 |
868 in_be32(&FIFO_5125(port)->rximr);
869 out_be32(&FIFO_5125(port)->tximr, 0);
870 out_be32(&FIFO_5125(port)->rximr, 0);
873 static void mpc5125_psc_cw_restore_ints(struct uart_port *port)
875 out_be32(&FIFO_5125(port)->tximr,
876 (port->read_status_mask >> 16) & 0x7f);
877 out_be32(&FIFO_5125(port)->rximr, port->read_status_mask & 0x7f);
880 static inline void mpc5125_set_divisor(struct mpc5125_psc __iomem *psc,
881 u8 prescaler, unsigned int divisor)
883 /* select prescaler */
884 out_8(&psc->mpc52xx_psc_clock_select, prescaler);
885 out_8(&psc->ctur, divisor >> 8);
886 out_8(&psc->ctlr, divisor & 0xff);
889 static unsigned int mpc5125_psc_set_baudrate(struct uart_port *port,
890 struct ktermios *new,
891 struct ktermios *old)
894 unsigned int divisor;
897 * Calculate with a /16 prescaler here.
900 /* uartclk contains the ips freq */
901 baud = uart_get_baud_rate(port, new, old,
902 port->uartclk / (16 * 0xffff) + 1,
904 divisor = (port->uartclk + 8 * baud) / (16 * baud);
906 /* enable the /16 prescaler and set the divisor */
907 mpc5125_set_divisor(PSC_5125(port), 0xdd, divisor);
912 * MPC5125 have compatible PSC FIFO Controller.
913 * Special init not needed.
915 static u16 mpc5125_psc_get_status(struct uart_port *port)
917 return in_be16(&PSC_5125(port)->mpc52xx_psc_status);
920 static u8 mpc5125_psc_get_ipcr(struct uart_port *port)
922 return in_8(&PSC_5125(port)->mpc52xx_psc_ipcr);
925 static void mpc5125_psc_command(struct uart_port *port, u8 cmd)
927 out_8(&PSC_5125(port)->command, cmd);
930 static void mpc5125_psc_set_mode(struct uart_port *port, u8 mr1, u8 mr2)
932 out_8(&PSC_5125(port)->mr1, mr1);
933 out_8(&PSC_5125(port)->mr2, mr2);
936 static void mpc5125_psc_set_rts(struct uart_port *port, int state)
938 if (state & TIOCM_RTS)
939 out_8(&PSC_5125(port)->op1, MPC52xx_PSC_OP_RTS);
941 out_8(&PSC_5125(port)->op0, MPC52xx_PSC_OP_RTS);
944 static void mpc5125_psc_enable_ms(struct uart_port *port)
946 struct mpc5125_psc __iomem *psc = PSC_5125(port);
948 /* clear D_*-bits by reading them */
949 in_8(&psc->mpc52xx_psc_ipcr);
950 /* enable CTS and DCD as IPC interrupts */
951 out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD);
953 port->read_status_mask |= MPC52xx_PSC_IMR_IPC;
954 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
957 static void mpc5125_psc_set_sicr(struct uart_port *port, u32 val)
959 out_be32(&PSC_5125(port)->sicr, val);
962 static void mpc5125_psc_set_imr(struct uart_port *port, u16 val)
964 out_be16(&PSC_5125(port)->mpc52xx_psc_imr, val);
967 static u8 mpc5125_psc_get_mr1(struct uart_port *port)
969 return in_8(&PSC_5125(port)->mr1);
972 static struct psc_ops mpc5125_psc_ops = {
973 .fifo_init = mpc5125_psc_fifo_init,
974 .raw_rx_rdy = mpc5125_psc_raw_rx_rdy,
975 .raw_tx_rdy = mpc5125_psc_raw_tx_rdy,
976 .rx_rdy = mpc5125_psc_rx_rdy,
977 .tx_rdy = mpc5125_psc_tx_rdy,
978 .tx_empty = mpc5125_psc_tx_empty,
979 .stop_rx = mpc5125_psc_stop_rx,
980 .start_tx = mpc5125_psc_start_tx,
981 .stop_tx = mpc5125_psc_stop_tx,
982 .rx_clr_irq = mpc5125_psc_rx_clr_irq,
983 .tx_clr_irq = mpc5125_psc_tx_clr_irq,
984 .write_char = mpc5125_psc_write_char,
985 .read_char = mpc5125_psc_read_char,
986 .cw_disable_ints = mpc5125_psc_cw_disable_ints,
987 .cw_restore_ints = mpc5125_psc_cw_restore_ints,
988 .set_baudrate = mpc5125_psc_set_baudrate,
989 .clock_alloc = mpc512x_psc_alloc_clock,
990 .clock_relse = mpc512x_psc_relse_clock,
991 .clock = mpc512x_psc_endis_clock,
992 .fifoc_init = mpc512x_psc_fifoc_init,
993 .fifoc_uninit = mpc512x_psc_fifoc_uninit,
994 .get_irq = mpc512x_psc_get_irq,
995 .handle_irq = mpc512x_psc_handle_irq,
996 .get_status = mpc5125_psc_get_status,
997 .get_ipcr = mpc5125_psc_get_ipcr,
998 .command = mpc5125_psc_command,
999 .set_mode = mpc5125_psc_set_mode,
1000 .set_rts = mpc5125_psc_set_rts,
1001 .enable_ms = mpc5125_psc_enable_ms,
1002 .set_sicr = mpc5125_psc_set_sicr,
1003 .set_imr = mpc5125_psc_set_imr,
1004 .get_mr1 = mpc5125_psc_get_mr1,
1007 static struct psc_ops mpc512x_psc_ops = {
1008 .fifo_init = mpc512x_psc_fifo_init,
1009 .raw_rx_rdy = mpc512x_psc_raw_rx_rdy,
1010 .raw_tx_rdy = mpc512x_psc_raw_tx_rdy,
1011 .rx_rdy = mpc512x_psc_rx_rdy,
1012 .tx_rdy = mpc512x_psc_tx_rdy,
1013 .tx_empty = mpc512x_psc_tx_empty,
1014 .stop_rx = mpc512x_psc_stop_rx,
1015 .start_tx = mpc512x_psc_start_tx,
1016 .stop_tx = mpc512x_psc_stop_tx,
1017 .rx_clr_irq = mpc512x_psc_rx_clr_irq,
1018 .tx_clr_irq = mpc512x_psc_tx_clr_irq,
1019 .write_char = mpc512x_psc_write_char,
1020 .read_char = mpc512x_psc_read_char,
1021 .cw_disable_ints = mpc512x_psc_cw_disable_ints,
1022 .cw_restore_ints = mpc512x_psc_cw_restore_ints,
1023 .set_baudrate = mpc512x_psc_set_baudrate,
1024 .clock_alloc = mpc512x_psc_alloc_clock,
1025 .clock_relse = mpc512x_psc_relse_clock,
1026 .clock = mpc512x_psc_endis_clock,
1027 .fifoc_init = mpc512x_psc_fifoc_init,
1028 .fifoc_uninit = mpc512x_psc_fifoc_uninit,
1029 .get_irq = mpc512x_psc_get_irq,
1030 .handle_irq = mpc512x_psc_handle_irq,
1031 .get_status = mpc52xx_psc_get_status,
1032 .get_ipcr = mpc52xx_psc_get_ipcr,
1033 .command = mpc52xx_psc_command,
1034 .set_mode = mpc52xx_psc_set_mode,
1035 .set_rts = mpc52xx_psc_set_rts,
1036 .enable_ms = mpc52xx_psc_enable_ms,
1037 .set_sicr = mpc52xx_psc_set_sicr,
1038 .set_imr = mpc52xx_psc_set_imr,
1039 .get_mr1 = mpc52xx_psc_get_mr1,
1041 #endif /* CONFIG_PPC_MPC512x */
1044 static const struct psc_ops *psc_ops;
1046 /* ======================================================================== */
1047 /* UART operations */
1048 /* ======================================================================== */
1051 mpc52xx_uart_tx_empty(struct uart_port *port)
1053 return psc_ops->tx_empty(port) ? TIOCSER_TEMT : 0;
1057 mpc52xx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1059 psc_ops->set_rts(port, mctrl & TIOCM_RTS);
1063 mpc52xx_uart_get_mctrl(struct uart_port *port)
1065 unsigned int ret = TIOCM_DSR;
1066 u8 status = psc_ops->get_ipcr(port);
1068 if (!(status & MPC52xx_PSC_CTS))
1070 if (!(status & MPC52xx_PSC_DCD))
1077 mpc52xx_uart_stop_tx(struct uart_port *port)
1079 /* port->lock taken by caller */
1080 psc_ops->stop_tx(port);
1084 mpc52xx_uart_start_tx(struct uart_port *port)
1086 /* port->lock taken by caller */
1087 psc_ops->start_tx(port);
1091 mpc52xx_uart_stop_rx(struct uart_port *port)
1093 /* port->lock taken by caller */
1094 psc_ops->stop_rx(port);
1098 mpc52xx_uart_enable_ms(struct uart_port *port)
1100 psc_ops->enable_ms(port);
1104 mpc52xx_uart_break_ctl(struct uart_port *port, int ctl)
1106 unsigned long flags;
1107 spin_lock_irqsave(&port->lock, flags);
1110 psc_ops->command(port, MPC52xx_PSC_START_BRK);
1112 psc_ops->command(port, MPC52xx_PSC_STOP_BRK);
1114 spin_unlock_irqrestore(&port->lock, flags);
1118 mpc52xx_uart_startup(struct uart_port *port)
1122 if (psc_ops->clock) {
1123 ret = psc_ops->clock(port, 1);
1129 ret = request_irq(port->irq, mpc52xx_uart_int,
1130 port->irqflags, "mpc52xx_psc_uart", port);
1134 /* Reset/activate the port, clear and enable interrupts */
1135 psc_ops->command(port, MPC52xx_PSC_RST_RX);
1136 psc_ops->command(port, MPC52xx_PSC_RST_TX);
1138 psc_ops->set_sicr(port, 0); /* UART mode DCD ignored */
1140 psc_ops->fifo_init(port);
1142 psc_ops->command(port, MPC52xx_PSC_TX_ENABLE);
1143 psc_ops->command(port, MPC52xx_PSC_RX_ENABLE);
1149 mpc52xx_uart_shutdown(struct uart_port *port)
1151 /* Shut down the port. Leave TX active if on a console port */
1152 psc_ops->command(port, MPC52xx_PSC_RST_RX);
1153 if (!uart_console(port))
1154 psc_ops->command(port, MPC52xx_PSC_RST_TX);
1156 port->read_status_mask = 0;
1157 psc_ops->set_imr(port, port->read_status_mask);
1160 psc_ops->clock(port, 0);
1162 /* Disable interrupt */
1163 psc_ops->cw_disable_ints(port);
1165 /* Release interrupt */
1166 free_irq(port->irq, port);
1170 mpc52xx_uart_set_termios(struct uart_port *port, struct ktermios *new,
1171 struct ktermios *old)
1173 unsigned long flags;
1174 unsigned char mr1, mr2;
1178 /* Prepare what we're gonna write */
1181 switch (new->c_cflag & CSIZE) {
1182 case CS5: mr1 |= MPC52xx_PSC_MODE_5_BITS;
1184 case CS6: mr1 |= MPC52xx_PSC_MODE_6_BITS;
1186 case CS7: mr1 |= MPC52xx_PSC_MODE_7_BITS;
1189 default: mr1 |= MPC52xx_PSC_MODE_8_BITS;
1192 if (new->c_cflag & PARENB) {
1193 if (new->c_cflag & CMSPAR)
1194 mr1 |= MPC52xx_PSC_MODE_PARFORCE;
1196 /* With CMSPAR, PARODD also means high parity (same as termios) */
1197 mr1 |= (new->c_cflag & PARODD) ?
1198 MPC52xx_PSC_MODE_PARODD : MPC52xx_PSC_MODE_PAREVEN;
1200 mr1 |= MPC52xx_PSC_MODE_PARNONE;
1205 if (new->c_cflag & CSTOPB)
1206 mr2 |= MPC52xx_PSC_MODE_TWO_STOP;
1208 mr2 |= ((new->c_cflag & CSIZE) == CS5) ?
1209 MPC52xx_PSC_MODE_ONE_STOP_5_BITS :
1210 MPC52xx_PSC_MODE_ONE_STOP;
1212 if (new->c_cflag & CRTSCTS) {
1213 mr1 |= MPC52xx_PSC_MODE_RXRTS;
1214 mr2 |= MPC52xx_PSC_MODE_TXCTS;
1218 spin_lock_irqsave(&port->lock, flags);
1220 /* Do our best to flush TX & RX, so we don't lose anything */
1221 /* But we don't wait indefinitely ! */
1222 j = 5000000; /* Maximum wait */
1223 /* FIXME Can't receive chars since set_termios might be called at early
1224 * boot for the console, all stuff is not yet ready to receive at that
1225 * time and that just makes the kernel oops */
1226 /* while (j-- && mpc52xx_uart_int_rx_chars(port)); */
1227 while (!mpc52xx_uart_tx_empty(port) && --j)
1231 printk(KERN_ERR "mpc52xx_uart.c: "
1232 "Unable to flush RX & TX fifos in-time in set_termios."
1233 "Some chars may have been lost.\n");
1235 /* Reset the TX & RX */
1236 psc_ops->command(port, MPC52xx_PSC_RST_RX);
1237 psc_ops->command(port, MPC52xx_PSC_RST_TX);
1239 /* Send new mode settings */
1240 psc_ops->set_mode(port, mr1, mr2);
1241 baud = psc_ops->set_baudrate(port, new, old);
1243 /* Update the per-port timeout */
1244 uart_update_timeout(port, new->c_cflag, baud);
1246 if (UART_ENABLE_MS(port, new->c_cflag))
1247 mpc52xx_uart_enable_ms(port);
1249 /* Reenable TX & RX */
1250 psc_ops->command(port, MPC52xx_PSC_TX_ENABLE);
1251 psc_ops->command(port, MPC52xx_PSC_RX_ENABLE);
1253 /* We're all set, release the lock */
1254 spin_unlock_irqrestore(&port->lock, flags);
1258 mpc52xx_uart_type(struct uart_port *port)
1261 * We keep using PORT_MPC52xx for historic reasons although it applies
1262 * for MPC512x, too, but print "MPC5xxx" to not irritate users
1264 return port->type == PORT_MPC52xx ? "MPC5xxx PSC" : NULL;
1268 mpc52xx_uart_release_port(struct uart_port *port)
1270 if (psc_ops->clock_relse)
1271 psc_ops->clock_relse(port);
1273 /* remapped by us ? */
1274 if (port->flags & UPF_IOREMAP) {
1275 iounmap(port->membase);
1276 port->membase = NULL;
1279 release_mem_region(port->mapbase, sizeof(struct mpc52xx_psc));
1283 mpc52xx_uart_request_port(struct uart_port *port)
1287 if (port->flags & UPF_IOREMAP) /* Need to remap ? */
1288 port->membase = ioremap(port->mapbase,
1289 sizeof(struct mpc52xx_psc));
1294 err = request_mem_region(port->mapbase, sizeof(struct mpc52xx_psc),
1295 "mpc52xx_psc_uart") != NULL ? 0 : -EBUSY;
1300 if (psc_ops->clock_alloc) {
1301 err = psc_ops->clock_alloc(port);
1309 release_mem_region(port->mapbase, sizeof(struct mpc52xx_psc));
1311 if (port->flags & UPF_IOREMAP) {
1312 iounmap(port->membase);
1313 port->membase = NULL;
1319 mpc52xx_uart_config_port(struct uart_port *port, int flags)
1321 if ((flags & UART_CONFIG_TYPE)
1322 && (mpc52xx_uart_request_port(port) == 0))
1323 port->type = PORT_MPC52xx;
1327 mpc52xx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
1329 if (ser->type != PORT_UNKNOWN && ser->type != PORT_MPC52xx)
1332 if ((ser->irq != port->irq) ||
1333 (ser->io_type != UPIO_MEM) ||
1334 (ser->baud_base != port->uartclk) ||
1335 (ser->iomem_base != (void *)port->mapbase) ||
1343 static struct uart_ops mpc52xx_uart_ops = {
1344 .tx_empty = mpc52xx_uart_tx_empty,
1345 .set_mctrl = mpc52xx_uart_set_mctrl,
1346 .get_mctrl = mpc52xx_uart_get_mctrl,
1347 .stop_tx = mpc52xx_uart_stop_tx,
1348 .start_tx = mpc52xx_uart_start_tx,
1349 .stop_rx = mpc52xx_uart_stop_rx,
1350 .enable_ms = mpc52xx_uart_enable_ms,
1351 .break_ctl = mpc52xx_uart_break_ctl,
1352 .startup = mpc52xx_uart_startup,
1353 .shutdown = mpc52xx_uart_shutdown,
1354 .set_termios = mpc52xx_uart_set_termios,
1355 /* .pm = mpc52xx_uart_pm, Not supported yet */
1356 .type = mpc52xx_uart_type,
1357 .release_port = mpc52xx_uart_release_port,
1358 .request_port = mpc52xx_uart_request_port,
1359 .config_port = mpc52xx_uart_config_port,
1360 .verify_port = mpc52xx_uart_verify_port
1364 /* ======================================================================== */
1365 /* Interrupt handling */
1366 /* ======================================================================== */
1369 mpc52xx_uart_int_rx_chars(struct uart_port *port)
1371 struct tty_port *tport = &port->state->port;
1372 unsigned char ch, flag;
1373 unsigned short status;
1375 /* While we can read, do so ! */
1376 while (psc_ops->raw_rx_rdy(port)) {
1378 ch = psc_ops->read_char(port);
1380 /* Handle sysreq char */
1381 #ifdef SUPPORT_SYSRQ
1382 if (uart_handle_sysrq_char(port, ch)) {
1393 status = psc_ops->get_status(port);
1395 if (status & (MPC52xx_PSC_SR_PE |
1397 MPC52xx_PSC_SR_RB)) {
1399 if (status & MPC52xx_PSC_SR_RB) {
1401 uart_handle_break(port);
1403 } else if (status & MPC52xx_PSC_SR_PE) {
1405 port->icount.parity++;
1407 else if (status & MPC52xx_PSC_SR_FE) {
1409 port->icount.frame++;
1412 /* Clear error condition */
1413 psc_ops->command(port, MPC52xx_PSC_RST_ERR_STAT);
1416 tty_insert_flip_char(tport, ch, flag);
1417 if (status & MPC52xx_PSC_SR_OE) {
1419 * Overrun is special, since it's
1420 * reported immediately, and doesn't
1421 * affect the current character
1423 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
1424 port->icount.overrun++;
1428 spin_unlock(&port->lock);
1429 tty_flip_buffer_push(tport);
1430 spin_lock(&port->lock);
1432 return psc_ops->raw_rx_rdy(port);
1436 mpc52xx_uart_int_tx_chars(struct uart_port *port)
1438 struct circ_buf *xmit = &port->state->xmit;
1440 /* Process out of band chars */
1442 psc_ops->write_char(port, port->x_char);
1448 /* Nothing to do ? */
1449 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
1450 mpc52xx_uart_stop_tx(port);
1455 while (psc_ops->raw_tx_rdy(port)) {
1456 psc_ops->write_char(port, xmit->buf[xmit->tail]);
1457 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1459 if (uart_circ_empty(xmit))
1464 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1465 uart_write_wakeup(port);
1467 /* Maybe we're done after all */
1468 if (uart_circ_empty(xmit)) {
1469 mpc52xx_uart_stop_tx(port);
1477 mpc5xxx_uart_process_int(struct uart_port *port)
1479 unsigned long pass = ISR_PASS_LIMIT;
1480 unsigned int keepgoing;
1483 /* While we have stuff to do, we continue */
1485 /* If we don't find anything to do, we stop */
1488 psc_ops->rx_clr_irq(port);
1489 if (psc_ops->rx_rdy(port))
1490 keepgoing |= mpc52xx_uart_int_rx_chars(port);
1492 psc_ops->tx_clr_irq(port);
1493 if (psc_ops->tx_rdy(port))
1494 keepgoing |= mpc52xx_uart_int_tx_chars(port);
1496 status = psc_ops->get_ipcr(port);
1497 if (status & MPC52xx_PSC_D_DCD)
1498 uart_handle_dcd_change(port, !(status & MPC52xx_PSC_DCD));
1500 if (status & MPC52xx_PSC_D_CTS)
1501 uart_handle_cts_change(port, !(status & MPC52xx_PSC_CTS));
1503 /* Limit number of iteration */
1507 } while (keepgoing);
1513 mpc52xx_uart_int(int irq, void *dev_id)
1515 struct uart_port *port = dev_id;
1518 spin_lock(&port->lock);
1520 ret = psc_ops->handle_irq(port);
1522 spin_unlock(&port->lock);
1527 /* ======================================================================== */
1528 /* Console ( if applicable ) */
1529 /* ======================================================================== */
1531 #ifdef CONFIG_SERIAL_MPC52xx_CONSOLE
1534 mpc52xx_console_get_options(struct uart_port *port,
1535 int *baud, int *parity, int *bits, int *flow)
1539 pr_debug("mpc52xx_console_get_options(port=%p)\n", port);
1541 /* Read the mode registers */
1542 mr1 = psc_ops->get_mr1(port);
1544 /* CT{U,L}R are write-only ! */
1545 *baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD;
1548 switch (mr1 & MPC52xx_PSC_MODE_BITS_MASK) {
1549 case MPC52xx_PSC_MODE_5_BITS:
1552 case MPC52xx_PSC_MODE_6_BITS:
1555 case MPC52xx_PSC_MODE_7_BITS:
1558 case MPC52xx_PSC_MODE_8_BITS:
1563 if (mr1 & MPC52xx_PSC_MODE_PARNONE)
1566 *parity = mr1 & MPC52xx_PSC_MODE_PARODD ? 'o' : 'e';
1570 mpc52xx_console_write(struct console *co, const char *s, unsigned int count)
1572 struct uart_port *port = &mpc52xx_uart_ports[co->index];
1575 /* Disable interrupts */
1576 psc_ops->cw_disable_ints(port);
1578 /* Wait the TX buffer to be empty */
1579 j = 5000000; /* Maximum wait */
1580 while (!mpc52xx_uart_tx_empty(port) && --j)
1583 /* Write all the chars */
1584 for (i = 0; i < count; i++, s++) {
1585 /* Line return handling */
1587 psc_ops->write_char(port, '\r');
1590 psc_ops->write_char(port, *s);
1592 /* Wait the TX buffer to be empty */
1593 j = 20000; /* Maximum wait */
1594 while (!mpc52xx_uart_tx_empty(port) && --j)
1598 /* Restore interrupt state */
1599 psc_ops->cw_restore_ints(port);
1604 mpc52xx_console_setup(struct console *co, char *options)
1606 struct uart_port *port = &mpc52xx_uart_ports[co->index];
1607 struct device_node *np = mpc52xx_uart_nodes[co->index];
1608 unsigned int uartclk;
1609 struct resource res;
1612 int baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD;
1617 pr_debug("mpc52xx_console_setup co=%p, co->index=%i, options=%s\n",
1618 co, co->index, options);
1620 if ((co->index < 0) || (co->index >= MPC52xx_PSC_MAXNUM)) {
1621 pr_debug("PSC%x out of range\n", co->index);
1626 pr_debug("PSC%x not found in device tree\n", co->index);
1630 pr_debug("Console on ttyPSC%x is %s\n",
1631 co->index, mpc52xx_uart_nodes[co->index]->full_name);
1633 /* Fetch register locations */
1634 ret = of_address_to_resource(np, 0, &res);
1636 pr_debug("Could not get resources for PSC%x\n", co->index);
1640 uartclk = mpc5xxx_get_bus_frequency(np);
1642 pr_debug("Could not find uart clock frequency!\n");
1646 /* Basic port init. Needed since we use some uart_??? func before
1647 * real init for early access */
1648 spin_lock_init(&port->lock);
1649 port->uartclk = uartclk;
1650 port->ops = &mpc52xx_uart_ops;
1651 port->mapbase = res.start;
1652 port->membase = ioremap(res.start, sizeof(struct mpc52xx_psc));
1653 port->irq = irq_of_parse_and_map(np, 0);
1655 if (port->membase == NULL)
1658 pr_debug("mpc52xx-psc uart at %p, mapped to %p, irq=%x, freq=%i\n",
1659 (void *)port->mapbase, port->membase,
1660 port->irq, port->uartclk);
1662 /* Setup the port parameters accoding to options */
1664 uart_parse_options(options, &baud, &parity, &bits, &flow);
1666 mpc52xx_console_get_options(port, &baud, &parity, &bits, &flow);
1668 pr_debug("Setting console parameters: %i %i%c1 flow=%c\n",
1669 baud, bits, parity, flow);
1671 return uart_set_options(port, co, baud, parity, bits, flow);
1675 static struct uart_driver mpc52xx_uart_driver;
1677 static struct console mpc52xx_console = {
1679 .write = mpc52xx_console_write,
1680 .device = uart_console_device,
1681 .setup = mpc52xx_console_setup,
1682 .flags = CON_PRINTBUFFER,
1683 .index = -1, /* Specified on the cmdline (e.g. console=ttyPSC0) */
1684 .data = &mpc52xx_uart_driver,
1689 mpc52xx_console_init(void)
1691 mpc52xx_uart_of_enumerate();
1692 register_console(&mpc52xx_console);
1696 console_initcall(mpc52xx_console_init);
1698 #define MPC52xx_PSC_CONSOLE &mpc52xx_console
1700 #define MPC52xx_PSC_CONSOLE NULL
1704 /* ======================================================================== */
1706 /* ======================================================================== */
1708 static struct uart_driver mpc52xx_uart_driver = {
1709 .driver_name = "mpc52xx_psc_uart",
1710 .dev_name = "ttyPSC",
1711 .major = SERIAL_PSC_MAJOR,
1712 .minor = SERIAL_PSC_MINOR,
1713 .nr = MPC52xx_PSC_MAXNUM,
1714 .cons = MPC52xx_PSC_CONSOLE,
1717 /* ======================================================================== */
1718 /* OF Platform Driver */
1719 /* ======================================================================== */
1721 static const struct of_device_id mpc52xx_uart_of_match[] = {
1722 #ifdef CONFIG_PPC_MPC52xx
1723 { .compatible = "fsl,mpc5200b-psc-uart", .data = &mpc5200b_psc_ops, },
1724 { .compatible = "fsl,mpc5200-psc-uart", .data = &mpc52xx_psc_ops, },
1725 /* binding used by old lite5200 device trees: */
1726 { .compatible = "mpc5200-psc-uart", .data = &mpc52xx_psc_ops, },
1727 /* binding used by efika: */
1728 { .compatible = "mpc5200-serial", .data = &mpc52xx_psc_ops, },
1730 #ifdef CONFIG_PPC_MPC512x
1731 { .compatible = "fsl,mpc5121-psc-uart", .data = &mpc512x_psc_ops, },
1732 { .compatible = "fsl,mpc5125-psc-uart", .data = &mpc5125_psc_ops, },
1737 static int mpc52xx_uart_of_probe(struct platform_device *op)
1740 unsigned int uartclk;
1741 struct uart_port *port = NULL;
1742 struct resource res;
1745 /* Check validity & presence */
1746 for (idx = 0; idx < MPC52xx_PSC_MAXNUM; idx++)
1747 if (mpc52xx_uart_nodes[idx] == op->dev.of_node)
1749 if (idx >= MPC52xx_PSC_MAXNUM)
1751 pr_debug("Found %s assigned to ttyPSC%x\n",
1752 mpc52xx_uart_nodes[idx]->full_name, idx);
1754 /* set the uart clock to the input clock of the psc, the different
1755 * prescalers are taken into account in the set_baudrate() methods
1756 * of the respective chip */
1757 uartclk = mpc5xxx_get_bus_frequency(op->dev.of_node);
1759 dev_dbg(&op->dev, "Could not find uart clock frequency!\n");
1763 /* Init the port structure */
1764 port = &mpc52xx_uart_ports[idx];
1766 spin_lock_init(&port->lock);
1767 port->uartclk = uartclk;
1768 port->fifosize = 512;
1769 port->iotype = UPIO_MEM;
1770 port->flags = UPF_BOOT_AUTOCONF |
1771 (uart_console(port) ? 0 : UPF_IOREMAP);
1773 port->ops = &mpc52xx_uart_ops;
1774 port->dev = &op->dev;
1776 /* Search for IRQ and mapbase */
1777 ret = of_address_to_resource(op->dev.of_node, 0, &res);
1781 port->mapbase = res.start;
1782 if (!port->mapbase) {
1783 dev_dbg(&op->dev, "Could not allocate resources for PSC\n");
1787 psc_ops->get_irq(port, op->dev.of_node);
1788 if (port->irq == 0) {
1789 dev_dbg(&op->dev, "Could not get irq\n");
1793 dev_dbg(&op->dev, "mpc52xx-psc uart at %p, irq=%x, freq=%i\n",
1794 (void *)port->mapbase, port->irq, port->uartclk);
1796 /* Add the port to the uart sub-system */
1797 ret = uart_add_one_port(&mpc52xx_uart_driver, port);
1801 platform_set_drvdata(op, (void *)port);
1806 mpc52xx_uart_of_remove(struct platform_device *op)
1808 struct uart_port *port = platform_get_drvdata(op);
1811 uart_remove_one_port(&mpc52xx_uart_driver, port);
1818 mpc52xx_uart_of_suspend(struct platform_device *op, pm_message_t state)
1820 struct uart_port *port = platform_get_drvdata(op);
1823 uart_suspend_port(&mpc52xx_uart_driver, port);
1829 mpc52xx_uart_of_resume(struct platform_device *op)
1831 struct uart_port *port = platform_get_drvdata(op);
1834 uart_resume_port(&mpc52xx_uart_driver, port);
1841 mpc52xx_uart_of_assign(struct device_node *np)
1845 /* Find the first free PSC number */
1846 for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) {
1847 if (mpc52xx_uart_nodes[i] == NULL) {
1849 mpc52xx_uart_nodes[i] = np;
1856 mpc52xx_uart_of_enumerate(void)
1858 static int enum_done;
1859 struct device_node *np;
1860 const struct of_device_id *match;
1866 /* Assign index to each PSC in device tree */
1867 for_each_matching_node(np, mpc52xx_uart_of_match) {
1868 match = of_match_node(mpc52xx_uart_of_match, np);
1869 psc_ops = match->data;
1870 mpc52xx_uart_of_assign(np);
1875 for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) {
1876 if (mpc52xx_uart_nodes[i])
1877 pr_debug("%s assigned to ttyPSC%x\n",
1878 mpc52xx_uart_nodes[i]->full_name, i);
1882 MODULE_DEVICE_TABLE(of, mpc52xx_uart_of_match);
1884 static struct platform_driver mpc52xx_uart_of_driver = {
1885 .probe = mpc52xx_uart_of_probe,
1886 .remove = mpc52xx_uart_of_remove,
1888 .suspend = mpc52xx_uart_of_suspend,
1889 .resume = mpc52xx_uart_of_resume,
1892 .name = "mpc52xx-psc-uart",
1893 .of_match_table = mpc52xx_uart_of_match,
1898 /* ======================================================================== */
1900 /* ======================================================================== */
1903 mpc52xx_uart_init(void)
1907 printk(KERN_INFO "Serial: MPC52xx PSC UART driver\n");
1909 ret = uart_register_driver(&mpc52xx_uart_driver);
1911 printk(KERN_ERR "%s: uart_register_driver failed (%i)\n",
1916 mpc52xx_uart_of_enumerate();
1919 * Map the PSC FIFO Controller and init if on MPC512x.
1921 if (psc_ops && psc_ops->fifoc_init) {
1922 ret = psc_ops->fifoc_init();
1927 ret = platform_driver_register(&mpc52xx_uart_of_driver);
1929 printk(KERN_ERR "%s: platform_driver_register failed (%i)\n",
1936 if (psc_ops && psc_ops->fifoc_uninit)
1937 psc_ops->fifoc_uninit();
1939 uart_unregister_driver(&mpc52xx_uart_driver);
1944 mpc52xx_uart_exit(void)
1946 if (psc_ops->fifoc_uninit)
1947 psc_ops->fifoc_uninit();
1949 platform_driver_unregister(&mpc52xx_uart_of_driver);
1950 uart_unregister_driver(&mpc52xx_uart_driver);
1954 module_init(mpc52xx_uart_init);
1955 module_exit(mpc52xx_uart_exit);
1957 MODULE_AUTHOR("Sylvain Munaut <tnt@246tNt.com>");
1958 MODULE_DESCRIPTION("Freescale MPC52xx PSC UART");
1959 MODULE_LICENSE("GPL");