2 * Driver for msm7k serial device and console
4 * Copyright (C) 2007 Google, Inc.
5 * Author: Robert Love <rlove@google.com>
6 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #if defined(CONFIG_SERIAL_MSM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
19 # define SUPPORT_SYSRQ
22 #include <linux/atomic.h>
23 #include <linux/hrtimer.h>
24 #include <linux/module.h>
26 #include <linux/ioport.h>
27 #include <linux/irq.h>
28 #include <linux/init.h>
29 #include <linux/console.h>
30 #include <linux/tty.h>
31 #include <linux/tty_flip.h>
32 #include <linux/serial_core.h>
33 #include <linux/serial.h>
34 #include <linux/clk.h>
35 #include <linux/platform_device.h>
36 #include <linux/delay.h>
38 #include <linux/of_device.h>
40 #include "msm_serial.h"
50 struct uart_port uart;
56 unsigned int old_snap_state;
59 static inline void wait_for_xmitr(struct uart_port *port)
61 while (!(msm_read(port, UART_SR) & UART_SR_TX_EMPTY)) {
62 if (msm_read(port, UART_ISR) & UART_ISR_TX_READY)
66 msm_write(port, UART_CR_CMD_RESET_TX_READY, UART_CR);
69 static void msm_stop_tx(struct uart_port *port)
71 struct msm_port *msm_port = UART_TO_MSM(port);
73 msm_port->imr &= ~UART_IMR_TXLEV;
74 msm_write(port, msm_port->imr, UART_IMR);
77 static void msm_start_tx(struct uart_port *port)
79 struct msm_port *msm_port = UART_TO_MSM(port);
81 msm_port->imr |= UART_IMR_TXLEV;
82 msm_write(port, msm_port->imr, UART_IMR);
85 static void msm_stop_rx(struct uart_port *port)
87 struct msm_port *msm_port = UART_TO_MSM(port);
89 msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE);
90 msm_write(port, msm_port->imr, UART_IMR);
93 static void msm_enable_ms(struct uart_port *port)
95 struct msm_port *msm_port = UART_TO_MSM(port);
97 msm_port->imr |= UART_IMR_DELTA_CTS;
98 msm_write(port, msm_port->imr, UART_IMR);
101 static void handle_rx_dm(struct uart_port *port, unsigned int misr)
103 struct tty_port *tport = &port->state->port;
106 struct msm_port *msm_port = UART_TO_MSM(port);
108 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
109 port->icount.overrun++;
110 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
111 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
114 if (misr & UART_IMR_RXSTALE) {
115 count = msm_read(port, UARTDM_RX_TOTAL_SNAP) -
116 msm_port->old_snap_state;
117 msm_port->old_snap_state = 0;
119 count = 4 * (msm_read(port, UART_RFWR));
120 msm_port->old_snap_state += count;
123 /* TODO: Precise error reporting */
125 port->icount.rx += count;
128 unsigned char buf[4];
130 sr = msm_read(port, UART_SR);
131 if ((sr & UART_SR_RX_READY) == 0) {
132 msm_port->old_snap_state -= count;
135 ioread32_rep(port->membase + UARTDM_RF, buf, 1);
136 if (sr & UART_SR_RX_BREAK) {
138 if (uart_handle_break(port))
140 } else if (sr & UART_SR_PAR_FRAME_ERR)
141 port->icount.frame++;
143 /* TODO: handle sysrq */
144 tty_insert_flip_string(tport, buf, min(count, 4));
148 spin_unlock(&port->lock);
149 tty_flip_buffer_push(tport);
150 spin_lock(&port->lock);
152 if (misr & (UART_IMR_RXSTALE))
153 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
154 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
155 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
158 static void handle_rx(struct uart_port *port)
160 struct tty_port *tport = &port->state->port;
164 * Handle overrun. My understanding of the hardware is that overrun
165 * is not tied to the RX buffer, so we handle the case out of band.
167 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
168 port->icount.overrun++;
169 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
170 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
173 /* and now the main RX loop */
174 while ((sr = msm_read(port, UART_SR)) & UART_SR_RX_READY) {
176 char flag = TTY_NORMAL;
178 c = msm_read(port, UART_RF);
180 if (sr & UART_SR_RX_BREAK) {
182 if (uart_handle_break(port))
184 } else if (sr & UART_SR_PAR_FRAME_ERR) {
185 port->icount.frame++;
190 /* Mask conditions we're ignorning. */
191 sr &= port->read_status_mask;
193 if (sr & UART_SR_RX_BREAK) {
195 } else if (sr & UART_SR_PAR_FRAME_ERR) {
199 if (!uart_handle_sysrq_char(port, c))
200 tty_insert_flip_char(tport, c, flag);
203 spin_unlock(&port->lock);
204 tty_flip_buffer_push(tport);
205 spin_lock(&port->lock);
208 static void reset_dm_count(struct uart_port *port, int count)
210 wait_for_xmitr(port);
211 msm_write(port, count, UARTDM_NCF_TX);
212 msm_read(port, UARTDM_NCF_TX);
215 static void handle_tx(struct uart_port *port)
217 struct circ_buf *xmit = &port->state->xmit;
218 struct msm_port *msm_port = UART_TO_MSM(port);
219 unsigned int tx_count, num_chars;
220 unsigned int tf_pointer = 0;
223 if (msm_port->is_uartdm)
224 tf = port->membase + UARTDM_TF;
226 tf = port->membase + UART_TF;
228 tx_count = uart_circ_chars_pending(xmit);
229 tx_count = min3(tx_count, (unsigned int)UART_XMIT_SIZE - xmit->tail,
233 if (msm_port->is_uartdm)
234 reset_dm_count(port, tx_count + 1);
236 iowrite8_rep(tf, &port->x_char, 1);
239 } else if (tx_count && msm_port->is_uartdm) {
240 reset_dm_count(port, tx_count);
243 while (tf_pointer < tx_count) {
247 if (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
250 if (msm_port->is_uartdm)
251 num_chars = min(tx_count - tf_pointer,
252 (unsigned int)sizeof(buf));
256 for (i = 0; i < num_chars; i++) {
257 buf[i] = xmit->buf[xmit->tail + i];
261 iowrite32_rep(tf, buf, 1);
262 xmit->tail = (xmit->tail + num_chars) & (UART_XMIT_SIZE - 1);
263 tf_pointer += num_chars;
266 /* disable tx interrupts if nothing more to send */
267 if (uart_circ_empty(xmit))
270 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
271 uart_write_wakeup(port);
274 static void handle_delta_cts(struct uart_port *port)
276 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
278 wake_up_interruptible(&port->state->port.delta_msr_wait);
281 static irqreturn_t msm_irq(int irq, void *dev_id)
283 struct uart_port *port = dev_id;
284 struct msm_port *msm_port = UART_TO_MSM(port);
287 spin_lock(&port->lock);
288 misr = msm_read(port, UART_MISR);
289 msm_write(port, 0, UART_IMR); /* disable interrupt */
291 if (misr & (UART_IMR_RXLEV | UART_IMR_RXSTALE)) {
292 if (msm_port->is_uartdm)
293 handle_rx_dm(port, misr);
297 if (misr & UART_IMR_TXLEV)
299 if (misr & UART_IMR_DELTA_CTS)
300 handle_delta_cts(port);
302 msm_write(port, msm_port->imr, UART_IMR); /* restore interrupt */
303 spin_unlock(&port->lock);
308 static unsigned int msm_tx_empty(struct uart_port *port)
310 return (msm_read(port, UART_SR) & UART_SR_TX_EMPTY) ? TIOCSER_TEMT : 0;
313 static unsigned int msm_get_mctrl(struct uart_port *port)
315 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR | TIOCM_RTS;
319 static void msm_reset(struct uart_port *port)
321 struct msm_port *msm_port = UART_TO_MSM(port);
323 /* reset everything */
324 msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);
325 msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);
326 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
327 msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR);
328 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
329 msm_write(port, UART_CR_CMD_SET_RFR, UART_CR);
331 /* Disable DM modes */
332 if (msm_port->is_uartdm)
333 msm_write(port, 0, UARTDM_DMEN);
336 static void msm_set_mctrl(struct uart_port *port, unsigned int mctrl)
339 mr = msm_read(port, UART_MR1);
341 if (!(mctrl & TIOCM_RTS)) {
342 mr &= ~UART_MR1_RX_RDY_CTL;
343 msm_write(port, mr, UART_MR1);
344 msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);
346 mr |= UART_MR1_RX_RDY_CTL;
347 msm_write(port, mr, UART_MR1);
351 static void msm_break_ctl(struct uart_port *port, int break_ctl)
354 msm_write(port, UART_CR_CMD_START_BREAK, UART_CR);
356 msm_write(port, UART_CR_CMD_STOP_BREAK, UART_CR);
359 struct msm_baud_map {
365 static const struct msm_baud_map *
366 msm_find_best_baud(struct uart_port *port, unsigned int baud)
368 unsigned int i, divisor;
369 const struct msm_baud_map *entry;
370 static const struct msm_baud_map table[] = {
389 divisor = uart_get_divisor(port, baud);
391 for (i = 0, entry = table; i < ARRAY_SIZE(table); i++, entry++)
392 if (entry->divisor <= divisor)
395 return entry; /* Default to smallest divider */
398 static int msm_set_baud_rate(struct uart_port *port, unsigned int baud)
400 unsigned int rxstale, watermark;
401 struct msm_port *msm_port = UART_TO_MSM(port);
402 const struct msm_baud_map *entry;
404 entry = msm_find_best_baud(port, baud);
406 if (msm_port->is_uartdm)
407 msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);
409 msm_write(port, entry->code, UART_CSR);
411 /* RX stale watermark */
412 rxstale = entry->rxstale;
413 watermark = UART_IPR_STALE_LSB & rxstale;
414 watermark |= UART_IPR_RXSTALE_LAST;
415 watermark |= UART_IPR_STALE_TIMEOUT_MSB & (rxstale << 2);
416 msm_write(port, watermark, UART_IPR);
418 /* set RX watermark */
419 watermark = (port->fifosize * 3) / 4;
420 msm_write(port, watermark, UART_RFWR);
422 /* set TX watermark */
423 msm_write(port, 10, UART_TFWR);
425 if (msm_port->is_uartdm) {
426 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
427 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
428 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
435 static void msm_init_clock(struct uart_port *port)
437 struct msm_port *msm_port = UART_TO_MSM(port);
439 clk_prepare_enable(msm_port->clk);
440 clk_prepare_enable(msm_port->pclk);
441 msm_serial_set_mnd_regs(port);
444 static int msm_startup(struct uart_port *port)
446 struct msm_port *msm_port = UART_TO_MSM(port);
447 unsigned int data, rfr_level;
450 snprintf(msm_port->name, sizeof(msm_port->name),
451 "msm_serial%d", port->line);
453 ret = request_irq(port->irq, msm_irq, IRQF_TRIGGER_HIGH,
454 msm_port->name, port);
458 msm_init_clock(port);
460 if (likely(port->fifosize > 12))
461 rfr_level = port->fifosize - 12;
463 rfr_level = port->fifosize;
465 /* set automatic RFR level */
466 data = msm_read(port, UART_MR1);
467 data &= ~UART_MR1_AUTO_RFR_LEVEL1;
468 data &= ~UART_MR1_AUTO_RFR_LEVEL0;
469 data |= UART_MR1_AUTO_RFR_LEVEL1 & (rfr_level << 2);
470 data |= UART_MR1_AUTO_RFR_LEVEL0 & rfr_level;
471 msm_write(port, data, UART_MR1);
473 /* make sure that RXSTALE count is non-zero */
474 data = msm_read(port, UART_IPR);
475 if (unlikely(!data)) {
476 data |= UART_IPR_RXSTALE_LAST;
477 data |= UART_IPR_STALE_LSB;
478 msm_write(port, data, UART_IPR);
482 if (!port->cons || (port->cons && !(port->cons->flags & CON_ENABLED))) {
483 msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);
485 data = UART_CR_TX_ENABLE;
488 data |= UART_CR_RX_ENABLE;
489 msm_write(port, data, UART_CR); /* enable TX & RX */
491 /* Make sure IPR is not 0 to start with*/
492 if (msm_port->is_uartdm)
493 msm_write(port, UART_IPR_STALE_LSB, UART_IPR);
495 /* turn on RX and CTS interrupts */
496 msm_port->imr = UART_IMR_RXLEV | UART_IMR_RXSTALE |
497 UART_IMR_CURRENT_CTS;
499 if (msm_port->is_uartdm) {
500 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
501 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
502 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
505 msm_write(port, msm_port->imr, UART_IMR);
509 static void msm_shutdown(struct uart_port *port)
511 struct msm_port *msm_port = UART_TO_MSM(port);
514 msm_write(port, 0, UART_IMR); /* disable interrupts */
516 clk_disable_unprepare(msm_port->clk);
518 free_irq(port->irq, port);
521 static void msm_set_termios(struct uart_port *port, struct ktermios *termios,
522 struct ktermios *old)
525 unsigned int baud, mr;
527 spin_lock_irqsave(&port->lock, flags);
529 /* calculate and set baud rate */
530 baud = uart_get_baud_rate(port, termios, old, 300, 115200);
531 baud = msm_set_baud_rate(port, baud);
532 if (tty_termios_baud_rate(termios))
533 tty_termios_encode_baud_rate(termios, baud, baud);
535 /* calculate parity */
536 mr = msm_read(port, UART_MR2);
537 mr &= ~UART_MR2_PARITY_MODE;
538 if (termios->c_cflag & PARENB) {
539 if (termios->c_cflag & PARODD)
540 mr |= UART_MR2_PARITY_MODE_ODD;
541 else if (termios->c_cflag & CMSPAR)
542 mr |= UART_MR2_PARITY_MODE_SPACE;
544 mr |= UART_MR2_PARITY_MODE_EVEN;
547 /* calculate bits per char */
548 mr &= ~UART_MR2_BITS_PER_CHAR;
549 switch (termios->c_cflag & CSIZE) {
551 mr |= UART_MR2_BITS_PER_CHAR_5;
554 mr |= UART_MR2_BITS_PER_CHAR_6;
557 mr |= UART_MR2_BITS_PER_CHAR_7;
561 mr |= UART_MR2_BITS_PER_CHAR_8;
565 /* calculate stop bits */
566 mr &= ~(UART_MR2_STOP_BIT_LEN_ONE | UART_MR2_STOP_BIT_LEN_TWO);
567 if (termios->c_cflag & CSTOPB)
568 mr |= UART_MR2_STOP_BIT_LEN_TWO;
570 mr |= UART_MR2_STOP_BIT_LEN_ONE;
572 /* set parity, bits per char, and stop bit */
573 msm_write(port, mr, UART_MR2);
575 /* calculate and set hardware flow control */
576 mr = msm_read(port, UART_MR1);
577 mr &= ~(UART_MR1_CTS_CTL | UART_MR1_RX_RDY_CTL);
578 if (termios->c_cflag & CRTSCTS) {
579 mr |= UART_MR1_CTS_CTL;
580 mr |= UART_MR1_RX_RDY_CTL;
582 msm_write(port, mr, UART_MR1);
584 /* Configure status bits to ignore based on termio flags. */
585 port->read_status_mask = 0;
586 if (termios->c_iflag & INPCK)
587 port->read_status_mask |= UART_SR_PAR_FRAME_ERR;
588 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
589 port->read_status_mask |= UART_SR_RX_BREAK;
591 uart_update_timeout(port, termios->c_cflag, baud);
593 spin_unlock_irqrestore(&port->lock, flags);
596 static const char *msm_type(struct uart_port *port)
601 static void msm_release_port(struct uart_port *port)
603 struct platform_device *pdev = to_platform_device(port->dev);
604 struct resource *uart_resource;
605 resource_size_t size;
607 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
608 if (unlikely(!uart_resource))
610 size = resource_size(uart_resource);
612 release_mem_region(port->mapbase, size);
613 iounmap(port->membase);
614 port->membase = NULL;
617 static int msm_request_port(struct uart_port *port)
619 struct platform_device *pdev = to_platform_device(port->dev);
620 struct resource *uart_resource;
621 resource_size_t size;
624 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
625 if (unlikely(!uart_resource))
628 size = resource_size(uart_resource);
630 if (!request_mem_region(port->mapbase, size, "msm_serial"))
633 port->membase = ioremap(port->mapbase, size);
634 if (!port->membase) {
636 goto fail_release_port;
642 release_mem_region(port->mapbase, size);
646 static void msm_config_port(struct uart_port *port, int flags)
649 if (flags & UART_CONFIG_TYPE) {
650 port->type = PORT_MSM;
651 ret = msm_request_port(port);
657 static int msm_verify_port(struct uart_port *port, struct serial_struct *ser)
659 if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_MSM))
661 if (unlikely(port->irq != ser->irq))
666 static void msm_power(struct uart_port *port, unsigned int state,
667 unsigned int oldstate)
669 struct msm_port *msm_port = UART_TO_MSM(port);
673 clk_prepare_enable(msm_port->clk);
674 clk_prepare_enable(msm_port->pclk);
677 clk_disable_unprepare(msm_port->clk);
678 clk_disable_unprepare(msm_port->pclk);
681 printk(KERN_ERR "msm_serial: Unknown PM state %d\n", state);
685 #ifdef CONFIG_CONSOLE_POLL
686 static int msm_poll_init(struct uart_port *port)
688 struct msm_port *msm_port = UART_TO_MSM(port);
690 /* Enable single character mode on RX FIFO */
691 if (msm_port->is_uartdm >= UARTDM_1P4)
692 msm_write(port, UARTDM_DMEN_RX_SC_ENABLE, UARTDM_DMEN);
697 static int msm_poll_get_char_single(struct uart_port *port)
699 struct msm_port *msm_port = UART_TO_MSM(port);
700 unsigned int rf_reg = msm_port->is_uartdm ? UARTDM_RF : UART_RF;
702 if (!(msm_read(port, UART_SR) & UART_SR_RX_READY))
705 return msm_read(port, rf_reg) & 0xff;
708 static int msm_poll_get_char_dm_1p3(struct uart_port *port)
713 unsigned char *sp = (unsigned char *)&slop;
715 /* Check if a previous read had more than one char */
717 c = sp[sizeof(slop) - count];
719 /* Or if FIFO is empty */
720 } else if (!(msm_read(port, UART_SR) & UART_SR_RX_READY)) {
722 * If RX packing buffer has less than a word, force stale to
723 * push contents into RX FIFO
725 count = msm_read(port, UARTDM_RXFS);
726 count = (count >> UARTDM_RXFS_BUF_SHIFT) & UARTDM_RXFS_BUF_MASK;
728 msm_write(port, UART_CR_CMD_FORCE_STALE, UART_CR);
729 slop = msm_read(port, UARTDM_RF);
735 /* FIFO has a word */
737 slop = msm_read(port, UARTDM_RF);
739 count = sizeof(slop) - 1;
745 static int msm_poll_get_char(struct uart_port *port)
749 struct msm_port *msm_port = UART_TO_MSM(port);
751 /* Disable all interrupts */
752 imr = msm_read(port, UART_IMR);
753 msm_write(port, 0, UART_IMR);
755 if (msm_port->is_uartdm == UARTDM_1P3)
756 c = msm_poll_get_char_dm_1p3(port);
758 c = msm_poll_get_char_single(port);
760 /* Enable interrupts */
761 msm_write(port, imr, UART_IMR);
766 static void msm_poll_put_char(struct uart_port *port, unsigned char c)
769 struct msm_port *msm_port = UART_TO_MSM(port);
771 /* Disable all interrupts */
772 imr = msm_read(port, UART_IMR);
773 msm_write(port, 0, UART_IMR);
775 if (msm_port->is_uartdm)
776 reset_dm_count(port, 1);
778 /* Wait until FIFO is empty */
779 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
782 /* Write a character */
783 msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : UART_TF);
785 /* Wait until FIFO is empty */
786 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
789 /* Enable interrupts */
790 msm_write(port, imr, UART_IMR);
796 static struct uart_ops msm_uart_pops = {
797 .tx_empty = msm_tx_empty,
798 .set_mctrl = msm_set_mctrl,
799 .get_mctrl = msm_get_mctrl,
800 .stop_tx = msm_stop_tx,
801 .start_tx = msm_start_tx,
802 .stop_rx = msm_stop_rx,
803 .enable_ms = msm_enable_ms,
804 .break_ctl = msm_break_ctl,
805 .startup = msm_startup,
806 .shutdown = msm_shutdown,
807 .set_termios = msm_set_termios,
809 .release_port = msm_release_port,
810 .request_port = msm_request_port,
811 .config_port = msm_config_port,
812 .verify_port = msm_verify_port,
814 #ifdef CONFIG_CONSOLE_POLL
815 .poll_init = msm_poll_init,
816 .poll_get_char = msm_poll_get_char,
817 .poll_put_char = msm_poll_put_char,
821 static struct msm_port msm_uart_ports[] = {
825 .ops = &msm_uart_pops,
826 .flags = UPF_BOOT_AUTOCONF,
834 .ops = &msm_uart_pops,
835 .flags = UPF_BOOT_AUTOCONF,
843 .ops = &msm_uart_pops,
844 .flags = UPF_BOOT_AUTOCONF,
851 #define UART_NR ARRAY_SIZE(msm_uart_ports)
853 static inline struct uart_port *get_port_from_line(unsigned int line)
855 return &msm_uart_ports[line].uart;
858 #ifdef CONFIG_SERIAL_MSM_CONSOLE
859 static void msm_console_write(struct console *co, const char *s,
863 struct uart_port *port;
864 struct msm_port *msm_port;
865 int num_newlines = 0;
866 bool replaced = false;
869 BUG_ON(co->index < 0 || co->index >= UART_NR);
871 port = get_port_from_line(co->index);
872 msm_port = UART_TO_MSM(port);
874 if (msm_port->is_uartdm)
875 tf = port->membase + UARTDM_TF;
877 tf = port->membase + UART_TF;
879 /* Account for newlines that will get a carriage return added */
880 for (i = 0; i < count; i++)
883 count += num_newlines;
885 spin_lock(&port->lock);
886 if (msm_port->is_uartdm)
887 reset_dm_count(port, count);
892 unsigned int num_chars;
895 if (msm_port->is_uartdm)
896 num_chars = min(count - i, (unsigned int)sizeof(buf));
900 for (j = 0; j < num_chars; j++) {
903 if (c == '\n' && !replaced) {
915 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
918 iowrite32_rep(tf, buf, 1);
921 spin_unlock(&port->lock);
924 static int __init msm_console_setup(struct console *co, char *options)
926 struct uart_port *port;
927 struct msm_port *msm_port;
928 int baud = 0, flow, bits, parity;
930 if (unlikely(co->index >= UART_NR || co->index < 0))
933 port = get_port_from_line(co->index);
934 msm_port = UART_TO_MSM(port);
936 if (unlikely(!port->membase))
939 msm_init_clock(port);
942 uart_parse_options(options, &baud, &parity, &bits, &flow);
947 msm_write(port, UART_MR2_BITS_PER_CHAR_8 | UART_MR2_STOP_BIT_LEN_ONE,
950 if (baud < 300 || baud > 115200)
952 msm_set_baud_rate(port, baud);
956 if (msm_port->is_uartdm) {
957 msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);
958 msm_write(port, UART_CR_TX_ENABLE, UART_CR);
961 printk(KERN_INFO "msm_serial: console setup on port #%d\n", port->line);
963 return uart_set_options(port, co, baud, parity, bits, flow);
966 static struct uart_driver msm_uart_driver;
968 static struct console msm_console = {
970 .write = msm_console_write,
971 .device = uart_console_device,
972 .setup = msm_console_setup,
973 .flags = CON_PRINTBUFFER,
975 .data = &msm_uart_driver,
978 #define MSM_CONSOLE (&msm_console)
981 #define MSM_CONSOLE NULL
984 static struct uart_driver msm_uart_driver = {
985 .owner = THIS_MODULE,
986 .driver_name = "msm_serial",
987 .dev_name = "ttyMSM",
992 static atomic_t msm_uart_next_id = ATOMIC_INIT(0);
994 static const struct of_device_id msm_uartdm_table[] = {
995 { .compatible = "qcom,msm-uartdm-v1.1", .data = (void *)UARTDM_1P1 },
996 { .compatible = "qcom,msm-uartdm-v1.2", .data = (void *)UARTDM_1P2 },
997 { .compatible = "qcom,msm-uartdm-v1.3", .data = (void *)UARTDM_1P3 },
998 { .compatible = "qcom,msm-uartdm-v1.4", .data = (void *)UARTDM_1P4 },
1002 static int msm_serial_probe(struct platform_device *pdev)
1004 struct msm_port *msm_port;
1005 struct resource *resource;
1006 struct uart_port *port;
1007 const struct of_device_id *id;
1011 pdev->id = atomic_inc_return(&msm_uart_next_id) - 1;
1013 if (unlikely(pdev->id < 0 || pdev->id >= UART_NR))
1016 printk(KERN_INFO "msm_serial: detected port #%d\n", pdev->id);
1018 port = get_port_from_line(pdev->id);
1019 port->dev = &pdev->dev;
1020 msm_port = UART_TO_MSM(port);
1022 id = of_match_device(msm_uartdm_table, &pdev->dev);
1024 msm_port->is_uartdm = (unsigned long)id->data;
1026 msm_port->is_uartdm = 0;
1028 msm_port->clk = devm_clk_get(&pdev->dev, "core");
1029 if (IS_ERR(msm_port->clk))
1030 return PTR_ERR(msm_port->clk);
1032 if (msm_port->is_uartdm) {
1033 msm_port->pclk = devm_clk_get(&pdev->dev, "iface");
1034 if (IS_ERR(msm_port->pclk))
1035 return PTR_ERR(msm_port->pclk);
1037 clk_set_rate(msm_port->clk, 1843200);
1040 port->uartclk = clk_get_rate(msm_port->clk);
1041 printk(KERN_INFO "uartclk = %d\n", port->uartclk);
1044 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1045 if (unlikely(!resource))
1047 port->mapbase = resource->start;
1049 irq = platform_get_irq(pdev, 0);
1050 if (unlikely(irq < 0))
1054 platform_set_drvdata(pdev, port);
1056 return uart_add_one_port(&msm_uart_driver, port);
1059 static int msm_serial_remove(struct platform_device *pdev)
1061 struct uart_port *port = platform_get_drvdata(pdev);
1063 uart_remove_one_port(&msm_uart_driver, port);
1068 static const struct of_device_id msm_match_table[] = {
1069 { .compatible = "qcom,msm-uart" },
1070 { .compatible = "qcom,msm-uartdm" },
1074 static struct platform_driver msm_platform_driver = {
1075 .remove = msm_serial_remove,
1076 .probe = msm_serial_probe,
1078 .name = "msm_serial",
1079 .owner = THIS_MODULE,
1080 .of_match_table = msm_match_table,
1084 static int __init msm_serial_init(void)
1088 ret = uart_register_driver(&msm_uart_driver);
1092 ret = platform_driver_register(&msm_platform_driver);
1094 uart_unregister_driver(&msm_uart_driver);
1096 printk(KERN_INFO "msm_serial: driver initialized\n");
1101 static void __exit msm_serial_exit(void)
1103 #ifdef CONFIG_SERIAL_MSM_CONSOLE
1104 unregister_console(&msm_console);
1106 platform_driver_unregister(&msm_platform_driver);
1107 uart_unregister_driver(&msm_uart_driver);
1110 module_init(msm_serial_init);
1111 module_exit(msm_serial_exit);
1113 MODULE_AUTHOR("Robert Love <rlove@google.com>");
1114 MODULE_DESCRIPTION("Driver for msm7x serial device");
1115 MODULE_LICENSE("GPL");