2 * Freescale STMP37XX/STMP378X Application UART driver
4 * Author: dmitry pervushin <dimka@embeddedalley.com>
6 * Copyright 2008-2010 Freescale Semiconductor, Inc.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
17 #if defined(CONFIG_SERIAL_MXS_AUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21 #include <linux/kernel.h>
22 #include <linux/errno.h>
23 #include <linux/init.h>
24 #include <linux/console.h>
25 #include <linux/interrupt.h>
26 #include <linux/module.h>
27 #include <linux/slab.h>
28 #include <linux/wait.h>
29 #include <linux/tty.h>
30 #include <linux/tty_driver.h>
31 #include <linux/tty_flip.h>
32 #include <linux/serial.h>
33 #include <linux/serial_core.h>
34 #include <linux/platform_device.h>
35 #include <linux/device.h>
36 #include <linux/clk.h>
37 #include <linux/delay.h>
39 #include <linux/of_device.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/dmaengine.h>
43 #include <asm/cacheflush.h>
45 #include <linux/gpio.h>
46 #include <linux/gpio/consumer.h>
47 #include <linux/err.h>
48 #include <linux/irq.h>
49 #include "serial_mctrl_gpio.h"
51 #define MXS_AUART_PORTS 5
52 #define MXS_AUART_FIFO_SIZE 16
54 #define AUART_CTRL0 0x00000000
55 #define AUART_CTRL0_SET 0x00000004
56 #define AUART_CTRL0_CLR 0x00000008
57 #define AUART_CTRL0_TOG 0x0000000c
58 #define AUART_CTRL1 0x00000010
59 #define AUART_CTRL1_SET 0x00000014
60 #define AUART_CTRL1_CLR 0x00000018
61 #define AUART_CTRL1_TOG 0x0000001c
62 #define AUART_CTRL2 0x00000020
63 #define AUART_CTRL2_SET 0x00000024
64 #define AUART_CTRL2_CLR 0x00000028
65 #define AUART_CTRL2_TOG 0x0000002c
66 #define AUART_LINECTRL 0x00000030
67 #define AUART_LINECTRL_SET 0x00000034
68 #define AUART_LINECTRL_CLR 0x00000038
69 #define AUART_LINECTRL_TOG 0x0000003c
70 #define AUART_LINECTRL2 0x00000040
71 #define AUART_LINECTRL2_SET 0x00000044
72 #define AUART_LINECTRL2_CLR 0x00000048
73 #define AUART_LINECTRL2_TOG 0x0000004c
74 #define AUART_INTR 0x00000050
75 #define AUART_INTR_SET 0x00000054
76 #define AUART_INTR_CLR 0x00000058
77 #define AUART_INTR_TOG 0x0000005c
78 #define AUART_DATA 0x00000060
79 #define AUART_STAT 0x00000070
80 #define AUART_DEBUG 0x00000080
81 #define AUART_VERSION 0x00000090
82 #define AUART_AUTOBAUD 0x000000a0
84 #define AUART_CTRL0_SFTRST (1 << 31)
85 #define AUART_CTRL0_CLKGATE (1 << 30)
86 #define AUART_CTRL0_RXTO_ENABLE (1 << 27)
87 #define AUART_CTRL0_RXTIMEOUT(v) (((v) & 0x7ff) << 16)
88 #define AUART_CTRL0_XFER_COUNT(v) ((v) & 0xffff)
90 #define AUART_CTRL1_XFER_COUNT(v) ((v) & 0xffff)
92 #define AUART_CTRL2_DMAONERR (1 << 26)
93 #define AUART_CTRL2_TXDMAE (1 << 25)
94 #define AUART_CTRL2_RXDMAE (1 << 24)
96 #define AUART_CTRL2_CTSEN (1 << 15)
97 #define AUART_CTRL2_RTSEN (1 << 14)
98 #define AUART_CTRL2_RTS (1 << 11)
99 #define AUART_CTRL2_RXE (1 << 9)
100 #define AUART_CTRL2_TXE (1 << 8)
101 #define AUART_CTRL2_UARTEN (1 << 0)
103 #define AUART_LINECTRL_BAUD_DIVINT_SHIFT 16
104 #define AUART_LINECTRL_BAUD_DIVINT_MASK 0xffff0000
105 #define AUART_LINECTRL_BAUD_DIVINT(v) (((v) & 0xffff) << 16)
106 #define AUART_LINECTRL_BAUD_DIVFRAC_SHIFT 8
107 #define AUART_LINECTRL_BAUD_DIVFRAC_MASK 0x00003f00
108 #define AUART_LINECTRL_BAUD_DIVFRAC(v) (((v) & 0x3f) << 8)
109 #define AUART_LINECTRL_WLEN_MASK 0x00000060
110 #define AUART_LINECTRL_WLEN(v) (((v) & 0x3) << 5)
111 #define AUART_LINECTRL_FEN (1 << 4)
112 #define AUART_LINECTRL_STP2 (1 << 3)
113 #define AUART_LINECTRL_EPS (1 << 2)
114 #define AUART_LINECTRL_PEN (1 << 1)
115 #define AUART_LINECTRL_BRK (1 << 0)
117 #define AUART_INTR_RTIEN (1 << 22)
118 #define AUART_INTR_TXIEN (1 << 21)
119 #define AUART_INTR_RXIEN (1 << 20)
120 #define AUART_INTR_CTSMIEN (1 << 17)
121 #define AUART_INTR_RTIS (1 << 6)
122 #define AUART_INTR_TXIS (1 << 5)
123 #define AUART_INTR_RXIS (1 << 4)
124 #define AUART_INTR_CTSMIS (1 << 1)
126 #define AUART_STAT_BUSY (1 << 29)
127 #define AUART_STAT_CTS (1 << 28)
128 #define AUART_STAT_TXFE (1 << 27)
129 #define AUART_STAT_TXFF (1 << 25)
130 #define AUART_STAT_RXFE (1 << 24)
131 #define AUART_STAT_OERR (1 << 19)
132 #define AUART_STAT_BERR (1 << 18)
133 #define AUART_STAT_PERR (1 << 17)
134 #define AUART_STAT_FERR (1 << 16)
135 #define AUART_STAT_RXCOUNT_MASK 0xffff
137 static struct uart_driver auart_driver;
139 enum mxs_auart_type {
144 struct mxs_auart_port {
145 struct uart_port port;
147 #define MXS_AUART_DMA_ENABLED 0x2
148 #define MXS_AUART_DMA_TX_SYNC 2 /* bit 2 */
149 #define MXS_AUART_DMA_RX_READY 3 /* bit 3 */
150 #define MXS_AUART_RTSCTS 4 /* bit 4 */
152 unsigned int mctrl_prev;
153 enum mxs_auart_type devtype;
161 struct scatterlist tx_sgl;
162 struct dma_chan *tx_dma_chan;
165 struct scatterlist rx_sgl;
166 struct dma_chan *rx_dma_chan;
169 struct mctrl_gpios *gpios;
170 int gpio_irq[UART_GPIO_MAX];
174 static struct platform_device_id mxs_auart_devtype[] = {
175 { .name = "mxs-auart-imx23", .driver_data = IMX23_AUART },
176 { .name = "mxs-auart-imx28", .driver_data = IMX28_AUART },
179 MODULE_DEVICE_TABLE(platform, mxs_auart_devtype);
181 static struct of_device_id mxs_auart_dt_ids[] = {
183 .compatible = "fsl,imx28-auart",
184 .data = &mxs_auart_devtype[IMX28_AUART]
186 .compatible = "fsl,imx23-auart",
187 .data = &mxs_auart_devtype[IMX23_AUART]
188 }, { /* sentinel */ }
190 MODULE_DEVICE_TABLE(of, mxs_auart_dt_ids);
192 static inline int is_imx28_auart(struct mxs_auart_port *s)
194 return s->devtype == IMX28_AUART;
197 static inline bool auart_dma_enabled(struct mxs_auart_port *s)
199 return s->flags & MXS_AUART_DMA_ENABLED;
202 static void mxs_auart_stop_tx(struct uart_port *u);
204 #define to_auart_port(u) container_of(u, struct mxs_auart_port, port)
206 static void mxs_auart_tx_chars(struct mxs_auart_port *s);
208 static void dma_tx_callback(void *param)
210 struct mxs_auart_port *s = param;
211 struct circ_buf *xmit = &s->port.state->xmit;
213 dma_unmap_sg(s->dev, &s->tx_sgl, 1, DMA_TO_DEVICE);
215 /* clear the bit used to serialize the DMA tx. */
216 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
217 smp_mb__after_atomic();
219 /* wake up the possible processes. */
220 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
221 uart_write_wakeup(&s->port);
223 mxs_auart_tx_chars(s);
226 static int mxs_auart_dma_tx(struct mxs_auart_port *s, int size)
228 struct dma_async_tx_descriptor *desc;
229 struct scatterlist *sgl = &s->tx_sgl;
230 struct dma_chan *channel = s->tx_dma_chan;
233 /* [1] : send PIO. Note, the first pio word is CTRL1. */
234 pio = AUART_CTRL1_XFER_COUNT(size);
235 desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)&pio,
236 1, DMA_TRANS_NONE, 0);
238 dev_err(s->dev, "step 1 error\n");
242 /* [2] : set DMA buffer. */
243 sg_init_one(sgl, s->tx_dma_buf, size);
244 dma_map_sg(s->dev, sgl, 1, DMA_TO_DEVICE);
245 desc = dmaengine_prep_slave_sg(channel, sgl,
246 1, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
248 dev_err(s->dev, "step 2 error\n");
252 /* [3] : submit the DMA */
253 desc->callback = dma_tx_callback;
254 desc->callback_param = s;
255 dmaengine_submit(desc);
256 dma_async_issue_pending(channel);
260 static void mxs_auart_tx_chars(struct mxs_auart_port *s)
262 struct circ_buf *xmit = &s->port.state->xmit;
264 if (auart_dma_enabled(s)) {
267 void *buffer = s->tx_dma_buf;
269 if (test_and_set_bit(MXS_AUART_DMA_TX_SYNC, &s->flags))
272 while (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) {
273 size = min_t(u32, UART_XMIT_SIZE - i,
274 CIRC_CNT_TO_END(xmit->head,
277 memcpy(buffer + i, xmit->buf + xmit->tail, size);
278 xmit->tail = (xmit->tail + size) & (UART_XMIT_SIZE - 1);
281 if (i >= UART_XMIT_SIZE)
285 if (uart_tx_stopped(&s->port))
286 mxs_auart_stop_tx(&s->port);
289 mxs_auart_dma_tx(s, i);
291 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
292 smp_mb__after_atomic();
298 while (!(readl(s->port.membase + AUART_STAT) &
300 if (s->port.x_char) {
302 writel(s->port.x_char,
303 s->port.membase + AUART_DATA);
307 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) {
309 writel(xmit->buf[xmit->tail],
310 s->port.membase + AUART_DATA);
311 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
315 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
316 uart_write_wakeup(&s->port);
318 if (uart_circ_empty(&(s->port.state->xmit)))
319 writel(AUART_INTR_TXIEN,
320 s->port.membase + AUART_INTR_CLR);
322 writel(AUART_INTR_TXIEN,
323 s->port.membase + AUART_INTR_SET);
325 if (uart_tx_stopped(&s->port))
326 mxs_auart_stop_tx(&s->port);
329 static void mxs_auart_rx_char(struct mxs_auart_port *s)
335 c = readl(s->port.membase + AUART_DATA);
336 stat = readl(s->port.membase + AUART_STAT);
341 if (stat & AUART_STAT_BERR) {
342 s->port.icount.brk++;
343 if (uart_handle_break(&s->port))
345 } else if (stat & AUART_STAT_PERR) {
346 s->port.icount.parity++;
347 } else if (stat & AUART_STAT_FERR) {
348 s->port.icount.frame++;
352 * Mask off conditions which should be ingored.
354 stat &= s->port.read_status_mask;
356 if (stat & AUART_STAT_BERR) {
358 } else if (stat & AUART_STAT_PERR)
360 else if (stat & AUART_STAT_FERR)
363 if (stat & AUART_STAT_OERR)
364 s->port.icount.overrun++;
366 if (uart_handle_sysrq_char(&s->port, c))
369 uart_insert_char(&s->port, stat, AUART_STAT_OERR, c, flag);
371 writel(stat, s->port.membase + AUART_STAT);
374 static void mxs_auart_rx_chars(struct mxs_auart_port *s)
379 stat = readl(s->port.membase + AUART_STAT);
380 if (stat & AUART_STAT_RXFE)
382 mxs_auart_rx_char(s);
385 writel(stat, s->port.membase + AUART_STAT);
386 tty_flip_buffer_push(&s->port.state->port);
389 static int mxs_auart_request_port(struct uart_port *u)
394 static int mxs_auart_verify_port(struct uart_port *u,
395 struct serial_struct *ser)
397 if (u->type != PORT_UNKNOWN && u->type != PORT_IMX)
402 static void mxs_auart_config_port(struct uart_port *u, int flags)
406 static const char *mxs_auart_type(struct uart_port *u)
408 struct mxs_auart_port *s = to_auart_port(u);
410 return dev_name(s->dev);
413 static void mxs_auart_release_port(struct uart_port *u)
417 static void mxs_auart_set_mctrl(struct uart_port *u, unsigned mctrl)
419 struct mxs_auart_port *s = to_auart_port(u);
421 u32 ctrl = readl(u->membase + AUART_CTRL2);
423 ctrl &= ~(AUART_CTRL2_RTSEN | AUART_CTRL2_RTS);
424 if (mctrl & TIOCM_RTS) {
425 if (uart_cts_enabled(u))
426 ctrl |= AUART_CTRL2_RTSEN;
428 ctrl |= AUART_CTRL2_RTS;
431 writel(ctrl, u->membase + AUART_CTRL2);
433 mctrl_gpio_set(s->gpios, mctrl);
436 #define MCTRL_ANY_DELTA (TIOCM_RI | TIOCM_DSR | TIOCM_CD | TIOCM_CTS)
437 static u32 mxs_auart_modem_status(struct mxs_auart_port *s, u32 mctrl)
441 mctrl_diff = mctrl ^ s->mctrl_prev;
442 s->mctrl_prev = mctrl;
443 if (mctrl_diff & MCTRL_ANY_DELTA && s->ms_irq_enabled &&
444 s->port.state != NULL) {
445 if (mctrl_diff & TIOCM_RI)
446 s->port.icount.rng++;
447 if (mctrl_diff & TIOCM_DSR)
448 s->port.icount.dsr++;
449 if (mctrl_diff & TIOCM_CD)
450 uart_handle_dcd_change(&s->port, mctrl & TIOCM_CD);
451 if (mctrl_diff & TIOCM_CTS)
452 uart_handle_cts_change(&s->port, mctrl & TIOCM_CTS);
454 wake_up_interruptible(&s->port.state->port.delta_msr_wait);
459 static u32 mxs_auart_get_mctrl(struct uart_port *u)
461 struct mxs_auart_port *s = to_auart_port(u);
462 u32 stat = readl(u->membase + AUART_STAT);
465 if (stat & AUART_STAT_CTS)
468 return mctrl_gpio_get(s->gpios, &mctrl);
472 * Enable modem status interrupts
474 static void mxs_auart_enable_ms(struct uart_port *port)
476 struct mxs_auart_port *s = to_auart_port(port);
479 * Interrupt should not be enabled twice
481 if (s->ms_irq_enabled)
484 s->ms_irq_enabled = true;
486 if (s->gpio_irq[UART_GPIO_CTS] >= 0)
487 enable_irq(s->gpio_irq[UART_GPIO_CTS]);
488 /* TODO: enable AUART_INTR_CTSMIEN otherwise */
490 if (s->gpio_irq[UART_GPIO_DSR] >= 0)
491 enable_irq(s->gpio_irq[UART_GPIO_DSR]);
493 if (s->gpio_irq[UART_GPIO_RI] >= 0)
494 enable_irq(s->gpio_irq[UART_GPIO_RI]);
496 if (s->gpio_irq[UART_GPIO_DCD] >= 0)
497 enable_irq(s->gpio_irq[UART_GPIO_DCD]);
501 * Disable modem status interrupts
503 static void mxs_auart_disable_ms(struct uart_port *port)
505 struct mxs_auart_port *s = to_auart_port(port);
508 * Interrupt should not be disabled twice
510 if (!s->ms_irq_enabled)
513 s->ms_irq_enabled = false;
515 if (s->gpio_irq[UART_GPIO_CTS] >= 0)
516 disable_irq(s->gpio_irq[UART_GPIO_CTS]);
517 /* TODO: disable AUART_INTR_CTSMIEN otherwise */
519 if (s->gpio_irq[UART_GPIO_DSR] >= 0)
520 disable_irq(s->gpio_irq[UART_GPIO_DSR]);
522 if (s->gpio_irq[UART_GPIO_RI] >= 0)
523 disable_irq(s->gpio_irq[UART_GPIO_RI]);
525 if (s->gpio_irq[UART_GPIO_DCD] >= 0)
526 disable_irq(s->gpio_irq[UART_GPIO_DCD]);
529 static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s);
530 static void dma_rx_callback(void *arg)
532 struct mxs_auart_port *s = (struct mxs_auart_port *) arg;
533 struct tty_port *port = &s->port.state->port;
537 dma_unmap_sg(s->dev, &s->rx_sgl, 1, DMA_FROM_DEVICE);
539 stat = readl(s->port.membase + AUART_STAT);
540 stat &= ~(AUART_STAT_OERR | AUART_STAT_BERR |
541 AUART_STAT_PERR | AUART_STAT_FERR);
543 count = stat & AUART_STAT_RXCOUNT_MASK;
544 tty_insert_flip_string(port, s->rx_dma_buf, count);
546 writel(stat, s->port.membase + AUART_STAT);
547 tty_flip_buffer_push(port);
549 /* start the next DMA for RX. */
550 mxs_auart_dma_prep_rx(s);
553 static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s)
555 struct dma_async_tx_descriptor *desc;
556 struct scatterlist *sgl = &s->rx_sgl;
557 struct dma_chan *channel = s->rx_dma_chan;
561 pio[0] = AUART_CTRL0_RXTO_ENABLE
562 | AUART_CTRL0_RXTIMEOUT(0x80)
563 | AUART_CTRL0_XFER_COUNT(UART_XMIT_SIZE);
564 desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)pio,
565 1, DMA_TRANS_NONE, 0);
567 dev_err(s->dev, "step 1 error\n");
571 /* [2] : send DMA request */
572 sg_init_one(sgl, s->rx_dma_buf, UART_XMIT_SIZE);
573 dma_map_sg(s->dev, sgl, 1, DMA_FROM_DEVICE);
574 desc = dmaengine_prep_slave_sg(channel, sgl, 1, DMA_DEV_TO_MEM,
575 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
577 dev_err(s->dev, "step 2 error\n");
581 /* [3] : submit the DMA, but do not issue it. */
582 desc->callback = dma_rx_callback;
583 desc->callback_param = s;
584 dmaengine_submit(desc);
585 dma_async_issue_pending(channel);
589 static void mxs_auart_dma_exit_channel(struct mxs_auart_port *s)
591 if (s->tx_dma_chan) {
592 dma_release_channel(s->tx_dma_chan);
593 s->tx_dma_chan = NULL;
595 if (s->rx_dma_chan) {
596 dma_release_channel(s->rx_dma_chan);
597 s->rx_dma_chan = NULL;
600 kfree(s->tx_dma_buf);
601 kfree(s->rx_dma_buf);
602 s->tx_dma_buf = NULL;
603 s->rx_dma_buf = NULL;
606 static void mxs_auart_dma_exit(struct mxs_auart_port *s)
609 writel(AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE | AUART_CTRL2_DMAONERR,
610 s->port.membase + AUART_CTRL2_CLR);
612 mxs_auart_dma_exit_channel(s);
613 s->flags &= ~MXS_AUART_DMA_ENABLED;
614 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
615 clear_bit(MXS_AUART_DMA_RX_READY, &s->flags);
618 static int mxs_auart_dma_init(struct mxs_auart_port *s)
620 if (auart_dma_enabled(s))
624 s->rx_dma_chan = dma_request_slave_channel(s->dev, "rx");
627 s->rx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA);
632 s->tx_dma_chan = dma_request_slave_channel(s->dev, "tx");
635 s->tx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA);
640 s->flags |= MXS_AUART_DMA_ENABLED;
641 dev_dbg(s->dev, "enabled the DMA support.");
643 /* The DMA buffer is now the FIFO the TTY subsystem can use */
644 s->port.fifosize = UART_XMIT_SIZE;
649 mxs_auart_dma_exit_channel(s);
654 #define RTS_AT_AUART() IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(s->gpios, \
656 #define CTS_AT_AUART() IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(s->gpios, \
658 static void mxs_auart_settermios(struct uart_port *u,
659 struct ktermios *termios,
660 struct ktermios *old)
662 struct mxs_auart_port *s = to_auart_port(u);
663 u32 bm, ctrl, ctrl2, div;
664 unsigned int cflag, baud;
666 cflag = termios->c_cflag;
668 ctrl = AUART_LINECTRL_FEN;
669 ctrl2 = readl(u->membase + AUART_CTRL2);
672 switch (cflag & CSIZE) {
689 ctrl |= AUART_LINECTRL_WLEN(bm);
692 if (cflag & PARENB) {
693 ctrl |= AUART_LINECTRL_PEN;
694 if ((cflag & PARODD) == 0)
695 ctrl |= AUART_LINECTRL_EPS;
698 u->read_status_mask = 0;
700 if (termios->c_iflag & INPCK)
701 u->read_status_mask |= AUART_STAT_PERR;
702 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
703 u->read_status_mask |= AUART_STAT_BERR;
706 * Characters to ignore
708 u->ignore_status_mask = 0;
709 if (termios->c_iflag & IGNPAR)
710 u->ignore_status_mask |= AUART_STAT_PERR;
711 if (termios->c_iflag & IGNBRK) {
712 u->ignore_status_mask |= AUART_STAT_BERR;
714 * If we're ignoring parity and break indicators,
715 * ignore overruns too (for real raw support).
717 if (termios->c_iflag & IGNPAR)
718 u->ignore_status_mask |= AUART_STAT_OERR;
722 * ignore all characters if CREAD is not set
725 ctrl2 |= AUART_CTRL2_RXE;
727 ctrl2 &= ~AUART_CTRL2_RXE;
729 /* figure out the stop bits requested */
731 ctrl |= AUART_LINECTRL_STP2;
733 /* figure out the hardware flow control settings */
734 ctrl2 &= ~(AUART_CTRL2_CTSEN | AUART_CTRL2_RTSEN);
735 if (cflag & CRTSCTS) {
737 * The DMA has a bug(see errata:2836) in mx23.
738 * So we can not implement the DMA for auart in mx23,
739 * we can only implement the DMA support for auart
742 if (is_imx28_auart(s)
743 && test_bit(MXS_AUART_RTSCTS, &s->flags)) {
744 if (!mxs_auart_dma_init(s))
745 /* enable DMA tranfer */
746 ctrl2 |= AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE
747 | AUART_CTRL2_DMAONERR;
749 /* Even if RTS is GPIO line RTSEN can be enabled because
750 * the pinctrl configuration decides about RTS pin function */
751 ctrl2 |= AUART_CTRL2_RTSEN;
753 ctrl2 |= AUART_CTRL2_CTSEN;
757 baud = uart_get_baud_rate(u, termios, old, 0, u->uartclk);
758 div = u->uartclk * 32 / baud;
759 ctrl |= AUART_LINECTRL_BAUD_DIVFRAC(div & 0x3F);
760 ctrl |= AUART_LINECTRL_BAUD_DIVINT(div >> 6);
762 writel(ctrl, u->membase + AUART_LINECTRL);
763 writel(ctrl2, u->membase + AUART_CTRL2);
765 uart_update_timeout(u, termios->c_cflag, baud);
767 /* prepare for the DMA RX. */
768 if (auart_dma_enabled(s) &&
769 !test_and_set_bit(MXS_AUART_DMA_RX_READY, &s->flags)) {
770 if (!mxs_auart_dma_prep_rx(s)) {
771 /* Disable the normal RX interrupt. */
772 writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN,
773 u->membase + AUART_INTR_CLR);
775 mxs_auart_dma_exit(s);
776 dev_err(s->dev, "We can not start up the DMA.\n");
780 /* CTS flow-control and modem-status interrupts */
781 if (UART_ENABLE_MS(u, termios->c_cflag))
782 mxs_auart_enable_ms(u);
784 mxs_auart_disable_ms(u);
787 static void mxs_auart_set_ldisc(struct uart_port *port,
788 struct ktermios *termios)
790 if (termios->c_line == N_PPS) {
791 port->flags |= UPF_HARDPPS_CD;
792 mxs_auart_enable_ms(port);
794 port->flags &= ~UPF_HARDPPS_CD;
798 static irqreturn_t mxs_auart_irq_handle(int irq, void *context)
801 struct mxs_auart_port *s = context;
802 u32 mctrl_temp = s->mctrl_prev;
803 u32 stat = readl(s->port.membase + AUART_STAT);
805 istat = readl(s->port.membase + AUART_INTR);
808 writel(istat & (AUART_INTR_RTIS
811 | AUART_INTR_CTSMIS),
812 s->port.membase + AUART_INTR_CLR);
815 * Dealing with GPIO interrupt
817 if (irq == s->gpio_irq[UART_GPIO_CTS] ||
818 irq == s->gpio_irq[UART_GPIO_DCD] ||
819 irq == s->gpio_irq[UART_GPIO_DSR] ||
820 irq == s->gpio_irq[UART_GPIO_RI])
821 mxs_auart_modem_status(s,
822 mctrl_gpio_get(s->gpios, &mctrl_temp));
824 if (istat & AUART_INTR_CTSMIS) {
825 if (CTS_AT_AUART() && s->ms_irq_enabled)
826 uart_handle_cts_change(&s->port,
827 stat & AUART_STAT_CTS);
828 writel(AUART_INTR_CTSMIS,
829 s->port.membase + AUART_INTR_CLR);
830 istat &= ~AUART_INTR_CTSMIS;
833 if (istat & (AUART_INTR_RTIS | AUART_INTR_RXIS)) {
834 if (!auart_dma_enabled(s))
835 mxs_auart_rx_chars(s);
836 istat &= ~(AUART_INTR_RTIS | AUART_INTR_RXIS);
839 if (istat & AUART_INTR_TXIS) {
840 mxs_auart_tx_chars(s);
841 istat &= ~AUART_INTR_TXIS;
847 static void mxs_auart_reset(struct uart_port *u)
852 writel(AUART_CTRL0_SFTRST, u->membase + AUART_CTRL0_CLR);
854 for (i = 0; i < 10000; i++) {
855 reg = readl(u->membase + AUART_CTRL0);
856 if (!(reg & AUART_CTRL0_SFTRST))
860 writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR);
863 static int mxs_auart_startup(struct uart_port *u)
866 struct mxs_auart_port *s = to_auart_port(u);
868 ret = clk_prepare_enable(s->clk);
872 writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR);
874 writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_SET);
876 writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,
877 u->membase + AUART_INTR);
879 /* Reset FIFO size (it could have changed if DMA was enabled) */
880 u->fifosize = MXS_AUART_FIFO_SIZE;
883 * Enable fifo so all four bytes of a DMA word are written to
884 * output (otherwise, only the LSB is written, ie. 1 in 4 bytes)
886 writel(AUART_LINECTRL_FEN, u->membase + AUART_LINECTRL_SET);
888 /* get initial status of modem lines */
889 mctrl_gpio_get(s->gpios, &s->mctrl_prev);
891 s->ms_irq_enabled = false;
895 static void mxs_auart_shutdown(struct uart_port *u)
897 struct mxs_auart_port *s = to_auart_port(u);
899 mxs_auart_disable_ms(u);
901 if (auart_dma_enabled(s))
902 mxs_auart_dma_exit(s);
904 writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_CLR);
906 writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,
907 u->membase + AUART_INTR_CLR);
909 writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_SET);
911 clk_disable_unprepare(s->clk);
914 static unsigned int mxs_auart_tx_empty(struct uart_port *u)
916 if ((readl(u->membase + AUART_STAT) &
917 (AUART_STAT_TXFE | AUART_STAT_BUSY)) == AUART_STAT_TXFE)
923 static void mxs_auart_start_tx(struct uart_port *u)
925 struct mxs_auart_port *s = to_auart_port(u);
927 /* enable transmitter */
928 writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_SET);
930 mxs_auart_tx_chars(s);
933 static void mxs_auart_stop_tx(struct uart_port *u)
935 writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_CLR);
938 static void mxs_auart_stop_rx(struct uart_port *u)
940 writel(AUART_CTRL2_RXE, u->membase + AUART_CTRL2_CLR);
943 static void mxs_auart_break_ctl(struct uart_port *u, int ctl)
946 writel(AUART_LINECTRL_BRK,
947 u->membase + AUART_LINECTRL_SET);
949 writel(AUART_LINECTRL_BRK,
950 u->membase + AUART_LINECTRL_CLR);
953 static struct uart_ops mxs_auart_ops = {
954 .tx_empty = mxs_auart_tx_empty,
955 .start_tx = mxs_auart_start_tx,
956 .stop_tx = mxs_auart_stop_tx,
957 .stop_rx = mxs_auart_stop_rx,
958 .enable_ms = mxs_auart_enable_ms,
959 .break_ctl = mxs_auart_break_ctl,
960 .set_mctrl = mxs_auart_set_mctrl,
961 .get_mctrl = mxs_auart_get_mctrl,
962 .startup = mxs_auart_startup,
963 .shutdown = mxs_auart_shutdown,
964 .set_termios = mxs_auart_settermios,
965 .set_ldisc = mxs_auart_set_ldisc,
966 .type = mxs_auart_type,
967 .release_port = mxs_auart_release_port,
968 .request_port = mxs_auart_request_port,
969 .config_port = mxs_auart_config_port,
970 .verify_port = mxs_auart_verify_port,
973 static struct mxs_auart_port *auart_port[MXS_AUART_PORTS];
975 #ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
976 static void mxs_auart_console_putchar(struct uart_port *port, int ch)
978 unsigned int to = 1000;
980 while (readl(port->membase + AUART_STAT) & AUART_STAT_TXFF) {
986 writel(ch, port->membase + AUART_DATA);
990 auart_console_write(struct console *co, const char *str, unsigned int count)
992 struct mxs_auart_port *s;
993 struct uart_port *port;
994 unsigned int old_ctrl0, old_ctrl2;
995 unsigned int to = 20000;
997 if (co->index >= MXS_AUART_PORTS || co->index < 0)
1000 s = auart_port[co->index];
1005 /* First save the CR then disable the interrupts */
1006 old_ctrl2 = readl(port->membase + AUART_CTRL2);
1007 old_ctrl0 = readl(port->membase + AUART_CTRL0);
1009 writel(AUART_CTRL0_CLKGATE,
1010 port->membase + AUART_CTRL0_CLR);
1011 writel(AUART_CTRL2_UARTEN | AUART_CTRL2_TXE,
1012 port->membase + AUART_CTRL2_SET);
1014 uart_console_write(port, str, count, mxs_auart_console_putchar);
1016 /* Finally, wait for transmitter to become empty ... */
1017 while (readl(port->membase + AUART_STAT) & AUART_STAT_BUSY) {
1024 * ... and restore the TCR if we waited long enough for the transmitter
1025 * to be idle. This might keep the transmitter enabled although it is
1026 * unused, but that is better than to disable it while it is still
1029 if (!(readl(port->membase + AUART_STAT) & AUART_STAT_BUSY)) {
1030 writel(old_ctrl0, port->membase + AUART_CTRL0);
1031 writel(old_ctrl2, port->membase + AUART_CTRL2);
1034 clk_disable(s->clk);
1038 auart_console_get_options(struct uart_port *port, int *baud,
1039 int *parity, int *bits)
1041 unsigned int lcr_h, quot;
1043 if (!(readl(port->membase + AUART_CTRL2) & AUART_CTRL2_UARTEN))
1046 lcr_h = readl(port->membase + AUART_LINECTRL);
1049 if (lcr_h & AUART_LINECTRL_PEN) {
1050 if (lcr_h & AUART_LINECTRL_EPS)
1056 if ((lcr_h & AUART_LINECTRL_WLEN_MASK) == AUART_LINECTRL_WLEN(2))
1061 quot = ((readl(port->membase + AUART_LINECTRL)
1062 & AUART_LINECTRL_BAUD_DIVINT_MASK))
1063 >> (AUART_LINECTRL_BAUD_DIVINT_SHIFT - 6);
1064 quot |= ((readl(port->membase + AUART_LINECTRL)
1065 & AUART_LINECTRL_BAUD_DIVFRAC_MASK))
1066 >> AUART_LINECTRL_BAUD_DIVFRAC_SHIFT;
1070 *baud = (port->uartclk << 2) / quot;
1074 auart_console_setup(struct console *co, char *options)
1076 struct mxs_auart_port *s;
1084 * Check whether an invalid uart number has been specified, and
1085 * if so, search for the first available port that does have
1088 if (co->index == -1 || co->index >= ARRAY_SIZE(auart_port))
1090 s = auart_port[co->index];
1094 ret = clk_prepare_enable(s->clk);
1099 uart_parse_options(options, &baud, &parity, &bits, &flow);
1101 auart_console_get_options(&s->port, &baud, &parity, &bits);
1103 ret = uart_set_options(&s->port, co, baud, parity, bits, flow);
1105 clk_disable_unprepare(s->clk);
1110 static struct console auart_console = {
1112 .write = auart_console_write,
1113 .device = uart_console_device,
1114 .setup = auart_console_setup,
1115 .flags = CON_PRINTBUFFER,
1117 .data = &auart_driver,
1121 static struct uart_driver auart_driver = {
1122 .owner = THIS_MODULE,
1123 .driver_name = "ttyAPP",
1124 .dev_name = "ttyAPP",
1127 .nr = MXS_AUART_PORTS,
1128 #ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
1129 .cons = &auart_console,
1134 * This function returns 1 if pdev isn't a device instatiated by dt, 0 if it
1135 * could successfully get all information from dt or a negative errno.
1137 static int serial_mxs_probe_dt(struct mxs_auart_port *s,
1138 struct platform_device *pdev)
1140 struct device_node *np = pdev->dev.of_node;
1144 /* no device tree device */
1147 ret = of_alias_get_id(np, "serial");
1149 dev_err(&pdev->dev, "failed to get alias id: %d\n", ret);
1154 if (of_get_property(np, "fsl,uart-has-rtscts", NULL))
1155 set_bit(MXS_AUART_RTSCTS, &s->flags);
1160 static bool mxs_auart_init_gpios(struct mxs_auart_port *s, struct device *dev)
1162 enum mctrl_gpio_idx i;
1163 struct gpio_desc *gpiod;
1165 s->gpios = mctrl_gpio_init(dev, 0);
1166 if (IS_ERR_OR_NULL(s->gpios))
1169 /* Block (enabled before) DMA option if RTS or CTS is GPIO line */
1170 if (!RTS_AT_AUART() || !CTS_AT_AUART()) {
1171 if (test_bit(MXS_AUART_RTSCTS, &s->flags))
1173 "DMA and flow control via gpio may cause some problems. DMA disabled!\n");
1174 clear_bit(MXS_AUART_RTSCTS, &s->flags);
1177 for (i = 0; i < UART_GPIO_MAX; i++) {
1178 gpiod = mctrl_gpio_to_gpiod(s->gpios, i);
1179 if (gpiod && (gpiod_get_direction(gpiod) == GPIOF_DIR_IN))
1180 s->gpio_irq[i] = gpiod_to_irq(gpiod);
1182 s->gpio_irq[i] = -EINVAL;
1188 static void mxs_auart_free_gpio_irq(struct mxs_auart_port *s)
1190 enum mctrl_gpio_idx i;
1192 for (i = 0; i < UART_GPIO_MAX; i++)
1193 if (s->gpio_irq[i] >= 0)
1194 free_irq(s->gpio_irq[i], s);
1197 static int mxs_auart_request_gpio_irq(struct mxs_auart_port *s)
1199 int *irq = s->gpio_irq;
1200 enum mctrl_gpio_idx i;
1203 for (i = 0; (i < UART_GPIO_MAX) && !err; i++) {
1207 irq_set_status_flags(irq[i], IRQ_NOAUTOEN);
1208 err = request_irq(irq[i], mxs_auart_irq_handle,
1209 IRQ_TYPE_EDGE_BOTH, dev_name(s->dev), s);
1211 dev_err(s->dev, "%s - Can't get %d irq\n",
1216 * If something went wrong, rollback.
1218 while (err && (--i >= 0))
1220 free_irq(irq[i], s);
1225 static int mxs_auart_probe(struct platform_device *pdev)
1227 const struct of_device_id *of_id =
1228 of_match_device(mxs_auart_dt_ids, &pdev->dev);
1229 struct mxs_auart_port *s;
1234 s = kzalloc(sizeof(struct mxs_auart_port), GFP_KERNEL);
1240 ret = serial_mxs_probe_dt(s, pdev);
1242 s->port.line = pdev->id < 0 ? 0 : pdev->id;
1247 pdev->id_entry = of_id->data;
1248 s->devtype = pdev->id_entry->driver_data;
1251 s->clk = clk_get(&pdev->dev, NULL);
1252 if (IS_ERR(s->clk)) {
1253 ret = PTR_ERR(s->clk);
1257 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1263 s->port.mapbase = r->start;
1264 s->port.membase = ioremap(r->start, resource_size(r));
1265 s->port.ops = &mxs_auart_ops;
1266 s->port.iotype = UPIO_MEM;
1267 s->port.fifosize = MXS_AUART_FIFO_SIZE;
1268 s->port.uartclk = clk_get_rate(s->clk);
1269 s->port.type = PORT_IMX;
1270 s->port.dev = s->dev = &pdev->dev;
1274 s->irq = platform_get_irq(pdev, 0);
1275 s->port.irq = s->irq;
1276 ret = request_irq(s->irq, mxs_auart_irq_handle, 0, dev_name(&pdev->dev), s);
1280 platform_set_drvdata(pdev, s);
1282 if (!mxs_auart_init_gpios(s, &pdev->dev))
1284 "Failed to initialize GPIOs. The serial port may not work as expected\n");
1287 * Get the GPIO lines IRQ
1289 ret = mxs_auart_request_gpio_irq(s);
1293 auart_port[s->port.line] = s;
1295 mxs_auart_reset(&s->port);
1297 ret = uart_add_one_port(&auart_driver, &s->port);
1299 goto out_free_gpio_irq;
1301 version = readl(s->port.membase + AUART_VERSION);
1302 dev_info(&pdev->dev, "Found APPUART %d.%d.%d\n",
1303 (version >> 24) & 0xff,
1304 (version >> 16) & 0xff, version & 0xffff);
1309 mxs_auart_free_gpio_irq(s);
1311 auart_port[pdev->id] = NULL;
1312 free_irq(s->irq, s);
1321 static int mxs_auart_remove(struct platform_device *pdev)
1323 struct mxs_auart_port *s = platform_get_drvdata(pdev);
1325 uart_remove_one_port(&auart_driver, &s->port);
1327 auart_port[pdev->id] = NULL;
1329 mxs_auart_free_gpio_irq(s);
1331 free_irq(s->irq, s);
1337 static struct platform_driver mxs_auart_driver = {
1338 .probe = mxs_auart_probe,
1339 .remove = mxs_auart_remove,
1341 .name = "mxs-auart",
1342 .of_match_table = mxs_auart_dt_ids,
1346 static int __init mxs_auart_init(void)
1350 r = uart_register_driver(&auart_driver);
1354 r = platform_driver_register(&mxs_auart_driver);
1360 uart_unregister_driver(&auart_driver);
1365 static void __exit mxs_auart_exit(void)
1367 platform_driver_unregister(&mxs_auart_driver);
1368 uart_unregister_driver(&auart_driver);
1371 module_init(mxs_auart_init);
1372 module_exit(mxs_auart_exit);
1373 MODULE_LICENSE("GPL");
1374 MODULE_DESCRIPTION("Freescale MXS application uart driver");
1375 MODULE_ALIAS("platform:mxs-auart");