2 * Freescale STMP37XX/STMP378X Application UART driver
4 * Author: dmitry pervushin <dimka@embeddedalley.com>
6 * Copyright 2008-2010 Freescale Semiconductor, Inc.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
17 #if defined(CONFIG_SERIAL_MXS_AUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21 #include <linux/kernel.h>
22 #include <linux/errno.h>
23 #include <linux/init.h>
24 #include <linux/console.h>
25 #include <linux/interrupt.h>
26 #include <linux/module.h>
27 #include <linux/slab.h>
28 #include <linux/wait.h>
29 #include <linux/tty.h>
30 #include <linux/tty_driver.h>
31 #include <linux/tty_flip.h>
32 #include <linux/serial.h>
33 #include <linux/serial_core.h>
34 #include <linux/platform_device.h>
35 #include <linux/device.h>
36 #include <linux/clk.h>
37 #include <linux/delay.h>
39 #include <linux/of_device.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/dmaengine.h>
43 #include <asm/cacheflush.h>
45 #include <linux/gpio.h>
46 #include <linux/gpio/consumer.h>
47 #include <linux/err.h>
48 #include <linux/irq.h>
49 #include "serial_mctrl_gpio.h"
51 #define MXS_AUART_PORTS 5
52 #define MXS_AUART_FIFO_SIZE 16
54 #define AUART_CTRL0 0x00000000
55 #define AUART_CTRL0_SET 0x00000004
56 #define AUART_CTRL0_CLR 0x00000008
57 #define AUART_CTRL0_TOG 0x0000000c
58 #define AUART_CTRL1 0x00000010
59 #define AUART_CTRL1_SET 0x00000014
60 #define AUART_CTRL1_CLR 0x00000018
61 #define AUART_CTRL1_TOG 0x0000001c
62 #define AUART_CTRL2 0x00000020
63 #define AUART_CTRL2_SET 0x00000024
64 #define AUART_CTRL2_CLR 0x00000028
65 #define AUART_CTRL2_TOG 0x0000002c
66 #define AUART_LINECTRL 0x00000030
67 #define AUART_LINECTRL_SET 0x00000034
68 #define AUART_LINECTRL_CLR 0x00000038
69 #define AUART_LINECTRL_TOG 0x0000003c
70 #define AUART_LINECTRL2 0x00000040
71 #define AUART_LINECTRL2_SET 0x00000044
72 #define AUART_LINECTRL2_CLR 0x00000048
73 #define AUART_LINECTRL2_TOG 0x0000004c
74 #define AUART_INTR 0x00000050
75 #define AUART_INTR_SET 0x00000054
76 #define AUART_INTR_CLR 0x00000058
77 #define AUART_INTR_TOG 0x0000005c
78 #define AUART_DATA 0x00000060
79 #define AUART_STAT 0x00000070
80 #define AUART_DEBUG 0x00000080
81 #define AUART_VERSION 0x00000090
82 #define AUART_AUTOBAUD 0x000000a0
84 #define AUART_CTRL0_SFTRST (1 << 31)
85 #define AUART_CTRL0_CLKGATE (1 << 30)
86 #define AUART_CTRL0_RXTO_ENABLE (1 << 27)
87 #define AUART_CTRL0_RXTIMEOUT(v) (((v) & 0x7ff) << 16)
88 #define AUART_CTRL0_XFER_COUNT(v) ((v) & 0xffff)
90 #define AUART_CTRL1_XFER_COUNT(v) ((v) & 0xffff)
92 #define AUART_CTRL2_DMAONERR (1 << 26)
93 #define AUART_CTRL2_TXDMAE (1 << 25)
94 #define AUART_CTRL2_RXDMAE (1 << 24)
96 #define AUART_CTRL2_CTSEN (1 << 15)
97 #define AUART_CTRL2_RTSEN (1 << 14)
98 #define AUART_CTRL2_RTS (1 << 11)
99 #define AUART_CTRL2_RXE (1 << 9)
100 #define AUART_CTRL2_TXE (1 << 8)
101 #define AUART_CTRL2_UARTEN (1 << 0)
103 #define AUART_LINECTRL_BAUD_DIVINT_SHIFT 16
104 #define AUART_LINECTRL_BAUD_DIVINT_MASK 0xffff0000
105 #define AUART_LINECTRL_BAUD_DIVINT(v) (((v) & 0xffff) << 16)
106 #define AUART_LINECTRL_BAUD_DIVFRAC_SHIFT 8
107 #define AUART_LINECTRL_BAUD_DIVFRAC_MASK 0x00003f00
108 #define AUART_LINECTRL_BAUD_DIVFRAC(v) (((v) & 0x3f) << 8)
109 #define AUART_LINECTRL_WLEN_MASK 0x00000060
110 #define AUART_LINECTRL_WLEN(v) (((v) & 0x3) << 5)
111 #define AUART_LINECTRL_FEN (1 << 4)
112 #define AUART_LINECTRL_STP2 (1 << 3)
113 #define AUART_LINECTRL_EPS (1 << 2)
114 #define AUART_LINECTRL_PEN (1 << 1)
115 #define AUART_LINECTRL_BRK (1 << 0)
117 #define AUART_INTR_RTIEN (1 << 22)
118 #define AUART_INTR_TXIEN (1 << 21)
119 #define AUART_INTR_RXIEN (1 << 20)
120 #define AUART_INTR_CTSMIEN (1 << 17)
121 #define AUART_INTR_RTIS (1 << 6)
122 #define AUART_INTR_TXIS (1 << 5)
123 #define AUART_INTR_RXIS (1 << 4)
124 #define AUART_INTR_CTSMIS (1 << 1)
126 #define AUART_STAT_BUSY (1 << 29)
127 #define AUART_STAT_CTS (1 << 28)
128 #define AUART_STAT_TXFE (1 << 27)
129 #define AUART_STAT_TXFF (1 << 25)
130 #define AUART_STAT_RXFE (1 << 24)
131 #define AUART_STAT_OERR (1 << 19)
132 #define AUART_STAT_BERR (1 << 18)
133 #define AUART_STAT_PERR (1 << 17)
134 #define AUART_STAT_FERR (1 << 16)
135 #define AUART_STAT_RXCOUNT_MASK 0xffff
137 static struct uart_driver auart_driver;
139 enum mxs_auart_type {
144 struct mxs_auart_port {
145 struct uart_port port;
147 #define MXS_AUART_DMA_ENABLED 0x2
148 #define MXS_AUART_DMA_TX_SYNC 2 /* bit 2 */
149 #define MXS_AUART_DMA_RX_READY 3 /* bit 3 */
150 #define MXS_AUART_RTSCTS 4 /* bit 4 */
152 unsigned int mctrl_prev;
153 enum mxs_auart_type devtype;
159 struct scatterlist tx_sgl;
160 struct dma_chan *tx_dma_chan;
163 struct scatterlist rx_sgl;
164 struct dma_chan *rx_dma_chan;
167 struct mctrl_gpios *gpios;
168 int gpio_irq[UART_GPIO_MAX];
172 static const struct platform_device_id mxs_auart_devtype[] = {
173 { .name = "mxs-auart-imx23", .driver_data = IMX23_AUART },
174 { .name = "mxs-auart-imx28", .driver_data = IMX28_AUART },
177 MODULE_DEVICE_TABLE(platform, mxs_auart_devtype);
179 static const struct of_device_id mxs_auart_dt_ids[] = {
181 .compatible = "fsl,imx28-auart",
182 .data = &mxs_auart_devtype[IMX28_AUART]
184 .compatible = "fsl,imx23-auart",
185 .data = &mxs_auart_devtype[IMX23_AUART]
186 }, { /* sentinel */ }
188 MODULE_DEVICE_TABLE(of, mxs_auart_dt_ids);
190 static inline int is_imx28_auart(struct mxs_auart_port *s)
192 return s->devtype == IMX28_AUART;
195 static inline bool auart_dma_enabled(struct mxs_auart_port *s)
197 return s->flags & MXS_AUART_DMA_ENABLED;
200 static void mxs_auart_stop_tx(struct uart_port *u);
202 #define to_auart_port(u) container_of(u, struct mxs_auart_port, port)
204 static void mxs_auart_tx_chars(struct mxs_auart_port *s);
206 static void dma_tx_callback(void *param)
208 struct mxs_auart_port *s = param;
209 struct circ_buf *xmit = &s->port.state->xmit;
211 dma_unmap_sg(s->dev, &s->tx_sgl, 1, DMA_TO_DEVICE);
213 /* clear the bit used to serialize the DMA tx. */
214 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
215 smp_mb__after_atomic();
217 /* wake up the possible processes. */
218 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
219 uart_write_wakeup(&s->port);
221 mxs_auart_tx_chars(s);
224 static int mxs_auart_dma_tx(struct mxs_auart_port *s, int size)
226 struct dma_async_tx_descriptor *desc;
227 struct scatterlist *sgl = &s->tx_sgl;
228 struct dma_chan *channel = s->tx_dma_chan;
231 /* [1] : send PIO. Note, the first pio word is CTRL1. */
232 pio = AUART_CTRL1_XFER_COUNT(size);
233 desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)&pio,
234 1, DMA_TRANS_NONE, 0);
236 dev_err(s->dev, "step 1 error\n");
240 /* [2] : set DMA buffer. */
241 sg_init_one(sgl, s->tx_dma_buf, size);
242 dma_map_sg(s->dev, sgl, 1, DMA_TO_DEVICE);
243 desc = dmaengine_prep_slave_sg(channel, sgl,
244 1, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
246 dev_err(s->dev, "step 2 error\n");
250 /* [3] : submit the DMA */
251 desc->callback = dma_tx_callback;
252 desc->callback_param = s;
253 dmaengine_submit(desc);
254 dma_async_issue_pending(channel);
258 static void mxs_auart_tx_chars(struct mxs_auart_port *s)
260 struct circ_buf *xmit = &s->port.state->xmit;
262 if (auart_dma_enabled(s)) {
265 void *buffer = s->tx_dma_buf;
267 if (test_and_set_bit(MXS_AUART_DMA_TX_SYNC, &s->flags))
270 while (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) {
271 size = min_t(u32, UART_XMIT_SIZE - i,
272 CIRC_CNT_TO_END(xmit->head,
275 memcpy(buffer + i, xmit->buf + xmit->tail, size);
276 xmit->tail = (xmit->tail + size) & (UART_XMIT_SIZE - 1);
279 if (i >= UART_XMIT_SIZE)
283 if (uart_tx_stopped(&s->port))
284 mxs_auart_stop_tx(&s->port);
287 mxs_auart_dma_tx(s, i);
289 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
290 smp_mb__after_atomic();
296 while (!(readl(s->port.membase + AUART_STAT) &
298 if (s->port.x_char) {
300 writel(s->port.x_char,
301 s->port.membase + AUART_DATA);
305 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) {
307 writel(xmit->buf[xmit->tail],
308 s->port.membase + AUART_DATA);
309 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
313 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
314 uart_write_wakeup(&s->port);
316 if (uart_circ_empty(&(s->port.state->xmit)))
317 writel(AUART_INTR_TXIEN,
318 s->port.membase + AUART_INTR_CLR);
320 writel(AUART_INTR_TXIEN,
321 s->port.membase + AUART_INTR_SET);
323 if (uart_tx_stopped(&s->port))
324 mxs_auart_stop_tx(&s->port);
327 static void mxs_auart_rx_char(struct mxs_auart_port *s)
333 c = readl(s->port.membase + AUART_DATA);
334 stat = readl(s->port.membase + AUART_STAT);
339 if (stat & AUART_STAT_BERR) {
340 s->port.icount.brk++;
341 if (uart_handle_break(&s->port))
343 } else if (stat & AUART_STAT_PERR) {
344 s->port.icount.parity++;
345 } else if (stat & AUART_STAT_FERR) {
346 s->port.icount.frame++;
350 * Mask off conditions which should be ingored.
352 stat &= s->port.read_status_mask;
354 if (stat & AUART_STAT_BERR) {
356 } else if (stat & AUART_STAT_PERR)
358 else if (stat & AUART_STAT_FERR)
361 if (stat & AUART_STAT_OERR)
362 s->port.icount.overrun++;
364 if (uart_handle_sysrq_char(&s->port, c))
367 uart_insert_char(&s->port, stat, AUART_STAT_OERR, c, flag);
369 writel(stat, s->port.membase + AUART_STAT);
372 static void mxs_auart_rx_chars(struct mxs_auart_port *s)
377 stat = readl(s->port.membase + AUART_STAT);
378 if (stat & AUART_STAT_RXFE)
380 mxs_auart_rx_char(s);
383 writel(stat, s->port.membase + AUART_STAT);
384 tty_flip_buffer_push(&s->port.state->port);
387 static int mxs_auart_request_port(struct uart_port *u)
392 static int mxs_auart_verify_port(struct uart_port *u,
393 struct serial_struct *ser)
395 if (u->type != PORT_UNKNOWN && u->type != PORT_IMX)
400 static void mxs_auart_config_port(struct uart_port *u, int flags)
404 static const char *mxs_auart_type(struct uart_port *u)
406 struct mxs_auart_port *s = to_auart_port(u);
408 return dev_name(s->dev);
411 static void mxs_auart_release_port(struct uart_port *u)
415 static void mxs_auart_set_mctrl(struct uart_port *u, unsigned mctrl)
417 struct mxs_auart_port *s = to_auart_port(u);
419 u32 ctrl = readl(u->membase + AUART_CTRL2);
421 ctrl &= ~(AUART_CTRL2_RTSEN | AUART_CTRL2_RTS);
422 if (mctrl & TIOCM_RTS) {
423 if (uart_cts_enabled(u))
424 ctrl |= AUART_CTRL2_RTSEN;
426 ctrl |= AUART_CTRL2_RTS;
429 writel(ctrl, u->membase + AUART_CTRL2);
431 mctrl_gpio_set(s->gpios, mctrl);
434 #define MCTRL_ANY_DELTA (TIOCM_RI | TIOCM_DSR | TIOCM_CD | TIOCM_CTS)
435 static u32 mxs_auart_modem_status(struct mxs_auart_port *s, u32 mctrl)
439 mctrl_diff = mctrl ^ s->mctrl_prev;
440 s->mctrl_prev = mctrl;
441 if (mctrl_diff & MCTRL_ANY_DELTA && s->ms_irq_enabled &&
442 s->port.state != NULL) {
443 if (mctrl_diff & TIOCM_RI)
444 s->port.icount.rng++;
445 if (mctrl_diff & TIOCM_DSR)
446 s->port.icount.dsr++;
447 if (mctrl_diff & TIOCM_CD)
448 uart_handle_dcd_change(&s->port, mctrl & TIOCM_CD);
449 if (mctrl_diff & TIOCM_CTS)
450 uart_handle_cts_change(&s->port, mctrl & TIOCM_CTS);
452 wake_up_interruptible(&s->port.state->port.delta_msr_wait);
457 static u32 mxs_auart_get_mctrl(struct uart_port *u)
459 struct mxs_auart_port *s = to_auart_port(u);
460 u32 stat = readl(u->membase + AUART_STAT);
463 if (stat & AUART_STAT_CTS)
466 return mctrl_gpio_get(s->gpios, &mctrl);
470 * Enable modem status interrupts
472 static void mxs_auart_enable_ms(struct uart_port *port)
474 struct mxs_auart_port *s = to_auart_port(port);
477 * Interrupt should not be enabled twice
479 if (s->ms_irq_enabled)
482 s->ms_irq_enabled = true;
484 if (s->gpio_irq[UART_GPIO_CTS] >= 0)
485 enable_irq(s->gpio_irq[UART_GPIO_CTS]);
486 /* TODO: enable AUART_INTR_CTSMIEN otherwise */
488 if (s->gpio_irq[UART_GPIO_DSR] >= 0)
489 enable_irq(s->gpio_irq[UART_GPIO_DSR]);
491 if (s->gpio_irq[UART_GPIO_RI] >= 0)
492 enable_irq(s->gpio_irq[UART_GPIO_RI]);
494 if (s->gpio_irq[UART_GPIO_DCD] >= 0)
495 enable_irq(s->gpio_irq[UART_GPIO_DCD]);
499 * Disable modem status interrupts
501 static void mxs_auart_disable_ms(struct uart_port *port)
503 struct mxs_auart_port *s = to_auart_port(port);
506 * Interrupt should not be disabled twice
508 if (!s->ms_irq_enabled)
511 s->ms_irq_enabled = false;
513 if (s->gpio_irq[UART_GPIO_CTS] >= 0)
514 disable_irq(s->gpio_irq[UART_GPIO_CTS]);
515 /* TODO: disable AUART_INTR_CTSMIEN otherwise */
517 if (s->gpio_irq[UART_GPIO_DSR] >= 0)
518 disable_irq(s->gpio_irq[UART_GPIO_DSR]);
520 if (s->gpio_irq[UART_GPIO_RI] >= 0)
521 disable_irq(s->gpio_irq[UART_GPIO_RI]);
523 if (s->gpio_irq[UART_GPIO_DCD] >= 0)
524 disable_irq(s->gpio_irq[UART_GPIO_DCD]);
527 static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s);
528 static void dma_rx_callback(void *arg)
530 struct mxs_auart_port *s = (struct mxs_auart_port *) arg;
531 struct tty_port *port = &s->port.state->port;
535 dma_unmap_sg(s->dev, &s->rx_sgl, 1, DMA_FROM_DEVICE);
537 stat = readl(s->port.membase + AUART_STAT);
538 stat &= ~(AUART_STAT_OERR | AUART_STAT_BERR |
539 AUART_STAT_PERR | AUART_STAT_FERR);
541 count = stat & AUART_STAT_RXCOUNT_MASK;
542 tty_insert_flip_string(port, s->rx_dma_buf, count);
544 writel(stat, s->port.membase + AUART_STAT);
545 tty_flip_buffer_push(port);
547 /* start the next DMA for RX. */
548 mxs_auart_dma_prep_rx(s);
551 static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s)
553 struct dma_async_tx_descriptor *desc;
554 struct scatterlist *sgl = &s->rx_sgl;
555 struct dma_chan *channel = s->rx_dma_chan;
559 pio[0] = AUART_CTRL0_RXTO_ENABLE
560 | AUART_CTRL0_RXTIMEOUT(0x80)
561 | AUART_CTRL0_XFER_COUNT(UART_XMIT_SIZE);
562 desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)pio,
563 1, DMA_TRANS_NONE, 0);
565 dev_err(s->dev, "step 1 error\n");
569 /* [2] : send DMA request */
570 sg_init_one(sgl, s->rx_dma_buf, UART_XMIT_SIZE);
571 dma_map_sg(s->dev, sgl, 1, DMA_FROM_DEVICE);
572 desc = dmaengine_prep_slave_sg(channel, sgl, 1, DMA_DEV_TO_MEM,
573 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
575 dev_err(s->dev, "step 2 error\n");
579 /* [3] : submit the DMA, but do not issue it. */
580 desc->callback = dma_rx_callback;
581 desc->callback_param = s;
582 dmaengine_submit(desc);
583 dma_async_issue_pending(channel);
587 static void mxs_auart_dma_exit_channel(struct mxs_auart_port *s)
589 if (s->tx_dma_chan) {
590 dma_release_channel(s->tx_dma_chan);
591 s->tx_dma_chan = NULL;
593 if (s->rx_dma_chan) {
594 dma_release_channel(s->rx_dma_chan);
595 s->rx_dma_chan = NULL;
598 kfree(s->tx_dma_buf);
599 kfree(s->rx_dma_buf);
600 s->tx_dma_buf = NULL;
601 s->rx_dma_buf = NULL;
604 static void mxs_auart_dma_exit(struct mxs_auart_port *s)
607 writel(AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE | AUART_CTRL2_DMAONERR,
608 s->port.membase + AUART_CTRL2_CLR);
610 mxs_auart_dma_exit_channel(s);
611 s->flags &= ~MXS_AUART_DMA_ENABLED;
612 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
613 clear_bit(MXS_AUART_DMA_RX_READY, &s->flags);
616 static int mxs_auart_dma_init(struct mxs_auart_port *s)
618 if (auart_dma_enabled(s))
622 s->rx_dma_chan = dma_request_slave_channel(s->dev, "rx");
625 s->rx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA);
630 s->tx_dma_chan = dma_request_slave_channel(s->dev, "tx");
633 s->tx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA);
638 s->flags |= MXS_AUART_DMA_ENABLED;
639 dev_dbg(s->dev, "enabled the DMA support.");
641 /* The DMA buffer is now the FIFO the TTY subsystem can use */
642 s->port.fifosize = UART_XMIT_SIZE;
647 mxs_auart_dma_exit_channel(s);
652 #define RTS_AT_AUART() IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(s->gpios, \
654 #define CTS_AT_AUART() IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(s->gpios, \
656 static void mxs_auart_settermios(struct uart_port *u,
657 struct ktermios *termios,
658 struct ktermios *old)
660 struct mxs_auart_port *s = to_auart_port(u);
661 u32 bm, ctrl, ctrl2, div;
662 unsigned int cflag, baud;
664 cflag = termios->c_cflag;
666 ctrl = AUART_LINECTRL_FEN;
667 ctrl2 = readl(u->membase + AUART_CTRL2);
670 switch (cflag & CSIZE) {
687 ctrl |= AUART_LINECTRL_WLEN(bm);
690 if (cflag & PARENB) {
691 ctrl |= AUART_LINECTRL_PEN;
692 if ((cflag & PARODD) == 0)
693 ctrl |= AUART_LINECTRL_EPS;
696 u->read_status_mask = 0;
698 if (termios->c_iflag & INPCK)
699 u->read_status_mask |= AUART_STAT_PERR;
700 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
701 u->read_status_mask |= AUART_STAT_BERR;
704 * Characters to ignore
706 u->ignore_status_mask = 0;
707 if (termios->c_iflag & IGNPAR)
708 u->ignore_status_mask |= AUART_STAT_PERR;
709 if (termios->c_iflag & IGNBRK) {
710 u->ignore_status_mask |= AUART_STAT_BERR;
712 * If we're ignoring parity and break indicators,
713 * ignore overruns too (for real raw support).
715 if (termios->c_iflag & IGNPAR)
716 u->ignore_status_mask |= AUART_STAT_OERR;
720 * ignore all characters if CREAD is not set
723 ctrl2 |= AUART_CTRL2_RXE;
725 ctrl2 &= ~AUART_CTRL2_RXE;
727 /* figure out the stop bits requested */
729 ctrl |= AUART_LINECTRL_STP2;
731 /* figure out the hardware flow control settings */
732 ctrl2 &= ~(AUART_CTRL2_CTSEN | AUART_CTRL2_RTSEN);
733 if (cflag & CRTSCTS) {
735 * The DMA has a bug(see errata:2836) in mx23.
736 * So we can not implement the DMA for auart in mx23,
737 * we can only implement the DMA support for auart
740 if (is_imx28_auart(s)
741 && test_bit(MXS_AUART_RTSCTS, &s->flags)) {
742 if (!mxs_auart_dma_init(s))
743 /* enable DMA tranfer */
744 ctrl2 |= AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE
745 | AUART_CTRL2_DMAONERR;
747 /* Even if RTS is GPIO line RTSEN can be enabled because
748 * the pinctrl configuration decides about RTS pin function */
749 ctrl2 |= AUART_CTRL2_RTSEN;
751 ctrl2 |= AUART_CTRL2_CTSEN;
755 baud = uart_get_baud_rate(u, termios, old, 0, u->uartclk);
756 div = u->uartclk * 32 / baud;
757 ctrl |= AUART_LINECTRL_BAUD_DIVFRAC(div & 0x3F);
758 ctrl |= AUART_LINECTRL_BAUD_DIVINT(div >> 6);
760 writel(ctrl, u->membase + AUART_LINECTRL);
761 writel(ctrl2, u->membase + AUART_CTRL2);
763 uart_update_timeout(u, termios->c_cflag, baud);
765 /* prepare for the DMA RX. */
766 if (auart_dma_enabled(s) &&
767 !test_and_set_bit(MXS_AUART_DMA_RX_READY, &s->flags)) {
768 if (!mxs_auart_dma_prep_rx(s)) {
769 /* Disable the normal RX interrupt. */
770 writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN,
771 u->membase + AUART_INTR_CLR);
773 mxs_auart_dma_exit(s);
774 dev_err(s->dev, "We can not start up the DMA.\n");
778 /* CTS flow-control and modem-status interrupts */
779 if (UART_ENABLE_MS(u, termios->c_cflag))
780 mxs_auart_enable_ms(u);
782 mxs_auart_disable_ms(u);
785 static void mxs_auart_set_ldisc(struct uart_port *port,
786 struct ktermios *termios)
788 if (termios->c_line == N_PPS) {
789 port->flags |= UPF_HARDPPS_CD;
790 mxs_auart_enable_ms(port);
792 port->flags &= ~UPF_HARDPPS_CD;
796 static irqreturn_t mxs_auart_irq_handle(int irq, void *context)
799 struct mxs_auart_port *s = context;
800 u32 mctrl_temp = s->mctrl_prev;
801 u32 stat = readl(s->port.membase + AUART_STAT);
803 istat = readl(s->port.membase + AUART_INTR);
806 writel(istat & (AUART_INTR_RTIS
809 | AUART_INTR_CTSMIS),
810 s->port.membase + AUART_INTR_CLR);
813 * Dealing with GPIO interrupt
815 if (irq == s->gpio_irq[UART_GPIO_CTS] ||
816 irq == s->gpio_irq[UART_GPIO_DCD] ||
817 irq == s->gpio_irq[UART_GPIO_DSR] ||
818 irq == s->gpio_irq[UART_GPIO_RI])
819 mxs_auart_modem_status(s,
820 mctrl_gpio_get(s->gpios, &mctrl_temp));
822 if (istat & AUART_INTR_CTSMIS) {
823 if (CTS_AT_AUART() && s->ms_irq_enabled)
824 uart_handle_cts_change(&s->port,
825 stat & AUART_STAT_CTS);
826 writel(AUART_INTR_CTSMIS,
827 s->port.membase + AUART_INTR_CLR);
828 istat &= ~AUART_INTR_CTSMIS;
831 if (istat & (AUART_INTR_RTIS | AUART_INTR_RXIS)) {
832 if (!auart_dma_enabled(s))
833 mxs_auart_rx_chars(s);
834 istat &= ~(AUART_INTR_RTIS | AUART_INTR_RXIS);
837 if (istat & AUART_INTR_TXIS) {
838 mxs_auart_tx_chars(s);
839 istat &= ~AUART_INTR_TXIS;
845 static void mxs_auart_reset(struct uart_port *u)
850 writel(AUART_CTRL0_SFTRST, u->membase + AUART_CTRL0_CLR);
852 for (i = 0; i < 10000; i++) {
853 reg = readl(u->membase + AUART_CTRL0);
854 if (!(reg & AUART_CTRL0_SFTRST))
858 writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR);
861 static int mxs_auart_startup(struct uart_port *u)
864 struct mxs_auart_port *s = to_auart_port(u);
866 ret = clk_prepare_enable(s->clk);
870 writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR);
872 writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_SET);
874 writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,
875 u->membase + AUART_INTR);
877 /* Reset FIFO size (it could have changed if DMA was enabled) */
878 u->fifosize = MXS_AUART_FIFO_SIZE;
881 * Enable fifo so all four bytes of a DMA word are written to
882 * output (otherwise, only the LSB is written, ie. 1 in 4 bytes)
884 writel(AUART_LINECTRL_FEN, u->membase + AUART_LINECTRL_SET);
886 /* get initial status of modem lines */
887 mctrl_gpio_get(s->gpios, &s->mctrl_prev);
889 s->ms_irq_enabled = false;
893 static void mxs_auart_shutdown(struct uart_port *u)
895 struct mxs_auart_port *s = to_auart_port(u);
897 mxs_auart_disable_ms(u);
899 if (auart_dma_enabled(s))
900 mxs_auart_dma_exit(s);
902 writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_CLR);
904 writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,
905 u->membase + AUART_INTR_CLR);
907 writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_SET);
909 clk_disable_unprepare(s->clk);
912 static unsigned int mxs_auart_tx_empty(struct uart_port *u)
914 if ((readl(u->membase + AUART_STAT) &
915 (AUART_STAT_TXFE | AUART_STAT_BUSY)) == AUART_STAT_TXFE)
921 static void mxs_auart_start_tx(struct uart_port *u)
923 struct mxs_auart_port *s = to_auart_port(u);
925 /* enable transmitter */
926 writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_SET);
928 mxs_auart_tx_chars(s);
931 static void mxs_auart_stop_tx(struct uart_port *u)
933 writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_CLR);
936 static void mxs_auart_stop_rx(struct uart_port *u)
938 writel(AUART_CTRL2_RXE, u->membase + AUART_CTRL2_CLR);
941 static void mxs_auart_break_ctl(struct uart_port *u, int ctl)
944 writel(AUART_LINECTRL_BRK,
945 u->membase + AUART_LINECTRL_SET);
947 writel(AUART_LINECTRL_BRK,
948 u->membase + AUART_LINECTRL_CLR);
951 static struct uart_ops mxs_auart_ops = {
952 .tx_empty = mxs_auart_tx_empty,
953 .start_tx = mxs_auart_start_tx,
954 .stop_tx = mxs_auart_stop_tx,
955 .stop_rx = mxs_auart_stop_rx,
956 .enable_ms = mxs_auart_enable_ms,
957 .break_ctl = mxs_auart_break_ctl,
958 .set_mctrl = mxs_auart_set_mctrl,
959 .get_mctrl = mxs_auart_get_mctrl,
960 .startup = mxs_auart_startup,
961 .shutdown = mxs_auart_shutdown,
962 .set_termios = mxs_auart_settermios,
963 .set_ldisc = mxs_auart_set_ldisc,
964 .type = mxs_auart_type,
965 .release_port = mxs_auart_release_port,
966 .request_port = mxs_auart_request_port,
967 .config_port = mxs_auart_config_port,
968 .verify_port = mxs_auart_verify_port,
971 static struct mxs_auart_port *auart_port[MXS_AUART_PORTS];
973 #ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
974 static void mxs_auart_console_putchar(struct uart_port *port, int ch)
976 unsigned int to = 1000;
978 while (readl(port->membase + AUART_STAT) & AUART_STAT_TXFF) {
984 writel(ch, port->membase + AUART_DATA);
988 auart_console_write(struct console *co, const char *str, unsigned int count)
990 struct mxs_auart_port *s;
991 struct uart_port *port;
992 unsigned int old_ctrl0, old_ctrl2;
993 unsigned int to = 20000;
995 if (co->index >= MXS_AUART_PORTS || co->index < 0)
998 s = auart_port[co->index];
1003 /* First save the CR then disable the interrupts */
1004 old_ctrl2 = readl(port->membase + AUART_CTRL2);
1005 old_ctrl0 = readl(port->membase + AUART_CTRL0);
1007 writel(AUART_CTRL0_CLKGATE,
1008 port->membase + AUART_CTRL0_CLR);
1009 writel(AUART_CTRL2_UARTEN | AUART_CTRL2_TXE,
1010 port->membase + AUART_CTRL2_SET);
1012 uart_console_write(port, str, count, mxs_auart_console_putchar);
1014 /* Finally, wait for transmitter to become empty ... */
1015 while (readl(port->membase + AUART_STAT) & AUART_STAT_BUSY) {
1022 * ... and restore the TCR if we waited long enough for the transmitter
1023 * to be idle. This might keep the transmitter enabled although it is
1024 * unused, but that is better than to disable it while it is still
1027 if (!(readl(port->membase + AUART_STAT) & AUART_STAT_BUSY)) {
1028 writel(old_ctrl0, port->membase + AUART_CTRL0);
1029 writel(old_ctrl2, port->membase + AUART_CTRL2);
1032 clk_disable(s->clk);
1036 auart_console_get_options(struct uart_port *port, int *baud,
1037 int *parity, int *bits)
1039 unsigned int lcr_h, quot;
1041 if (!(readl(port->membase + AUART_CTRL2) & AUART_CTRL2_UARTEN))
1044 lcr_h = readl(port->membase + AUART_LINECTRL);
1047 if (lcr_h & AUART_LINECTRL_PEN) {
1048 if (lcr_h & AUART_LINECTRL_EPS)
1054 if ((lcr_h & AUART_LINECTRL_WLEN_MASK) == AUART_LINECTRL_WLEN(2))
1059 quot = ((readl(port->membase + AUART_LINECTRL)
1060 & AUART_LINECTRL_BAUD_DIVINT_MASK))
1061 >> (AUART_LINECTRL_BAUD_DIVINT_SHIFT - 6);
1062 quot |= ((readl(port->membase + AUART_LINECTRL)
1063 & AUART_LINECTRL_BAUD_DIVFRAC_MASK))
1064 >> AUART_LINECTRL_BAUD_DIVFRAC_SHIFT;
1068 *baud = (port->uartclk << 2) / quot;
1072 auart_console_setup(struct console *co, char *options)
1074 struct mxs_auart_port *s;
1082 * Check whether an invalid uart number has been specified, and
1083 * if so, search for the first available port that does have
1086 if (co->index == -1 || co->index >= ARRAY_SIZE(auart_port))
1088 s = auart_port[co->index];
1092 ret = clk_prepare_enable(s->clk);
1097 uart_parse_options(options, &baud, &parity, &bits, &flow);
1099 auart_console_get_options(&s->port, &baud, &parity, &bits);
1101 ret = uart_set_options(&s->port, co, baud, parity, bits, flow);
1103 clk_disable_unprepare(s->clk);
1108 static struct console auart_console = {
1110 .write = auart_console_write,
1111 .device = uart_console_device,
1112 .setup = auart_console_setup,
1113 .flags = CON_PRINTBUFFER,
1115 .data = &auart_driver,
1119 static struct uart_driver auart_driver = {
1120 .owner = THIS_MODULE,
1121 .driver_name = "ttyAPP",
1122 .dev_name = "ttyAPP",
1125 .nr = MXS_AUART_PORTS,
1126 #ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
1127 .cons = &auart_console,
1132 * This function returns 1 if pdev isn't a device instatiated by dt, 0 if it
1133 * could successfully get all information from dt or a negative errno.
1135 static int serial_mxs_probe_dt(struct mxs_auart_port *s,
1136 struct platform_device *pdev)
1138 struct device_node *np = pdev->dev.of_node;
1142 /* no device tree device */
1145 ret = of_alias_get_id(np, "serial");
1147 dev_err(&pdev->dev, "failed to get alias id: %d\n", ret);
1152 if (of_get_property(np, "fsl,uart-has-rtscts", NULL))
1153 set_bit(MXS_AUART_RTSCTS, &s->flags);
1158 static int mxs_auart_init_gpios(struct mxs_auart_port *s, struct device *dev)
1160 enum mctrl_gpio_idx i;
1161 struct gpio_desc *gpiod;
1163 s->gpios = mctrl_gpio_init(dev, 0);
1164 if (IS_ERR(s->gpios))
1165 return PTR_ERR(s->gpios);
1167 /* Block (enabled before) DMA option if RTS or CTS is GPIO line */
1168 if (!RTS_AT_AUART() || !CTS_AT_AUART()) {
1169 if (test_bit(MXS_AUART_RTSCTS, &s->flags))
1171 "DMA and flow control via gpio may cause some problems. DMA disabled!\n");
1172 clear_bit(MXS_AUART_RTSCTS, &s->flags);
1175 for (i = 0; i < UART_GPIO_MAX; i++) {
1176 gpiod = mctrl_gpio_to_gpiod(s->gpios, i);
1177 if (gpiod && (gpiod_get_direction(gpiod) == GPIOF_DIR_IN))
1178 s->gpio_irq[i] = gpiod_to_irq(gpiod);
1180 s->gpio_irq[i] = -EINVAL;
1186 static void mxs_auart_free_gpio_irq(struct mxs_auart_port *s)
1188 enum mctrl_gpio_idx i;
1190 for (i = 0; i < UART_GPIO_MAX; i++)
1191 if (s->gpio_irq[i] >= 0)
1192 free_irq(s->gpio_irq[i], s);
1195 static int mxs_auart_request_gpio_irq(struct mxs_auart_port *s)
1197 int *irq = s->gpio_irq;
1198 enum mctrl_gpio_idx i;
1201 for (i = 0; (i < UART_GPIO_MAX) && !err; i++) {
1205 irq_set_status_flags(irq[i], IRQ_NOAUTOEN);
1206 err = request_irq(irq[i], mxs_auart_irq_handle,
1207 IRQ_TYPE_EDGE_BOTH, dev_name(s->dev), s);
1209 dev_err(s->dev, "%s - Can't get %d irq\n",
1214 * If something went wrong, rollback.
1216 while (err && (--i >= 0))
1218 free_irq(irq[i], s);
1223 static int mxs_auart_probe(struct platform_device *pdev)
1225 const struct of_device_id *of_id =
1226 of_match_device(mxs_auart_dt_ids, &pdev->dev);
1227 struct mxs_auart_port *s;
1232 s = devm_kzalloc(&pdev->dev, sizeof(*s), GFP_KERNEL);
1236 ret = serial_mxs_probe_dt(s, pdev);
1238 s->port.line = pdev->id < 0 ? 0 : pdev->id;
1243 pdev->id_entry = of_id->data;
1244 s->devtype = pdev->id_entry->driver_data;
1247 s->clk = devm_clk_get(&pdev->dev, NULL);
1249 return PTR_ERR(s->clk);
1251 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1256 s->port.mapbase = r->start;
1257 s->port.membase = ioremap(r->start, resource_size(r));
1258 s->port.ops = &mxs_auart_ops;
1259 s->port.iotype = UPIO_MEM;
1260 s->port.fifosize = MXS_AUART_FIFO_SIZE;
1261 s->port.uartclk = clk_get_rate(s->clk);
1262 s->port.type = PORT_IMX;
1263 s->port.dev = s->dev = &pdev->dev;
1267 irq = platform_get_irq(pdev, 0);
1272 ret = devm_request_irq(&pdev->dev, irq, mxs_auart_irq_handle, 0,
1273 dev_name(&pdev->dev), s);
1277 platform_set_drvdata(pdev, s);
1279 ret = mxs_auart_init_gpios(s, &pdev->dev);
1281 dev_err(&pdev->dev, "Failed to initialize GPIOs.\n");
1286 * Get the GPIO lines IRQ
1288 ret = mxs_auart_request_gpio_irq(s);
1292 auart_port[s->port.line] = s;
1294 mxs_auart_reset(&s->port);
1296 ret = uart_add_one_port(&auart_driver, &s->port);
1298 goto out_free_gpio_irq;
1300 version = readl(s->port.membase + AUART_VERSION);
1301 dev_info(&pdev->dev, "Found APPUART %d.%d.%d\n",
1302 (version >> 24) & 0xff,
1303 (version >> 16) & 0xff, version & 0xffff);
1308 mxs_auart_free_gpio_irq(s);
1309 auart_port[pdev->id] = NULL;
1313 static int mxs_auart_remove(struct platform_device *pdev)
1315 struct mxs_auart_port *s = platform_get_drvdata(pdev);
1317 uart_remove_one_port(&auart_driver, &s->port);
1318 auart_port[pdev->id] = NULL;
1319 mxs_auart_free_gpio_irq(s);
1324 static struct platform_driver mxs_auart_driver = {
1325 .probe = mxs_auart_probe,
1326 .remove = mxs_auart_remove,
1328 .name = "mxs-auart",
1329 .of_match_table = mxs_auart_dt_ids,
1333 static int __init mxs_auart_init(void)
1337 r = uart_register_driver(&auart_driver);
1341 r = platform_driver_register(&mxs_auart_driver);
1347 uart_unregister_driver(&auart_driver);
1352 static void __exit mxs_auart_exit(void)
1354 platform_driver_unregister(&mxs_auart_driver);
1355 uart_unregister_driver(&auart_driver);
1358 module_init(mxs_auart_init);
1359 module_exit(mxs_auart_exit);
1360 MODULE_LICENSE("GPL");
1361 MODULE_DESCRIPTION("Freescale MXS application uart driver");
1362 MODULE_ALIAS("platform:mxs-auart");