drivers/tty/serial/omap-serial.c

   1 /*
   2  * Driver for OMAP-UART controller.
   3  * Based on drivers/serial/8250.c
   4  *
   5  * Copyright (C) 2010 Texas Instruments.
   6  *
   7  * Authors:
   8  *      Govindraj R     <govindraj.raja@ti.com>
   9  *      Thara Gopinath  <thara@ti.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * Note: This driver is made separate from 8250 driver as we cannot
  17  * over load 8250 driver with omap platform specific configuration for
  18  * features like DMA, it makes easier to implement features like DMA and
  19  * hardware flow control and software flow control configuration with
  20  * this driver as required for the omap-platform.
  21  */
  22
  23 #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  24 #define SUPPORT_SYSRQ
  25 #endif
  26
  27 #include <linux/module.h>
  28 #include <linux/init.h>
  29 #include <linux/console.h>
  30 #include <linux/serial_reg.h>
  31 #include <linux/delay.h>
  32 #include <linux/slab.h>
  33 #include <linux/tty.h>
  34 #include <linux/tty_flip.h>
  35 #include <linux/platform_device.h>
  36 #include <linux/io.h>
  37 #include <linux/clk.h>
  38 #include <linux/serial_core.h>
  39 #include <linux/irq.h>
  40 #include <linux/pm_runtime.h>
  41 #include <linux/of.h>
  42 #include <linux/gpio.h>
  43 #include <linux/pinctrl/consumer.h>
  44
  45 #include <plat/omap-serial.h>
  46
  47 #define UART_BUILD_REVISION(x, y)       (((x) << 8) | (y))
  48
  49 #define OMAP_UART_REV_42 0x0402
  50 #define OMAP_UART_REV_46 0x0406
  51 #define OMAP_UART_REV_52 0x0502
  52 #define OMAP_UART_REV_63 0x0603
  53
  54 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
  55
  56 /* SCR register bitmasks */
  57 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK               (1 << 7)
  58
  59 /* FCR register bitmasks */
  60 #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK                 (0x3 << 6)
  61 #define OMAP_UART_FCR_TX_FIFO_TRIG_MASK                 (0x3 << 4)
  62
  63 /* MVR register bitmasks */
  64 #define OMAP_UART_MVR_SCHEME_SHIFT      30
  65
  66 #define OMAP_UART_LEGACY_MVR_MAJ_MASK   0xf0
  67 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT  4
  68 #define OMAP_UART_LEGACY_MVR_MIN_MASK   0x0f
  69
  70 #define OMAP_UART_MVR_MAJ_MASK          0x700
  71 #define OMAP_UART_MVR_MAJ_SHIFT         8
  72 #define OMAP_UART_MVR_MIN_MASK          0x3f
  73
  74 struct uart_omap_port {
  75         struct uart_port        port;
  76         struct uart_omap_dma    uart_dma;
  77         struct device           *dev;
  78
  79         unsigned char           ier;
  80         unsigned char           lcr;
  81         unsigned char           mcr;
  82         unsigned char           fcr;
  83         unsigned char           efr;
  84         unsigned char           dll;
  85         unsigned char           dlh;
  86         unsigned char           mdr1;
  87         unsigned char           scr;
  88
  89         int                     use_dma;
  90         /*
  91          * Some bits in registers are cleared on a read, so they must
  92          * be saved whenever the register is read but the bits will not
  93          * be immediately processed.
  94          */
  95         unsigned int            lsr_break_flag;
  96         unsigned char           msr_saved_flags;
  97         char                    name[20];
  98         unsigned long           port_activity;
  99         u32                     context_loss_cnt;
 100         u32                     errata;
 101         u8                      wakeups_enabled;
 102         unsigned int            irq_pending:1;
 103
 104         int                     DTR_gpio;
 105         int                     DTR_inverted;
 106         int                     DTR_active;
 107
 108         struct pm_qos_request   pm_qos_request;
 109         u32                     latency;
 110         u32                     calc_latency;
 111         struct work_struct      qos_work;
 112         struct pinctrl          *pins;
 113 };
 114
 115 #define to_uart_omap_port(p)    ((container_of((p), struct uart_omap_port, port)))
 116
 117 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
 118
 119 /* Forward declaration of functions */
 120 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
 121
 122 static struct workqueue_struct *serial_omap_uart_wq;
 123
 124 static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
 125 {
 126         offset <<= up->port.regshift;
 127         return readw(up->port.membase + offset);
 128 }
 129
 130 static inline void serial_out(struct uart_omap_port *up, int offset, int value)
 131 {
 132         offset <<= up->port.regshift;
 133         writew(value, up->port.membase + offset);
 134 }
 135
 136 static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
 137 {
 138         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
 139         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
 140                        UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
 141         serial_out(up, UART_FCR, 0);
 142 }
 143
 144 static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
 145 {
 146         struct omap_uart_port_info *pdata = up->dev->platform_data;
 147
 148         if (!pdata || !pdata->get_context_loss_count)
 149                 return 0;
 150
 151         return pdata->get_context_loss_count(up->dev);
 152 }
 153
 154 static void serial_omap_set_forceidle(struct uart_omap_port *up)
 155 {
 156         struct omap_uart_port_info *pdata = up->dev->platform_data;
 157
 158         if (!pdata || !pdata->set_forceidle)
 159                 return;
 160
 161         pdata->set_forceidle(up->dev);
 162 }
 163
 164 static void serial_omap_set_noidle(struct uart_omap_port *up)
 165 {
 166         struct omap_uart_port_info *pdata = up->dev->platform_data;
 167
 168         if (!pdata || !pdata->set_noidle)
 169                 return;
 170
 171         pdata->set_noidle(up->dev);
 172 }
 173
 174 static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
 175 {
 176         struct omap_uart_port_info *pdata = up->dev->platform_data;
 177
 178         if (!pdata || !pdata->enable_wakeup)
 179                 return;
 180
 181         pdata->enable_wakeup(up->dev, enable);
 182 }
 183
 184 /*
 185  * serial_omap_get_divisor - calculate divisor value
 186  * @port: uart port info
 187  * @baud: baudrate for which divisor needs to be calculated.
 188  *
 189  * We have written our own function to get the divisor so as to support
 190  * 13x mode. 3Mbps Baudrate as an different divisor.
 191  * Reference OMAP TRM Chapter 17:
 192  * Table 17-1. UART Mode Baud Rates, Divisor Values, and Error Rates
 193  * referring to oversampling - divisor value
 194  * baudrate 460,800 to 3,686,400 all have divisor 13
 195  * except 3,000,000 which has divisor value 16
 196  */
 197 static unsigned int
 198 serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
 199 {
 200         unsigned int divisor;
 201
 202         if (baud > OMAP_MODE13X_SPEED && baud != 3000000)
 203                 divisor = 13;
 204         else
 205                 divisor = 16;
 206         return port->uartclk/(baud * divisor);
 207 }
 208
 209 static void serial_omap_enable_ms(struct uart_port *port)
 210 {
 211         struct uart_omap_port *up = to_uart_omap_port(port);
 212
 213         dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
 214
 215         pm_runtime_get_sync(up->dev);
 216         up->ier |= UART_IER_MSI;
 217         serial_out(up, UART_IER, up->ier);
 218         pm_runtime_mark_last_busy(up->dev);
 219         pm_runtime_put_autosuspend(up->dev);
 220 }
 221
 222 static void serial_omap_stop_tx(struct uart_port *port)
 223 {
 224         struct uart_omap_port *up = to_uart_omap_port(port);
 225
 226         pm_runtime_get_sync(up->dev);
 227         if (up->ier & UART_IER_THRI) {
 228                 up->ier &= ~UART_IER_THRI;
 229                 serial_out(up, UART_IER, up->ier);
 230         }
 231
 232         serial_omap_set_forceidle(up);
 233
 234         pm_runtime_mark_last_busy(up->dev);
 235         pm_runtime_put_autosuspend(up->dev);
 236 }
 237
 238 static void serial_omap_stop_rx(struct uart_port *port)
 239 {
 240         struct uart_omap_port *up = to_uart_omap_port(port);
 241
 242         pm_runtime_get_sync(up->dev);
 243         up->ier &= ~UART_IER_RLSI;
 244         up->port.read_status_mask &= ~UART_LSR_DR;
 245         serial_out(up, UART_IER, up->ier);
 246         pm_runtime_mark_last_busy(up->dev);
 247         pm_runtime_put_autosuspend(up->dev);
 248 }
 249
 250 static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
 251 {
 252         struct circ_buf *xmit = &up->port.state->xmit;
 253         int count;
 254
 255         if (!(lsr & UART_LSR_THRE))
 256                 return;
 257
 258         if (up->port.x_char) {
 259                 serial_out(up, UART_TX, up->port.x_char);
 260                 up->port.icount.tx++;
 261                 up->port.x_char = 0;
 262                 return;
 263         }
 264         if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
 265                 serial_omap_stop_tx(&up->port);
 266                 return;
 267         }
 268         count = up->port.fifosize / 4;
 269         do {
 270                 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
 271                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 272                 up->port.icount.tx++;
 273                 if (uart_circ_empty(xmit))
 274                         break;
 275         } while (--count > 0);
 276
 277         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
 278                 spin_unlock(&up->port.lock);
 279                 uart_write_wakeup(&up->port);
 280                 spin_lock(&up->port.lock);
 281         }
 282
 283         if (uart_circ_empty(xmit))
 284                 serial_omap_stop_tx(&up->port);
 285 }
 286
 287 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
 288 {
 289         if (!(up->ier & UART_IER_THRI)) {
 290                 up->ier |= UART_IER_THRI;
 291                 serial_out(up, UART_IER, up->ier);
 292         }
 293 }
 294
 295 static void serial_omap_start_tx(struct uart_port *port)
 296 {
 297         struct uart_omap_port *up = to_uart_omap_port(port);
 298
 299         pm_runtime_get_sync(up->dev);
 300         serial_omap_enable_ier_thri(up);
 301         serial_omap_set_noidle(up);
 302         pm_runtime_mark_last_busy(up->dev);
 303         pm_runtime_put_autosuspend(up->dev);
 304 }
 305
 306 static unsigned int check_modem_status(struct uart_omap_port *up)
 307 {
 308         unsigned int status;
 309
 310         status = serial_in(up, UART_MSR);
 311         status |= up->msr_saved_flags;
 312         up->msr_saved_flags = 0;
 313         if ((status & UART_MSR_ANY_DELTA) == 0)
 314                 return status;
 315
 316         if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
 317             up->port.state != NULL) {
 318                 if (status & UART_MSR_TERI)
 319                         up->port.icount.rng++;
 320                 if (status & UART_MSR_DDSR)
 321                         up->port.icount.dsr++;
 322                 if (status & UART_MSR_DDCD)
 323                         uart_handle_dcd_change
 324                                 (&up->port, status & UART_MSR_DCD);
 325                 if (status & UART_MSR_DCTS)
 326                         uart_handle_cts_change
 327                                 (&up->port, status & UART_MSR_CTS);
 328                 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
 329         }
 330
 331         return status;
 332 }
 333
 334 static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)
 335 {
 336         unsigned int flag;
 337         unsigned char ch = 0;
 338
 339         if (likely(lsr & UART_LSR_DR))
 340                 ch = serial_in(up, UART_RX);
 341
 342         up->port.icount.rx++;
 343         flag = TTY_NORMAL;
 344
 345         if (lsr & UART_LSR_BI) {
 346                 flag = TTY_BREAK;
 347                 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
 348                 up->port.icount.brk++;
 349                 /*
 350                  * We do the SysRQ and SAK checking
 351                  * here because otherwise the break
 352                  * may get masked by ignore_status_mask
 353                  * or read_status_mask.
 354                  */
 355                 if (uart_handle_break(&up->port))
 356                         return;
 357
 358         }
 359
 360         if (lsr & UART_LSR_PE) {
 361                 flag = TTY_PARITY;
 362                 up->port.icount.parity++;
 363         }
 364
 365         if (lsr & UART_LSR_FE) {
 366                 flag = TTY_FRAME;
 367                 up->port.icount.frame++;
 368         }
 369
 370         if (lsr & UART_LSR_OE)
 371                 up->port.icount.overrun++;
 372
 373 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
 374         if (up->port.line == up->port.cons->index) {
 375                 /* Recover the break flag from console xmit */
 376                 lsr |= up->lsr_break_flag;
 377         }
 378 #endif
 379         uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);
 380 }
 381
 382 static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
 383 {
 384         unsigned char ch = 0;
 385         unsigned int flag;
 386
 387         if (!(lsr & UART_LSR_DR))
 388                 return;
 389
 390         ch = serial_in(up, UART_RX);
 391         flag = TTY_NORMAL;
 392         up->port.icount.rx++;
 393
 394         if (uart_handle_sysrq_char(&up->port, ch))
 395                 return;
 396
 397         uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
 398 }
 399
 400 /**
 401  * serial_omap_irq() - This handles the interrupt from one port
 402  * @irq: uart port irq number
 403  * @dev_id: uart port info
 404  */
 405 static irqreturn_t serial_omap_irq(int irq, void *dev_id)
 406 {
 407         struct uart_omap_port *up = dev_id;
 408         struct tty_struct *tty = up->port.state->port.tty;
 409         unsigned int iir, lsr;
 410         unsigned int type;
 411         irqreturn_t ret = IRQ_NONE;
 412         int max_count = 256;
 413
 414         spin_lock(&up->port.lock);
 415         pm_runtime_get_sync(up->dev);
 416
 417         do {
 418                 iir = serial_in(up, UART_IIR);
 419                 if (iir & UART_IIR_NO_INT)
 420                         break;
 421
 422                 ret = IRQ_HANDLED;
 423                 lsr = serial_in(up, UART_LSR);
 424
 425                 /* extract IRQ type from IIR register */
 426                 type = iir & 0x3e;
 427
 428                 switch (type) {
 429                 case UART_IIR_MSI:
 430                         check_modem_status(up);
 431                         break;
 432                 case UART_IIR_THRI:
 433                         transmit_chars(up, lsr);
 434                         break;
 435                 case UART_IIR_RX_TIMEOUT:
 436                         /* FALLTHROUGH */
 437                 case UART_IIR_RDI:
 438                         serial_omap_rdi(up, lsr);
 439                         break;
 440                 case UART_IIR_RLSI:
 441                         serial_omap_rlsi(up, lsr);
 442                         break;
 443                 case UART_IIR_CTS_RTS_DSR:
 444                         /* simply try again */
 445                         break;
 446                 case UART_IIR_XOFF:
 447                         /* FALLTHROUGH */
 448                 default:
 449                         break;
 450                 }
 451         } while (!(iir & UART_IIR_NO_INT) && max_count--);
 452
 453         spin_unlock(&up->port.lock);
 454
 455         tty_flip_buffer_push(tty);
 456
 457         pm_runtime_mark_last_busy(up->dev);
 458         pm_runtime_put_autosuspend(up->dev);
 459         up->port_activity = jiffies;
 460
 461         return ret;
 462 }
 463
 464 static unsigned int serial_omap_tx_empty(struct uart_port *port)
 465 {
 466         struct uart_omap_port *up = to_uart_omap_port(port);
 467         unsigned long flags = 0;
 468         unsigned int ret = 0;
 469
 470         pm_runtime_get_sync(up->dev);
 471         dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
 472         spin_lock_irqsave(&up->port.lock, flags);
 473         ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
 474         spin_unlock_irqrestore(&up->port.lock, flags);
 475         pm_runtime_mark_last_busy(up->dev);
 476         pm_runtime_put_autosuspend(up->dev);
 477         return ret;
 478 }
 479
 480 static unsigned int serial_omap_get_mctrl(struct uart_port *port)
 481 {
 482         struct uart_omap_port *up = to_uart_omap_port(port);
 483         unsigned int status;
 484         unsigned int ret = 0;
 485
 486         pm_runtime_get_sync(up->dev);
 487         status = check_modem_status(up);
 488         pm_runtime_mark_last_busy(up->dev);
 489         pm_runtime_put_autosuspend(up->dev);
 490
 491         dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
 492
 493         if (status & UART_MSR_DCD)
 494                 ret |= TIOCM_CAR;
 495         if (status & UART_MSR_RI)
 496                 ret |= TIOCM_RNG;
 497         if (status & UART_MSR_DSR)
 498                 ret |= TIOCM_DSR;
 499         if (status & UART_MSR_CTS)
 500                 ret |= TIOCM_CTS;
 501         return ret;
 502 }
 503
 504 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
 505 {
 506         struct uart_omap_port *up = to_uart_omap_port(port);
 507         unsigned char mcr = 0, old_mcr;
 508
 509         dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
 510         if (mctrl & TIOCM_RTS)
 511                 mcr |= UART_MCR_RTS;
 512         if (mctrl & TIOCM_DTR)
 513                 mcr |= UART_MCR_DTR;
 514         if (mctrl & TIOCM_OUT1)
 515                 mcr |= UART_MCR_OUT1;
 516         if (mctrl & TIOCM_OUT2)
 517                 mcr |= UART_MCR_OUT2;
 518         if (mctrl & TIOCM_LOOP)
 519                 mcr |= UART_MCR_LOOP;
 520
 521         pm_runtime_get_sync(up->dev);
 522         old_mcr = serial_in(up, UART_MCR);
 523         old_mcr &= ~(UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_OUT1 |
 524                      UART_MCR_DTR | UART_MCR_RTS);
 525         up->mcr = old_mcr | mcr;
 526         serial_out(up, UART_MCR, up->mcr);
 527         pm_runtime_mark_last_busy(up->dev);
 528         pm_runtime_put_autosuspend(up->dev);
 529
 530         if (gpio_is_valid(up->DTR_gpio) &&
 531             !!(mctrl & TIOCM_DTR) != up->DTR_active) {
 532                 up->DTR_active = !up->DTR_active;
 533                 if (gpio_cansleep(up->DTR_gpio))
 534                         schedule_work(&up->qos_work);
 535                 else
 536                         gpio_set_value(up->DTR_gpio,
 537                                        up->DTR_active != up->DTR_inverted);
 538         }
 539 }
 540
 541 static void serial_omap_break_ctl(struct uart_port *port, int break_state)
 542 {
 543         struct uart_omap_port *up = to_uart_omap_port(port);
 544         unsigned long flags = 0;
 545
 546         dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
 547         pm_runtime_get_sync(up->dev);
 548         spin_lock_irqsave(&up->port.lock, flags);
 549         if (break_state == -1)
 550                 up->lcr |= UART_LCR_SBC;
 551         else
 552                 up->lcr &= ~UART_LCR_SBC;
 553         serial_out(up, UART_LCR, up->lcr);
 554         spin_unlock_irqrestore(&up->port.lock, flags);
 555         pm_runtime_mark_last_busy(up->dev);
 556         pm_runtime_put_autosuspend(up->dev);
 557 }
 558
 559 static int serial_omap_startup(struct uart_port *port)
 560 {
 561         struct uart_omap_port *up = to_uart_omap_port(port);
 562         unsigned long flags = 0;
 563         int retval;
 564
 565         /*
 566          * Allocate the IRQ
 567          */
 568         retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
 569                                 up->name, up);
 570         if (retval)
 571                 return retval;
 572
 573         dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
 574
 575         pm_runtime_get_sync(up->dev);
 576         /*
 577          * Clear the FIFO buffers and disable them.
 578          * (they will be reenabled in set_termios())
 579          */
 580         serial_omap_clear_fifos(up);
 581         /* For Hardware flow control */
 582         serial_out(up, UART_MCR, UART_MCR_RTS);
 583
 584         /*
 585          * Clear the interrupt registers.
 586          */
 587         (void) serial_in(up, UART_LSR);
 588         if (serial_in(up, UART_LSR) & UART_LSR_DR)
 589                 (void) serial_in(up, UART_RX);
 590         (void) serial_in(up, UART_IIR);
 591         (void) serial_in(up, UART_MSR);
 592
 593         /*
 594          * Now, initialize the UART
 595          */
 596         serial_out(up, UART_LCR, UART_LCR_WLEN8);
 597         spin_lock_irqsave(&up->port.lock, flags);
 598         /*
 599          * Most PC uarts need OUT2 raised to enable interrupts.
 600          */
 601         up->port.mctrl |= TIOCM_OUT2;
 602         serial_omap_set_mctrl(&up->port, up->port.mctrl);
 603         spin_unlock_irqrestore(&up->port.lock, flags);
 604
 605         up->msr_saved_flags = 0;
 606         /*
 607          * Finally, enable interrupts. Note: Modem status interrupts
 608          * are set via set_termios(), which will be occurring imminently
 609          * anyway, so we don't enable them here.
 610          */
 611         up->ier = UART_IER_RLSI | UART_IER_RDI;
 612         serial_out(up, UART_IER, up->ier);
 613
 614         /* Enable module level wake up */
 615         serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP);
 616
 617         pm_runtime_mark_last_busy(up->dev);
 618         pm_runtime_put_autosuspend(up->dev);
 619         up->port_activity = jiffies;
 620         return 0;
 621 }
 622
 623 static void serial_omap_shutdown(struct uart_port *port)
 624 {
 625         struct uart_omap_port *up = to_uart_omap_port(port);
 626         unsigned long flags = 0;
 627
 628         dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
 629
 630         pm_runtime_get_sync(up->dev);
 631         /*
 632          * Disable interrupts from this port
 633          */
 634         up->ier = 0;
 635         serial_out(up, UART_IER, 0);
 636
 637         spin_lock_irqsave(&up->port.lock, flags);
 638         up->port.mctrl &= ~TIOCM_OUT2;
 639         serial_omap_set_mctrl(&up->port, up->port.mctrl);
 640         spin_unlock_irqrestore(&up->port.lock, flags);
 641
 642         /*
 643          * Disable break condition and FIFOs
 644          */
 645         serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
 646         serial_omap_clear_fifos(up);
 647
 648         /*
 649          * Read data port to reset things, and then free the irq
 650          */
 651         if (serial_in(up, UART_LSR) & UART_LSR_DR)
 652                 (void) serial_in(up, UART_RX);
 653
 654         pm_runtime_mark_last_busy(up->dev);
 655         pm_runtime_put_autosuspend(up->dev);
 656         free_irq(up->port.irq, up);
 657 }
 658
 659 static inline void
 660 serial_omap_configure_xonxoff
 661                 (struct uart_omap_port *up, struct ktermios *termios)
 662 {
 663         up->lcr = serial_in(up, UART_LCR);
 664         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 665         up->efr = serial_in(up, UART_EFR);
 666         serial_out(up, UART_EFR, up->efr & ~UART_EFR_ECB);
 667
 668         serial_out(up, UART_XON1, termios->c_cc[VSTART]);
 669         serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
 670
 671         /* clear SW control mode bits */
 672         up->efr &= OMAP_UART_SW_CLR;
 673
 674         /*
 675          * IXON Flag:
 676          * Enable XON/XOFF flow control on output.
 677          * Transmit XON1, XOFF1
 678          */
 679         if (termios->c_iflag & IXON)
 680                 up->efr |= OMAP_UART_SW_TX;
 681
 682         /*
 683          * IXOFF Flag:
 684          * Enable XON/XOFF flow control on input.
 685          * Receiver compares XON1, XOFF1.
 686          */
 687         if (termios->c_iflag & IXOFF)
 688                 up->efr |= OMAP_UART_SW_RX;
 689
 690         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 691         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 692
 693         up->mcr = serial_in(up, UART_MCR);
 694
 695         /*
 696          * IXANY Flag:
 697          * Enable any character to restart output.
 698          * Operation resumes after receiving any
 699          * character after recognition of the XOFF character
 700          */
 701         if (termios->c_iflag & IXANY)
 702                 up->mcr |= UART_MCR_XONANY;
 703         else
 704                 up->mcr &= ~UART_MCR_XONANY;
 705
 706         serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
 707         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 708         serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
 709         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 710         serial_out(up, UART_MCR, up->mcr & ~UART_MCR_TCRTLR);
 711         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 712         serial_out(up, UART_EFR, up->efr);
 713         serial_out(up, UART_LCR, up->lcr);
 714 }
 715
 716 static void serial_omap_uart_qos_work(struct work_struct *work)
 717 {
 718         struct uart_omap_port *up = container_of(work, struct uart_omap_port,
 719                                                 qos_work);
 720
 721         pm_qos_update_request(&up->pm_qos_request, up->latency);
 722         if (gpio_is_valid(up->DTR_gpio))
 723                 gpio_set_value_cansleep(up->DTR_gpio,
 724                                         up->DTR_active != up->DTR_inverted);
 725 }
 726
 727 static void
 728 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
 729                         struct ktermios *old)
 730 {
 731         struct uart_omap_port *up = to_uart_omap_port(port);
 732         unsigned char cval = 0;
 733         unsigned long flags = 0;
 734         unsigned int baud, quot;
 735
 736         switch (termios->c_cflag & CSIZE) {
 737         case CS5:
 738                 cval = UART_LCR_WLEN5;
 739                 break;
 740         case CS6:
 741                 cval = UART_LCR_WLEN6;
 742                 break;
 743         case CS7:
 744                 cval = UART_LCR_WLEN7;
 745                 break;
 746         default:
 747         case CS8:
 748                 cval = UART_LCR_WLEN8;
 749                 break;
 750         }
 751
 752         if (termios->c_cflag & CSTOPB)
 753                 cval |= UART_LCR_STOP;
 754         if (termios->c_cflag & PARENB)
 755                 cval |= UART_LCR_PARITY;
 756         if (!(termios->c_cflag & PARODD))
 757                 cval |= UART_LCR_EPAR;
 758
 759         /*
 760          * Ask the core to calculate the divisor for us.
 761          */
 762
 763         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
 764         quot = serial_omap_get_divisor(port, baud);
 765
 766         /* calculate wakeup latency constraint */
 767         up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8);
 768         up->latency = up->calc_latency;
 769         schedule_work(&up->qos_work);
 770
 771         up->dll = quot & 0xff;
 772         up->dlh = quot >> 8;
 773         up->mdr1 = UART_OMAP_MDR1_DISABLE;
 774
 775         up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
 776                         UART_FCR_ENABLE_FIFO;
 777
 778         /*
 779          * Ok, we're now changing the port state. Do it with
 780          * interrupts disabled.
 781          */
 782         pm_runtime_get_sync(up->dev);
 783         spin_lock_irqsave(&up->port.lock, flags);
 784
 785         /*
 786          * Update the per-port timeout.
 787          */
 788         uart_update_timeout(port, termios->c_cflag, baud);
 789
 790         up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
 791         if (termios->c_iflag & INPCK)
 792                 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
 793         if (termios->c_iflag & (BRKINT | PARMRK))
 794                 up->port.read_status_mask |= UART_LSR_BI;
 795
 796         /*
 797          * Characters to ignore
 798          */
 799         up->port.ignore_status_mask = 0;
 800         if (termios->c_iflag & IGNPAR)
 801                 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
 802         if (termios->c_iflag & IGNBRK) {
 803                 up->port.ignore_status_mask |= UART_LSR_BI;
 804                 /*
 805                  * If we're ignoring parity and break indicators,
 806                  * ignore overruns too (for real raw support).
 807                  */
 808                 if (termios->c_iflag & IGNPAR)
 809                         up->port.ignore_status_mask |= UART_LSR_OE;
 810         }
 811
 812         /*
 813          * ignore all characters if CREAD is not set
 814          */
 815         if ((termios->c_cflag & CREAD) == 0)
 816                 up->port.ignore_status_mask |= UART_LSR_DR;
 817
 818         /*
 819          * Modem status interrupts
 820          */
 821         up->ier &= ~UART_IER_MSI;
 822         if (UART_ENABLE_MS(&up->port, termios->c_cflag))
 823                 up->ier |= UART_IER_MSI;
 824         serial_out(up, UART_IER, up->ier);
 825         serial_out(up, UART_LCR, cval);         /* reset DLAB */
 826         up->lcr = cval;
 827         up->scr = OMAP_UART_SCR_TX_EMPTY;
 828
 829         /* FIFOs and DMA Settings */
 830
 831         /* FCR can be changed only when the
 832          * baud clock is not running
 833          * DLL_REG and DLH_REG set to 0.
 834          */
 835         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 836         serial_out(up, UART_DLL, 0);
 837         serial_out(up, UART_DLM, 0);
 838         serial_out(up, UART_LCR, 0);
 839
 840         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 841
 842         up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB;
 843         up->efr &= ~UART_EFR_SCD;
 844         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 845
 846         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 847         up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR;
 848         serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
 849         /* FIFO ENABLE, DMA MODE */
 850
 851         up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
 852
 853         /* Set receive FIFO threshold to 16 characters and
 854          * transmit FIFO threshold to 16 spaces
 855          */
 856         up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
 857         up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK;
 858         up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 |
 859                 UART_FCR_ENABLE_FIFO;
 860
 861         serial_out(up, UART_FCR, up->fcr);
 862         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 863
 864         serial_out(up, UART_OMAP_SCR, up->scr);
 865
 866         /* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */
 867         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 868         serial_out(up, UART_MCR, up->mcr);
 869         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 870         serial_out(up, UART_EFR, up->efr);
 871         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 872
 873         /* Protocol, Baud Rate, and Interrupt Settings */
 874
 875         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
 876                 serial_omap_mdr1_errataset(up, up->mdr1);
 877         else
 878                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
 879
 880         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 881         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 882
 883         serial_out(up, UART_LCR, 0);
 884         serial_out(up, UART_IER, 0);
 885         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 886
 887         serial_out(up, UART_DLL, up->dll);      /* LS of divisor */
 888         serial_out(up, UART_DLM, up->dlh);      /* MS of divisor */
 889
 890         serial_out(up, UART_LCR, 0);
 891         serial_out(up, UART_IER, up->ier);
 892         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 893
 894         serial_out(up, UART_EFR, up->efr);
 895         serial_out(up, UART_LCR, cval);
 896
 897         if (baud > 230400 && baud != 3000000)
 898                 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
 899         else
 900                 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
 901
 902         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
 903                 serial_omap_mdr1_errataset(up, up->mdr1);
 904         else
 905                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
 906
 907         /* Hardware Flow Control Configuration */
 908
 909         if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
 910                 /* Enable access to TCR/TLR */
 911                 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 912                 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 913                 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 914                 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
 915
 916                 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
 917
 918                 /* Enable AUTORTS and AUTOCTS */
 919                 up->efr |= UART_EFR_CTS | UART_EFR_RTS;
 920
 921                 /* Disable access to TCR/TLR */
 922                 serial_out(up, UART_MCR, up->mcr | UART_MCR_RTS);
 923                 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 924                 serial_out(up, UART_EFR, up->efr);
 925                 serial_out(up, UART_LCR, cval);
 926         } else {
 927                 /* Disable AUTORTS and AUTOCTS */
 928                 up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS);
 929
 930                 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 931                 serial_out(up, UART_EFR, up->efr);
 932                 serial_out(up, UART_LCR, cval);
 933         }
 934
 935         serial_omap_set_mctrl(&up->port, up->port.mctrl);
 936         /* Software Flow Control Configuration */
 937         if (up->port.flags & UPF_SOFT_FLOW)
 938                 serial_omap_configure_xonxoff(up, termios);
 939
 940         spin_unlock_irqrestore(&up->port.lock, flags);
 941         pm_runtime_mark_last_busy(up->dev);
 942         pm_runtime_put_autosuspend(up->dev);
 943         dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
 944 }
 945
 946 static int serial_omap_set_wake(struct uart_port *port, unsigned int state)
 947 {
 948         struct uart_omap_port *up = to_uart_omap_port(port);
 949
 950         serial_omap_enable_wakeup(up, state);
 951
 952         return 0;
 953 }
 954
 955 static void
 956 serial_omap_pm(struct uart_port *port, unsigned int state,
 957                unsigned int oldstate)
 958 {
 959         struct uart_omap_port *up = to_uart_omap_port(port);
 960         unsigned char efr;
 961
 962         dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
 963
 964         pm_runtime_get_sync(up->dev);
 965         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 966         efr = serial_in(up, UART_EFR);
 967         serial_out(up, UART_EFR, efr | UART_EFR_ECB);
 968         serial_out(up, UART_LCR, 0);
 969
 970         serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
 971         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 972         serial_out(up, UART_EFR, efr);
 973         serial_out(up, UART_LCR, 0);
 974
 975         if (!device_may_wakeup(up->dev)) {
 976                 if (!state)
 977                         pm_runtime_forbid(up->dev);
 978                 else
 979                         pm_runtime_allow(up->dev);
 980         }
 981
 982         pm_runtime_mark_last_busy(up->dev);
 983         pm_runtime_put_autosuspend(up->dev);
 984 }
 985
 986 static void serial_omap_release_port(struct uart_port *port)
 987 {
 988         dev_dbg(port->dev, "serial_omap_release_port+\n");
 989 }
 990
 991 static int serial_omap_request_port(struct uart_port *port)
 992 {
 993         dev_dbg(port->dev, "serial_omap_request_port+\n");
 994         return 0;
 995 }
 996
 997 static void serial_omap_config_port(struct uart_port *port, int flags)
 998 {
 999         struct uart_omap_port *up = to_uart_omap_port(port);
1000
1001         dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
1002                                                         up->port.line);
1003         up->port.type = PORT_OMAP;
1004 }
1005
1006 static int
1007 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
1008 {
1009         /* we don't want the core code to modify any port params */
1010         dev_dbg(port->dev, "serial_omap_verify_port+\n");
1011         return -EINVAL;
1012 }
1013
1014 static const char *
1015 serial_omap_type(struct uart_port *port)
1016 {
1017         struct uart_omap_port *up = to_uart_omap_port(port);
1018
1019         dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
1020         return up->name;
1021 }
1022
1023 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1024
1025 static inline void wait_for_xmitr(struct uart_omap_port *up)
1026 {
1027         unsigned int status, tmout = 10000;
1028
1029         /* Wait up to 10ms for the character(s) to be sent. */
1030         do {
1031                 status = serial_in(up, UART_LSR);
1032
1033                 if (status & UART_LSR_BI)
1034                         up->lsr_break_flag = UART_LSR_BI;
1035
1036                 if (--tmout == 0)
1037                         break;
1038                 udelay(1);
1039         } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
1040
1041         /* Wait up to 1s for flow control if necessary */
1042         if (up->port.flags & UPF_CONS_FLOW) {
1043                 tmout = 1000000;
1044                 for (tmout = 1000000; tmout; tmout--) {
1045                         unsigned int msr = serial_in(up, UART_MSR);
1046
1047                         up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1048                         if (msr & UART_MSR_CTS)
1049                                 break;
1050
1051                         udelay(1);
1052                 }
1053         }
1054 }
1055
1056 #ifdef CONFIG_CONSOLE_POLL
1057
1058 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
1059 {
1060         struct uart_omap_port *up = to_uart_omap_port(port);
1061
1062         pm_runtime_get_sync(up->dev);
1063         wait_for_xmitr(up);
1064         serial_out(up, UART_TX, ch);
1065         pm_runtime_mark_last_busy(up->dev);
1066         pm_runtime_put_autosuspend(up->dev);
1067 }
1068
1069 static int serial_omap_poll_get_char(struct uart_port *port)
1070 {
1071         struct uart_omap_port *up = to_uart_omap_port(port);
1072         unsigned int status;
1073
1074         pm_runtime_get_sync(up->dev);
1075         status = serial_in(up, UART_LSR);
1076         if (!(status & UART_LSR_DR)) {
1077                 status = NO_POLL_CHAR;
1078                 goto out;
1079         }
1080
1081         status = serial_in(up, UART_RX);
1082
1083 out:
1084         pm_runtime_mark_last_busy(up->dev);
1085         pm_runtime_put_autosuspend(up->dev);
1086
1087         return status;
1088 }
1089
1090 #endif /* CONFIG_CONSOLE_POLL */
1091
1092 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
1093
1094 static struct uart_omap_port *serial_omap_console_ports[4];
1095
1096 static struct uart_driver serial_omap_reg;
1097
1098 static void serial_omap_console_putchar(struct uart_port *port, int ch)
1099 {
1100         struct uart_omap_port *up = to_uart_omap_port(port);
1101
1102         wait_for_xmitr(up);
1103         serial_out(up, UART_TX, ch);
1104 }
1105
1106 static void
1107 serial_omap_console_write(struct console *co, const char *s,
1108                 unsigned int count)
1109 {
1110         struct uart_omap_port *up = serial_omap_console_ports[co->index];
1111         unsigned long flags;
1112         unsigned int ier;
1113         int locked = 1;
1114
1115         pm_runtime_get_sync(up->dev);
1116
1117         local_irq_save(flags);
1118         if (up->port.sysrq)
1119                 locked = 0;
1120         else if (oops_in_progress)
1121                 locked = spin_trylock(&up->port.lock);
1122         else
1123                 spin_lock(&up->port.lock);
1124
1125         /*
1126          * First save the IER then disable the interrupts
1127          */
1128         ier = serial_in(up, UART_IER);
1129         serial_out(up, UART_IER, 0);
1130
1131         uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1132
1133         /*
1134          * Finally, wait for transmitter to become empty
1135          * and restore the IER
1136          */
1137         wait_for_xmitr(up);
1138         serial_out(up, UART_IER, ier);
1139         /*
1140          * The receive handling will happen properly because the
1141          * receive ready bit will still be set; it is not cleared
1142          * on read.  However, modem control will not, we must
1143          * call it if we have saved something in the saved flags
1144          * while processing with interrupts off.
1145          */
1146         if (up->msr_saved_flags)
1147                 check_modem_status(up);
1148
1149         pm_runtime_mark_last_busy(up->dev);
1150         pm_runtime_put_autosuspend(up->dev);
1151         if (locked)
1152                 spin_unlock(&up->port.lock);
1153         local_irq_restore(flags);
1154 }
1155
1156 static int __init
1157 serial_omap_console_setup(struct console *co, char *options)
1158 {
1159         struct uart_omap_port *up;
1160         int baud = 115200;
1161         int bits = 8;
1162         int parity = 'n';
1163         int flow = 'n';
1164
1165         if (serial_omap_console_ports[co->index] == NULL)
1166                 return -ENODEV;
1167         up = serial_omap_console_ports[co->index];
1168
1169         if (options)
1170                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1171
1172         return uart_set_options(&up->port, co, baud, parity, bits, flow);
1173 }
1174
1175 static struct console serial_omap_console = {
1176         .name           = OMAP_SERIAL_NAME,
1177         .write          = serial_omap_console_write,
1178         .device         = uart_console_device,
1179         .setup          = serial_omap_console_setup,
1180         .flags          = CON_PRINTBUFFER,
1181         .index          = -1,
1182         .data           = &serial_omap_reg,
1183 };
1184
1185 static void serial_omap_add_console_port(struct uart_omap_port *up)
1186 {
1187         serial_omap_console_ports[up->port.line] = up;
1188 }
1189
1190 #define OMAP_CONSOLE    (&serial_omap_console)
1191
1192 #else
1193
1194 #define OMAP_CONSOLE    NULL
1195
1196 static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1197 {}
1198
1199 #endif
1200
1201 static struct uart_ops serial_omap_pops = {
1202         .tx_empty       = serial_omap_tx_empty,
1203         .set_mctrl      = serial_omap_set_mctrl,
1204         .get_mctrl      = serial_omap_get_mctrl,
1205         .stop_tx        = serial_omap_stop_tx,
1206         .start_tx       = serial_omap_start_tx,
1207         .stop_rx        = serial_omap_stop_rx,
1208         .enable_ms      = serial_omap_enable_ms,
1209         .break_ctl      = serial_omap_break_ctl,
1210         .startup        = serial_omap_startup,
1211         .shutdown       = serial_omap_shutdown,
1212         .set_termios    = serial_omap_set_termios,
1213         .pm             = serial_omap_pm,
1214         .set_wake       = serial_omap_set_wake,
1215         .type           = serial_omap_type,
1216         .release_port   = serial_omap_release_port,
1217         .request_port   = serial_omap_request_port,
1218         .config_port    = serial_omap_config_port,
1219         .verify_port    = serial_omap_verify_port,
1220 #ifdef CONFIG_CONSOLE_POLL
1221         .poll_put_char  = serial_omap_poll_put_char,
1222         .poll_get_char  = serial_omap_poll_get_char,
1223 #endif
1224 };
1225
1226 static struct uart_driver serial_omap_reg = {
1227         .owner          = THIS_MODULE,
1228         .driver_name    = "OMAP-SERIAL",
1229         .dev_name       = OMAP_SERIAL_NAME,
1230         .nr             = OMAP_MAX_HSUART_PORTS,
1231         .cons           = OMAP_CONSOLE,
1232 };
1233
1234 #ifdef CONFIG_PM_SLEEP
1235 static int serial_omap_suspend(struct device *dev)
1236 {
1237         struct uart_omap_port *up = dev_get_drvdata(dev);
1238
1239         uart_suspend_port(&serial_omap_reg, &up->port);
1240         flush_work(&up->qos_work);
1241
1242         return 0;
1243 }
1244
1245 static int serial_omap_resume(struct device *dev)
1246 {
1247         struct uart_omap_port *up = dev_get_drvdata(dev);
1248
1249         uart_resume_port(&serial_omap_reg, &up->port);
1250
1251         return 0;
1252 }
1253 #endif
1254
1255 static void __devinit omap_serial_fill_features_erratas(struct uart_omap_port *up)
1256 {
1257         u32 mvr, scheme;
1258         u16 revision, major, minor;
1259
1260         mvr = serial_in(up, UART_OMAP_MVER);
1261
1262         /* Check revision register scheme */
1263         scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
1264
1265         switch (scheme) {
1266         case 0: /* Legacy Scheme: OMAP2/3 */
1267                 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
1268                 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
1269                                         OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
1270                 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
1271                 break;
1272         case 1:
1273                 /* New Scheme: OMAP4+ */
1274                 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
1275                 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
1276                                         OMAP_UART_MVR_MAJ_SHIFT;
1277                 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
1278                 break;
1279         default:
1280                 dev_warn(up->dev,
1281                         "Unknown %s revision, defaulting to highest\n",
1282                         up->name);
1283                 /* highest possible revision */
1284                 major = 0xff;
1285                 minor = 0xff;
1286         }
1287
1288         /* normalize revision for the driver */
1289         revision = UART_BUILD_REVISION(major, minor);
1290
1291         switch (revision) {
1292         case OMAP_UART_REV_46:
1293                 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1294                                 UART_ERRATA_i291_DMA_FORCEIDLE);
1295                 break;
1296         case OMAP_UART_REV_52:
1297                 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1298                                 UART_ERRATA_i291_DMA_FORCEIDLE);
1299                 break;
1300         case OMAP_UART_REV_63:
1301                 up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
1302                 break;
1303         default:
1304                 break;
1305         }
1306 }
1307
1308 static __devinit struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
1309 {
1310         struct omap_uart_port_info *omap_up_info;
1311
1312         omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
1313         if (!omap_up_info)
1314                 return NULL; /* out of memory */
1315
1316         of_property_read_u32(dev->of_node, "clock-frequency",
1317                                          &omap_up_info->uartclk);
1318         return omap_up_info;
1319 }
1320
1321 static int __devinit serial_omap_probe(struct platform_device *pdev)
1322 {
1323         struct uart_omap_port   *up;
1324         struct resource         *mem, *irq;
1325         struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data;
1326         int ret;
1327
1328         if (pdev->dev.of_node)
1329                 omap_up_info = of_get_uart_port_info(&pdev->dev);
1330
1331         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1332         if (!mem) {
1333                 dev_err(&pdev->dev, "no mem resource?\n");
1334                 return -ENODEV;
1335         }
1336
1337         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1338         if (!irq) {
1339                 dev_err(&pdev->dev, "no irq resource?\n");
1340                 return -ENODEV;
1341         }
1342
1343         if (!devm_request_mem_region(&pdev->dev, mem->start, resource_size(mem),
1344                                 pdev->dev.driver->name)) {
1345                 dev_err(&pdev->dev, "memory region already claimed\n");
1346                 return -EBUSY;
1347         }
1348
1349         if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1350             omap_up_info->DTR_present) {
1351                 ret = gpio_request(omap_up_info->DTR_gpio, "omap-serial");
1352                 if (ret < 0)
1353                         return ret;
1354                 ret = gpio_direction_output(omap_up_info->DTR_gpio,
1355                                             omap_up_info->DTR_inverted);
1356                 if (ret < 0)
1357                         return ret;
1358         }
1359
1360         up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
1361         if (!up)
1362                 return -ENOMEM;
1363
1364         if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1365             omap_up_info->DTR_present) {
1366                 up->DTR_gpio = omap_up_info->DTR_gpio;
1367                 up->DTR_inverted = omap_up_info->DTR_inverted;
1368         } else
1369                 up->DTR_gpio = -EINVAL;
1370         up->DTR_active = 0;
1371
1372         up->dev = &pdev->dev;
1373         up->port.dev = &pdev->dev;
1374         up->port.type = PORT_OMAP;
1375         up->port.iotype = UPIO_MEM;
1376         up->port.irq = irq->start;
1377
1378         up->port.regshift = 2;
1379         up->port.fifosize = 64;
1380         up->port.ops = &serial_omap_pops;
1381
1382         if (pdev->dev.of_node)
1383                 up->port.line = of_alias_get_id(pdev->dev.of_node, "serial");
1384         else
1385                 up->port.line = pdev->id;
1386
1387         if (up->port.line < 0) {
1388                 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
1389                                                                 up->port.line);
1390                 ret = -ENODEV;
1391                 goto err_port_line;
1392         }
1393
1394         up->pins = devm_pinctrl_get_select_default(&pdev->dev);
1395         if (IS_ERR(up->pins)) {
1396                 dev_warn(&pdev->dev, "did not get pins for uart%i error: %li\n",
1397                          up->port.line, PTR_ERR(up->pins));
1398                 up->pins = NULL;
1399         }
1400
1401         sprintf(up->name, "OMAP UART%d", up->port.line);
1402         up->port.mapbase = mem->start;
1403         up->port.membase = devm_ioremap(&pdev->dev, mem->start,
1404                                                 resource_size(mem));
1405         if (!up->port.membase) {
1406                 dev_err(&pdev->dev, "can't ioremap UART\n");
1407                 ret = -ENOMEM;
1408                 goto err_ioremap;
1409         }
1410
1411         up->port.flags = omap_up_info->flags;
1412         up->port.uartclk = omap_up_info->uartclk;
1413         if (!up->port.uartclk) {
1414                 up->port.uartclk = DEFAULT_CLK_SPEED;
1415                 dev_warn(&pdev->dev, "No clock speed specified: using default:"
1416                                                 "%d\n", DEFAULT_CLK_SPEED);
1417         }
1418
1419         up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1420         up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1421         pm_qos_add_request(&up->pm_qos_request,
1422                 PM_QOS_CPU_DMA_LATENCY, up->latency);
1423         serial_omap_uart_wq = create_singlethread_workqueue(up->name);
1424         INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1425
1426         platform_set_drvdata(pdev, up);
1427         pm_runtime_enable(&pdev->dev);
1428         pm_runtime_use_autosuspend(&pdev->dev);
1429         pm_runtime_set_autosuspend_delay(&pdev->dev,
1430                         omap_up_info->autosuspend_timeout);
1431
1432         pm_runtime_irq_safe(&pdev->dev);
1433         pm_runtime_get_sync(&pdev->dev);
1434
1435         omap_serial_fill_features_erratas(up);
1436
1437         ui[up->port.line] = up;
1438         serial_omap_add_console_port(up);
1439
1440         ret = uart_add_one_port(&serial_omap_reg, &up->port);
1441         if (ret != 0)
1442                 goto err_add_port;
1443
1444         pm_runtime_mark_last_busy(up->dev);
1445         pm_runtime_put_autosuspend(up->dev);
1446         return 0;
1447
1448 err_add_port:
1449         pm_runtime_put(&pdev->dev);
1450         pm_runtime_disable(&pdev->dev);
1451 err_ioremap:
1452 err_port_line:
1453         dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n",
1454                                 pdev->id, __func__, ret);
1455         return ret;
1456 }
1457
1458 static int __devexit serial_omap_remove(struct platform_device *dev)
1459 {
1460         struct uart_omap_port *up = platform_get_drvdata(dev);
1461
1462         pm_runtime_put_sync(up->dev);
1463         pm_runtime_disable(up->dev);
1464         uart_remove_one_port(&serial_omap_reg, &up->port);
1465         pm_qos_remove_request(&up->pm_qos_request);
1466
1467         return 0;
1468 }
1469
1470 /*
1471  * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1472  * The access to uart register after MDR1 Access
1473  * causes UART to corrupt data.
1474  *
1475  * Need a delay =
1476  * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1477  * give 10 times as much
1478  */
1479 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1480 {
1481         u8 timeout = 255;
1482
1483         serial_out(up, UART_OMAP_MDR1, mdr1);
1484         udelay(2);
1485         serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1486                         UART_FCR_CLEAR_RCVR);
1487         /*
1488          * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1489          * TX_FIFO_E bit is 1.
1490          */
1491         while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1492                                 (UART_LSR_THRE | UART_LSR_DR))) {
1493                 timeout--;
1494                 if (!timeout) {
1495                         /* Should *never* happen. we warn and carry on */
1496                         dev_crit(up->dev, "Errata i202: timedout %x\n",
1497                                                 serial_in(up, UART_LSR));
1498                         break;
1499                 }
1500                 udelay(1);
1501         }
1502 }
1503
1504 #ifdef CONFIG_PM_RUNTIME
1505 static void serial_omap_restore_context(struct uart_omap_port *up)
1506 {
1507         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1508                 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1509         else
1510                 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1511
1512         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1513         serial_out(up, UART_EFR, UART_EFR_ECB);
1514         serial_out(up, UART_LCR, 0x0); /* Operational mode */
1515         serial_out(up, UART_IER, 0x0);
1516         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1517         serial_out(up, UART_DLL, up->dll);
1518         serial_out(up, UART_DLM, up->dlh);
1519         serial_out(up, UART_LCR, 0x0); /* Operational mode */
1520         serial_out(up, UART_IER, up->ier);
1521         serial_out(up, UART_FCR, up->fcr);
1522         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1523         serial_out(up, UART_MCR, up->mcr);
1524         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1525         serial_out(up, UART_OMAP_SCR, up->scr);
1526         serial_out(up, UART_EFR, up->efr);
1527         serial_out(up, UART_LCR, up->lcr);
1528         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1529                 serial_omap_mdr1_errataset(up, up->mdr1);
1530         else
1531                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1532 }
1533
1534 static int serial_omap_runtime_suspend(struct device *dev)
1535 {
1536         struct uart_omap_port *up = dev_get_drvdata(dev);
1537         struct omap_uart_port_info *pdata = dev->platform_data;
1538
1539         if (!up)
1540                 return -EINVAL;
1541
1542         if (!pdata)
1543                 return 0;
1544
1545         up->context_loss_cnt = serial_omap_get_context_loss_count(up);
1546
1547         if (device_may_wakeup(dev)) {
1548                 if (!up->wakeups_enabled) {
1549                         serial_omap_enable_wakeup(up, true);
1550                         up->wakeups_enabled = true;
1551                 }
1552         } else {
1553                 if (up->wakeups_enabled) {
1554                         serial_omap_enable_wakeup(up, false);
1555                         up->wakeups_enabled = false;
1556                 }
1557         }
1558
1559         up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1560         schedule_work(&up->qos_work);
1561
1562         return 0;
1563 }
1564
1565 static int serial_omap_runtime_resume(struct device *dev)
1566 {
1567         struct uart_omap_port *up = dev_get_drvdata(dev);
1568
1569         u32 loss_cnt = serial_omap_get_context_loss_count(up);
1570
1571         if (up->context_loss_cnt != loss_cnt)
1572                 serial_omap_restore_context(up);
1573
1574         up->latency = up->calc_latency;
1575         schedule_work(&up->qos_work);
1576
1577         return 0;
1578 }
1579 #endif
1580
1581 static const struct dev_pm_ops serial_omap_dev_pm_ops = {
1582         SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
1583         SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
1584                                 serial_omap_runtime_resume, NULL)
1585 };
1586
1587 #if defined(CONFIG_OF)
1588 static const struct of_device_id omap_serial_of_match[] = {
1589         { .compatible = "ti,omap2-uart" },
1590         { .compatible = "ti,omap3-uart" },
1591         { .compatible = "ti,omap4-uart" },
1592         {},
1593 };
1594 MODULE_DEVICE_TABLE(of, omap_serial_of_match);
1595 #endif
1596
1597 static struct platform_driver serial_omap_driver = {
1598         .probe          = serial_omap_probe,
1599         .remove         = __devexit_p(serial_omap_remove),
1600         .driver         = {
1601                 .name   = DRIVER_NAME,
1602                 .pm     = &serial_omap_dev_pm_ops,
1603                 .of_match_table = of_match_ptr(omap_serial_of_match),
1604         },
1605 };
1606
1607 static int __init serial_omap_init(void)
1608 {
1609         int ret;
1610
1611         ret = uart_register_driver(&serial_omap_reg);
1612         if (ret != 0)
1613                 return ret;
1614         ret = platform_driver_register(&serial_omap_driver);
1615         if (ret != 0)
1616                 uart_unregister_driver(&serial_omap_reg);
1617         return ret;
1618 }
1619
1620 static void __exit serial_omap_exit(void)
1621 {
1622         platform_driver_unregister(&serial_omap_driver);
1623         uart_unregister_driver(&serial_omap_reg);
1624 }
1625
1626 module_init(serial_omap_init);
1627 module_exit(serial_omap_exit);
1628
1629 MODULE_DESCRIPTION("OMAP High Speed UART driver");
1630 MODULE_LICENSE("GPL");
1631 MODULE_AUTHOR("Texas Instruments Inc");