drivers/tty/serial/omap-serial.c

   1 /*
   2  * Driver for OMAP-UART controller.
   3  * Based on drivers/serial/8250.c
   4  *
   5  * Copyright (C) 2010 Texas Instruments.
   6  *
   7  * Authors:
   8  *      Govindraj R     <govindraj.raja@ti.com>
   9  *      Thara Gopinath  <thara@ti.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * Note: This driver is made separate from 8250 driver as we cannot
  17  * over load 8250 driver with omap platform specific configuration for
  18  * features like DMA, it makes easier to implement features like DMA and
  19  * hardware flow control and software flow control configuration with
  20  * this driver as required for the omap-platform.
  21  */
  22
  23 #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  24 #define SUPPORT_SYSRQ
  25 #endif
  26
  27 #include <linux/module.h>
  28 #include <linux/init.h>
  29 #include <linux/console.h>
  30 #include <linux/serial_reg.h>
  31 #include <linux/delay.h>
  32 #include <linux/slab.h>
  33 #include <linux/tty.h>
  34 #include <linux/tty_flip.h>
  35 #include <linux/platform_device.h>
  36 #include <linux/io.h>
  37 #include <linux/clk.h>
  38 #include <linux/serial_core.h>
  39 #include <linux/irq.h>
  40 #include <linux/pm_runtime.h>
  41 #include <linux/of.h>
  42 #include <linux/gpio.h>
  43 #include <linux/pinctrl/consumer.h>
  44 #include <linux/platform_data/serial-omap.h>
  45
  46 #define OMAP_MAX_HSUART_PORTS   6
  47
  48 #define UART_BUILD_REVISION(x, y)       (((x) << 8) | (y))
  49
  50 #define OMAP_UART_REV_42 0x0402
  51 #define OMAP_UART_REV_46 0x0406
  52 #define OMAP_UART_REV_52 0x0502
  53 #define OMAP_UART_REV_63 0x0603
  54
  55 #define UART_ERRATA_i202_MDR1_ACCESS    BIT(0)
  56 #define UART_ERRATA_i291_DMA_FORCEIDLE  BIT(1)
  57
  58 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
  59
  60 /* SCR register bitmasks */
  61 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK               (1 << 7)
  62 #define OMAP_UART_SCR_TX_EMPTY                  (1 << 3)
  63
  64 /* FCR register bitmasks */
  65 #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK                 (0x3 << 6)
  66 #define OMAP_UART_FCR_TX_FIFO_TRIG_MASK                 (0x3 << 4)
  67
  68 /* MVR register bitmasks */
  69 #define OMAP_UART_MVR_SCHEME_SHIFT      30
  70
  71 #define OMAP_UART_LEGACY_MVR_MAJ_MASK   0xf0
  72 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT  4
  73 #define OMAP_UART_LEGACY_MVR_MIN_MASK   0x0f
  74
  75 #define OMAP_UART_MVR_MAJ_MASK          0x700
  76 #define OMAP_UART_MVR_MAJ_SHIFT         8
  77 #define OMAP_UART_MVR_MIN_MASK          0x3f
  78
  79 #define OMAP_UART_DMA_CH_FREE   -1
  80
  81 #define MSR_SAVE_FLAGS          UART_MSR_ANY_DELTA
  82 #define OMAP_MODE13X_SPEED      230400
  83
  84 /* WER = 0x7F
  85  * Enable module level wakeup in WER reg
  86  */
  87 #define OMAP_UART_WER_MOD_WKUP  0X7F
  88
  89 /* Enable XON/XOFF flow control on output */
  90 #define OMAP_UART_SW_TX         0x08
  91
  92 /* Enable XON/XOFF flow control on input */
  93 #define OMAP_UART_SW_RX         0x02
  94
  95 #define OMAP_UART_SW_CLR        0xF0
  96
  97 #define OMAP_UART_TCR_TRIG      0x0F
  98
  99 struct uart_omap_dma {
 100         u8                      uart_dma_tx;
 101         u8                      uart_dma_rx;
 102         int                     rx_dma_channel;
 103         int                     tx_dma_channel;
 104         dma_addr_t              rx_buf_dma_phys;
 105         dma_addr_t              tx_buf_dma_phys;
 106         unsigned int            uart_base;
 107         /*
 108          * Buffer for rx dma.It is not required for tx because the buffer
 109          * comes from port structure.
 110          */
 111         unsigned char           *rx_buf;
 112         unsigned int            prev_rx_dma_pos;
 113         int                     tx_buf_size;
 114         int                     tx_dma_used;
 115         int                     rx_dma_used;
 116         spinlock_t              tx_lock;
 117         spinlock_t              rx_lock;
 118         /* timer to poll activity on rx dma */
 119         struct timer_list       rx_timer;
 120         unsigned int            rx_buf_size;
 121         unsigned int            rx_poll_rate;
 122         unsigned int            rx_timeout;
 123 };
 124
 125 struct uart_omap_port {
 126         struct uart_port        port;
 127         struct uart_omap_dma    uart_dma;
 128         struct device           *dev;
 129
 130         unsigned char           ier;
 131         unsigned char           lcr;
 132         unsigned char           mcr;
 133         unsigned char           fcr;
 134         unsigned char           efr;
 135         unsigned char           dll;
 136         unsigned char           dlh;
 137         unsigned char           mdr1;
 138         unsigned char           scr;
 139
 140         int                     use_dma;
 141         /*
 142          * Some bits in registers are cleared on a read, so they must
 143          * be saved whenever the register is read but the bits will not
 144          * be immediately processed.
 145          */
 146         unsigned int            lsr_break_flag;
 147         unsigned char           msr_saved_flags;
 148         char                    name[20];
 149         unsigned long           port_activity;
 150         int                     context_loss_cnt;
 151         u32                     errata;
 152         u8                      wakeups_enabled;
 153
 154         int                     DTR_gpio;
 155         int                     DTR_inverted;
 156         int                     DTR_active;
 157
 158         struct pm_qos_request   pm_qos_request;
 159         u32                     latency;
 160         u32                     calc_latency;
 161         struct work_struct      qos_work;
 162         struct pinctrl          *pins;
 163 };
 164
 165 #define to_uart_omap_port(p)    ((container_of((p), struct uart_omap_port, port)))
 166
 167 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
 168
 169 /* Forward declaration of functions */
 170 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
 171
 172 static struct workqueue_struct *serial_omap_uart_wq;
 173
 174 static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
 175 {
 176         offset <<= up->port.regshift;
 177         return readw(up->port.membase + offset);
 178 }
 179
 180 static inline void serial_out(struct uart_omap_port *up, int offset, int value)
 181 {
 182         offset <<= up->port.regshift;
 183         writew(value, up->port.membase + offset);
 184 }
 185
 186 static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
 187 {
 188         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
 189         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
 190                        UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
 191         serial_out(up, UART_FCR, 0);
 192 }
 193
 194 static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
 195 {
 196         struct omap_uart_port_info *pdata = up->dev->platform_data;
 197
 198         if (!pdata || !pdata->get_context_loss_count)
 199                 return 0;
 200
 201         return pdata->get_context_loss_count(up->dev);
 202 }
 203
 204 static void serial_omap_set_forceidle(struct uart_omap_port *up)
 205 {
 206         struct omap_uart_port_info *pdata = up->dev->platform_data;
 207
 208         if (!pdata || !pdata->set_forceidle)
 209                 return;
 210
 211         pdata->set_forceidle(up->dev);
 212 }
 213
 214 static void serial_omap_set_noidle(struct uart_omap_port *up)
 215 {
 216         struct omap_uart_port_info *pdata = up->dev->platform_data;
 217
 218         if (!pdata || !pdata->set_noidle)
 219                 return;
 220
 221         pdata->set_noidle(up->dev);
 222 }
 223
 224 static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
 225 {
 226         struct omap_uart_port_info *pdata = up->dev->platform_data;
 227
 228         if (!pdata || !pdata->enable_wakeup)
 229                 return;
 230
 231         pdata->enable_wakeup(up->dev, enable);
 232 }
 233
 234 /*
 235  * serial_omap_get_divisor - calculate divisor value
 236  * @port: uart port info
 237  * @baud: baudrate for which divisor needs to be calculated.
 238  *
 239  * We have written our own function to get the divisor so as to support
 240  * 13x mode. 3Mbps Baudrate as an different divisor.
 241  * Reference OMAP TRM Chapter 17:
 242  * Table 17-1. UART Mode Baud Rates, Divisor Values, and Error Rates
 243  * referring to oversampling - divisor value
 244  * baudrate 460,800 to 3,686,400 all have divisor 13
 245  * except 3,000,000 which has divisor value 16
 246  */
 247 static unsigned int
 248 serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
 249 {
 250         unsigned int divisor;
 251
 252         if (baud > OMAP_MODE13X_SPEED && baud != 3000000)
 253                 divisor = 13;
 254         else
 255                 divisor = 16;
 256         return port->uartclk/(baud * divisor);
 257 }
 258
 259 static void serial_omap_enable_ms(struct uart_port *port)
 260 {
 261         struct uart_omap_port *up = to_uart_omap_port(port);
 262
 263         dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
 264
 265         pm_runtime_get_sync(up->dev);
 266         up->ier |= UART_IER_MSI;
 267         serial_out(up, UART_IER, up->ier);
 268         pm_runtime_mark_last_busy(up->dev);
 269         pm_runtime_put_autosuspend(up->dev);
 270 }
 271
 272 static void serial_omap_stop_tx(struct uart_port *port)
 273 {
 274         struct uart_omap_port *up = to_uart_omap_port(port);
 275
 276         pm_runtime_get_sync(up->dev);
 277         if (up->ier & UART_IER_THRI) {
 278                 up->ier &= ~UART_IER_THRI;
 279                 serial_out(up, UART_IER, up->ier);
 280         }
 281
 282         serial_omap_set_forceidle(up);
 283
 284         pm_runtime_mark_last_busy(up->dev);
 285         pm_runtime_put_autosuspend(up->dev);
 286 }
 287
 288 static void serial_omap_stop_rx(struct uart_port *port)
 289 {
 290         struct uart_omap_port *up = to_uart_omap_port(port);
 291
 292         pm_runtime_get_sync(up->dev);
 293         up->ier &= ~UART_IER_RLSI;
 294         up->port.read_status_mask &= ~UART_LSR_DR;
 295         serial_out(up, UART_IER, up->ier);
 296         pm_runtime_mark_last_busy(up->dev);
 297         pm_runtime_put_autosuspend(up->dev);
 298 }
 299
 300 static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
 301 {
 302         struct circ_buf *xmit = &up->port.state->xmit;
 303         int count;
 304
 305         if (!(lsr & UART_LSR_THRE))
 306                 return;
 307
 308         if (up->port.x_char) {
 309                 serial_out(up, UART_TX, up->port.x_char);
 310                 up->port.icount.tx++;
 311                 up->port.x_char = 0;
 312                 return;
 313         }
 314         if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
 315                 serial_omap_stop_tx(&up->port);
 316                 return;
 317         }
 318         count = up->port.fifosize / 4;
 319         do {
 320                 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
 321                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 322                 up->port.icount.tx++;
 323                 if (uart_circ_empty(xmit))
 324                         break;
 325         } while (--count > 0);
 326
 327         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
 328                 spin_unlock(&up->port.lock);
 329                 uart_write_wakeup(&up->port);
 330                 spin_lock(&up->port.lock);
 331         }
 332
 333         if (uart_circ_empty(xmit))
 334                 serial_omap_stop_tx(&up->port);
 335 }
 336
 337 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
 338 {
 339         if (!(up->ier & UART_IER_THRI)) {
 340                 up->ier |= UART_IER_THRI;
 341                 serial_out(up, UART_IER, up->ier);
 342         }
 343 }
 344
 345 static void serial_omap_start_tx(struct uart_port *port)
 346 {
 347         struct uart_omap_port *up = to_uart_omap_port(port);
 348
 349         pm_runtime_get_sync(up->dev);
 350         serial_omap_enable_ier_thri(up);
 351         serial_omap_set_noidle(up);
 352         pm_runtime_mark_last_busy(up->dev);
 353         pm_runtime_put_autosuspend(up->dev);
 354 }
 355
 356 static void serial_omap_throttle(struct uart_port *port)
 357 {
 358         struct uart_omap_port *up = to_uart_omap_port(port);
 359         unsigned long flags;
 360
 361         pm_runtime_get_sync(up->dev);
 362         spin_lock_irqsave(&up->port.lock, flags);
 363         up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
 364         serial_out(up, UART_IER, up->ier);
 365         spin_unlock_irqrestore(&up->port.lock, flags);
 366         pm_runtime_mark_last_busy(up->dev);
 367         pm_runtime_put_autosuspend(up->dev);
 368 }
 369
 370 static void serial_omap_unthrottle(struct uart_port *port)
 371 {
 372         struct uart_omap_port *up = to_uart_omap_port(port);
 373         unsigned long flags;
 374
 375         pm_runtime_get_sync(up->dev);
 376         spin_lock_irqsave(&up->port.lock, flags);
 377         up->ier |= UART_IER_RLSI | UART_IER_RDI;
 378         serial_out(up, UART_IER, up->ier);
 379         spin_unlock_irqrestore(&up->port.lock, flags);
 380         pm_runtime_mark_last_busy(up->dev);
 381         pm_runtime_put_autosuspend(up->dev);
 382 }
 383
 384 static unsigned int check_modem_status(struct uart_omap_port *up)
 385 {
 386         unsigned int status;
 387
 388         status = serial_in(up, UART_MSR);
 389         status |= up->msr_saved_flags;
 390         up->msr_saved_flags = 0;
 391         if ((status & UART_MSR_ANY_DELTA) == 0)
 392                 return status;
 393
 394         if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
 395             up->port.state != NULL) {
 396                 if (status & UART_MSR_TERI)
 397                         up->port.icount.rng++;
 398                 if (status & UART_MSR_DDSR)
 399                         up->port.icount.dsr++;
 400                 if (status & UART_MSR_DDCD)
 401                         uart_handle_dcd_change
 402                                 (&up->port, status & UART_MSR_DCD);
 403                 if (status & UART_MSR_DCTS)
 404                         uart_handle_cts_change
 405                                 (&up->port, status & UART_MSR_CTS);
 406                 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
 407         }
 408
 409         return status;
 410 }
 411
 412 static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)
 413 {
 414         unsigned int flag;
 415         unsigned char ch = 0;
 416
 417         if (likely(lsr & UART_LSR_DR))
 418                 ch = serial_in(up, UART_RX);
 419
 420         up->port.icount.rx++;
 421         flag = TTY_NORMAL;
 422
 423         if (lsr & UART_LSR_BI) {
 424                 flag = TTY_BREAK;
 425                 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
 426                 up->port.icount.brk++;
 427                 /*
 428                  * We do the SysRQ and SAK checking
 429                  * here because otherwise the break
 430                  * may get masked by ignore_status_mask
 431                  * or read_status_mask.
 432                  */
 433                 if (uart_handle_break(&up->port))
 434                         return;
 435
 436         }
 437
 438         if (lsr & UART_LSR_PE) {
 439                 flag = TTY_PARITY;
 440                 up->port.icount.parity++;
 441         }
 442
 443         if (lsr & UART_LSR_FE) {
 444                 flag = TTY_FRAME;
 445                 up->port.icount.frame++;
 446         }
 447
 448         if (lsr & UART_LSR_OE)
 449                 up->port.icount.overrun++;
 450
 451 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
 452         if (up->port.line == up->port.cons->index) {
 453                 /* Recover the break flag from console xmit */
 454                 lsr |= up->lsr_break_flag;
 455         }
 456 #endif
 457         uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);
 458 }
 459
 460 static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
 461 {
 462         unsigned char ch = 0;
 463         unsigned int flag;
 464
 465         if (!(lsr & UART_LSR_DR))
 466                 return;
 467
 468         ch = serial_in(up, UART_RX);
 469         flag = TTY_NORMAL;
 470         up->port.icount.rx++;
 471
 472         if (uart_handle_sysrq_char(&up->port, ch))
 473                 return;
 474
 475         uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
 476 }
 477
 478 /**
 479  * serial_omap_irq() - This handles the interrupt from one port
 480  * @irq: uart port irq number
 481  * @dev_id: uart port info
 482  */
 483 static irqreturn_t serial_omap_irq(int irq, void *dev_id)
 484 {
 485         struct uart_omap_port *up = dev_id;
 486         struct tty_struct *tty = up->port.state->port.tty;
 487         unsigned int iir, lsr;
 488         unsigned int type;
 489         irqreturn_t ret = IRQ_NONE;
 490         int max_count = 256;
 491
 492         spin_lock(&up->port.lock);
 493         pm_runtime_get_sync(up->dev);
 494
 495         do {
 496                 iir = serial_in(up, UART_IIR);
 497                 if (iir & UART_IIR_NO_INT)
 498                         break;
 499
 500                 ret = IRQ_HANDLED;
 501                 lsr = serial_in(up, UART_LSR);
 502
 503                 /* extract IRQ type from IIR register */
 504                 type = iir & 0x3e;
 505
 506                 switch (type) {
 507                 case UART_IIR_MSI:
 508                         check_modem_status(up);
 509                         break;
 510                 case UART_IIR_THRI:
 511                         transmit_chars(up, lsr);
 512                         break;
 513                 case UART_IIR_RX_TIMEOUT:
 514                         /* FALLTHROUGH */
 515                 case UART_IIR_RDI:
 516                         serial_omap_rdi(up, lsr);
 517                         break;
 518                 case UART_IIR_RLSI:
 519                         serial_omap_rlsi(up, lsr);
 520                         break;
 521                 case UART_IIR_CTS_RTS_DSR:
 522                         /* simply try again */
 523                         break;
 524                 case UART_IIR_XOFF:
 525                         /* FALLTHROUGH */
 526                 default:
 527                         break;
 528                 }
 529         } while (!(iir & UART_IIR_NO_INT) && max_count--);
 530
 531         spin_unlock(&up->port.lock);
 532
 533         tty_flip_buffer_push(tty);
 534
 535         pm_runtime_mark_last_busy(up->dev);
 536         pm_runtime_put_autosuspend(up->dev);
 537         up->port_activity = jiffies;
 538
 539         return ret;
 540 }
 541
 542 static unsigned int serial_omap_tx_empty(struct uart_port *port)
 543 {
 544         struct uart_omap_port *up = to_uart_omap_port(port);
 545         unsigned long flags = 0;
 546         unsigned int ret = 0;
 547
 548         pm_runtime_get_sync(up->dev);
 549         dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
 550         spin_lock_irqsave(&up->port.lock, flags);
 551         ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
 552         spin_unlock_irqrestore(&up->port.lock, flags);
 553         pm_runtime_mark_last_busy(up->dev);
 554         pm_runtime_put_autosuspend(up->dev);
 555         return ret;
 556 }
 557
 558 static unsigned int serial_omap_get_mctrl(struct uart_port *port)
 559 {
 560         struct uart_omap_port *up = to_uart_omap_port(port);
 561         unsigned int status;
 562         unsigned int ret = 0;
 563
 564         pm_runtime_get_sync(up->dev);
 565         status = check_modem_status(up);
 566         pm_runtime_mark_last_busy(up->dev);
 567         pm_runtime_put_autosuspend(up->dev);
 568
 569         dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
 570
 571         if (status & UART_MSR_DCD)
 572                 ret |= TIOCM_CAR;
 573         if (status & UART_MSR_RI)
 574                 ret |= TIOCM_RNG;
 575         if (status & UART_MSR_DSR)
 576                 ret |= TIOCM_DSR;
 577         if (status & UART_MSR_CTS)
 578                 ret |= TIOCM_CTS;
 579         return ret;
 580 }
 581
 582 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
 583 {
 584         struct uart_omap_port *up = to_uart_omap_port(port);
 585         unsigned char mcr = 0, old_mcr;
 586
 587         dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
 588         if (mctrl & TIOCM_RTS)
 589                 mcr |= UART_MCR_RTS;
 590         if (mctrl & TIOCM_DTR)
 591                 mcr |= UART_MCR_DTR;
 592         if (mctrl & TIOCM_OUT1)
 593                 mcr |= UART_MCR_OUT1;
 594         if (mctrl & TIOCM_OUT2)
 595                 mcr |= UART_MCR_OUT2;
 596         if (mctrl & TIOCM_LOOP)
 597                 mcr |= UART_MCR_LOOP;
 598
 599         pm_runtime_get_sync(up->dev);
 600         old_mcr = serial_in(up, UART_MCR);
 601         old_mcr &= ~(UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_OUT1 |
 602                      UART_MCR_DTR | UART_MCR_RTS);
 603         up->mcr = old_mcr | mcr;
 604         serial_out(up, UART_MCR, up->mcr);
 605         pm_runtime_mark_last_busy(up->dev);
 606         pm_runtime_put_autosuspend(up->dev);
 607
 608         if (gpio_is_valid(up->DTR_gpio) &&
 609             !!(mctrl & TIOCM_DTR) != up->DTR_active) {
 610                 up->DTR_active = !up->DTR_active;
 611                 if (gpio_cansleep(up->DTR_gpio))
 612                         schedule_work(&up->qos_work);
 613                 else
 614                         gpio_set_value(up->DTR_gpio,
 615                                        up->DTR_active != up->DTR_inverted);
 616         }
 617 }
 618
 619 static void serial_omap_break_ctl(struct uart_port *port, int break_state)
 620 {
 621         struct uart_omap_port *up = to_uart_omap_port(port);
 622         unsigned long flags = 0;
 623
 624         dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
 625         pm_runtime_get_sync(up->dev);
 626         spin_lock_irqsave(&up->port.lock, flags);
 627         if (break_state == -1)
 628                 up->lcr |= UART_LCR_SBC;
 629         else
 630                 up->lcr &= ~UART_LCR_SBC;
 631         serial_out(up, UART_LCR, up->lcr);
 632         spin_unlock_irqrestore(&up->port.lock, flags);
 633         pm_runtime_mark_last_busy(up->dev);
 634         pm_runtime_put_autosuspend(up->dev);
 635 }
 636
 637 static int serial_omap_startup(struct uart_port *port)
 638 {
 639         struct uart_omap_port *up = to_uart_omap_port(port);
 640         unsigned long flags = 0;
 641         int retval;
 642
 643         /*
 644          * Allocate the IRQ
 645          */
 646         retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
 647                                 up->name, up);
 648         if (retval)
 649                 return retval;
 650
 651         dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
 652
 653         pm_runtime_get_sync(up->dev);
 654         /*
 655          * Clear the FIFO buffers and disable them.
 656          * (they will be reenabled in set_termios())
 657          */
 658         serial_omap_clear_fifos(up);
 659         /* For Hardware flow control */
 660         serial_out(up, UART_MCR, UART_MCR_RTS);
 661
 662         /*
 663          * Clear the interrupt registers.
 664          */
 665         (void) serial_in(up, UART_LSR);
 666         if (serial_in(up, UART_LSR) & UART_LSR_DR)
 667                 (void) serial_in(up, UART_RX);
 668         (void) serial_in(up, UART_IIR);
 669         (void) serial_in(up, UART_MSR);
 670
 671         /*
 672          * Now, initialize the UART
 673          */
 674         serial_out(up, UART_LCR, UART_LCR_WLEN8);
 675         spin_lock_irqsave(&up->port.lock, flags);
 676         /*
 677          * Most PC uarts need OUT2 raised to enable interrupts.
 678          */
 679         up->port.mctrl |= TIOCM_OUT2;
 680         serial_omap_set_mctrl(&up->port, up->port.mctrl);
 681         spin_unlock_irqrestore(&up->port.lock, flags);
 682
 683         up->msr_saved_flags = 0;
 684         /*
 685          * Finally, enable interrupts. Note: Modem status interrupts
 686          * are set via set_termios(), which will be occurring imminently
 687          * anyway, so we don't enable them here.
 688          */
 689         up->ier = UART_IER_RLSI | UART_IER_RDI;
 690         serial_out(up, UART_IER, up->ier);
 691
 692         /* Enable module level wake up */
 693         serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP);
 694
 695         pm_runtime_mark_last_busy(up->dev);
 696         pm_runtime_put_autosuspend(up->dev);
 697         up->port_activity = jiffies;
 698         return 0;
 699 }
 700
 701 static void serial_omap_shutdown(struct uart_port *port)
 702 {
 703         struct uart_omap_port *up = to_uart_omap_port(port);
 704         unsigned long flags = 0;
 705
 706         dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
 707
 708         pm_runtime_get_sync(up->dev);
 709         /*
 710          * Disable interrupts from this port
 711          */
 712         up->ier = 0;
 713         serial_out(up, UART_IER, 0);
 714
 715         spin_lock_irqsave(&up->port.lock, flags);
 716         up->port.mctrl &= ~TIOCM_OUT2;
 717         serial_omap_set_mctrl(&up->port, up->port.mctrl);
 718         spin_unlock_irqrestore(&up->port.lock, flags);
 719
 720         /*
 721          * Disable break condition and FIFOs
 722          */
 723         serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
 724         serial_omap_clear_fifos(up);
 725
 726         /*
 727          * Read data port to reset things, and then free the irq
 728          */
 729         if (serial_in(up, UART_LSR) & UART_LSR_DR)
 730                 (void) serial_in(up, UART_RX);
 731
 732         pm_runtime_mark_last_busy(up->dev);
 733         pm_runtime_put_autosuspend(up->dev);
 734         free_irq(up->port.irq, up);
 735 }
 736
 737 static void serial_omap_uart_qos_work(struct work_struct *work)
 738 {
 739         struct uart_omap_port *up = container_of(work, struct uart_omap_port,
 740                                                 qos_work);
 741
 742         pm_qos_update_request(&up->pm_qos_request, up->latency);
 743         if (gpio_is_valid(up->DTR_gpio))
 744                 gpio_set_value_cansleep(up->DTR_gpio,
 745                                         up->DTR_active != up->DTR_inverted);
 746 }
 747
 748 static void
 749 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
 750                         struct ktermios *old)
 751 {
 752         struct uart_omap_port *up = to_uart_omap_port(port);
 753         unsigned char cval = 0;
 754         unsigned long flags = 0;
 755         unsigned int baud, quot;
 756
 757         switch (termios->c_cflag & CSIZE) {
 758         case CS5:
 759                 cval = UART_LCR_WLEN5;
 760                 break;
 761         case CS6:
 762                 cval = UART_LCR_WLEN6;
 763                 break;
 764         case CS7:
 765                 cval = UART_LCR_WLEN7;
 766                 break;
 767         default:
 768         case CS8:
 769                 cval = UART_LCR_WLEN8;
 770                 break;
 771         }
 772
 773         if (termios->c_cflag & CSTOPB)
 774                 cval |= UART_LCR_STOP;
 775         if (termios->c_cflag & PARENB)
 776                 cval |= UART_LCR_PARITY;
 777         if (!(termios->c_cflag & PARODD))
 778                 cval |= UART_LCR_EPAR;
 779
 780         /*
 781          * Ask the core to calculate the divisor for us.
 782          */
 783
 784         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
 785         quot = serial_omap_get_divisor(port, baud);
 786
 787         /* calculate wakeup latency constraint */
 788         up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8);
 789         up->latency = up->calc_latency;
 790         schedule_work(&up->qos_work);
 791
 792         up->dll = quot & 0xff;
 793         up->dlh = quot >> 8;
 794         up->mdr1 = UART_OMAP_MDR1_DISABLE;
 795
 796         up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
 797                         UART_FCR_ENABLE_FIFO;
 798
 799         /*
 800          * Ok, we're now changing the port state. Do it with
 801          * interrupts disabled.
 802          */
 803         pm_runtime_get_sync(up->dev);
 804         spin_lock_irqsave(&up->port.lock, flags);
 805
 806         /*
 807          * Update the per-port timeout.
 808          */
 809         uart_update_timeout(port, termios->c_cflag, baud);
 810
 811         up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
 812         if (termios->c_iflag & INPCK)
 813                 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
 814         if (termios->c_iflag & (BRKINT | PARMRK))
 815                 up->port.read_status_mask |= UART_LSR_BI;
 816
 817         /*
 818          * Characters to ignore
 819          */
 820         up->port.ignore_status_mask = 0;
 821         if (termios->c_iflag & IGNPAR)
 822                 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
 823         if (termios->c_iflag & IGNBRK) {
 824                 up->port.ignore_status_mask |= UART_LSR_BI;
 825                 /*
 826                  * If we're ignoring parity and break indicators,
 827                  * ignore overruns too (for real raw support).
 828                  */
 829                 if (termios->c_iflag & IGNPAR)
 830                         up->port.ignore_status_mask |= UART_LSR_OE;
 831         }
 832
 833         /*
 834          * ignore all characters if CREAD is not set
 835          */
 836         if ((termios->c_cflag & CREAD) == 0)
 837                 up->port.ignore_status_mask |= UART_LSR_DR;
 838
 839         /*
 840          * Modem status interrupts
 841          */
 842         up->ier &= ~UART_IER_MSI;
 843         if (UART_ENABLE_MS(&up->port, termios->c_cflag))
 844                 up->ier |= UART_IER_MSI;
 845         serial_out(up, UART_IER, up->ier);
 846         serial_out(up, UART_LCR, cval);         /* reset DLAB */
 847         up->lcr = cval;
 848         up->scr = OMAP_UART_SCR_TX_EMPTY;
 849
 850         /* FIFOs and DMA Settings */
 851
 852         /* FCR can be changed only when the
 853          * baud clock is not running
 854          * DLL_REG and DLH_REG set to 0.
 855          */
 856         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 857         serial_out(up, UART_DLL, 0);
 858         serial_out(up, UART_DLM, 0);
 859         serial_out(up, UART_LCR, 0);
 860
 861         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 862
 863         up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB;
 864         up->efr &= ~UART_EFR_SCD;
 865         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 866
 867         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 868         up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR;
 869         serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
 870         /* FIFO ENABLE, DMA MODE */
 871
 872         up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
 873
 874         /* Set receive FIFO threshold to 16 characters and
 875          * transmit FIFO threshold to 16 spaces
 876          */
 877         up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
 878         up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK;
 879         up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 |
 880                 UART_FCR_ENABLE_FIFO;
 881
 882         serial_out(up, UART_FCR, up->fcr);
 883         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 884
 885         serial_out(up, UART_OMAP_SCR, up->scr);
 886
 887         /* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */
 888         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 889         serial_out(up, UART_MCR, up->mcr);
 890         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 891         serial_out(up, UART_EFR, up->efr);
 892         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 893
 894         /* Protocol, Baud Rate, and Interrupt Settings */
 895
 896         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
 897                 serial_omap_mdr1_errataset(up, up->mdr1);
 898         else
 899                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
 900
 901         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 902         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 903
 904         serial_out(up, UART_LCR, 0);
 905         serial_out(up, UART_IER, 0);
 906         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 907
 908         serial_out(up, UART_DLL, up->dll);      /* LS of divisor */
 909         serial_out(up, UART_DLM, up->dlh);      /* MS of divisor */
 910
 911         serial_out(up, UART_LCR, 0);
 912         serial_out(up, UART_IER, up->ier);
 913         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 914
 915         serial_out(up, UART_EFR, up->efr);
 916         serial_out(up, UART_LCR, cval);
 917
 918         if (baud > 230400 && baud != 3000000)
 919                 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
 920         else
 921                 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
 922
 923         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
 924                 serial_omap_mdr1_errataset(up, up->mdr1);
 925         else
 926                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
 927
 928         /* Configure flow control */
 929         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 930
 931         /* XON1/XOFF1 accessible mode B, TCRTLR=0, ECB=0 */
 932         serial_out(up, UART_XON1, termios->c_cc[VSTART]);
 933         serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
 934
 935         /* Enable access to TCR/TLR */
 936         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 937         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 938         serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
 939
 940         serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
 941
 942         if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
 943                 /* Enable AUTORTS and AUTOCTS */
 944                 up->efr |= UART_EFR_CTS | UART_EFR_RTS;
 945
 946                 /* Ensure MCR RTS is asserted */
 947                 up->mcr |= UART_MCR_RTS;
 948         } else {
 949                 /* Disable AUTORTS and AUTOCTS */
 950                 up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS);
 951         }
 952
 953         if (up->port.flags & UPF_SOFT_FLOW) {
 954                 /* clear SW control mode bits */
 955                 up->efr &= OMAP_UART_SW_CLR;
 956
 957                 /*
 958                  * IXON Flag:
 959                  * Enable XON/XOFF flow control on input.
 960                  * Receiver compares XON1, XOFF1.
 961                  */
 962                 if (termios->c_iflag & IXON)
 963                         up->efr |= OMAP_UART_SW_RX;
 964
 965                 /*
 966                  * IXOFF Flag:
 967                  * Enable XON/XOFF flow control on output.
 968                  * Transmit XON1, XOFF1
 969                  */
 970                 if (termios->c_iflag & IXOFF)
 971                         up->efr |= OMAP_UART_SW_TX;
 972
 973                 /*
 974                  * IXANY Flag:
 975                  * Enable any character to restart output.
 976                  * Operation resumes after receiving any
 977                  * character after recognition of the XOFF character
 978                  */
 979                 if (termios->c_iflag & IXANY)
 980                         up->mcr |= UART_MCR_XONANY;
 981                 else
 982                         up->mcr &= ~UART_MCR_XONANY;
 983         }
 984         serial_out(up, UART_MCR, up->mcr);
 985         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 986         serial_out(up, UART_EFR, up->efr);
 987         serial_out(up, UART_LCR, up->lcr);
 988
 989         serial_omap_set_mctrl(&up->port, up->port.mctrl);
 990
 991         spin_unlock_irqrestore(&up->port.lock, flags);
 992         pm_runtime_mark_last_busy(up->dev);
 993         pm_runtime_put_autosuspend(up->dev);
 994         dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
 995 }
 996
 997 static int serial_omap_set_wake(struct uart_port *port, unsigned int state)
 998 {
 999         struct uart_omap_port *up = to_uart_omap_port(port);
1000
1001         serial_omap_enable_wakeup(up, state);
1002
1003         return 0;
1004 }
1005
1006 static void
1007 serial_omap_pm(struct uart_port *port, unsigned int state,
1008                unsigned int oldstate)
1009 {
1010         struct uart_omap_port *up = to_uart_omap_port(port);
1011         unsigned char efr;
1012
1013         dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
1014
1015         pm_runtime_get_sync(up->dev);
1016         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1017         efr = serial_in(up, UART_EFR);
1018         serial_out(up, UART_EFR, efr | UART_EFR_ECB);
1019         serial_out(up, UART_LCR, 0);
1020
1021         serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
1022         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1023         serial_out(up, UART_EFR, efr);
1024         serial_out(up, UART_LCR, 0);
1025
1026         if (!device_may_wakeup(up->dev)) {
1027                 if (!state)
1028                         pm_runtime_forbid(up->dev);
1029                 else
1030                         pm_runtime_allow(up->dev);
1031         }
1032
1033         pm_runtime_mark_last_busy(up->dev);
1034         pm_runtime_put_autosuspend(up->dev);
1035 }
1036
1037 static void serial_omap_release_port(struct uart_port *port)
1038 {
1039         dev_dbg(port->dev, "serial_omap_release_port+\n");
1040 }
1041
1042 static int serial_omap_request_port(struct uart_port *port)
1043 {
1044         dev_dbg(port->dev, "serial_omap_request_port+\n");
1045         return 0;
1046 }
1047
1048 static void serial_omap_config_port(struct uart_port *port, int flags)
1049 {
1050         struct uart_omap_port *up = to_uart_omap_port(port);
1051
1052         dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
1053                                                         up->port.line);
1054         up->port.type = PORT_OMAP;
1055         up->port.flags |= UPF_SOFT_FLOW | UPF_HARD_FLOW;
1056 }
1057
1058 static int
1059 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
1060 {
1061         /* we don't want the core code to modify any port params */
1062         dev_dbg(port->dev, "serial_omap_verify_port+\n");
1063         return -EINVAL;
1064 }
1065
1066 static const char *
1067 serial_omap_type(struct uart_port *port)
1068 {
1069         struct uart_omap_port *up = to_uart_omap_port(port);
1070
1071         dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
1072         return up->name;
1073 }
1074
1075 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1076
1077 static inline void wait_for_xmitr(struct uart_omap_port *up)
1078 {
1079         unsigned int status, tmout = 10000;
1080
1081         /* Wait up to 10ms for the character(s) to be sent. */
1082         do {
1083                 status = serial_in(up, UART_LSR);
1084
1085                 if (status & UART_LSR_BI)
1086                         up->lsr_break_flag = UART_LSR_BI;
1087
1088                 if (--tmout == 0)
1089                         break;
1090                 udelay(1);
1091         } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
1092
1093         /* Wait up to 1s for flow control if necessary */
1094         if (up->port.flags & UPF_CONS_FLOW) {
1095                 tmout = 1000000;
1096                 for (tmout = 1000000; tmout; tmout--) {
1097                         unsigned int msr = serial_in(up, UART_MSR);
1098
1099                         up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1100                         if (msr & UART_MSR_CTS)
1101                                 break;
1102
1103                         udelay(1);
1104                 }
1105         }
1106 }
1107
1108 #ifdef CONFIG_CONSOLE_POLL
1109
1110 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
1111 {
1112         struct uart_omap_port *up = to_uart_omap_port(port);
1113
1114         pm_runtime_get_sync(up->dev);
1115         wait_for_xmitr(up);
1116         serial_out(up, UART_TX, ch);
1117         pm_runtime_mark_last_busy(up->dev);
1118         pm_runtime_put_autosuspend(up->dev);
1119 }
1120
1121 static int serial_omap_poll_get_char(struct uart_port *port)
1122 {
1123         struct uart_omap_port *up = to_uart_omap_port(port);
1124         unsigned int status;
1125
1126         pm_runtime_get_sync(up->dev);
1127         status = serial_in(up, UART_LSR);
1128         if (!(status & UART_LSR_DR)) {
1129                 status = NO_POLL_CHAR;
1130                 goto out;
1131         }
1132
1133         status = serial_in(up, UART_RX);
1134
1135 out:
1136         pm_runtime_mark_last_busy(up->dev);
1137         pm_runtime_put_autosuspend(up->dev);
1138
1139         return status;
1140 }
1141
1142 #endif /* CONFIG_CONSOLE_POLL */
1143
1144 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
1145
1146 static struct uart_omap_port *serial_omap_console_ports[OMAP_MAX_HSUART_PORTS];
1147
1148 static struct uart_driver serial_omap_reg;
1149
1150 static void serial_omap_console_putchar(struct uart_port *port, int ch)
1151 {
1152         struct uart_omap_port *up = to_uart_omap_port(port);
1153
1154         wait_for_xmitr(up);
1155         serial_out(up, UART_TX, ch);
1156 }
1157
1158 static void
1159 serial_omap_console_write(struct console *co, const char *s,
1160                 unsigned int count)
1161 {
1162         struct uart_omap_port *up = serial_omap_console_ports[co->index];
1163         unsigned long flags;
1164         unsigned int ier;
1165         int locked = 1;
1166
1167         pm_runtime_get_sync(up->dev);
1168
1169         local_irq_save(flags);
1170         if (up->port.sysrq)
1171                 locked = 0;
1172         else if (oops_in_progress)
1173                 locked = spin_trylock(&up->port.lock);
1174         else
1175                 spin_lock(&up->port.lock);
1176
1177         /*
1178          * First save the IER then disable the interrupts
1179          */
1180         ier = serial_in(up, UART_IER);
1181         serial_out(up, UART_IER, 0);
1182
1183         uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1184
1185         /*
1186          * Finally, wait for transmitter to become empty
1187          * and restore the IER
1188          */
1189         wait_for_xmitr(up);
1190         serial_out(up, UART_IER, ier);
1191         /*
1192          * The receive handling will happen properly because the
1193          * receive ready bit will still be set; it is not cleared
1194          * on read.  However, modem control will not, we must
1195          * call it if we have saved something in the saved flags
1196          * while processing with interrupts off.
1197          */
1198         if (up->msr_saved_flags)
1199                 check_modem_status(up);
1200
1201         pm_runtime_mark_last_busy(up->dev);
1202         pm_runtime_put_autosuspend(up->dev);
1203         if (locked)
1204                 spin_unlock(&up->port.lock);
1205         local_irq_restore(flags);
1206 }
1207
1208 static int __init
1209 serial_omap_console_setup(struct console *co, char *options)
1210 {
1211         struct uart_omap_port *up;
1212         int baud = 115200;
1213         int bits = 8;
1214         int parity = 'n';
1215         int flow = 'n';
1216
1217         if (serial_omap_console_ports[co->index] == NULL)
1218                 return -ENODEV;
1219         up = serial_omap_console_ports[co->index];
1220
1221         if (options)
1222                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1223
1224         return uart_set_options(&up->port, co, baud, parity, bits, flow);
1225 }
1226
1227 static struct console serial_omap_console = {
1228         .name           = OMAP_SERIAL_NAME,
1229         .write          = serial_omap_console_write,
1230         .device         = uart_console_device,
1231         .setup          = serial_omap_console_setup,
1232         .flags          = CON_PRINTBUFFER,
1233         .index          = -1,
1234         .data           = &serial_omap_reg,
1235 };
1236
1237 static void serial_omap_add_console_port(struct uart_omap_port *up)
1238 {
1239         serial_omap_console_ports[up->port.line] = up;
1240 }
1241
1242 #define OMAP_CONSOLE    (&serial_omap_console)
1243
1244 #else
1245
1246 #define OMAP_CONSOLE    NULL
1247
1248 static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1249 {}
1250
1251 #endif
1252
1253 static struct uart_ops serial_omap_pops = {
1254         .tx_empty       = serial_omap_tx_empty,
1255         .set_mctrl      = serial_omap_set_mctrl,
1256         .get_mctrl      = serial_omap_get_mctrl,
1257         .stop_tx        = serial_omap_stop_tx,
1258         .start_tx       = serial_omap_start_tx,
1259         .throttle       = serial_omap_throttle,
1260         .unthrottle     = serial_omap_unthrottle,
1261         .stop_rx        = serial_omap_stop_rx,
1262         .enable_ms      = serial_omap_enable_ms,
1263         .break_ctl      = serial_omap_break_ctl,
1264         .startup        = serial_omap_startup,
1265         .shutdown       = serial_omap_shutdown,
1266         .set_termios    = serial_omap_set_termios,
1267         .pm             = serial_omap_pm,
1268         .set_wake       = serial_omap_set_wake,
1269         .type           = serial_omap_type,
1270         .release_port   = serial_omap_release_port,
1271         .request_port   = serial_omap_request_port,
1272         .config_port    = serial_omap_config_port,
1273         .verify_port    = serial_omap_verify_port,
1274 #ifdef CONFIG_CONSOLE_POLL
1275         .poll_put_char  = serial_omap_poll_put_char,
1276         .poll_get_char  = serial_omap_poll_get_char,
1277 #endif
1278 };
1279
1280 static struct uart_driver serial_omap_reg = {
1281         .owner          = THIS_MODULE,
1282         .driver_name    = "OMAP-SERIAL",
1283         .dev_name       = OMAP_SERIAL_NAME,
1284         .nr             = OMAP_MAX_HSUART_PORTS,
1285         .cons           = OMAP_CONSOLE,
1286 };
1287
1288 #ifdef CONFIG_PM_SLEEP
1289 static int serial_omap_suspend(struct device *dev)
1290 {
1291         struct uart_omap_port *up = dev_get_drvdata(dev);
1292
1293         uart_suspend_port(&serial_omap_reg, &up->port);
1294         flush_work(&up->qos_work);
1295
1296         return 0;
1297 }
1298
1299 static int serial_omap_resume(struct device *dev)
1300 {
1301         struct uart_omap_port *up = dev_get_drvdata(dev);
1302
1303         uart_resume_port(&serial_omap_reg, &up->port);
1304
1305         return 0;
1306 }
1307 #endif
1308
1309 static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
1310 {
1311         u32 mvr, scheme;
1312         u16 revision, major, minor;
1313
1314         mvr = serial_in(up, UART_OMAP_MVER);
1315
1316         /* Check revision register scheme */
1317         scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
1318
1319         switch (scheme) {
1320         case 0: /* Legacy Scheme: OMAP2/3 */
1321                 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
1322                 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
1323                                         OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
1324                 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
1325                 break;
1326         case 1:
1327                 /* New Scheme: OMAP4+ */
1328                 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
1329                 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
1330                                         OMAP_UART_MVR_MAJ_SHIFT;
1331                 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
1332                 break;
1333         default:
1334                 dev_warn(up->dev,
1335                         "Unknown %s revision, defaulting to highest\n",
1336                         up->name);
1337                 /* highest possible revision */
1338                 major = 0xff;
1339                 minor = 0xff;
1340         }
1341
1342         /* normalize revision for the driver */
1343         revision = UART_BUILD_REVISION(major, minor);
1344
1345         switch (revision) {
1346         case OMAP_UART_REV_46:
1347                 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1348                                 UART_ERRATA_i291_DMA_FORCEIDLE);
1349                 break;
1350         case OMAP_UART_REV_52:
1351                 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1352                                 UART_ERRATA_i291_DMA_FORCEIDLE);
1353                 break;
1354         case OMAP_UART_REV_63:
1355                 up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
1356                 break;
1357         default:
1358                 break;
1359         }
1360 }
1361
1362 static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
1363 {
1364         struct omap_uart_port_info *omap_up_info;
1365
1366         omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
1367         if (!omap_up_info)
1368                 return NULL; /* out of memory */
1369
1370         of_property_read_u32(dev->of_node, "clock-frequency",
1371                                          &omap_up_info->uartclk);
1372         return omap_up_info;
1373 }
1374
1375 static int serial_omap_probe(struct platform_device *pdev)
1376 {
1377         struct uart_omap_port   *up;
1378         struct resource         *mem, *irq;
1379         struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data;
1380         int ret;
1381
1382         if (pdev->dev.of_node)
1383                 omap_up_info = of_get_uart_port_info(&pdev->dev);
1384
1385         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1386         if (!mem) {
1387                 dev_err(&pdev->dev, "no mem resource?\n");
1388                 return -ENODEV;
1389         }
1390
1391         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1392         if (!irq) {
1393                 dev_err(&pdev->dev, "no irq resource?\n");
1394                 return -ENODEV;
1395         }
1396
1397         if (!devm_request_mem_region(&pdev->dev, mem->start, resource_size(mem),
1398                                 pdev->dev.driver->name)) {
1399                 dev_err(&pdev->dev, "memory region already claimed\n");
1400                 return -EBUSY;
1401         }
1402
1403         if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1404             omap_up_info->DTR_present) {
1405                 ret = gpio_request(omap_up_info->DTR_gpio, "omap-serial");
1406                 if (ret < 0)
1407                         return ret;
1408                 ret = gpio_direction_output(omap_up_info->DTR_gpio,
1409                                             omap_up_info->DTR_inverted);
1410                 if (ret < 0)
1411                         return ret;
1412         }
1413
1414         up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
1415         if (!up)
1416                 return -ENOMEM;
1417
1418         if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1419             omap_up_info->DTR_present) {
1420                 up->DTR_gpio = omap_up_info->DTR_gpio;
1421                 up->DTR_inverted = omap_up_info->DTR_inverted;
1422         } else
1423                 up->DTR_gpio = -EINVAL;
1424         up->DTR_active = 0;
1425
1426         up->dev = &pdev->dev;
1427         up->port.dev = &pdev->dev;
1428         up->port.type = PORT_OMAP;
1429         up->port.iotype = UPIO_MEM;
1430         up->port.irq = irq->start;
1431
1432         up->port.regshift = 2;
1433         up->port.fifosize = 64;
1434         up->port.ops = &serial_omap_pops;
1435
1436         if (pdev->dev.of_node)
1437                 up->port.line = of_alias_get_id(pdev->dev.of_node, "serial");
1438         else
1439                 up->port.line = pdev->id;
1440
1441         if (up->port.line < 0) {
1442                 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
1443                                                                 up->port.line);
1444                 ret = -ENODEV;
1445                 goto err_port_line;
1446         }
1447
1448         up->pins = devm_pinctrl_get_select_default(&pdev->dev);
1449         if (IS_ERR(up->pins)) {
1450                 dev_warn(&pdev->dev, "did not get pins for uart%i error: %li\n",
1451                          up->port.line, PTR_ERR(up->pins));
1452                 up->pins = NULL;
1453         }
1454
1455         sprintf(up->name, "OMAP UART%d", up->port.line);
1456         up->port.mapbase = mem->start;
1457         up->port.membase = devm_ioremap(&pdev->dev, mem->start,
1458                                                 resource_size(mem));
1459         if (!up->port.membase) {
1460                 dev_err(&pdev->dev, "can't ioremap UART\n");
1461                 ret = -ENOMEM;
1462                 goto err_ioremap;
1463         }
1464
1465         up->port.flags = omap_up_info->flags;
1466         up->port.uartclk = omap_up_info->uartclk;
1467         if (!up->port.uartclk) {
1468                 up->port.uartclk = DEFAULT_CLK_SPEED;
1469                 dev_warn(&pdev->dev, "No clock speed specified: using default:"
1470                                                 "%d\n", DEFAULT_CLK_SPEED);
1471         }
1472
1473         up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1474         up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1475         pm_qos_add_request(&up->pm_qos_request,
1476                 PM_QOS_CPU_DMA_LATENCY, up->latency);
1477         serial_omap_uart_wq = create_singlethread_workqueue(up->name);
1478         INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1479
1480         platform_set_drvdata(pdev, up);
1481         pm_runtime_enable(&pdev->dev);
1482         pm_runtime_use_autosuspend(&pdev->dev);
1483         pm_runtime_set_autosuspend_delay(&pdev->dev,
1484                         omap_up_info->autosuspend_timeout);
1485
1486         pm_runtime_irq_safe(&pdev->dev);
1487         pm_runtime_get_sync(&pdev->dev);
1488
1489         omap_serial_fill_features_erratas(up);
1490
1491         ui[up->port.line] = up;
1492         serial_omap_add_console_port(up);
1493
1494         ret = uart_add_one_port(&serial_omap_reg, &up->port);
1495         if (ret != 0)
1496                 goto err_add_port;
1497
1498         pm_runtime_mark_last_busy(up->dev);
1499         pm_runtime_put_autosuspend(up->dev);
1500         return 0;
1501
1502 err_add_port:
1503         pm_runtime_put(&pdev->dev);
1504         pm_runtime_disable(&pdev->dev);
1505 err_ioremap:
1506 err_port_line:
1507         dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n",
1508                                 pdev->id, __func__, ret);
1509         return ret;
1510 }
1511
1512 static int serial_omap_remove(struct platform_device *dev)
1513 {
1514         struct uart_omap_port *up = platform_get_drvdata(dev);
1515
1516         pm_runtime_put_sync(up->dev);
1517         pm_runtime_disable(up->dev);
1518         uart_remove_one_port(&serial_omap_reg, &up->port);
1519         pm_qos_remove_request(&up->pm_qos_request);
1520
1521         return 0;
1522 }
1523
1524 /*
1525  * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1526  * The access to uart register after MDR1 Access
1527  * causes UART to corrupt data.
1528  *
1529  * Need a delay =
1530  * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1531  * give 10 times as much
1532  */
1533 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1534 {
1535         u8 timeout = 255;
1536
1537         serial_out(up, UART_OMAP_MDR1, mdr1);
1538         udelay(2);
1539         serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1540                         UART_FCR_CLEAR_RCVR);
1541         /*
1542          * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1543          * TX_FIFO_E bit is 1.
1544          */
1545         while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1546                                 (UART_LSR_THRE | UART_LSR_DR))) {
1547                 timeout--;
1548                 if (!timeout) {
1549                         /* Should *never* happen. we warn and carry on */
1550                         dev_crit(up->dev, "Errata i202: timedout %x\n",
1551                                                 serial_in(up, UART_LSR));
1552                         break;
1553                 }
1554                 udelay(1);
1555         }
1556 }
1557
1558 #ifdef CONFIG_PM_RUNTIME
1559 static void serial_omap_restore_context(struct uart_omap_port *up)
1560 {
1561         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1562                 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1563         else
1564                 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1565
1566         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1567         serial_out(up, UART_EFR, UART_EFR_ECB);
1568         serial_out(up, UART_LCR, 0x0); /* Operational mode */
1569         serial_out(up, UART_IER, 0x0);
1570         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1571         serial_out(up, UART_DLL, up->dll);
1572         serial_out(up, UART_DLM, up->dlh);
1573         serial_out(up, UART_LCR, 0x0); /* Operational mode */
1574         serial_out(up, UART_IER, up->ier);
1575         serial_out(up, UART_FCR, up->fcr);
1576         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1577         serial_out(up, UART_MCR, up->mcr);
1578         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1579         serial_out(up, UART_OMAP_SCR, up->scr);
1580         serial_out(up, UART_EFR, up->efr);
1581         serial_out(up, UART_LCR, up->lcr);
1582         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1583                 serial_omap_mdr1_errataset(up, up->mdr1);
1584         else
1585                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1586 }
1587
1588 static int serial_omap_runtime_suspend(struct device *dev)
1589 {
1590         struct uart_omap_port *up = dev_get_drvdata(dev);
1591         struct omap_uart_port_info *pdata = dev->platform_data;
1592
1593         if (!up)
1594                 return -EINVAL;
1595
1596         if (!pdata)
1597                 return 0;
1598
1599         up->context_loss_cnt = serial_omap_get_context_loss_count(up);
1600
1601         if (device_may_wakeup(dev)) {
1602                 if (!up->wakeups_enabled) {
1603                         serial_omap_enable_wakeup(up, true);
1604                         up->wakeups_enabled = true;
1605                 }
1606         } else {
1607                 if (up->wakeups_enabled) {
1608                         serial_omap_enable_wakeup(up, false);
1609                         up->wakeups_enabled = false;
1610                 }
1611         }
1612
1613         up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1614         schedule_work(&up->qos_work);
1615
1616         return 0;
1617 }
1618
1619 static int serial_omap_runtime_resume(struct device *dev)
1620 {
1621         struct uart_omap_port *up = dev_get_drvdata(dev);
1622
1623         int loss_cnt = serial_omap_get_context_loss_count(up);
1624
1625         if (loss_cnt < 0) {
1626                 dev_err(dev, "serial_omap_get_context_loss_count failed : %d\n",
1627                         loss_cnt);
1628                 serial_omap_restore_context(up);
1629         } else if (up->context_loss_cnt != loss_cnt) {
1630                 serial_omap_restore_context(up);
1631         }
1632         up->latency = up->calc_latency;
1633         schedule_work(&up->qos_work);
1634
1635         return 0;
1636 }
1637 #endif
1638
1639 static const struct dev_pm_ops serial_omap_dev_pm_ops = {
1640         SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
1641         SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
1642                                 serial_omap_runtime_resume, NULL)
1643 };
1644
1645 #if defined(CONFIG_OF)
1646 static const struct of_device_id omap_serial_of_match[] = {
1647         { .compatible = "ti,omap2-uart" },
1648         { .compatible = "ti,omap3-uart" },
1649         { .compatible = "ti,omap4-uart" },
1650         {},
1651 };
1652 MODULE_DEVICE_TABLE(of, omap_serial_of_match);
1653 #endif
1654
1655 static struct platform_driver serial_omap_driver = {
1656         .probe          = serial_omap_probe,
1657         .remove         = serial_omap_remove,
1658         .driver         = {
1659                 .name   = DRIVER_NAME,
1660                 .pm     = &serial_omap_dev_pm_ops,
1661                 .of_match_table = of_match_ptr(omap_serial_of_match),
1662         },
1663 };
1664
1665 static int __init serial_omap_init(void)
1666 {
1667         int ret;
1668
1669         ret = uart_register_driver(&serial_omap_reg);
1670         if (ret != 0)
1671                 return ret;
1672         ret = platform_driver_register(&serial_omap_driver);
1673         if (ret != 0)
1674                 uart_unregister_driver(&serial_omap_reg);
1675         return ret;
1676 }
1677
1678 static void __exit serial_omap_exit(void)
1679 {
1680         platform_driver_unregister(&serial_omap_driver);
1681         uart_unregister_driver(&serial_omap_reg);
1682 }
1683
1684 module_init(serial_omap_init);
1685 module_exit(serial_omap_exit);
1686
1687 MODULE_DESCRIPTION("OMAP High Speed UART driver");
1688 MODULE_LICENSE("GPL");
1689 MODULE_AUTHOR("Texas Instruments Inc");