drivers/tty/serial/omap-serial.c

   1 /*
   2  * Driver for OMAP-UART controller.
   3  * Based on drivers/serial/8250.c
   4  *
   5  * Copyright (C) 2010 Texas Instruments.
   6  *
   7  * Authors:
   8  *      Govindraj R     <govindraj.raja@ti.com>
   9  *      Thara Gopinath  <thara@ti.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * Note: This driver is made separate from 8250 driver as we cannot
  17  * over load 8250 driver with omap platform specific configuration for
  18  * features like DMA, it makes easier to implement features like DMA and
  19  * hardware flow control and software flow control configuration with
  20  * this driver as required for the omap-platform.
  21  */
  22
  23 #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  24 #define SUPPORT_SYSRQ
  25 #endif
  26
  27 #include <linux/module.h>
  28 #include <linux/init.h>
  29 #include <linux/console.h>
  30 #include <linux/serial_reg.h>
  31 #include <linux/delay.h>
  32 #include <linux/slab.h>
  33 #include <linux/tty.h>
  34 #include <linux/tty_flip.h>
  35 #include <linux/platform_device.h>
  36 #include <linux/io.h>
  37 #include <linux/clk.h>
  38 #include <linux/serial_core.h>
  39 #include <linux/irq.h>
  40 #include <linux/pm_runtime.h>
  41 #include <linux/of.h>
  42 #include <linux/gpio.h>
  43 #include <linux/pinctrl/consumer.h>
  44 #include <linux/platform_data/serial-omap.h>
  45
  46 #define OMAP_MAX_HSUART_PORTS   6
  47
  48 #define UART_BUILD_REVISION(x, y)       (((x) << 8) | (y))
  49
  50 #define OMAP_UART_REV_42 0x0402
  51 #define OMAP_UART_REV_46 0x0406
  52 #define OMAP_UART_REV_52 0x0502
  53 #define OMAP_UART_REV_63 0x0603
  54
  55 #define UART_ERRATA_i202_MDR1_ACCESS    BIT(0)
  56 #define UART_ERRATA_i291_DMA_FORCEIDLE  BIT(1)
  57
  58 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
  59
  60 /* SCR register bitmasks */
  61 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK               (1 << 7)
  62 #define OMAP_UART_SCR_TX_EMPTY                  (1 << 3)
  63
  64 /* FCR register bitmasks */
  65 #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK                 (0x3 << 6)
  66 #define OMAP_UART_FCR_TX_FIFO_TRIG_MASK                 (0x3 << 4)
  67
  68 /* MVR register bitmasks */
  69 #define OMAP_UART_MVR_SCHEME_SHIFT      30
  70
  71 #define OMAP_UART_LEGACY_MVR_MAJ_MASK   0xf0
  72 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT  4
  73 #define OMAP_UART_LEGACY_MVR_MIN_MASK   0x0f
  74
  75 #define OMAP_UART_MVR_MAJ_MASK          0x700
  76 #define OMAP_UART_MVR_MAJ_SHIFT         8
  77 #define OMAP_UART_MVR_MIN_MASK          0x3f
  78
  79 #define OMAP_UART_DMA_CH_FREE   -1
  80
  81 #define MSR_SAVE_FLAGS          UART_MSR_ANY_DELTA
  82 #define OMAP_MODE13X_SPEED      230400
  83
  84 /* WER = 0x7F
  85  * Enable module level wakeup in WER reg
  86  */
  87 #define OMAP_UART_WER_MOD_WKUP  0X7F
  88
  89 /* Enable XON/XOFF flow control on output */
  90 #define OMAP_UART_SW_TX         0x08
  91
  92 /* Enable XON/XOFF flow control on input */
  93 #define OMAP_UART_SW_RX         0x02
  94
  95 #define OMAP_UART_SW_CLR        0xF0
  96
  97 #define OMAP_UART_TCR_TRIG      0x0F
  98
  99 struct uart_omap_dma {
 100         u8                      uart_dma_tx;
 101         u8                      uart_dma_rx;
 102         int                     rx_dma_channel;
 103         int                     tx_dma_channel;
 104         dma_addr_t              rx_buf_dma_phys;
 105         dma_addr_t              tx_buf_dma_phys;
 106         unsigned int            uart_base;
 107         /*
 108          * Buffer for rx dma.It is not required for tx because the buffer
 109          * comes from port structure.
 110          */
 111         unsigned char           *rx_buf;
 112         unsigned int            prev_rx_dma_pos;
 113         int                     tx_buf_size;
 114         int                     tx_dma_used;
 115         int                     rx_dma_used;
 116         spinlock_t              tx_lock;
 117         spinlock_t              rx_lock;
 118         /* timer to poll activity on rx dma */
 119         struct timer_list       rx_timer;
 120         unsigned int            rx_buf_size;
 121         unsigned int            rx_poll_rate;
 122         unsigned int            rx_timeout;
 123 };
 124
 125 struct uart_omap_port {
 126         struct uart_port        port;
 127         struct uart_omap_dma    uart_dma;
 128         struct device           *dev;
 129
 130         unsigned char           ier;
 131         unsigned char           lcr;
 132         unsigned char           mcr;
 133         unsigned char           fcr;
 134         unsigned char           efr;
 135         unsigned char           dll;
 136         unsigned char           dlh;
 137         unsigned char           mdr1;
 138         unsigned char           scr;
 139
 140         int                     use_dma;
 141         /*
 142          * Some bits in registers are cleared on a read, so they must
 143          * be saved whenever the register is read but the bits will not
 144          * be immediately processed.
 145          */
 146         unsigned int            lsr_break_flag;
 147         unsigned char           msr_saved_flags;
 148         char                    name[20];
 149         unsigned long           port_activity;
 150         int                     context_loss_cnt;
 151         u32                     errata;
 152         u8                      wakeups_enabled;
 153
 154         int                     DTR_gpio;
 155         int                     DTR_inverted;
 156         int                     DTR_active;
 157
 158         struct pm_qos_request   pm_qos_request;
 159         u32                     latency;
 160         u32                     calc_latency;
 161         struct work_struct      qos_work;
 162         struct pinctrl          *pins;
 163 };
 164
 165 #define to_uart_omap_port(p)    ((container_of((p), struct uart_omap_port, port)))
 166
 167 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
 168
 169 /* Forward declaration of functions */
 170 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
 171
 172 static struct workqueue_struct *serial_omap_uart_wq;
 173
 174 static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
 175 {
 176         offset <<= up->port.regshift;
 177         return readw(up->port.membase + offset);
 178 }
 179
 180 static inline void serial_out(struct uart_omap_port *up, int offset, int value)
 181 {
 182         offset <<= up->port.regshift;
 183         writew(value, up->port.membase + offset);
 184 }
 185
 186 static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
 187 {
 188         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
 189         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
 190                        UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
 191         serial_out(up, UART_FCR, 0);
 192 }
 193
 194 static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
 195 {
 196         struct omap_uart_port_info *pdata = up->dev->platform_data;
 197
 198         if (!pdata || !pdata->get_context_loss_count)
 199                 return 0;
 200
 201         return pdata->get_context_loss_count(up->dev);
 202 }
 203
 204 static void serial_omap_set_forceidle(struct uart_omap_port *up)
 205 {
 206         struct omap_uart_port_info *pdata = up->dev->platform_data;
 207
 208         if (!pdata || !pdata->set_forceidle)
 209                 return;
 210
 211         pdata->set_forceidle(up->dev);
 212 }
 213
 214 static void serial_omap_set_noidle(struct uart_omap_port *up)
 215 {
 216         struct omap_uart_port_info *pdata = up->dev->platform_data;
 217
 218         if (!pdata || !pdata->set_noidle)
 219                 return;
 220
 221         pdata->set_noidle(up->dev);
 222 }
 223
 224 static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
 225 {
 226         struct omap_uart_port_info *pdata = up->dev->platform_data;
 227
 228         if (!pdata || !pdata->enable_wakeup)
 229                 return;
 230
 231         pdata->enable_wakeup(up->dev, enable);
 232 }
 233
 234 /*
 235  * serial_omap_get_divisor - calculate divisor value
 236  * @port: uart port info
 237  * @baud: baudrate for which divisor needs to be calculated.
 238  *
 239  * We have written our own function to get the divisor so as to support
 240  * 13x mode. 3Mbps Baudrate as an different divisor.
 241  * Reference OMAP TRM Chapter 17:
 242  * Table 17-1. UART Mode Baud Rates, Divisor Values, and Error Rates
 243  * referring to oversampling - divisor value
 244  * baudrate 460,800 to 3,686,400 all have divisor 13
 245  * except 3,000,000 which has divisor value 16
 246  */
 247 static unsigned int
 248 serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
 249 {
 250         unsigned int divisor;
 251
 252         if (baud > OMAP_MODE13X_SPEED && baud != 3000000)
 253                 divisor = 13;
 254         else
 255                 divisor = 16;
 256         return port->uartclk/(baud * divisor);
 257 }
 258
 259 static void serial_omap_enable_ms(struct uart_port *port)
 260 {
 261         struct uart_omap_port *up = to_uart_omap_port(port);
 262
 263         dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
 264
 265         pm_runtime_get_sync(up->dev);
 266         up->ier |= UART_IER_MSI;
 267         serial_out(up, UART_IER, up->ier);
 268         pm_runtime_mark_last_busy(up->dev);
 269         pm_runtime_put_autosuspend(up->dev);
 270 }
 271
 272 static void serial_omap_stop_tx(struct uart_port *port)
 273 {
 274         struct uart_omap_port *up = to_uart_omap_port(port);
 275
 276         pm_runtime_get_sync(up->dev);
 277         if (up->ier & UART_IER_THRI) {
 278                 up->ier &= ~UART_IER_THRI;
 279                 serial_out(up, UART_IER, up->ier);
 280         }
 281
 282         serial_omap_set_forceidle(up);
 283
 284         pm_runtime_mark_last_busy(up->dev);
 285         pm_runtime_put_autosuspend(up->dev);
 286 }
 287
 288 static void serial_omap_stop_rx(struct uart_port *port)
 289 {
 290         struct uart_omap_port *up = to_uart_omap_port(port);
 291
 292         pm_runtime_get_sync(up->dev);
 293         up->ier &= ~UART_IER_RLSI;
 294         up->port.read_status_mask &= ~UART_LSR_DR;
 295         serial_out(up, UART_IER, up->ier);
 296         pm_runtime_mark_last_busy(up->dev);
 297         pm_runtime_put_autosuspend(up->dev);
 298 }
 299
 300 static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
 301 {
 302         struct circ_buf *xmit = &up->port.state->xmit;
 303         int count;
 304
 305         if (!(lsr & UART_LSR_THRE))
 306                 return;
 307
 308         if (up->port.x_char) {
 309                 serial_out(up, UART_TX, up->port.x_char);
 310                 up->port.icount.tx++;
 311                 up->port.x_char = 0;
 312                 return;
 313         }
 314         if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
 315                 serial_omap_stop_tx(&up->port);
 316                 return;
 317         }
 318         count = up->port.fifosize / 4;
 319         do {
 320                 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
 321                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 322                 up->port.icount.tx++;
 323                 if (uart_circ_empty(xmit))
 324                         break;
 325         } while (--count > 0);
 326
 327         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
 328                 spin_unlock(&up->port.lock);
 329                 uart_write_wakeup(&up->port);
 330                 spin_lock(&up->port.lock);
 331         }
 332
 333         if (uart_circ_empty(xmit))
 334                 serial_omap_stop_tx(&up->port);
 335 }
 336
 337 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
 338 {
 339         if (!(up->ier & UART_IER_THRI)) {
 340                 up->ier |= UART_IER_THRI;
 341                 serial_out(up, UART_IER, up->ier);
 342         }
 343 }
 344
 345 static void serial_omap_start_tx(struct uart_port *port)
 346 {
 347         struct uart_omap_port *up = to_uart_omap_port(port);
 348
 349         pm_runtime_get_sync(up->dev);
 350         serial_omap_enable_ier_thri(up);
 351         serial_omap_set_noidle(up);
 352         pm_runtime_mark_last_busy(up->dev);
 353         pm_runtime_put_autosuspend(up->dev);
 354 }
 355
 356 static void serial_omap_throttle(struct uart_port *port)
 357 {
 358         struct uart_omap_port *up = to_uart_omap_port(port);
 359         unsigned long flags;
 360
 361         pm_runtime_get_sync(up->dev);
 362         spin_lock_irqsave(&up->port.lock, flags);
 363         up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
 364         serial_out(up, UART_IER, up->ier);
 365         spin_unlock_irqrestore(&up->port.lock, flags);
 366         pm_runtime_mark_last_busy(up->dev);
 367         pm_runtime_put_autosuspend(up->dev);
 368 }
 369
 370 static void serial_omap_unthrottle(struct uart_port *port)
 371 {
 372         struct uart_omap_port *up = to_uart_omap_port(port);
 373         unsigned long flags;
 374
 375         pm_runtime_get_sync(up->dev);
 376         spin_lock_irqsave(&up->port.lock, flags);
 377         up->ier |= UART_IER_RLSI | UART_IER_RDI;
 378         serial_out(up, UART_IER, up->ier);
 379         spin_unlock_irqrestore(&up->port.lock, flags);
 380         pm_runtime_mark_last_busy(up->dev);
 381         pm_runtime_put_autosuspend(up->dev);
 382 }
 383
 384 static unsigned int check_modem_status(struct uart_omap_port *up)
 385 {
 386         unsigned int status;
 387
 388         status = serial_in(up, UART_MSR);
 389         status |= up->msr_saved_flags;
 390         up->msr_saved_flags = 0;
 391         if ((status & UART_MSR_ANY_DELTA) == 0)
 392                 return status;
 393
 394         if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
 395             up->port.state != NULL) {
 396                 if (status & UART_MSR_TERI)
 397                         up->port.icount.rng++;
 398                 if (status & UART_MSR_DDSR)
 399                         up->port.icount.dsr++;
 400                 if (status & UART_MSR_DDCD)
 401                         uart_handle_dcd_change
 402                                 (&up->port, status & UART_MSR_DCD);
 403                 if (status & UART_MSR_DCTS)
 404                         uart_handle_cts_change
 405                                 (&up->port, status & UART_MSR_CTS);
 406                 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
 407         }
 408
 409         return status;
 410 }
 411
 412 static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)
 413 {
 414         unsigned int flag;
 415         unsigned char ch = 0;
 416
 417         if (likely(lsr & UART_LSR_DR))
 418                 ch = serial_in(up, UART_RX);
 419
 420         up->port.icount.rx++;
 421         flag = TTY_NORMAL;
 422
 423         if (lsr & UART_LSR_BI) {
 424                 flag = TTY_BREAK;
 425                 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
 426                 up->port.icount.brk++;
 427                 /*
 428                  * We do the SysRQ and SAK checking
 429                  * here because otherwise the break
 430                  * may get masked by ignore_status_mask
 431                  * or read_status_mask.
 432                  */
 433                 if (uart_handle_break(&up->port))
 434                         return;
 435
 436         }
 437
 438         if (lsr & UART_LSR_PE) {
 439                 flag = TTY_PARITY;
 440                 up->port.icount.parity++;
 441         }
 442
 443         if (lsr & UART_LSR_FE) {
 444                 flag = TTY_FRAME;
 445                 up->port.icount.frame++;
 446         }
 447
 448         if (lsr & UART_LSR_OE)
 449                 up->port.icount.overrun++;
 450
 451 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
 452         if (up->port.line == up->port.cons->index) {
 453                 /* Recover the break flag from console xmit */
 454                 lsr |= up->lsr_break_flag;
 455         }
 456 #endif
 457         uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);
 458 }
 459
 460 static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
 461 {
 462         unsigned char ch = 0;
 463         unsigned int flag;
 464
 465         if (!(lsr & UART_LSR_DR))
 466                 return;
 467
 468         ch = serial_in(up, UART_RX);
 469         flag = TTY_NORMAL;
 470         up->port.icount.rx++;
 471
 472         if (uart_handle_sysrq_char(&up->port, ch))
 473                 return;
 474
 475         uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
 476 }
 477
 478 /**
 479  * serial_omap_irq() - This handles the interrupt from one port
 480  * @irq: uart port irq number
 481  * @dev_id: uart port info
 482  */
 483 static irqreturn_t serial_omap_irq(int irq, void *dev_id)
 484 {
 485         struct uart_omap_port *up = dev_id;
 486         unsigned int iir, lsr;
 487         unsigned int type;
 488         irqreturn_t ret = IRQ_NONE;
 489         int max_count = 256;
 490
 491         spin_lock(&up->port.lock);
 492         pm_runtime_get_sync(up->dev);
 493
 494         do {
 495                 iir = serial_in(up, UART_IIR);
 496                 if (iir & UART_IIR_NO_INT)
 497                         break;
 498
 499                 ret = IRQ_HANDLED;
 500                 lsr = serial_in(up, UART_LSR);
 501
 502                 /* extract IRQ type from IIR register */
 503                 type = iir & 0x3e;
 504
 505                 switch (type) {
 506                 case UART_IIR_MSI:
 507                         check_modem_status(up);
 508                         break;
 509                 case UART_IIR_THRI:
 510                         transmit_chars(up, lsr);
 511                         break;
 512                 case UART_IIR_RX_TIMEOUT:
 513                         /* FALLTHROUGH */
 514                 case UART_IIR_RDI:
 515                         serial_omap_rdi(up, lsr);
 516                         break;
 517                 case UART_IIR_RLSI:
 518                         serial_omap_rlsi(up, lsr);
 519                         break;
 520                 case UART_IIR_CTS_RTS_DSR:
 521                         /* simply try again */
 522                         break;
 523                 case UART_IIR_XOFF:
 524                         /* FALLTHROUGH */
 525                 default:
 526                         break;
 527                 }
 528         } while (!(iir & UART_IIR_NO_INT) && max_count--);
 529
 530         spin_unlock(&up->port.lock);
 531
 532         tty_flip_buffer_push(&up->port.state->port);
 533
 534         pm_runtime_mark_last_busy(up->dev);
 535         pm_runtime_put_autosuspend(up->dev);
 536         up->port_activity = jiffies;
 537
 538         return ret;
 539 }
 540
 541 static unsigned int serial_omap_tx_empty(struct uart_port *port)
 542 {
 543         struct uart_omap_port *up = to_uart_omap_port(port);
 544         unsigned long flags = 0;
 545         unsigned int ret = 0;
 546
 547         pm_runtime_get_sync(up->dev);
 548         dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
 549         spin_lock_irqsave(&up->port.lock, flags);
 550         ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
 551         spin_unlock_irqrestore(&up->port.lock, flags);
 552         pm_runtime_mark_last_busy(up->dev);
 553         pm_runtime_put_autosuspend(up->dev);
 554         return ret;
 555 }
 556
 557 static unsigned int serial_omap_get_mctrl(struct uart_port *port)
 558 {
 559         struct uart_omap_port *up = to_uart_omap_port(port);
 560         unsigned int status;
 561         unsigned int ret = 0;
 562
 563         pm_runtime_get_sync(up->dev);
 564         status = check_modem_status(up);
 565         pm_runtime_mark_last_busy(up->dev);
 566         pm_runtime_put_autosuspend(up->dev);
 567
 568         dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
 569
 570         if (status & UART_MSR_DCD)
 571                 ret |= TIOCM_CAR;
 572         if (status & UART_MSR_RI)
 573                 ret |= TIOCM_RNG;
 574         if (status & UART_MSR_DSR)
 575                 ret |= TIOCM_DSR;
 576         if (status & UART_MSR_CTS)
 577                 ret |= TIOCM_CTS;
 578         return ret;
 579 }
 580
 581 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
 582 {
 583         struct uart_omap_port *up = to_uart_omap_port(port);
 584         unsigned char mcr = 0, old_mcr;
 585
 586         dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
 587         if (mctrl & TIOCM_RTS)
 588                 mcr |= UART_MCR_RTS;
 589         if (mctrl & TIOCM_DTR)
 590                 mcr |= UART_MCR_DTR;
 591         if (mctrl & TIOCM_OUT1)
 592                 mcr |= UART_MCR_OUT1;
 593         if (mctrl & TIOCM_OUT2)
 594                 mcr |= UART_MCR_OUT2;
 595         if (mctrl & TIOCM_LOOP)
 596                 mcr |= UART_MCR_LOOP;
 597
 598         pm_runtime_get_sync(up->dev);
 599         old_mcr = serial_in(up, UART_MCR);
 600         old_mcr &= ~(UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_OUT1 |
 601                      UART_MCR_DTR | UART_MCR_RTS);
 602         up->mcr = old_mcr | mcr;
 603         serial_out(up, UART_MCR, up->mcr);
 604         pm_runtime_mark_last_busy(up->dev);
 605         pm_runtime_put_autosuspend(up->dev);
 606
 607         if (gpio_is_valid(up->DTR_gpio) &&
 608             !!(mctrl & TIOCM_DTR) != up->DTR_active) {
 609                 up->DTR_active = !up->DTR_active;
 610                 if (gpio_cansleep(up->DTR_gpio))
 611                         schedule_work(&up->qos_work);
 612                 else
 613                         gpio_set_value(up->DTR_gpio,
 614                                        up->DTR_active != up->DTR_inverted);
 615         }
 616 }
 617
 618 static void serial_omap_break_ctl(struct uart_port *port, int break_state)
 619 {
 620         struct uart_omap_port *up = to_uart_omap_port(port);
 621         unsigned long flags = 0;
 622
 623         dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
 624         pm_runtime_get_sync(up->dev);
 625         spin_lock_irqsave(&up->port.lock, flags);
 626         if (break_state == -1)
 627                 up->lcr |= UART_LCR_SBC;
 628         else
 629                 up->lcr &= ~UART_LCR_SBC;
 630         serial_out(up, UART_LCR, up->lcr);
 631         spin_unlock_irqrestore(&up->port.lock, flags);
 632         pm_runtime_mark_last_busy(up->dev);
 633         pm_runtime_put_autosuspend(up->dev);
 634 }
 635
 636 static int serial_omap_startup(struct uart_port *port)
 637 {
 638         struct uart_omap_port *up = to_uart_omap_port(port);
 639         unsigned long flags = 0;
 640         int retval;
 641
 642         /*
 643          * Allocate the IRQ
 644          */
 645         retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
 646                                 up->name, up);
 647         if (retval)
 648                 return retval;
 649
 650         dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
 651
 652         pm_runtime_get_sync(up->dev);
 653         /*
 654          * Clear the FIFO buffers and disable them.
 655          * (they will be reenabled in set_termios())
 656          */
 657         serial_omap_clear_fifos(up);
 658         /* For Hardware flow control */
 659         serial_out(up, UART_MCR, UART_MCR_RTS);
 660
 661         /*
 662          * Clear the interrupt registers.
 663          */
 664         (void) serial_in(up, UART_LSR);
 665         if (serial_in(up, UART_LSR) & UART_LSR_DR)
 666                 (void) serial_in(up, UART_RX);
 667         (void) serial_in(up, UART_IIR);
 668         (void) serial_in(up, UART_MSR);
 669
 670         /*
 671          * Now, initialize the UART
 672          */
 673         serial_out(up, UART_LCR, UART_LCR_WLEN8);
 674         spin_lock_irqsave(&up->port.lock, flags);
 675         /*
 676          * Most PC uarts need OUT2 raised to enable interrupts.
 677          */
 678         up->port.mctrl |= TIOCM_OUT2;
 679         serial_omap_set_mctrl(&up->port, up->port.mctrl);
 680         spin_unlock_irqrestore(&up->port.lock, flags);
 681
 682         up->msr_saved_flags = 0;
 683         /*
 684          * Finally, enable interrupts. Note: Modem status interrupts
 685          * are set via set_termios(), which will be occurring imminently
 686          * anyway, so we don't enable them here.
 687          */
 688         up->ier = UART_IER_RLSI | UART_IER_RDI;
 689         serial_out(up, UART_IER, up->ier);
 690
 691         /* Enable module level wake up */
 692         serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP);
 693
 694         pm_runtime_mark_last_busy(up->dev);
 695         pm_runtime_put_autosuspend(up->dev);
 696         up->port_activity = jiffies;
 697         return 0;
 698 }
 699
 700 static void serial_omap_shutdown(struct uart_port *port)
 701 {
 702         struct uart_omap_port *up = to_uart_omap_port(port);
 703         unsigned long flags = 0;
 704
 705         dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
 706
 707         pm_runtime_get_sync(up->dev);
 708         /*
 709          * Disable interrupts from this port
 710          */
 711         up->ier = 0;
 712         serial_out(up, UART_IER, 0);
 713
 714         spin_lock_irqsave(&up->port.lock, flags);
 715         up->port.mctrl &= ~TIOCM_OUT2;
 716         serial_omap_set_mctrl(&up->port, up->port.mctrl);
 717         spin_unlock_irqrestore(&up->port.lock, flags);
 718
 719         /*
 720          * Disable break condition and FIFOs
 721          */
 722         serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
 723         serial_omap_clear_fifos(up);
 724
 725         /*
 726          * Read data port to reset things, and then free the irq
 727          */
 728         if (serial_in(up, UART_LSR) & UART_LSR_DR)
 729                 (void) serial_in(up, UART_RX);
 730
 731         pm_runtime_mark_last_busy(up->dev);
 732         pm_runtime_put_autosuspend(up->dev);
 733         free_irq(up->port.irq, up);
 734 }
 735
 736 static void serial_omap_uart_qos_work(struct work_struct *work)
 737 {
 738         struct uart_omap_port *up = container_of(work, struct uart_omap_port,
 739                                                 qos_work);
 740
 741         pm_qos_update_request(&up->pm_qos_request, up->latency);
 742         if (gpio_is_valid(up->DTR_gpio))
 743                 gpio_set_value_cansleep(up->DTR_gpio,
 744                                         up->DTR_active != up->DTR_inverted);
 745 }
 746
 747 static void
 748 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
 749                         struct ktermios *old)
 750 {
 751         struct uart_omap_port *up = to_uart_omap_port(port);
 752         unsigned char cval = 0;
 753         unsigned long flags = 0;
 754         unsigned int baud, quot;
 755
 756         switch (termios->c_cflag & CSIZE) {
 757         case CS5:
 758                 cval = UART_LCR_WLEN5;
 759                 break;
 760         case CS6:
 761                 cval = UART_LCR_WLEN6;
 762                 break;
 763         case CS7:
 764                 cval = UART_LCR_WLEN7;
 765                 break;
 766         default:
 767         case CS8:
 768                 cval = UART_LCR_WLEN8;
 769                 break;
 770         }
 771
 772         if (termios->c_cflag & CSTOPB)
 773                 cval |= UART_LCR_STOP;
 774         if (termios->c_cflag & PARENB)
 775                 cval |= UART_LCR_PARITY;
 776         if (!(termios->c_cflag & PARODD))
 777                 cval |= UART_LCR_EPAR;
 778         if (termios->c_cflag & CMSPAR)
 779                 cval |= UART_LCR_SPAR;
 780
 781         /*
 782          * Ask the core to calculate the divisor for us.
 783          */
 784
 785         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
 786         quot = serial_omap_get_divisor(port, baud);
 787
 788         /* calculate wakeup latency constraint */
 789         up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8);
 790         up->latency = up->calc_latency;
 791         schedule_work(&up->qos_work);
 792
 793         up->dll = quot & 0xff;
 794         up->dlh = quot >> 8;
 795         up->mdr1 = UART_OMAP_MDR1_DISABLE;
 796
 797         up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
 798                         UART_FCR_ENABLE_FIFO;
 799
 800         /*
 801          * Ok, we're now changing the port state. Do it with
 802          * interrupts disabled.
 803          */
 804         pm_runtime_get_sync(up->dev);
 805         spin_lock_irqsave(&up->port.lock, flags);
 806
 807         /*
 808          * Update the per-port timeout.
 809          */
 810         uart_update_timeout(port, termios->c_cflag, baud);
 811
 812         up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
 813         if (termios->c_iflag & INPCK)
 814                 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
 815         if (termios->c_iflag & (BRKINT | PARMRK))
 816                 up->port.read_status_mask |= UART_LSR_BI;
 817
 818         /*
 819          * Characters to ignore
 820          */
 821         up->port.ignore_status_mask = 0;
 822         if (termios->c_iflag & IGNPAR)
 823                 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
 824         if (termios->c_iflag & IGNBRK) {
 825                 up->port.ignore_status_mask |= UART_LSR_BI;
 826                 /*
 827                  * If we're ignoring parity and break indicators,
 828                  * ignore overruns too (for real raw support).
 829                  */
 830                 if (termios->c_iflag & IGNPAR)
 831                         up->port.ignore_status_mask |= UART_LSR_OE;
 832         }
 833
 834         /*
 835          * ignore all characters if CREAD is not set
 836          */
 837         if ((termios->c_cflag & CREAD) == 0)
 838                 up->port.ignore_status_mask |= UART_LSR_DR;
 839
 840         /*
 841          * Modem status interrupts
 842          */
 843         up->ier &= ~UART_IER_MSI;
 844         if (UART_ENABLE_MS(&up->port, termios->c_cflag))
 845                 up->ier |= UART_IER_MSI;
 846         serial_out(up, UART_IER, up->ier);
 847         serial_out(up, UART_LCR, cval);         /* reset DLAB */
 848         up->lcr = cval;
 849         up->scr = OMAP_UART_SCR_TX_EMPTY;
 850
 851         /* FIFOs and DMA Settings */
 852
 853         /* FCR can be changed only when the
 854          * baud clock is not running
 855          * DLL_REG and DLH_REG set to 0.
 856          */
 857         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 858         serial_out(up, UART_DLL, 0);
 859         serial_out(up, UART_DLM, 0);
 860         serial_out(up, UART_LCR, 0);
 861
 862         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 863
 864         up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB;
 865         up->efr &= ~UART_EFR_SCD;
 866         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 867
 868         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 869         up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR;
 870         serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
 871         /* FIFO ENABLE, DMA MODE */
 872
 873         up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
 874
 875         /* Set receive FIFO threshold to 16 characters and
 876          * transmit FIFO threshold to 16 spaces
 877          */
 878         up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
 879         up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK;
 880         up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 |
 881                 UART_FCR_ENABLE_FIFO;
 882
 883         serial_out(up, UART_FCR, up->fcr);
 884         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 885
 886         serial_out(up, UART_OMAP_SCR, up->scr);
 887
 888         /* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */
 889         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 890         serial_out(up, UART_MCR, up->mcr);
 891         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 892         serial_out(up, UART_EFR, up->efr);
 893         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 894
 895         /* Protocol, Baud Rate, and Interrupt Settings */
 896
 897         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
 898                 serial_omap_mdr1_errataset(up, up->mdr1);
 899         else
 900                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
 901
 902         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 903         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 904
 905         serial_out(up, UART_LCR, 0);
 906         serial_out(up, UART_IER, 0);
 907         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 908
 909         serial_out(up, UART_DLL, up->dll);      /* LS of divisor */
 910         serial_out(up, UART_DLM, up->dlh);      /* MS of divisor */
 911
 912         serial_out(up, UART_LCR, 0);
 913         serial_out(up, UART_IER, up->ier);
 914         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 915
 916         serial_out(up, UART_EFR, up->efr);
 917         serial_out(up, UART_LCR, cval);
 918
 919         if (baud > 230400 && baud != 3000000)
 920                 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
 921         else
 922                 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
 923
 924         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
 925                 serial_omap_mdr1_errataset(up, up->mdr1);
 926         else
 927                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
 928
 929         /* Configure flow control */
 930         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 931
 932         /* XON1/XOFF1 accessible mode B, TCRTLR=0, ECB=0 */
 933         serial_out(up, UART_XON1, termios->c_cc[VSTART]);
 934         serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
 935
 936         /* Enable access to TCR/TLR */
 937         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 938         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 939         serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
 940
 941         serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
 942
 943         if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
 944                 /* Enable AUTORTS and AUTOCTS */
 945                 up->efr |= UART_EFR_CTS | UART_EFR_RTS;
 946
 947                 /* Ensure MCR RTS is asserted */
 948                 up->mcr |= UART_MCR_RTS;
 949         } else {
 950                 /* Disable AUTORTS and AUTOCTS */
 951                 up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS);
 952         }
 953
 954         if (up->port.flags & UPF_SOFT_FLOW) {
 955                 /* clear SW control mode bits */
 956                 up->efr &= OMAP_UART_SW_CLR;
 957
 958                 /*
 959                  * IXON Flag:
 960                  * Enable XON/XOFF flow control on input.
 961                  * Receiver compares XON1, XOFF1.
 962                  */
 963                 if (termios->c_iflag & IXON)
 964                         up->efr |= OMAP_UART_SW_RX;
 965
 966                 /*
 967                  * IXOFF Flag:
 968                  * Enable XON/XOFF flow control on output.
 969                  * Transmit XON1, XOFF1
 970                  */
 971                 if (termios->c_iflag & IXOFF)
 972                         up->efr |= OMAP_UART_SW_TX;
 973
 974                 /*
 975                  * IXANY Flag:
 976                  * Enable any character to restart output.
 977                  * Operation resumes after receiving any
 978                  * character after recognition of the XOFF character
 979                  */
 980                 if (termios->c_iflag & IXANY)
 981                         up->mcr |= UART_MCR_XONANY;
 982                 else
 983                         up->mcr &= ~UART_MCR_XONANY;
 984         }
 985         serial_out(up, UART_MCR, up->mcr);
 986         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 987         serial_out(up, UART_EFR, up->efr);
 988         serial_out(up, UART_LCR, up->lcr);
 989
 990         serial_omap_set_mctrl(&up->port, up->port.mctrl);
 991
 992         spin_unlock_irqrestore(&up->port.lock, flags);
 993         pm_runtime_mark_last_busy(up->dev);
 994         pm_runtime_put_autosuspend(up->dev);
 995         dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
 996 }
 997
 998 static int serial_omap_set_wake(struct uart_port *port, unsigned int state)
 999 {
1000         struct uart_omap_port *up = to_uart_omap_port(port);
1001
1002         serial_omap_enable_wakeup(up, state);
1003
1004         return 0;
1005 }
1006
1007 static void
1008 serial_omap_pm(struct uart_port *port, unsigned int state,
1009                unsigned int oldstate)
1010 {
1011         struct uart_omap_port *up = to_uart_omap_port(port);
1012         unsigned char efr;
1013
1014         dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
1015
1016         pm_runtime_get_sync(up->dev);
1017         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1018         efr = serial_in(up, UART_EFR);
1019         serial_out(up, UART_EFR, efr | UART_EFR_ECB);
1020         serial_out(up, UART_LCR, 0);
1021
1022         serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
1023         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1024         serial_out(up, UART_EFR, efr);
1025         serial_out(up, UART_LCR, 0);
1026
1027         if (!device_may_wakeup(up->dev)) {
1028                 if (!state)
1029                         pm_runtime_forbid(up->dev);
1030                 else
1031                         pm_runtime_allow(up->dev);
1032         }
1033
1034         pm_runtime_mark_last_busy(up->dev);
1035         pm_runtime_put_autosuspend(up->dev);
1036 }
1037
1038 static void serial_omap_release_port(struct uart_port *port)
1039 {
1040         dev_dbg(port->dev, "serial_omap_release_port+\n");
1041 }
1042
1043 static int serial_omap_request_port(struct uart_port *port)
1044 {
1045         dev_dbg(port->dev, "serial_omap_request_port+\n");
1046         return 0;
1047 }
1048
1049 static void serial_omap_config_port(struct uart_port *port, int flags)
1050 {
1051         struct uart_omap_port *up = to_uart_omap_port(port);
1052
1053         dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
1054                                                         up->port.line);
1055         up->port.type = PORT_OMAP;
1056         up->port.flags |= UPF_SOFT_FLOW | UPF_HARD_FLOW;
1057 }
1058
1059 static int
1060 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
1061 {
1062         /* we don't want the core code to modify any port params */
1063         dev_dbg(port->dev, "serial_omap_verify_port+\n");
1064         return -EINVAL;
1065 }
1066
1067 static const char *
1068 serial_omap_type(struct uart_port *port)
1069 {
1070         struct uart_omap_port *up = to_uart_omap_port(port);
1071
1072         dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
1073         return up->name;
1074 }
1075
1076 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1077
1078 static inline void wait_for_xmitr(struct uart_omap_port *up)
1079 {
1080         unsigned int status, tmout = 10000;
1081
1082         /* Wait up to 10ms for the character(s) to be sent. */
1083         do {
1084                 status = serial_in(up, UART_LSR);
1085
1086                 if (status & UART_LSR_BI)
1087                         up->lsr_break_flag = UART_LSR_BI;
1088
1089                 if (--tmout == 0)
1090                         break;
1091                 udelay(1);
1092         } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
1093
1094         /* Wait up to 1s for flow control if necessary */
1095         if (up->port.flags & UPF_CONS_FLOW) {
1096                 tmout = 1000000;
1097                 for (tmout = 1000000; tmout; tmout--) {
1098                         unsigned int msr = serial_in(up, UART_MSR);
1099
1100                         up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1101                         if (msr & UART_MSR_CTS)
1102                                 break;
1103
1104                         udelay(1);
1105                 }
1106         }
1107 }
1108
1109 #ifdef CONFIG_CONSOLE_POLL
1110
1111 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
1112 {
1113         struct uart_omap_port *up = to_uart_omap_port(port);
1114
1115         pm_runtime_get_sync(up->dev);
1116         wait_for_xmitr(up);
1117         serial_out(up, UART_TX, ch);
1118         pm_runtime_mark_last_busy(up->dev);
1119         pm_runtime_put_autosuspend(up->dev);
1120 }
1121
1122 static int serial_omap_poll_get_char(struct uart_port *port)
1123 {
1124         struct uart_omap_port *up = to_uart_omap_port(port);
1125         unsigned int status;
1126
1127         pm_runtime_get_sync(up->dev);
1128         status = serial_in(up, UART_LSR);
1129         if (!(status & UART_LSR_DR)) {
1130                 status = NO_POLL_CHAR;
1131                 goto out;
1132         }
1133
1134         status = serial_in(up, UART_RX);
1135
1136 out:
1137         pm_runtime_mark_last_busy(up->dev);
1138         pm_runtime_put_autosuspend(up->dev);
1139
1140         return status;
1141 }
1142
1143 #endif /* CONFIG_CONSOLE_POLL */
1144
1145 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
1146
1147 static struct uart_omap_port *serial_omap_console_ports[OMAP_MAX_HSUART_PORTS];
1148
1149 static struct uart_driver serial_omap_reg;
1150
1151 static void serial_omap_console_putchar(struct uart_port *port, int ch)
1152 {
1153         struct uart_omap_port *up = to_uart_omap_port(port);
1154
1155         wait_for_xmitr(up);
1156         serial_out(up, UART_TX, ch);
1157 }
1158
1159 static void
1160 serial_omap_console_write(struct console *co, const char *s,
1161                 unsigned int count)
1162 {
1163         struct uart_omap_port *up = serial_omap_console_ports[co->index];
1164         unsigned long flags;
1165         unsigned int ier;
1166         int locked = 1;
1167
1168         pm_runtime_get_sync(up->dev);
1169
1170         local_irq_save(flags);
1171         if (up->port.sysrq)
1172                 locked = 0;
1173         else if (oops_in_progress)
1174                 locked = spin_trylock(&up->port.lock);
1175         else
1176                 spin_lock(&up->port.lock);
1177
1178         /*
1179          * First save the IER then disable the interrupts
1180          */
1181         ier = serial_in(up, UART_IER);
1182         serial_out(up, UART_IER, 0);
1183
1184         uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1185
1186         /*
1187          * Finally, wait for transmitter to become empty
1188          * and restore the IER
1189          */
1190         wait_for_xmitr(up);
1191         serial_out(up, UART_IER, ier);
1192         /*
1193          * The receive handling will happen properly because the
1194          * receive ready bit will still be set; it is not cleared
1195          * on read.  However, modem control will not, we must
1196          * call it if we have saved something in the saved flags
1197          * while processing with interrupts off.
1198          */
1199         if (up->msr_saved_flags)
1200                 check_modem_status(up);
1201
1202         pm_runtime_mark_last_busy(up->dev);
1203         pm_runtime_put_autosuspend(up->dev);
1204         if (locked)
1205                 spin_unlock(&up->port.lock);
1206         local_irq_restore(flags);
1207 }
1208
1209 static int __init
1210 serial_omap_console_setup(struct console *co, char *options)
1211 {
1212         struct uart_omap_port *up;
1213         int baud = 115200;
1214         int bits = 8;
1215         int parity = 'n';
1216         int flow = 'n';
1217
1218         if (serial_omap_console_ports[co->index] == NULL)
1219                 return -ENODEV;
1220         up = serial_omap_console_ports[co->index];
1221
1222         if (options)
1223                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1224
1225         return uart_set_options(&up->port, co, baud, parity, bits, flow);
1226 }
1227
1228 static struct console serial_omap_console = {
1229         .name           = OMAP_SERIAL_NAME,
1230         .write          = serial_omap_console_write,
1231         .device         = uart_console_device,
1232         .setup          = serial_omap_console_setup,
1233         .flags          = CON_PRINTBUFFER,
1234         .index          = -1,
1235         .data           = &serial_omap_reg,
1236 };
1237
1238 static void serial_omap_add_console_port(struct uart_omap_port *up)
1239 {
1240         serial_omap_console_ports[up->port.line] = up;
1241 }
1242
1243 #define OMAP_CONSOLE    (&serial_omap_console)
1244
1245 #else
1246
1247 #define OMAP_CONSOLE    NULL
1248
1249 static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1250 {}
1251
1252 #endif
1253
1254 static struct uart_ops serial_omap_pops = {
1255         .tx_empty       = serial_omap_tx_empty,
1256         .set_mctrl      = serial_omap_set_mctrl,
1257         .get_mctrl      = serial_omap_get_mctrl,
1258         .stop_tx        = serial_omap_stop_tx,
1259         .start_tx       = serial_omap_start_tx,
1260         .throttle       = serial_omap_throttle,
1261         .unthrottle     = serial_omap_unthrottle,
1262         .stop_rx        = serial_omap_stop_rx,
1263         .enable_ms      = serial_omap_enable_ms,
1264         .break_ctl      = serial_omap_break_ctl,
1265         .startup        = serial_omap_startup,
1266         .shutdown       = serial_omap_shutdown,
1267         .set_termios    = serial_omap_set_termios,
1268         .pm             = serial_omap_pm,
1269         .set_wake       = serial_omap_set_wake,
1270         .type           = serial_omap_type,
1271         .release_port   = serial_omap_release_port,
1272         .request_port   = serial_omap_request_port,
1273         .config_port    = serial_omap_config_port,
1274         .verify_port    = serial_omap_verify_port,
1275 #ifdef CONFIG_CONSOLE_POLL
1276         .poll_put_char  = serial_omap_poll_put_char,
1277         .poll_get_char  = serial_omap_poll_get_char,
1278 #endif
1279 };
1280
1281 static struct uart_driver serial_omap_reg = {
1282         .owner          = THIS_MODULE,
1283         .driver_name    = "OMAP-SERIAL",
1284         .dev_name       = OMAP_SERIAL_NAME,
1285         .nr             = OMAP_MAX_HSUART_PORTS,
1286         .cons           = OMAP_CONSOLE,
1287 };
1288
1289 #ifdef CONFIG_PM_SLEEP
1290 static int serial_omap_suspend(struct device *dev)
1291 {
1292         struct uart_omap_port *up = dev_get_drvdata(dev);
1293
1294         uart_suspend_port(&serial_omap_reg, &up->port);
1295         flush_work(&up->qos_work);
1296
1297         return 0;
1298 }
1299
1300 static int serial_omap_resume(struct device *dev)
1301 {
1302         struct uart_omap_port *up = dev_get_drvdata(dev);
1303
1304         uart_resume_port(&serial_omap_reg, &up->port);
1305
1306         return 0;
1307 }
1308 #endif
1309
1310 static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
1311 {
1312         u32 mvr, scheme;
1313         u16 revision, major, minor;
1314
1315         mvr = serial_in(up, UART_OMAP_MVER);
1316
1317         /* Check revision register scheme */
1318         scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
1319
1320         switch (scheme) {
1321         case 0: /* Legacy Scheme: OMAP2/3 */
1322                 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
1323                 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
1324                                         OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
1325                 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
1326                 break;
1327         case 1:
1328                 /* New Scheme: OMAP4+ */
1329                 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
1330                 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
1331                                         OMAP_UART_MVR_MAJ_SHIFT;
1332                 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
1333                 break;
1334         default:
1335                 dev_warn(up->dev,
1336                         "Unknown %s revision, defaulting to highest\n",
1337                         up->name);
1338                 /* highest possible revision */
1339                 major = 0xff;
1340                 minor = 0xff;
1341         }
1342
1343         /* normalize revision for the driver */
1344         revision = UART_BUILD_REVISION(major, minor);
1345
1346         switch (revision) {
1347         case OMAP_UART_REV_46:
1348                 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1349                                 UART_ERRATA_i291_DMA_FORCEIDLE);
1350                 break;
1351         case OMAP_UART_REV_52:
1352                 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1353                                 UART_ERRATA_i291_DMA_FORCEIDLE);
1354                 break;
1355         case OMAP_UART_REV_63:
1356                 up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
1357                 break;
1358         default:
1359                 break;
1360         }
1361 }
1362
1363 static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
1364 {
1365         struct omap_uart_port_info *omap_up_info;
1366
1367         omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
1368         if (!omap_up_info)
1369                 return NULL; /* out of memory */
1370
1371         of_property_read_u32(dev->of_node, "clock-frequency",
1372                                          &omap_up_info->uartclk);
1373         return omap_up_info;
1374 }
1375
1376 static int serial_omap_probe(struct platform_device *pdev)
1377 {
1378         struct uart_omap_port   *up;
1379         struct resource         *mem, *irq;
1380         struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data;
1381         int ret;
1382
1383         if (pdev->dev.of_node)
1384                 omap_up_info = of_get_uart_port_info(&pdev->dev);
1385
1386         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1387         if (!mem) {
1388                 dev_err(&pdev->dev, "no mem resource?\n");
1389                 return -ENODEV;
1390         }
1391
1392         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1393         if (!irq) {
1394                 dev_err(&pdev->dev, "no irq resource?\n");
1395                 return -ENODEV;
1396         }
1397
1398         if (!devm_request_mem_region(&pdev->dev, mem->start, resource_size(mem),
1399                                 pdev->dev.driver->name)) {
1400                 dev_err(&pdev->dev, "memory region already claimed\n");
1401                 return -EBUSY;
1402         }
1403
1404         if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1405             omap_up_info->DTR_present) {
1406                 ret = gpio_request(omap_up_info->DTR_gpio, "omap-serial");
1407                 if (ret < 0)
1408                         return ret;
1409                 ret = gpio_direction_output(omap_up_info->DTR_gpio,
1410                                             omap_up_info->DTR_inverted);
1411                 if (ret < 0)
1412                         return ret;
1413         }
1414
1415         up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
1416         if (!up)
1417                 return -ENOMEM;
1418
1419         if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1420             omap_up_info->DTR_present) {
1421                 up->DTR_gpio = omap_up_info->DTR_gpio;
1422                 up->DTR_inverted = omap_up_info->DTR_inverted;
1423         } else
1424                 up->DTR_gpio = -EINVAL;
1425         up->DTR_active = 0;
1426
1427         up->dev = &pdev->dev;
1428         up->port.dev = &pdev->dev;
1429         up->port.type = PORT_OMAP;
1430         up->port.iotype = UPIO_MEM;
1431         up->port.irq = irq->start;
1432
1433         up->port.regshift = 2;
1434         up->port.fifosize = 64;
1435         up->port.ops = &serial_omap_pops;
1436
1437         if (pdev->dev.of_node)
1438                 up->port.line = of_alias_get_id(pdev->dev.of_node, "serial");
1439         else
1440                 up->port.line = pdev->id;
1441
1442         if (up->port.line < 0) {
1443                 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
1444                                                                 up->port.line);
1445                 ret = -ENODEV;
1446                 goto err_port_line;
1447         }
1448
1449         up->pins = devm_pinctrl_get_select_default(&pdev->dev);
1450         if (IS_ERR(up->pins)) {
1451                 dev_warn(&pdev->dev, "did not get pins for uart%i error: %li\n",
1452                          up->port.line, PTR_ERR(up->pins));
1453                 up->pins = NULL;
1454         }
1455
1456         sprintf(up->name, "OMAP UART%d", up->port.line);
1457         up->port.mapbase = mem->start;
1458         up->port.membase = devm_ioremap(&pdev->dev, mem->start,
1459                                                 resource_size(mem));
1460         if (!up->port.membase) {
1461                 dev_err(&pdev->dev, "can't ioremap UART\n");
1462                 ret = -ENOMEM;
1463                 goto err_ioremap;
1464         }
1465
1466         up->port.flags = omap_up_info->flags;
1467         up->port.uartclk = omap_up_info->uartclk;
1468         if (!up->port.uartclk) {
1469                 up->port.uartclk = DEFAULT_CLK_SPEED;
1470                 dev_warn(&pdev->dev, "No clock speed specified: using default:"
1471                                                 "%d\n", DEFAULT_CLK_SPEED);
1472         }
1473
1474         up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1475         up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1476         pm_qos_add_request(&up->pm_qos_request,
1477                 PM_QOS_CPU_DMA_LATENCY, up->latency);
1478         serial_omap_uart_wq = create_singlethread_workqueue(up->name);
1479         INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1480
1481         platform_set_drvdata(pdev, up);
1482         pm_runtime_enable(&pdev->dev);
1483         pm_runtime_use_autosuspend(&pdev->dev);
1484         pm_runtime_set_autosuspend_delay(&pdev->dev,
1485                         omap_up_info->autosuspend_timeout);
1486
1487         pm_runtime_irq_safe(&pdev->dev);
1488         pm_runtime_get_sync(&pdev->dev);
1489
1490         omap_serial_fill_features_erratas(up);
1491
1492         ui[up->port.line] = up;
1493         serial_omap_add_console_port(up);
1494
1495         ret = uart_add_one_port(&serial_omap_reg, &up->port);
1496         if (ret != 0)
1497                 goto err_add_port;
1498
1499         pm_runtime_mark_last_busy(up->dev);
1500         pm_runtime_put_autosuspend(up->dev);
1501         return 0;
1502
1503 err_add_port:
1504         pm_runtime_put(&pdev->dev);
1505         pm_runtime_disable(&pdev->dev);
1506 err_ioremap:
1507 err_port_line:
1508         dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n",
1509                                 pdev->id, __func__, ret);
1510         return ret;
1511 }
1512
1513 static int serial_omap_remove(struct platform_device *dev)
1514 {
1515         struct uart_omap_port *up = platform_get_drvdata(dev);
1516
1517         pm_runtime_put_sync(up->dev);
1518         pm_runtime_disable(up->dev);
1519         uart_remove_one_port(&serial_omap_reg, &up->port);
1520         pm_qos_remove_request(&up->pm_qos_request);
1521
1522         return 0;
1523 }
1524
1525 /*
1526  * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1527  * The access to uart register after MDR1 Access
1528  * causes UART to corrupt data.
1529  *
1530  * Need a delay =
1531  * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1532  * give 10 times as much
1533  */
1534 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1535 {
1536         u8 timeout = 255;
1537
1538         serial_out(up, UART_OMAP_MDR1, mdr1);
1539         udelay(2);
1540         serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1541                         UART_FCR_CLEAR_RCVR);
1542         /*
1543          * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1544          * TX_FIFO_E bit is 1.
1545          */
1546         while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1547                                 (UART_LSR_THRE | UART_LSR_DR))) {
1548                 timeout--;
1549                 if (!timeout) {
1550                         /* Should *never* happen. we warn and carry on */
1551                         dev_crit(up->dev, "Errata i202: timedout %x\n",
1552                                                 serial_in(up, UART_LSR));
1553                         break;
1554                 }
1555                 udelay(1);
1556         }
1557 }
1558
1559 #ifdef CONFIG_PM_RUNTIME
1560 static void serial_omap_restore_context(struct uart_omap_port *up)
1561 {
1562         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1563                 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1564         else
1565                 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1566
1567         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1568         serial_out(up, UART_EFR, UART_EFR_ECB);
1569         serial_out(up, UART_LCR, 0x0); /* Operational mode */
1570         serial_out(up, UART_IER, 0x0);
1571         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1572         serial_out(up, UART_DLL, up->dll);
1573         serial_out(up, UART_DLM, up->dlh);
1574         serial_out(up, UART_LCR, 0x0); /* Operational mode */
1575         serial_out(up, UART_IER, up->ier);
1576         serial_out(up, UART_FCR, up->fcr);
1577         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1578         serial_out(up, UART_MCR, up->mcr);
1579         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1580         serial_out(up, UART_OMAP_SCR, up->scr);
1581         serial_out(up, UART_EFR, up->efr);
1582         serial_out(up, UART_LCR, up->lcr);
1583         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1584                 serial_omap_mdr1_errataset(up, up->mdr1);
1585         else
1586                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1587 }
1588
1589 static int serial_omap_runtime_suspend(struct device *dev)
1590 {
1591         struct uart_omap_port *up = dev_get_drvdata(dev);
1592         struct omap_uart_port_info *pdata = dev->platform_data;
1593
1594         if (!up)
1595                 return -EINVAL;
1596
1597         if (!pdata)
1598                 return 0;
1599
1600         up->context_loss_cnt = serial_omap_get_context_loss_count(up);
1601
1602         if (device_may_wakeup(dev)) {
1603                 if (!up->wakeups_enabled) {
1604                         serial_omap_enable_wakeup(up, true);
1605                         up->wakeups_enabled = true;
1606                 }
1607         } else {
1608                 if (up->wakeups_enabled) {
1609                         serial_omap_enable_wakeup(up, false);
1610                         up->wakeups_enabled = false;
1611                 }
1612         }
1613
1614         up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1615         schedule_work(&up->qos_work);
1616
1617         return 0;
1618 }
1619
1620 static int serial_omap_runtime_resume(struct device *dev)
1621 {
1622         struct uart_omap_port *up = dev_get_drvdata(dev);
1623
1624         int loss_cnt = serial_omap_get_context_loss_count(up);
1625
1626         if (loss_cnt < 0) {
1627                 dev_err(dev, "serial_omap_get_context_loss_count failed : %d\n",
1628                         loss_cnt);
1629                 serial_omap_restore_context(up);
1630         } else if (up->context_loss_cnt != loss_cnt) {
1631                 serial_omap_restore_context(up);
1632         }
1633         up->latency = up->calc_latency;
1634         schedule_work(&up->qos_work);
1635
1636         return 0;
1637 }
1638 #endif
1639
1640 static const struct dev_pm_ops serial_omap_dev_pm_ops = {
1641         SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
1642         SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
1643                                 serial_omap_runtime_resume, NULL)
1644 };
1645
1646 #if defined(CONFIG_OF)
1647 static const struct of_device_id omap_serial_of_match[] = {
1648         { .compatible = "ti,omap2-uart" },
1649         { .compatible = "ti,omap3-uart" },
1650         { .compatible = "ti,omap4-uart" },
1651         {},
1652 };
1653 MODULE_DEVICE_TABLE(of, omap_serial_of_match);
1654 #endif
1655
1656 static struct platform_driver serial_omap_driver = {
1657         .probe          = serial_omap_probe,
1658         .remove         = serial_omap_remove,
1659         .driver         = {
1660                 .name   = DRIVER_NAME,
1661                 .pm     = &serial_omap_dev_pm_ops,
1662                 .of_match_table = of_match_ptr(omap_serial_of_match),
1663         },
1664 };
1665
1666 static int __init serial_omap_init(void)
1667 {
1668         int ret;
1669
1670         ret = uart_register_driver(&serial_omap_reg);
1671         if (ret != 0)
1672                 return ret;
1673         ret = platform_driver_register(&serial_omap_driver);
1674         if (ret != 0)
1675                 uart_unregister_driver(&serial_omap_reg);
1676         return ret;
1677 }
1678
1679 static void __exit serial_omap_exit(void)
1680 {
1681         platform_driver_unregister(&serial_omap_driver);
1682         uart_unregister_driver(&serial_omap_reg);
1683 }
1684
1685 module_init(serial_omap_init);
1686 module_exit(serial_omap_exit);
1687
1688 MODULE_DESCRIPTION("OMAP High Speed UART driver");
1689 MODULE_LICENSE("GPL");
1690 MODULE_AUTHOR("Texas Instruments Inc");