drivers/tty/serial/omap-serial.c

   1 /*
   2  * Driver for OMAP-UART controller.
   3  * Based on drivers/serial/8250.c
   4  *
   5  * Copyright (C) 2010 Texas Instruments.
   6  *
   7  * Authors:
   8  *      Govindraj R     <govindraj.raja@ti.com>
   9  *      Thara Gopinath  <thara@ti.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * Note: This driver is made separate from 8250 driver as we cannot
  17  * over load 8250 driver with omap platform specific configuration for
  18  * features like DMA, it makes easier to implement features like DMA and
  19  * hardware flow control and software flow control configuration with
  20  * this driver as required for the omap-platform.
  21  */
  22
  23 #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  24 #define SUPPORT_SYSRQ
  25 #endif
  26
  27 #include <linux/module.h>
  28 #include <linux/init.h>
  29 #include <linux/console.h>
  30 #include <linux/serial_reg.h>
  31 #include <linux/delay.h>
  32 #include <linux/slab.h>
  33 #include <linux/tty.h>
  34 #include <linux/tty_flip.h>
  35 #include <linux/io.h>
  36 #include <linux/dma-mapping.h>
  37 #include <linux/clk.h>
  38 #include <linux/serial_core.h>
  39 #include <linux/irq.h>
  40 #include <linux/pm_runtime.h>
  41
  42 #include <plat/dma.h>
  43 #include <plat/dmtimer.h>
  44 #include <plat/omap-serial.h>
  45
  46 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
  47
  48 /* Forward declaration of functions */
  49 static void uart_tx_dma_callback(int lch, u16 ch_status, void *data);
  50 static void serial_omap_rxdma_poll(unsigned long uart_no);
  51 static int serial_omap_start_rxdma(struct uart_omap_port *up);
  52 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
  53
  54 static struct workqueue_struct *serial_omap_uart_wq;
  55
  56 static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
  57 {
  58         offset <<= up->port.regshift;
  59         return readw(up->port.membase + offset);
  60 }
  61
  62 static inline void serial_out(struct uart_omap_port *up, int offset, int value)
  63 {
  64         offset <<= up->port.regshift;
  65         writew(value, up->port.membase + offset);
  66 }
  67
  68 static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
  69 {
  70         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
  71         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
  72                        UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
  73         serial_out(up, UART_FCR, 0);
  74 }
  75
  76 /*
  77  * serial_omap_get_divisor - calculate divisor value
  78  * @port: uart port info
  79  * @baud: baudrate for which divisor needs to be calculated.
  80  *
  81  * We have written our own function to get the divisor so as to support
  82  * 13x mode. 3Mbps Baudrate as an different divisor.
  83  * Reference OMAP TRM Chapter 17:
  84  * Table 17-1. UART Mode Baud Rates, Divisor Values, and Error Rates
  85  * referring to oversampling - divisor value
  86  * baudrate 460,800 to 3,686,400 all have divisor 13
  87  * except 3,000,000 which has divisor value 16
  88  */
  89 static unsigned int
  90 serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
  91 {
  92         unsigned int divisor;
  93
  94         if (baud > OMAP_MODE13X_SPEED && baud != 3000000)
  95                 divisor = 13;
  96         else
  97                 divisor = 16;
  98         return port->uartclk/(baud * divisor);
  99 }
 100
 101 static void serial_omap_stop_rxdma(struct uart_omap_port *up)
 102 {
 103         if (up->uart_dma.rx_dma_used) {
 104                 del_timer(&up->uart_dma.rx_timer);
 105                 omap_stop_dma(up->uart_dma.rx_dma_channel);
 106                 omap_free_dma(up->uart_dma.rx_dma_channel);
 107                 up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE;
 108                 up->uart_dma.rx_dma_used = false;
 109                 pm_runtime_mark_last_busy(&up->pdev->dev);
 110                 pm_runtime_put_autosuspend(&up->pdev->dev);
 111         }
 112 }
 113
 114 static void serial_omap_enable_ms(struct uart_port *port)
 115 {
 116         struct uart_omap_port *up = (struct uart_omap_port *)port;
 117
 118         dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->pdev->id);
 119
 120         pm_runtime_get_sync(&up->pdev->dev);
 121         up->ier |= UART_IER_MSI;
 122         serial_out(up, UART_IER, up->ier);
 123         pm_runtime_put(&up->pdev->dev);
 124 }
 125
 126 static void serial_omap_stop_tx(struct uart_port *port)
 127 {
 128         struct uart_omap_port *up = (struct uart_omap_port *)port;
 129
 130         if (up->use_dma &&
 131                 up->uart_dma.tx_dma_channel != OMAP_UART_DMA_CH_FREE) {
 132                 /*
 133                  * Check if dma is still active. If yes do nothing,
 134                  * return. Else stop dma
 135                  */
 136                 if (omap_get_dma_active_status(up->uart_dma.tx_dma_channel))
 137                         return;
 138                 omap_stop_dma(up->uart_dma.tx_dma_channel);
 139                 omap_free_dma(up->uart_dma.tx_dma_channel);
 140                 up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE;
 141                 pm_runtime_mark_last_busy(&up->pdev->dev);
 142                 pm_runtime_put_autosuspend(&up->pdev->dev);
 143         }
 144
 145         pm_runtime_get_sync(&up->pdev->dev);
 146         if (up->ier & UART_IER_THRI) {
 147                 up->ier &= ~UART_IER_THRI;
 148                 serial_out(up, UART_IER, up->ier);
 149         }
 150
 151         pm_runtime_mark_last_busy(&up->pdev->dev);
 152         pm_runtime_put_autosuspend(&up->pdev->dev);
 153 }
 154
 155 static void serial_omap_stop_rx(struct uart_port *port)
 156 {
 157         struct uart_omap_port *up = (struct uart_omap_port *)port;
 158
 159         pm_runtime_get_sync(&up->pdev->dev);
 160         if (up->use_dma)
 161                 serial_omap_stop_rxdma(up);
 162         up->ier &= ~UART_IER_RLSI;
 163         up->port.read_status_mask &= ~UART_LSR_DR;
 164         serial_out(up, UART_IER, up->ier);
 165         pm_runtime_mark_last_busy(&up->pdev->dev);
 166         pm_runtime_put_autosuspend(&up->pdev->dev);
 167 }
 168
 169 static inline void receive_chars(struct uart_omap_port *up,
 170                 unsigned int *status)
 171 {
 172         struct tty_struct *tty = up->port.state->port.tty;
 173         unsigned int flag, lsr = *status;
 174         unsigned char ch = 0;
 175         int max_count = 256;
 176
 177         do {
 178                 if (likely(lsr & UART_LSR_DR))
 179                         ch = serial_in(up, UART_RX);
 180                 flag = TTY_NORMAL;
 181                 up->port.icount.rx++;
 182
 183                 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
 184                         /*
 185                          * For statistics only
 186                          */
 187                         if (lsr & UART_LSR_BI) {
 188                                 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
 189                                 up->port.icount.brk++;
 190                                 /*
 191                                  * We do the SysRQ and SAK checking
 192                                  * here because otherwise the break
 193                                  * may get masked by ignore_status_mask
 194                                  * or read_status_mask.
 195                                  */
 196                                 if (uart_handle_break(&up->port))
 197                                         goto ignore_char;
 198                         } else if (lsr & UART_LSR_PE) {
 199                                 up->port.icount.parity++;
 200                         } else if (lsr & UART_LSR_FE) {
 201                                 up->port.icount.frame++;
 202                         }
 203
 204                         if (lsr & UART_LSR_OE)
 205                                 up->port.icount.overrun++;
 206
 207                         /*
 208                          * Mask off conditions which should be ignored.
 209                          */
 210                         lsr &= up->port.read_status_mask;
 211
 212 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
 213                         if (up->port.line == up->port.cons->index) {
 214                                 /* Recover the break flag from console xmit */
 215                                 lsr |= up->lsr_break_flag;
 216                         }
 217 #endif
 218                         if (lsr & UART_LSR_BI)
 219                                 flag = TTY_BREAK;
 220                         else if (lsr & UART_LSR_PE)
 221                                 flag = TTY_PARITY;
 222                         else if (lsr & UART_LSR_FE)
 223                                 flag = TTY_FRAME;
 224                 }
 225
 226                 if (uart_handle_sysrq_char(&up->port, ch))
 227                         goto ignore_char;
 228                 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
 229 ignore_char:
 230                 lsr = serial_in(up, UART_LSR);
 231         } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
 232         spin_unlock(&up->port.lock);
 233         tty_flip_buffer_push(tty);
 234         spin_lock(&up->port.lock);
 235 }
 236
 237 static void transmit_chars(struct uart_omap_port *up)
 238 {
 239         struct circ_buf *xmit = &up->port.state->xmit;
 240         int count;
 241
 242         if (up->port.x_char) {
 243                 serial_out(up, UART_TX, up->port.x_char);
 244                 up->port.icount.tx++;
 245                 up->port.x_char = 0;
 246                 return;
 247         }
 248         if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
 249                 serial_omap_stop_tx(&up->port);
 250                 return;
 251         }
 252         count = up->port.fifosize / 4;
 253         do {
 254                 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
 255                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 256                 up->port.icount.tx++;
 257                 if (uart_circ_empty(xmit))
 258                         break;
 259         } while (--count > 0);
 260
 261         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 262                 uart_write_wakeup(&up->port);
 263
 264         if (uart_circ_empty(xmit))
 265                 serial_omap_stop_tx(&up->port);
 266 }
 267
 268 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
 269 {
 270         if (!(up->ier & UART_IER_THRI)) {
 271                 up->ier |= UART_IER_THRI;
 272                 serial_out(up, UART_IER, up->ier);
 273         }
 274 }
 275
 276 static void serial_omap_start_tx(struct uart_port *port)
 277 {
 278         struct uart_omap_port *up = (struct uart_omap_port *)port;
 279         struct circ_buf *xmit;
 280         unsigned int start;
 281         int ret = 0;
 282
 283         if (!up->use_dma) {
 284                 pm_runtime_get_sync(&up->pdev->dev);
 285                 serial_omap_enable_ier_thri(up);
 286                 pm_runtime_mark_last_busy(&up->pdev->dev);
 287                 pm_runtime_put_autosuspend(&up->pdev->dev);
 288                 return;
 289         }
 290
 291         if (up->uart_dma.tx_dma_used)
 292                 return;
 293
 294         xmit = &up->port.state->xmit;
 295
 296         if (up->uart_dma.tx_dma_channel == OMAP_UART_DMA_CH_FREE) {
 297                 pm_runtime_get_sync(&up->pdev->dev);
 298                 ret = omap_request_dma(up->uart_dma.uart_dma_tx,
 299                                 "UART Tx DMA",
 300                                 (void *)uart_tx_dma_callback, up,
 301                                 &(up->uart_dma.tx_dma_channel));
 302
 303                 if (ret < 0) {
 304                         serial_omap_enable_ier_thri(up);
 305                         return;
 306                 }
 307         }
 308         spin_lock(&(up->uart_dma.tx_lock));
 309         up->uart_dma.tx_dma_used = true;
 310         spin_unlock(&(up->uart_dma.tx_lock));
 311
 312         start = up->uart_dma.tx_buf_dma_phys +
 313                                 (xmit->tail & (UART_XMIT_SIZE - 1));
 314
 315         up->uart_dma.tx_buf_size = uart_circ_chars_pending(xmit);
 316         /*
 317          * It is a circular buffer. See if the buffer has wounded back.
 318          * If yes it will have to be transferred in two separate dma
 319          * transfers
 320          */
 321         if (start + up->uart_dma.tx_buf_size >=
 322                         up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE)
 323                 up->uart_dma.tx_buf_size =
 324                         (up->uart_dma.tx_buf_dma_phys +
 325                         UART_XMIT_SIZE) - start;
 326
 327         omap_set_dma_dest_params(up->uart_dma.tx_dma_channel, 0,
 328                                 OMAP_DMA_AMODE_CONSTANT,
 329                                 up->uart_dma.uart_base, 0, 0);
 330         omap_set_dma_src_params(up->uart_dma.tx_dma_channel, 0,
 331                                 OMAP_DMA_AMODE_POST_INC, start, 0, 0);
 332         omap_set_dma_transfer_params(up->uart_dma.tx_dma_channel,
 333                                 OMAP_DMA_DATA_TYPE_S8,
 334                                 up->uart_dma.tx_buf_size, 1,
 335                                 OMAP_DMA_SYNC_ELEMENT,
 336                                 up->uart_dma.uart_dma_tx, 0);
 337         /* FIXME: Cache maintenance needed here? */
 338         omap_start_dma(up->uart_dma.tx_dma_channel);
 339 }
 340
 341 static unsigned int check_modem_status(struct uart_omap_port *up)
 342 {
 343         unsigned int status;
 344
 345         status = serial_in(up, UART_MSR);
 346         status |= up->msr_saved_flags;
 347         up->msr_saved_flags = 0;
 348         if ((status & UART_MSR_ANY_DELTA) == 0)
 349                 return status;
 350
 351         if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
 352             up->port.state != NULL) {
 353                 if (status & UART_MSR_TERI)
 354                         up->port.icount.rng++;
 355                 if (status & UART_MSR_DDSR)
 356                         up->port.icount.dsr++;
 357                 if (status & UART_MSR_DDCD)
 358                         uart_handle_dcd_change
 359                                 (&up->port, status & UART_MSR_DCD);
 360                 if (status & UART_MSR_DCTS)
 361                         uart_handle_cts_change
 362                                 (&up->port, status & UART_MSR_CTS);
 363                 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
 364         }
 365
 366         return status;
 367 }
 368
 369 /**
 370  * serial_omap_irq() - This handles the interrupt from one port
 371  * @irq: uart port irq number
 372  * @dev_id: uart port info
 373  */
 374 static inline irqreturn_t serial_omap_irq(int irq, void *dev_id)
 375 {
 376         struct uart_omap_port *up = dev_id;
 377         unsigned int iir, lsr;
 378         unsigned long flags;
 379
 380         pm_runtime_get_sync(&up->pdev->dev);
 381         iir = serial_in(up, UART_IIR);
 382         if (iir & UART_IIR_NO_INT) {
 383                 pm_runtime_mark_last_busy(&up->pdev->dev);
 384                 pm_runtime_put_autosuspend(&up->pdev->dev);
 385                 return IRQ_NONE;
 386         }
 387
 388         spin_lock_irqsave(&up->port.lock, flags);
 389         lsr = serial_in(up, UART_LSR);
 390         if (iir & UART_IIR_RLSI) {
 391                 if (!up->use_dma) {
 392                         if (lsr & UART_LSR_DR)
 393                                 receive_chars(up, &lsr);
 394                 } else {
 395                         up->ier &= ~(UART_IER_RDI | UART_IER_RLSI);
 396                         serial_out(up, UART_IER, up->ier);
 397                         if ((serial_omap_start_rxdma(up) != 0) &&
 398                                         (lsr & UART_LSR_DR))
 399                                 receive_chars(up, &lsr);
 400                 }
 401         }
 402
 403         check_modem_status(up);
 404         if ((lsr & UART_LSR_THRE) && (iir & UART_IIR_THRI))
 405                 transmit_chars(up);
 406
 407         spin_unlock_irqrestore(&up->port.lock, flags);
 408         pm_runtime_mark_last_busy(&up->pdev->dev);
 409         pm_runtime_put_autosuspend(&up->pdev->dev);
 410
 411         up->port_activity = jiffies;
 412         return IRQ_HANDLED;
 413 }
 414
 415 static unsigned int serial_omap_tx_empty(struct uart_port *port)
 416 {
 417         struct uart_omap_port *up = (struct uart_omap_port *)port;
 418         unsigned long flags = 0;
 419         unsigned int ret = 0;
 420
 421         pm_runtime_get_sync(&up->pdev->dev);
 422         dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->pdev->id);
 423         spin_lock_irqsave(&up->port.lock, flags);
 424         ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
 425         spin_unlock_irqrestore(&up->port.lock, flags);
 426         pm_runtime_put(&up->pdev->dev);
 427         return ret;
 428 }
 429
 430 static unsigned int serial_omap_get_mctrl(struct uart_port *port)
 431 {
 432         struct uart_omap_port *up = (struct uart_omap_port *)port;
 433         unsigned char status;
 434         unsigned int ret = 0;
 435
 436         pm_runtime_get_sync(&up->pdev->dev);
 437         status = check_modem_status(up);
 438         pm_runtime_put(&up->pdev->dev);
 439
 440         dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->pdev->id);
 441
 442         if (status & UART_MSR_DCD)
 443                 ret |= TIOCM_CAR;
 444         if (status & UART_MSR_RI)
 445                 ret |= TIOCM_RNG;
 446         if (status & UART_MSR_DSR)
 447                 ret |= TIOCM_DSR;
 448         if (status & UART_MSR_CTS)
 449                 ret |= TIOCM_CTS;
 450         return ret;
 451 }
 452
 453 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
 454 {
 455         struct uart_omap_port *up = (struct uart_omap_port *)port;
 456         unsigned char mcr = 0;
 457
 458         dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->pdev->id);
 459         if (mctrl & TIOCM_RTS)
 460                 mcr |= UART_MCR_RTS;
 461         if (mctrl & TIOCM_DTR)
 462                 mcr |= UART_MCR_DTR;
 463         if (mctrl & TIOCM_OUT1)
 464                 mcr |= UART_MCR_OUT1;
 465         if (mctrl & TIOCM_OUT2)
 466                 mcr |= UART_MCR_OUT2;
 467         if (mctrl & TIOCM_LOOP)
 468                 mcr |= UART_MCR_LOOP;
 469
 470         pm_runtime_get_sync(&up->pdev->dev);
 471         up->mcr = serial_in(up, UART_MCR);
 472         up->mcr |= mcr;
 473         serial_out(up, UART_MCR, up->mcr);
 474         pm_runtime_put(&up->pdev->dev);
 475 }
 476
 477 static void serial_omap_break_ctl(struct uart_port *port, int break_state)
 478 {
 479         struct uart_omap_port *up = (struct uart_omap_port *)port;
 480         unsigned long flags = 0;
 481
 482         dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->pdev->id);
 483         pm_runtime_get_sync(&up->pdev->dev);
 484         spin_lock_irqsave(&up->port.lock, flags);
 485         if (break_state == -1)
 486                 up->lcr |= UART_LCR_SBC;
 487         else
 488                 up->lcr &= ~UART_LCR_SBC;
 489         serial_out(up, UART_LCR, up->lcr);
 490         spin_unlock_irqrestore(&up->port.lock, flags);
 491         pm_runtime_put(&up->pdev->dev);
 492 }
 493
 494 static int serial_omap_startup(struct uart_port *port)
 495 {
 496         struct uart_omap_port *up = (struct uart_omap_port *)port;
 497         unsigned long flags = 0;
 498         int retval;
 499
 500         /*
 501          * Allocate the IRQ
 502          */
 503         retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
 504                                 up->name, up);
 505         if (retval)
 506                 return retval;
 507
 508         dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->pdev->id);
 509
 510         pm_runtime_get_sync(&up->pdev->dev);
 511         /*
 512          * Clear the FIFO buffers and disable them.
 513          * (they will be reenabled in set_termios())
 514          */
 515         serial_omap_clear_fifos(up);
 516         /* For Hardware flow control */
 517         serial_out(up, UART_MCR, UART_MCR_RTS);
 518
 519         /*
 520          * Clear the interrupt registers.
 521          */
 522         (void) serial_in(up, UART_LSR);
 523         if (serial_in(up, UART_LSR) & UART_LSR_DR)
 524                 (void) serial_in(up, UART_RX);
 525         (void) serial_in(up, UART_IIR);
 526         (void) serial_in(up, UART_MSR);
 527
 528         /*
 529          * Now, initialize the UART
 530          */
 531         serial_out(up, UART_LCR, UART_LCR_WLEN8);
 532         spin_lock_irqsave(&up->port.lock, flags);
 533         /*
 534          * Most PC uarts need OUT2 raised to enable interrupts.
 535          */
 536         up->port.mctrl |= TIOCM_OUT2;
 537         serial_omap_set_mctrl(&up->port, up->port.mctrl);
 538         spin_unlock_irqrestore(&up->port.lock, flags);
 539
 540         up->msr_saved_flags = 0;
 541         if (up->use_dma) {
 542                 free_page((unsigned long)up->port.state->xmit.buf);
 543                 up->port.state->xmit.buf = dma_alloc_coherent(NULL,
 544                         UART_XMIT_SIZE,
 545                         (dma_addr_t *)&(up->uart_dma.tx_buf_dma_phys),
 546                         0);
 547                 init_timer(&(up->uart_dma.rx_timer));
 548                 up->uart_dma.rx_timer.function = serial_omap_rxdma_poll;
 549                 up->uart_dma.rx_timer.data = up->pdev->id;
 550                 /* Currently the buffer size is 4KB. Can increase it */
 551                 up->uart_dma.rx_buf = dma_alloc_coherent(NULL,
 552                         up->uart_dma.rx_buf_size,
 553                         (dma_addr_t *)&(up->uart_dma.rx_buf_dma_phys), 0);
 554         }
 555         /*
 556          * Finally, enable interrupts. Note: Modem status interrupts
 557          * are set via set_termios(), which will be occurring imminently
 558          * anyway, so we don't enable them here.
 559          */
 560         up->ier = UART_IER_RLSI | UART_IER_RDI;
 561         serial_out(up, UART_IER, up->ier);
 562
 563         /* Enable module level wake up */
 564         serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP);
 565
 566         pm_runtime_mark_last_busy(&up->pdev->dev);
 567         pm_runtime_put_autosuspend(&up->pdev->dev);
 568         up->port_activity = jiffies;
 569         return 0;
 570 }
 571
 572 static void serial_omap_shutdown(struct uart_port *port)
 573 {
 574         struct uart_omap_port *up = (struct uart_omap_port *)port;
 575         unsigned long flags = 0;
 576
 577         dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->pdev->id);
 578
 579         pm_runtime_get_sync(&up->pdev->dev);
 580         /*
 581          * Disable interrupts from this port
 582          */
 583         up->ier = 0;
 584         serial_out(up, UART_IER, 0);
 585
 586         spin_lock_irqsave(&up->port.lock, flags);
 587         up->port.mctrl &= ~TIOCM_OUT2;
 588         serial_omap_set_mctrl(&up->port, up->port.mctrl);
 589         spin_unlock_irqrestore(&up->port.lock, flags);
 590
 591         /*
 592          * Disable break condition and FIFOs
 593          */
 594         serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
 595         serial_omap_clear_fifos(up);
 596
 597         /*
 598          * Read data port to reset things, and then free the irq
 599          */
 600         if (serial_in(up, UART_LSR) & UART_LSR_DR)
 601                 (void) serial_in(up, UART_RX);
 602         if (up->use_dma) {
 603                 dma_free_coherent(up->port.dev,
 604                         UART_XMIT_SIZE, up->port.state->xmit.buf,
 605                         up->uart_dma.tx_buf_dma_phys);
 606                 up->port.state->xmit.buf = NULL;
 607                 serial_omap_stop_rx(port);
 608                 dma_free_coherent(up->port.dev,
 609                         up->uart_dma.rx_buf_size, up->uart_dma.rx_buf,
 610                         up->uart_dma.rx_buf_dma_phys);
 611                 up->uart_dma.rx_buf = NULL;
 612         }
 613
 614         pm_runtime_put(&up->pdev->dev);
 615         free_irq(up->port.irq, up);
 616 }
 617
 618 static inline void
 619 serial_omap_configure_xonxoff
 620                 (struct uart_omap_port *up, struct ktermios *termios)
 621 {
 622         up->lcr = serial_in(up, UART_LCR);
 623         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 624         up->efr = serial_in(up, UART_EFR);
 625         serial_out(up, UART_EFR, up->efr & ~UART_EFR_ECB);
 626
 627         serial_out(up, UART_XON1, termios->c_cc[VSTART]);
 628         serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
 629
 630         /* clear SW control mode bits */
 631         up->efr &= OMAP_UART_SW_CLR;
 632
 633         /*
 634          * IXON Flag:
 635          * Enable XON/XOFF flow control on output.
 636          * Transmit XON1, XOFF1
 637          */
 638         if (termios->c_iflag & IXON)
 639                 up->efr |= OMAP_UART_SW_TX;
 640
 641         /*
 642          * IXOFF Flag:
 643          * Enable XON/XOFF flow control on input.
 644          * Receiver compares XON1, XOFF1.
 645          */
 646         if (termios->c_iflag & IXOFF)
 647                 up->efr |= OMAP_UART_SW_RX;
 648
 649         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 650         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 651
 652         up->mcr = serial_in(up, UART_MCR);
 653
 654         /*
 655          * IXANY Flag:
 656          * Enable any character to restart output.
 657          * Operation resumes after receiving any
 658          * character after recognition of the XOFF character
 659          */
 660         if (termios->c_iflag & IXANY)
 661                 up->mcr |= UART_MCR_XONANY;
 662
 663         serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
 664         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 665         serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
 666         /* Enable special char function UARTi.EFR_REG[5] and
 667          * load the new software flow control mode IXON or IXOFF
 668          * and restore the UARTi.EFR_REG[4] ENHANCED_EN value.
 669          */
 670         serial_out(up, UART_EFR, up->efr | UART_EFR_SCD);
 671         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 672
 673         serial_out(up, UART_MCR, up->mcr & ~UART_MCR_TCRTLR);
 674         serial_out(up, UART_LCR, up->lcr);
 675 }
 676
 677 static void serial_omap_uart_qos_work(struct work_struct *work)
 678 {
 679         struct uart_omap_port *up = container_of(work, struct uart_omap_port,
 680                                                 qos_work);
 681
 682         pm_qos_update_request(&up->pm_qos_request, up->latency);
 683 }
 684
 685 static void
 686 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
 687                         struct ktermios *old)
 688 {
 689         struct uart_omap_port *up = (struct uart_omap_port *)port;
 690         unsigned char cval = 0;
 691         unsigned char efr = 0;
 692         unsigned long flags = 0;
 693         unsigned int baud, quot;
 694
 695         switch (termios->c_cflag & CSIZE) {
 696         case CS5:
 697                 cval = UART_LCR_WLEN5;
 698                 break;
 699         case CS6:
 700                 cval = UART_LCR_WLEN6;
 701                 break;
 702         case CS7:
 703                 cval = UART_LCR_WLEN7;
 704                 break;
 705         default:
 706         case CS8:
 707                 cval = UART_LCR_WLEN8;
 708                 break;
 709         }
 710
 711         if (termios->c_cflag & CSTOPB)
 712                 cval |= UART_LCR_STOP;
 713         if (termios->c_cflag & PARENB)
 714                 cval |= UART_LCR_PARITY;
 715         if (!(termios->c_cflag & PARODD))
 716                 cval |= UART_LCR_EPAR;
 717
 718         /*
 719          * Ask the core to calculate the divisor for us.
 720          */
 721
 722         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
 723         quot = serial_omap_get_divisor(port, baud);
 724
 725         /* calculate wakeup latency constraint */
 726         up->calc_latency = (1000000 * up->port.fifosize) /
 727                                 (1000 * baud / 8);
 728         up->latency = up->calc_latency;
 729         schedule_work(&up->qos_work);
 730
 731         up->dll = quot & 0xff;
 732         up->dlh = quot >> 8;
 733         up->mdr1 = UART_OMAP_MDR1_DISABLE;
 734
 735         up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
 736                         UART_FCR_ENABLE_FIFO;
 737         if (up->use_dma)
 738                 up->fcr |= UART_FCR_DMA_SELECT;
 739
 740         /*
 741          * Ok, we're now changing the port state. Do it with
 742          * interrupts disabled.
 743          */
 744         pm_runtime_get_sync(&up->pdev->dev);
 745         spin_lock_irqsave(&up->port.lock, flags);
 746
 747         /*
 748          * Update the per-port timeout.
 749          */
 750         uart_update_timeout(port, termios->c_cflag, baud);
 751
 752         up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
 753         if (termios->c_iflag & INPCK)
 754                 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
 755         if (termios->c_iflag & (BRKINT | PARMRK))
 756                 up->port.read_status_mask |= UART_LSR_BI;
 757
 758         /*
 759          * Characters to ignore
 760          */
 761         up->port.ignore_status_mask = 0;
 762         if (termios->c_iflag & IGNPAR)
 763                 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
 764         if (termios->c_iflag & IGNBRK) {
 765                 up->port.ignore_status_mask |= UART_LSR_BI;
 766                 /*
 767                  * If we're ignoring parity and break indicators,
 768                  * ignore overruns too (for real raw support).
 769                  */
 770                 if (termios->c_iflag & IGNPAR)
 771                         up->port.ignore_status_mask |= UART_LSR_OE;
 772         }
 773
 774         /*
 775          * ignore all characters if CREAD is not set
 776          */
 777         if ((termios->c_cflag & CREAD) == 0)
 778                 up->port.ignore_status_mask |= UART_LSR_DR;
 779
 780         /*
 781          * Modem status interrupts
 782          */
 783         up->ier &= ~UART_IER_MSI;
 784         if (UART_ENABLE_MS(&up->port, termios->c_cflag))
 785                 up->ier |= UART_IER_MSI;
 786         serial_out(up, UART_IER, up->ier);
 787         serial_out(up, UART_LCR, cval);         /* reset DLAB */
 788         up->lcr = cval;
 789         up->scr = OMAP_UART_SCR_TX_EMPTY;
 790
 791         /* FIFOs and DMA Settings */
 792
 793         /* FCR can be changed only when the
 794          * baud clock is not running
 795          * DLL_REG and DLH_REG set to 0.
 796          */
 797         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 798         serial_out(up, UART_DLL, 0);
 799         serial_out(up, UART_DLM, 0);
 800         serial_out(up, UART_LCR, 0);
 801
 802         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 803
 804         up->efr = serial_in(up, UART_EFR);
 805         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 806
 807         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 808         up->mcr = serial_in(up, UART_MCR);
 809         serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
 810         /* FIFO ENABLE, DMA MODE */
 811         serial_out(up, UART_FCR, up->fcr);
 812         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 813
 814         if (up->use_dma) {
 815                 serial_out(up, UART_TI752_TLR, 0);
 816                 up->scr |= (UART_FCR_TRIGGER_4 | UART_FCR_TRIGGER_8);
 817         }
 818
 819         serial_out(up, UART_OMAP_SCR, up->scr);
 820
 821         serial_out(up, UART_EFR, up->efr);
 822         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 823         serial_out(up, UART_MCR, up->mcr);
 824
 825         /* Protocol, Baud Rate, and Interrupt Settings */
 826
 827         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
 828                 serial_omap_mdr1_errataset(up, up->mdr1);
 829         else
 830                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
 831
 832         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 833
 834         up->efr = serial_in(up, UART_EFR);
 835         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 836
 837         serial_out(up, UART_LCR, 0);
 838         serial_out(up, UART_IER, 0);
 839         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 840
 841         serial_out(up, UART_DLL, up->dll);      /* LS of divisor */
 842         serial_out(up, UART_DLM, up->dlh);      /* MS of divisor */
 843
 844         serial_out(up, UART_LCR, 0);
 845         serial_out(up, UART_IER, up->ier);
 846         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 847
 848         serial_out(up, UART_EFR, up->efr);
 849         serial_out(up, UART_LCR, cval);
 850
 851         if (baud > 230400 && baud != 3000000)
 852                 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
 853         else
 854                 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
 855
 856         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
 857                 serial_omap_mdr1_errataset(up, up->mdr1);
 858         else
 859                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
 860
 861         /* Hardware Flow Control Configuration */
 862
 863         if (termios->c_cflag & CRTSCTS) {
 864                 efr |= (UART_EFR_CTS | UART_EFR_RTS);
 865                 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 866
 867                 up->mcr = serial_in(up, UART_MCR);
 868                 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
 869
 870                 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 871                 up->efr = serial_in(up, UART_EFR);
 872                 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 873
 874                 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
 875                 serial_out(up, UART_EFR, efr); /* Enable AUTORTS and AUTOCTS */
 876                 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 877                 serial_out(up, UART_MCR, up->mcr | UART_MCR_RTS);
 878                 serial_out(up, UART_LCR, cval);
 879         }
 880
 881         serial_omap_set_mctrl(&up->port, up->port.mctrl);
 882         /* Software Flow Control Configuration */
 883         serial_omap_configure_xonxoff(up, termios);
 884
 885         spin_unlock_irqrestore(&up->port.lock, flags);
 886         pm_runtime_put(&up->pdev->dev);
 887         dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->pdev->id);
 888 }
 889
 890 static void
 891 serial_omap_pm(struct uart_port *port, unsigned int state,
 892                unsigned int oldstate)
 893 {
 894         struct uart_omap_port *up = (struct uart_omap_port *)port;
 895         unsigned char efr;
 896
 897         dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->pdev->id);
 898
 899         pm_runtime_get_sync(&up->pdev->dev);
 900         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 901         efr = serial_in(up, UART_EFR);
 902         serial_out(up, UART_EFR, efr | UART_EFR_ECB);
 903         serial_out(up, UART_LCR, 0);
 904
 905         serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
 906         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 907         serial_out(up, UART_EFR, efr);
 908         serial_out(up, UART_LCR, 0);
 909
 910         if (!device_may_wakeup(&up->pdev->dev)) {
 911                 if (!state)
 912                         pm_runtime_forbid(&up->pdev->dev);
 913                 else
 914                         pm_runtime_allow(&up->pdev->dev);
 915         }
 916
 917         pm_runtime_put(&up->pdev->dev);
 918 }
 919
 920 static void serial_omap_release_port(struct uart_port *port)
 921 {
 922         dev_dbg(port->dev, "serial_omap_release_port+\n");
 923 }
 924
 925 static int serial_omap_request_port(struct uart_port *port)
 926 {
 927         dev_dbg(port->dev, "serial_omap_request_port+\n");
 928         return 0;
 929 }
 930
 931 static void serial_omap_config_port(struct uart_port *port, int flags)
 932 {
 933         struct uart_omap_port *up = (struct uart_omap_port *)port;
 934
 935         dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
 936                                                         up->pdev->id);
 937         up->port.type = PORT_OMAP;
 938 }
 939
 940 static int
 941 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
 942 {
 943         /* we don't want the core code to modify any port params */
 944         dev_dbg(port->dev, "serial_omap_verify_port+\n");
 945         return -EINVAL;
 946 }
 947
 948 static const char *
 949 serial_omap_type(struct uart_port *port)
 950 {
 951         struct uart_omap_port *up = (struct uart_omap_port *)port;
 952
 953         dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->pdev->id);
 954         return up->name;
 955 }
 956
 957 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
 958
 959 static inline void wait_for_xmitr(struct uart_omap_port *up)
 960 {
 961         unsigned int status, tmout = 10000;
 962
 963         /* Wait up to 10ms for the character(s) to be sent. */
 964         do {
 965                 status = serial_in(up, UART_LSR);
 966
 967                 if (status & UART_LSR_BI)
 968                         up->lsr_break_flag = UART_LSR_BI;
 969
 970                 if (--tmout == 0)
 971                         break;
 972                 udelay(1);
 973         } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
 974
 975         /* Wait up to 1s for flow control if necessary */
 976         if (up->port.flags & UPF_CONS_FLOW) {
 977                 tmout = 1000000;
 978                 for (tmout = 1000000; tmout; tmout--) {
 979                         unsigned int msr = serial_in(up, UART_MSR);
 980
 981                         up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
 982                         if (msr & UART_MSR_CTS)
 983                                 break;
 984
 985                         udelay(1);
 986                 }
 987         }
 988 }
 989
 990 #ifdef CONFIG_CONSOLE_POLL
 991
 992 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
 993 {
 994         struct uart_omap_port *up = (struct uart_omap_port *)port;
 995
 996         pm_runtime_get_sync(&up->pdev->dev);
 997         wait_for_xmitr(up);
 998         serial_out(up, UART_TX, ch);
 999         pm_runtime_put(&up->pdev->dev);
1000 }
1001
1002 static int serial_omap_poll_get_char(struct uart_port *port)
1003 {
1004         struct uart_omap_port *up = (struct uart_omap_port *)port;
1005         unsigned int status;
1006
1007         pm_runtime_get_sync(&up->pdev->dev);
1008         status = serial_in(up, UART_LSR);
1009         if (!(status & UART_LSR_DR))
1010                 return NO_POLL_CHAR;
1011
1012         status = serial_in(up, UART_RX);
1013         pm_runtime_put(&up->pdev->dev);
1014         return status;
1015 }
1016
1017 #endif /* CONFIG_CONSOLE_POLL */
1018
1019 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
1020
1021 static struct uart_omap_port *serial_omap_console_ports[4];
1022
1023 static struct uart_driver serial_omap_reg;
1024
1025 static void serial_omap_console_putchar(struct uart_port *port, int ch)
1026 {
1027         struct uart_omap_port *up = (struct uart_omap_port *)port;
1028
1029         wait_for_xmitr(up);
1030         serial_out(up, UART_TX, ch);
1031 }
1032
1033 static void
1034 serial_omap_console_write(struct console *co, const char *s,
1035                 unsigned int count)
1036 {
1037         struct uart_omap_port *up = serial_omap_console_ports[co->index];
1038         unsigned long flags;
1039         unsigned int ier;
1040         int locked = 1;
1041
1042         pm_runtime_get_sync(&up->pdev->dev);
1043
1044         local_irq_save(flags);
1045         if (up->port.sysrq)
1046                 locked = 0;
1047         else if (oops_in_progress)
1048                 locked = spin_trylock(&up->port.lock);
1049         else
1050                 spin_lock(&up->port.lock);
1051
1052         /*
1053          * First save the IER then disable the interrupts
1054          */
1055         ier = serial_in(up, UART_IER);
1056         serial_out(up, UART_IER, 0);
1057
1058         uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1059
1060         /*
1061          * Finally, wait for transmitter to become empty
1062          * and restore the IER
1063          */
1064         wait_for_xmitr(up);
1065         serial_out(up, UART_IER, ier);
1066         /*
1067          * The receive handling will happen properly because the
1068          * receive ready bit will still be set; it is not cleared
1069          * on read.  However, modem control will not, we must
1070          * call it if we have saved something in the saved flags
1071          * while processing with interrupts off.
1072          */
1073         if (up->msr_saved_flags)
1074                 check_modem_status(up);
1075
1076         pm_runtime_mark_last_busy(&up->pdev->dev);
1077         pm_runtime_put_autosuspend(&up->pdev->dev);
1078         if (locked)
1079                 spin_unlock(&up->port.lock);
1080         local_irq_restore(flags);
1081 }
1082
1083 static int __init
1084 serial_omap_console_setup(struct console *co, char *options)
1085 {
1086         struct uart_omap_port *up;
1087         int baud = 115200;
1088         int bits = 8;
1089         int parity = 'n';
1090         int flow = 'n';
1091
1092         if (serial_omap_console_ports[co->index] == NULL)
1093                 return -ENODEV;
1094         up = serial_omap_console_ports[co->index];
1095
1096         if (options)
1097                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1098
1099         return uart_set_options(&up->port, co, baud, parity, bits, flow);
1100 }
1101
1102 static struct console serial_omap_console = {
1103         .name           = OMAP_SERIAL_NAME,
1104         .write          = serial_omap_console_write,
1105         .device         = uart_console_device,
1106         .setup          = serial_omap_console_setup,
1107         .flags          = CON_PRINTBUFFER,
1108         .index          = -1,
1109         .data           = &serial_omap_reg,
1110 };
1111
1112 static void serial_omap_add_console_port(struct uart_omap_port *up)
1113 {
1114         serial_omap_console_ports[up->pdev->id] = up;
1115 }
1116
1117 #define OMAP_CONSOLE    (&serial_omap_console)
1118
1119 #else
1120
1121 #define OMAP_CONSOLE    NULL
1122
1123 static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1124 {}
1125
1126 #endif
1127
1128 static struct uart_ops serial_omap_pops = {
1129         .tx_empty       = serial_omap_tx_empty,
1130         .set_mctrl      = serial_omap_set_mctrl,
1131         .get_mctrl      = serial_omap_get_mctrl,
1132         .stop_tx        = serial_omap_stop_tx,
1133         .start_tx       = serial_omap_start_tx,
1134         .stop_rx        = serial_omap_stop_rx,
1135         .enable_ms      = serial_omap_enable_ms,
1136         .break_ctl      = serial_omap_break_ctl,
1137         .startup        = serial_omap_startup,
1138         .shutdown       = serial_omap_shutdown,
1139         .set_termios    = serial_omap_set_termios,
1140         .pm             = serial_omap_pm,
1141         .type           = serial_omap_type,
1142         .release_port   = serial_omap_release_port,
1143         .request_port   = serial_omap_request_port,
1144         .config_port    = serial_omap_config_port,
1145         .verify_port    = serial_omap_verify_port,
1146 #ifdef CONFIG_CONSOLE_POLL
1147         .poll_put_char  = serial_omap_poll_put_char,
1148         .poll_get_char  = serial_omap_poll_get_char,
1149 #endif
1150 };
1151
1152 static struct uart_driver serial_omap_reg = {
1153         .owner          = THIS_MODULE,
1154         .driver_name    = "OMAP-SERIAL",
1155         .dev_name       = OMAP_SERIAL_NAME,
1156         .nr             = OMAP_MAX_HSUART_PORTS,
1157         .cons           = OMAP_CONSOLE,
1158 };
1159
1160 #ifdef CONFIG_SUSPEND
1161 static int serial_omap_suspend(struct device *dev)
1162 {
1163         struct uart_omap_port *up = dev_get_drvdata(dev);
1164
1165         if (up) {
1166                 uart_suspend_port(&serial_omap_reg, &up->port);
1167                 flush_work_sync(&up->qos_work);
1168         }
1169
1170         return 0;
1171 }
1172
1173 static int serial_omap_resume(struct device *dev)
1174 {
1175         struct uart_omap_port *up = dev_get_drvdata(dev);
1176
1177         if (up)
1178                 uart_resume_port(&serial_omap_reg, &up->port);
1179         return 0;
1180 }
1181 #endif
1182
1183 static void serial_omap_rxdma_poll(unsigned long uart_no)
1184 {
1185         struct uart_omap_port *up = ui[uart_no];
1186         unsigned int curr_dma_pos, curr_transmitted_size;
1187         int ret = 0;
1188
1189         curr_dma_pos = omap_get_dma_dst_pos(up->uart_dma.rx_dma_channel);
1190         if ((curr_dma_pos == up->uart_dma.prev_rx_dma_pos) ||
1191                              (curr_dma_pos == 0)) {
1192                 if (jiffies_to_msecs(jiffies - up->port_activity) <
1193                                                 up->uart_dma.rx_timeout) {
1194                         mod_timer(&up->uart_dma.rx_timer, jiffies +
1195                                 usecs_to_jiffies(up->uart_dma.rx_poll_rate));
1196                 } else {
1197                         serial_omap_stop_rxdma(up);
1198                         up->ier |= (UART_IER_RDI | UART_IER_RLSI);
1199                         serial_out(up, UART_IER, up->ier);
1200                 }
1201                 return;
1202         }
1203
1204         curr_transmitted_size = curr_dma_pos -
1205                                         up->uart_dma.prev_rx_dma_pos;
1206         up->port.icount.rx += curr_transmitted_size;
1207         tty_insert_flip_string(up->port.state->port.tty,
1208                         up->uart_dma.rx_buf +
1209                         (up->uart_dma.prev_rx_dma_pos -
1210                         up->uart_dma.rx_buf_dma_phys),
1211                         curr_transmitted_size);
1212         tty_flip_buffer_push(up->port.state->port.tty);
1213         up->uart_dma.prev_rx_dma_pos = curr_dma_pos;
1214         if (up->uart_dma.rx_buf_size +
1215                         up->uart_dma.rx_buf_dma_phys == curr_dma_pos) {
1216                 ret = serial_omap_start_rxdma(up);
1217                 if (ret < 0) {
1218                         serial_omap_stop_rxdma(up);
1219                         up->ier |= (UART_IER_RDI | UART_IER_RLSI);
1220                         serial_out(up, UART_IER, up->ier);
1221                 }
1222         } else  {
1223                 mod_timer(&up->uart_dma.rx_timer, jiffies +
1224                         usecs_to_jiffies(up->uart_dma.rx_poll_rate));
1225         }
1226         up->port_activity = jiffies;
1227 }
1228
1229 static void uart_rx_dma_callback(int lch, u16 ch_status, void *data)
1230 {
1231         return;
1232 }
1233
1234 static int serial_omap_start_rxdma(struct uart_omap_port *up)
1235 {
1236         int ret = 0;
1237
1238         if (up->uart_dma.rx_dma_channel == -1) {
1239                 pm_runtime_get_sync(&up->pdev->dev);
1240                 ret = omap_request_dma(up->uart_dma.uart_dma_rx,
1241                                 "UART Rx DMA",
1242                                 (void *)uart_rx_dma_callback, up,
1243                                 &(up->uart_dma.rx_dma_channel));
1244                 if (ret < 0)
1245                         return ret;
1246
1247                 omap_set_dma_src_params(up->uart_dma.rx_dma_channel, 0,
1248                                 OMAP_DMA_AMODE_CONSTANT,
1249                                 up->uart_dma.uart_base, 0, 0);
1250                 omap_set_dma_dest_params(up->uart_dma.rx_dma_channel, 0,
1251                                 OMAP_DMA_AMODE_POST_INC,
1252                                 up->uart_dma.rx_buf_dma_phys, 0, 0);
1253                 omap_set_dma_transfer_params(up->uart_dma.rx_dma_channel,
1254                                 OMAP_DMA_DATA_TYPE_S8,
1255                                 up->uart_dma.rx_buf_size, 1,
1256                                 OMAP_DMA_SYNC_ELEMENT,
1257                                 up->uart_dma.uart_dma_rx, 0);
1258         }
1259         up->uart_dma.prev_rx_dma_pos = up->uart_dma.rx_buf_dma_phys;
1260         /* FIXME: Cache maintenance needed here? */
1261         omap_start_dma(up->uart_dma.rx_dma_channel);
1262         mod_timer(&up->uart_dma.rx_timer, jiffies +
1263                                 usecs_to_jiffies(up->uart_dma.rx_poll_rate));
1264         up->uart_dma.rx_dma_used = true;
1265         return ret;
1266 }
1267
1268 static void serial_omap_continue_tx(struct uart_omap_port *up)
1269 {
1270         struct circ_buf *xmit = &up->port.state->xmit;
1271         unsigned int start = up->uart_dma.tx_buf_dma_phys
1272                         + (xmit->tail & (UART_XMIT_SIZE - 1));
1273
1274         if (uart_circ_empty(xmit))
1275                 return;
1276
1277         up->uart_dma.tx_buf_size = uart_circ_chars_pending(xmit);
1278         /*
1279          * It is a circular buffer. See if the buffer has wounded back.
1280          * If yes it will have to be transferred in two separate dma
1281          * transfers
1282          */
1283         if (start + up->uart_dma.tx_buf_size >=
1284                         up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE)
1285                 up->uart_dma.tx_buf_size =
1286                         (up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE) - start;
1287         omap_set_dma_dest_params(up->uart_dma.tx_dma_channel, 0,
1288                                 OMAP_DMA_AMODE_CONSTANT,
1289                                 up->uart_dma.uart_base, 0, 0);
1290         omap_set_dma_src_params(up->uart_dma.tx_dma_channel, 0,
1291                                 OMAP_DMA_AMODE_POST_INC, start, 0, 0);
1292         omap_set_dma_transfer_params(up->uart_dma.tx_dma_channel,
1293                                 OMAP_DMA_DATA_TYPE_S8,
1294                                 up->uart_dma.tx_buf_size, 1,
1295                                 OMAP_DMA_SYNC_ELEMENT,
1296                                 up->uart_dma.uart_dma_tx, 0);
1297         /* FIXME: Cache maintenance needed here? */
1298         omap_start_dma(up->uart_dma.tx_dma_channel);
1299 }
1300
1301 static void uart_tx_dma_callback(int lch, u16 ch_status, void *data)
1302 {
1303         struct uart_omap_port *up = (struct uart_omap_port *)data;
1304         struct circ_buf *xmit = &up->port.state->xmit;
1305
1306         xmit->tail = (xmit->tail + up->uart_dma.tx_buf_size) & \
1307                         (UART_XMIT_SIZE - 1);
1308         up->port.icount.tx += up->uart_dma.tx_buf_size;
1309
1310         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1311                 uart_write_wakeup(&up->port);
1312
1313         if (uart_circ_empty(xmit)) {
1314                 spin_lock(&(up->uart_dma.tx_lock));
1315                 serial_omap_stop_tx(&up->port);
1316                 up->uart_dma.tx_dma_used = false;
1317                 spin_unlock(&(up->uart_dma.tx_lock));
1318         } else {
1319                 omap_stop_dma(up->uart_dma.tx_dma_channel);
1320                 serial_omap_continue_tx(up);
1321         }
1322         up->port_activity = jiffies;
1323         return;
1324 }
1325
1326 static int serial_omap_probe(struct platform_device *pdev)
1327 {
1328         struct uart_omap_port   *up;
1329         struct resource         *mem, *irq, *dma_tx, *dma_rx;
1330         struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data;
1331         int ret = -ENOSPC;
1332
1333         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1334         if (!mem) {
1335                 dev_err(&pdev->dev, "no mem resource?\n");
1336                 return -ENODEV;
1337         }
1338
1339         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1340         if (!irq) {
1341                 dev_err(&pdev->dev, "no irq resource?\n");
1342                 return -ENODEV;
1343         }
1344
1345         if (!request_mem_region(mem->start, resource_size(mem),
1346                                 pdev->dev.driver->name)) {
1347                 dev_err(&pdev->dev, "memory region already claimed\n");
1348                 return -EBUSY;
1349         }
1350
1351         dma_rx = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1352         if (!dma_rx) {
1353                 ret = -EINVAL;
1354                 goto err;
1355         }
1356
1357         dma_tx = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1358         if (!dma_tx) {
1359                 ret = -EINVAL;
1360                 goto err;
1361         }
1362
1363         up = kzalloc(sizeof(*up), GFP_KERNEL);
1364         if (up == NULL) {
1365                 ret = -ENOMEM;
1366                 goto do_release_region;
1367         }
1368         sprintf(up->name, "OMAP UART%d", pdev->id);
1369         up->pdev = pdev;
1370         up->port.dev = &pdev->dev;
1371         up->port.type = PORT_OMAP;
1372         up->port.iotype = UPIO_MEM;
1373         up->port.irq = irq->start;
1374
1375         up->port.regshift = 2;
1376         up->port.fifosize = 64;
1377         up->port.ops = &serial_omap_pops;
1378         up->port.line = pdev->id;
1379
1380         up->port.mapbase = mem->start;
1381         up->port.membase = ioremap(mem->start, resource_size(mem));
1382         if (!up->port.membase) {
1383                 dev_err(&pdev->dev, "can't ioremap UART\n");
1384                 ret = -ENOMEM;
1385                 goto err;
1386         }
1387
1388         up->port.flags = omap_up_info->flags;
1389         up->port.uartclk = omap_up_info->uartclk;
1390         up->uart_dma.uart_base = mem->start;
1391         up->errata = omap_up_info->errata;
1392
1393         if (omap_up_info->dma_enabled) {
1394                 up->uart_dma.uart_dma_tx = dma_tx->start;
1395                 up->uart_dma.uart_dma_rx = dma_rx->start;
1396                 up->use_dma = 1;
1397                 up->uart_dma.rx_buf_size = omap_up_info->dma_rx_buf_size;
1398                 up->uart_dma.rx_timeout = omap_up_info->dma_rx_timeout;
1399                 up->uart_dma.rx_poll_rate = omap_up_info->dma_rx_poll_rate;
1400                 spin_lock_init(&(up->uart_dma.tx_lock));
1401                 spin_lock_init(&(up->uart_dma.rx_lock));
1402                 up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE;
1403                 up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE;
1404         }
1405
1406         up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1407         up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1408         pm_qos_add_request(&up->pm_qos_request,
1409                 PM_QOS_CPU_DMA_LATENCY, up->latency);
1410         serial_omap_uart_wq = create_singlethread_workqueue(up->name);
1411         INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1412
1413         pm_runtime_use_autosuspend(&pdev->dev);
1414         pm_runtime_set_autosuspend_delay(&pdev->dev,
1415                         omap_up_info->autosuspend_timeout);
1416
1417         pm_runtime_irq_safe(&pdev->dev);
1418         pm_runtime_enable(&pdev->dev);
1419         pm_runtime_get_sync(&pdev->dev);
1420
1421         ui[pdev->id] = up;
1422         serial_omap_add_console_port(up);
1423
1424         ret = uart_add_one_port(&serial_omap_reg, &up->port);
1425         if (ret != 0)
1426                 goto do_release_region;
1427
1428         pm_runtime_put(&pdev->dev);
1429         platform_set_drvdata(pdev, up);
1430         return 0;
1431 err:
1432         dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n",
1433                                 pdev->id, __func__, ret);
1434 do_release_region:
1435         release_mem_region(mem->start, resource_size(mem));
1436         return ret;
1437 }
1438
1439 static int serial_omap_remove(struct platform_device *dev)
1440 {
1441         struct uart_omap_port *up = platform_get_drvdata(dev);
1442
1443         if (up) {
1444                 pm_runtime_disable(&up->pdev->dev);
1445                 uart_remove_one_port(&serial_omap_reg, &up->port);
1446                 pm_qos_remove_request(&up->pm_qos_request);
1447
1448                 kfree(up);
1449         }
1450
1451         platform_set_drvdata(dev, NULL);
1452         return 0;
1453 }
1454
1455 /*
1456  * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1457  * The access to uart register after MDR1 Access
1458  * causes UART to corrupt data.
1459  *
1460  * Need a delay =
1461  * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1462  * give 10 times as much
1463  */
1464 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1465 {
1466         u8 timeout = 255;
1467
1468         serial_out(up, UART_OMAP_MDR1, mdr1);
1469         udelay(2);
1470         serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1471                         UART_FCR_CLEAR_RCVR);
1472         /*
1473          * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1474          * TX_FIFO_E bit is 1.
1475          */
1476         while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1477                                 (UART_LSR_THRE | UART_LSR_DR))) {
1478                 timeout--;
1479                 if (!timeout) {
1480                         /* Should *never* happen. we warn and carry on */
1481                         dev_crit(&up->pdev->dev, "Errata i202: timedout %x\n",
1482                                                 serial_in(up, UART_LSR));
1483                         break;
1484                 }
1485                 udelay(1);
1486         }
1487 }
1488
1489 static void serial_omap_restore_context(struct uart_omap_port *up)
1490 {
1491         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1492                 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1493         else
1494                 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1495
1496         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1497         serial_out(up, UART_EFR, UART_EFR_ECB);
1498         serial_out(up, UART_LCR, 0x0); /* Operational mode */
1499         serial_out(up, UART_IER, 0x0);
1500         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1501         serial_out(up, UART_DLL, up->dll);
1502         serial_out(up, UART_DLM, up->dlh);
1503         serial_out(up, UART_LCR, 0x0); /* Operational mode */
1504         serial_out(up, UART_IER, up->ier);
1505         serial_out(up, UART_FCR, up->fcr);
1506         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1507         serial_out(up, UART_MCR, up->mcr);
1508         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1509         serial_out(up, UART_OMAP_SCR, up->scr);
1510         serial_out(up, UART_EFR, up->efr);
1511         serial_out(up, UART_LCR, up->lcr);
1512         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1513                 serial_omap_mdr1_errataset(up, up->mdr1);
1514         else
1515                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1516 }
1517
1518 #ifdef CONFIG_PM_RUNTIME
1519 static int serial_omap_runtime_suspend(struct device *dev)
1520 {
1521         struct uart_omap_port *up = dev_get_drvdata(dev);
1522         struct omap_uart_port_info *pdata = dev->platform_data;
1523
1524         if (!up)
1525                 return -EINVAL;
1526
1527         if (!pdata->enable_wakeup)
1528                 return 0;
1529
1530         if (pdata->get_context_loss_count)
1531                 up->context_loss_cnt = pdata->get_context_loss_count(dev);
1532
1533         if (device_may_wakeup(dev)) {
1534                 if (!up->wakeups_enabled) {
1535                         pdata->enable_wakeup(up->pdev, true);
1536                         up->wakeups_enabled = true;
1537                 }
1538         } else {
1539                 if (up->wakeups_enabled) {
1540                         pdata->enable_wakeup(up->pdev, false);
1541                         up->wakeups_enabled = false;
1542                 }
1543         }
1544
1545         /* Errata i291 */
1546         if (up->use_dma && pdata->set_forceidle &&
1547                         (up->errata & UART_ERRATA_i291_DMA_FORCEIDLE))
1548                 pdata->set_forceidle(up->pdev);
1549
1550         up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1551         schedule_work(&up->qos_work);
1552
1553         return 0;
1554 }
1555
1556 static int serial_omap_runtime_resume(struct device *dev)
1557 {
1558         struct uart_omap_port *up = dev_get_drvdata(dev);
1559         struct omap_uart_port_info *pdata = dev->platform_data;
1560
1561         if (up) {
1562                 if (pdata->get_context_loss_count) {
1563                         u32 loss_cnt = pdata->get_context_loss_count(dev);
1564
1565                         if (up->context_loss_cnt != loss_cnt)
1566                                 serial_omap_restore_context(up);
1567                 }
1568
1569                 /* Errata i291 */
1570                 if (up->use_dma && pdata->set_noidle &&
1571                                 (up->errata & UART_ERRATA_i291_DMA_FORCEIDLE))
1572                         pdata->set_noidle(up->pdev);
1573
1574                 up->latency = up->calc_latency;
1575                 schedule_work(&up->qos_work);
1576         }
1577
1578         return 0;
1579 }
1580 #endif
1581
1582 static const struct dev_pm_ops serial_omap_dev_pm_ops = {
1583         SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
1584         SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
1585                                 serial_omap_runtime_resume, NULL)
1586 };
1587
1588 static struct platform_driver serial_omap_driver = {
1589         .probe          = serial_omap_probe,
1590         .remove         = serial_omap_remove,
1591         .driver         = {
1592                 .name   = DRIVER_NAME,
1593                 .pm     = &serial_omap_dev_pm_ops,
1594         },
1595 };
1596
1597 static int __init serial_omap_init(void)
1598 {
1599         int ret;
1600
1601         ret = uart_register_driver(&serial_omap_reg);
1602         if (ret != 0)
1603                 return ret;
1604         ret = platform_driver_register(&serial_omap_driver);
1605         if (ret != 0)
1606                 uart_unregister_driver(&serial_omap_reg);
1607         return ret;
1608 }
1609
1610 static void __exit serial_omap_exit(void)
1611 {
1612         platform_driver_unregister(&serial_omap_driver);
1613         uart_unregister_driver(&serial_omap_reg);
1614 }
1615
1616 module_init(serial_omap_init);
1617 module_exit(serial_omap_exit);
1618
1619 MODULE_DESCRIPTION("OMAP High Speed UART driver");
1620 MODULE_LICENSE("GPL");
1621 MODULE_AUTHOR("Texas Instruments Inc");