drivers/tty/serial/omap-serial.c

   1 /*
   2  * Driver for OMAP-UART controller.
   3  * Based on drivers/serial/8250.c
   4  *
   5  * Copyright (C) 2010 Texas Instruments.
   6  *
   7  * Authors:
   8  *      Govindraj R     <govindraj.raja@ti.com>
   9  *      Thara Gopinath  <thara@ti.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * Note: This driver is made separate from 8250 driver as we cannot
  17  * over load 8250 driver with omap platform specific configuration for
  18  * features like DMA, it makes easier to implement features like DMA and
  19  * hardware flow control and software flow control configuration with
  20  * this driver as required for the omap-platform.
  21  */
  22
  23 #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  24 #define SUPPORT_SYSRQ
  25 #endif
  26
  27 #include <linux/module.h>
  28 #include <linux/init.h>
  29 #include <linux/console.h>
  30 #include <linux/serial_reg.h>
  31 #include <linux/delay.h>
  32 #include <linux/slab.h>
  33 #include <linux/tty.h>
  34 #include <linux/tty_flip.h>
  35 #include <linux/platform_device.h>
  36 #include <linux/io.h>
  37 #include <linux/clk.h>
  38 #include <linux/serial_core.h>
  39 #include <linux/irq.h>
  40 #include <linux/pm_runtime.h>
  41 #include <linux/of.h>
  42 #include <linux/of_irq.h>
  43 #include <linux/gpio.h>
  44 #include <linux/of_gpio.h>
  45 #include <linux/platform_data/serial-omap.h>
  46
  47 #include <dt-bindings/gpio/gpio.h>
  48
  49 #define OMAP_MAX_HSUART_PORTS   6
  50
  51 #define UART_BUILD_REVISION(x, y)       (((x) << 8) | (y))
  52
  53 #define OMAP_UART_REV_42 0x0402
  54 #define OMAP_UART_REV_46 0x0406
  55 #define OMAP_UART_REV_52 0x0502
  56 #define OMAP_UART_REV_63 0x0603
  57
  58 #define OMAP_UART_TX_WAKEUP_EN          BIT(7)
  59
  60 /* Feature flags */
  61 #define OMAP_UART_WER_HAS_TX_WAKEUP     BIT(0)
  62
  63 #define UART_ERRATA_i202_MDR1_ACCESS    BIT(0)
  64 #define UART_ERRATA_i291_DMA_FORCEIDLE  BIT(1)
  65
  66 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
  67
  68 /* SCR register bitmasks */
  69 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK               (1 << 7)
  70 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK               (1 << 6)
  71 #define OMAP_UART_SCR_TX_EMPTY                  (1 << 3)
  72
  73 /* FCR register bitmasks */
  74 #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK                 (0x3 << 6)
  75 #define OMAP_UART_FCR_TX_FIFO_TRIG_MASK                 (0x3 << 4)
  76
  77 /* MVR register bitmasks */
  78 #define OMAP_UART_MVR_SCHEME_SHIFT      30
  79
  80 #define OMAP_UART_LEGACY_MVR_MAJ_MASK   0xf0
  81 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT  4
  82 #define OMAP_UART_LEGACY_MVR_MIN_MASK   0x0f
  83
  84 #define OMAP_UART_MVR_MAJ_MASK          0x700
  85 #define OMAP_UART_MVR_MAJ_SHIFT         8
  86 #define OMAP_UART_MVR_MIN_MASK          0x3f
  87
  88 #define OMAP_UART_DMA_CH_FREE   -1
  89
  90 #define MSR_SAVE_FLAGS          UART_MSR_ANY_DELTA
  91 #define OMAP_MODE13X_SPEED      230400
  92
  93 /* WER = 0x7F
  94  * Enable module level wakeup in WER reg
  95  */
  96 #define OMAP_UART_WER_MOD_WKUP  0X7F
  97
  98 /* Enable XON/XOFF flow control on output */
  99 #define OMAP_UART_SW_TX         0x08
 100
 101 /* Enable XON/XOFF flow control on input */
 102 #define OMAP_UART_SW_RX         0x02
 103
 104 #define OMAP_UART_SW_CLR        0xF0
 105
 106 #define OMAP_UART_TCR_TRIG      0x0F
 107
 108 struct uart_omap_dma {
 109         u8                      uart_dma_tx;
 110         u8                      uart_dma_rx;
 111         int                     rx_dma_channel;
 112         int                     tx_dma_channel;
 113         dma_addr_t              rx_buf_dma_phys;
 114         dma_addr_t              tx_buf_dma_phys;
 115         unsigned int            uart_base;
 116         /*
 117          * Buffer for rx dma.It is not required for tx because the buffer
 118          * comes from port structure.
 119          */
 120         unsigned char           *rx_buf;
 121         unsigned int            prev_rx_dma_pos;
 122         int                     tx_buf_size;
 123         int                     tx_dma_used;
 124         int                     rx_dma_used;
 125         spinlock_t              tx_lock;
 126         spinlock_t              rx_lock;
 127         /* timer to poll activity on rx dma */
 128         struct timer_list       rx_timer;
 129         unsigned int            rx_buf_size;
 130         unsigned int            rx_poll_rate;
 131         unsigned int            rx_timeout;
 132 };
 133
 134 struct uart_omap_port {
 135         struct uart_port        port;
 136         struct uart_omap_dma    uart_dma;
 137         struct device           *dev;
 138         int                     wakeirq;
 139
 140         unsigned char           ier;
 141         unsigned char           lcr;
 142         unsigned char           mcr;
 143         unsigned char           fcr;
 144         unsigned char           efr;
 145         unsigned char           dll;
 146         unsigned char           dlh;
 147         unsigned char           mdr1;
 148         unsigned char           scr;
 149         unsigned char           wer;
 150
 151         int                     use_dma;
 152         /*
 153          * Some bits in registers are cleared on a read, so they must
 154          * be saved whenever the register is read but the bits will not
 155          * be immediately processed.
 156          */
 157         unsigned int            lsr_break_flag;
 158         unsigned char           msr_saved_flags;
 159         char                    name[20];
 160         unsigned long           port_activity;
 161         int                     context_loss_cnt;
 162         u32                     errata;
 163         u8                      wakeups_enabled;
 164         u32                     features;
 165
 166         int                     DTR_gpio;
 167         int                     DTR_inverted;
 168         int                     DTR_active;
 169
 170         struct serial_rs485     rs485;
 171         int                     rts_gpio;
 172
 173         struct pm_qos_request   pm_qos_request;
 174         u32                     latency;
 175         u32                     calc_latency;
 176         struct work_struct      qos_work;
 177         bool                    is_suspending;
 178 };
 179
 180 #define to_uart_omap_port(p)    ((container_of((p), struct uart_omap_port, port)))
 181
 182 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
 183
 184 /* Forward declaration of functions */
 185 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
 186
 187 static struct workqueue_struct *serial_omap_uart_wq;
 188
 189 static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
 190 {
 191         offset <<= up->port.regshift;
 192         return readw(up->port.membase + offset);
 193 }
 194
 195 static inline void serial_out(struct uart_omap_port *up, int offset, int value)
 196 {
 197         offset <<= up->port.regshift;
 198         writew(value, up->port.membase + offset);
 199 }
 200
 201 static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
 202 {
 203         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
 204         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
 205                        UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
 206         serial_out(up, UART_FCR, 0);
 207 }
 208
 209 static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
 210 {
 211         struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
 212
 213         if (!pdata || !pdata->get_context_loss_count)
 214                 return -EINVAL;
 215
 216         return pdata->get_context_loss_count(up->dev);
 217 }
 218
 219 static inline void serial_omap_enable_wakeirq(struct uart_omap_port *up,
 220                                        bool enable)
 221 {
 222         if (!up->wakeirq)
 223                 return;
 224
 225         if (enable)
 226                 enable_irq(up->wakeirq);
 227         else
 228                 disable_irq(up->wakeirq);
 229 }
 230
 231 static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
 232 {
 233         struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
 234
 235         serial_omap_enable_wakeirq(up, enable);
 236         if (!pdata || !pdata->enable_wakeup)
 237                 return;
 238
 239         pdata->enable_wakeup(up->dev, enable);
 240 }
 241
 242 /*
 243  * serial_omap_baud_is_mode16 - check if baud rate is MODE16X
 244  * @port: uart port info
 245  * @baud: baudrate for which mode needs to be determined
 246  *
 247  * Returns true if baud rate is MODE16X and false if MODE13X
 248  * Original table in OMAP TRM named "UART Mode Baud Rates, Divisor Values,
 249  * and Error Rates" determines modes not for all common baud rates.
 250  * E.g. for 1000000 baud rate mode must be 16x, but according to that
 251  * table it's determined as 13x.
 252  */
 253 static bool
 254 serial_omap_baud_is_mode16(struct uart_port *port, unsigned int baud)
 255 {
 256         unsigned int n13 = port->uartclk / (13 * baud);
 257         unsigned int n16 = port->uartclk / (16 * baud);
 258         int baudAbsDiff13 = baud - (port->uartclk / (13 * n13));
 259         int baudAbsDiff16 = baud - (port->uartclk / (16 * n16));
 260         if(baudAbsDiff13 < 0)
 261                 baudAbsDiff13 = -baudAbsDiff13;
 262         if(baudAbsDiff16 < 0)
 263                 baudAbsDiff16 = -baudAbsDiff16;
 264
 265         return (baudAbsDiff13 >= baudAbsDiff16);
 266 }
 267
 268 /*
 269  * serial_omap_get_divisor - calculate divisor value
 270  * @port: uart port info
 271  * @baud: baudrate for which divisor needs to be calculated.
 272  */
 273 static unsigned int
 274 serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
 275 {
 276         unsigned int mode;
 277
 278         if (!serial_omap_baud_is_mode16(port, baud))
 279                 mode = 13;
 280         else
 281                 mode = 16;
 282         return port->uartclk/(mode * baud);
 283 }
 284
 285 static void serial_omap_enable_ms(struct uart_port *port)
 286 {
 287         struct uart_omap_port *up = to_uart_omap_port(port);
 288
 289         dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
 290
 291         pm_runtime_get_sync(up->dev);
 292         up->ier |= UART_IER_MSI;
 293         serial_out(up, UART_IER, up->ier);
 294         pm_runtime_mark_last_busy(up->dev);
 295         pm_runtime_put_autosuspend(up->dev);
 296 }
 297
 298 static void serial_omap_stop_tx(struct uart_port *port)
 299 {
 300         struct uart_omap_port *up = to_uart_omap_port(port);
 301         struct circ_buf *xmit = &up->port.state->xmit;
 302         int res;
 303
 304         pm_runtime_get_sync(up->dev);
 305
 306         /* handle rs485 */
 307         if (up->rs485.flags & SER_RS485_ENABLED) {
 308                 /* do nothing if current tx not yet completed */
 309                 res = serial_in(up, UART_LSR) & UART_LSR_TEMT;
 310                 if (!res)
 311                         return;
 312
 313                 /* if there's no more data to send, turn off rts */
 314                 if (uart_circ_empty(xmit)) {
 315                         /* if rts not already disabled */
 316                         res = (up->rs485.flags & SER_RS485_RTS_AFTER_SEND) ? 1 : 0;
 317                         if (gpio_get_value(up->rts_gpio) != res) {
 318                                 if (up->rs485.delay_rts_after_send > 0) {
 319                                         mdelay(up->rs485.delay_rts_after_send);
 320                                 }
 321                                 gpio_set_value(up->rts_gpio, res);
 322                         }
 323                 }
 324         }
 325
 326         if (up->ier & UART_IER_THRI) {
 327                 up->ier &= ~UART_IER_THRI;
 328                 serial_out(up, UART_IER, up->ier);
 329         }
 330
 331         if ((up->rs485.flags & SER_RS485_ENABLED) &&
 332             !(up->rs485.flags & SER_RS485_RX_DURING_TX)) {
 333                 up->ier = UART_IER_RLSI | UART_IER_RDI;
 334                 serial_out(up, UART_IER, up->ier);
 335         }
 336
 337         pm_runtime_mark_last_busy(up->dev);
 338         pm_runtime_put_autosuspend(up->dev);
 339 }
 340
 341 static void serial_omap_stop_rx(struct uart_port *port)
 342 {
 343         struct uart_omap_port *up = to_uart_omap_port(port);
 344
 345         pm_runtime_get_sync(up->dev);
 346         up->ier &= ~UART_IER_RLSI;
 347         up->port.read_status_mask &= ~UART_LSR_DR;
 348         serial_out(up, UART_IER, up->ier);
 349         pm_runtime_mark_last_busy(up->dev);
 350         pm_runtime_put_autosuspend(up->dev);
 351 }
 352
 353 static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
 354 {
 355         struct circ_buf *xmit = &up->port.state->xmit;
 356         int count;
 357
 358         if (up->port.x_char) {
 359                 serial_out(up, UART_TX, up->port.x_char);
 360                 up->port.icount.tx++;
 361                 up->port.x_char = 0;
 362                 return;
 363         }
 364         if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
 365                 serial_omap_stop_tx(&up->port);
 366                 return;
 367         }
 368         count = up->port.fifosize / 4;
 369         do {
 370                 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
 371                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 372                 up->port.icount.tx++;
 373                 if (uart_circ_empty(xmit))
 374                         break;
 375         } while (--count > 0);
 376
 377         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
 378                 spin_unlock(&up->port.lock);
 379                 uart_write_wakeup(&up->port);
 380                 spin_lock(&up->port.lock);
 381         }
 382
 383         if (uart_circ_empty(xmit))
 384                 serial_omap_stop_tx(&up->port);
 385 }
 386
 387 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
 388 {
 389         if (!(up->ier & UART_IER_THRI)) {
 390                 up->ier |= UART_IER_THRI;
 391                 serial_out(up, UART_IER, up->ier);
 392         }
 393 }
 394
 395 static void serial_omap_start_tx(struct uart_port *port)
 396 {
 397         struct uart_omap_port *up = to_uart_omap_port(port);
 398         int res;
 399
 400         pm_runtime_get_sync(up->dev);
 401
 402         /* handle rs485 */
 403         if (up->rs485.flags & SER_RS485_ENABLED) {
 404                 /* if rts not already enabled */
 405                 res = (up->rs485.flags & SER_RS485_RTS_ON_SEND) ? 1 : 0;
 406                 if (gpio_get_value(up->rts_gpio) != res) {
 407                         gpio_set_value(up->rts_gpio, res);
 408                         if (up->rs485.delay_rts_before_send > 0) {
 409                                 mdelay(up->rs485.delay_rts_before_send);
 410                         }
 411                 }
 412         }
 413
 414         if ((up->rs485.flags & SER_RS485_ENABLED) &&
 415             !(up->rs485.flags & SER_RS485_RX_DURING_TX))
 416                 serial_omap_stop_rx(port);
 417
 418         serial_omap_enable_ier_thri(up);
 419         pm_runtime_mark_last_busy(up->dev);
 420         pm_runtime_put_autosuspend(up->dev);
 421 }
 422
 423 static void serial_omap_throttle(struct uart_port *port)
 424 {
 425         struct uart_omap_port *up = to_uart_omap_port(port);
 426         unsigned long flags;
 427
 428         pm_runtime_get_sync(up->dev);
 429         spin_lock_irqsave(&up->port.lock, flags);
 430         up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
 431         serial_out(up, UART_IER, up->ier);
 432         spin_unlock_irqrestore(&up->port.lock, flags);
 433         pm_runtime_mark_last_busy(up->dev);
 434         pm_runtime_put_autosuspend(up->dev);
 435 }
 436
 437 static void serial_omap_unthrottle(struct uart_port *port)
 438 {
 439         struct uart_omap_port *up = to_uart_omap_port(port);
 440         unsigned long flags;
 441
 442         pm_runtime_get_sync(up->dev);
 443         spin_lock_irqsave(&up->port.lock, flags);
 444         up->ier |= UART_IER_RLSI | UART_IER_RDI;
 445         serial_out(up, UART_IER, up->ier);
 446         spin_unlock_irqrestore(&up->port.lock, flags);
 447         pm_runtime_mark_last_busy(up->dev);
 448         pm_runtime_put_autosuspend(up->dev);
 449 }
 450
 451 static unsigned int check_modem_status(struct uart_omap_port *up)
 452 {
 453         unsigned int status;
 454
 455         status = serial_in(up, UART_MSR);
 456         status |= up->msr_saved_flags;
 457         up->msr_saved_flags = 0;
 458         if ((status & UART_MSR_ANY_DELTA) == 0)
 459                 return status;
 460
 461         if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
 462             up->port.state != NULL) {
 463                 if (status & UART_MSR_TERI)
 464                         up->port.icount.rng++;
 465                 if (status & UART_MSR_DDSR)
 466                         up->port.icount.dsr++;
 467                 if (status & UART_MSR_DDCD)
 468                         uart_handle_dcd_change
 469                                 (&up->port, status & UART_MSR_DCD);
 470                 if (status & UART_MSR_DCTS)
 471                         uart_handle_cts_change
 472                                 (&up->port, status & UART_MSR_CTS);
 473                 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
 474         }
 475
 476         return status;
 477 }
 478
 479 static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)
 480 {
 481         unsigned int flag;
 482         unsigned char ch = 0;
 483
 484         if (likely(lsr & UART_LSR_DR))
 485                 ch = serial_in(up, UART_RX);
 486
 487         up->port.icount.rx++;
 488         flag = TTY_NORMAL;
 489
 490         if (lsr & UART_LSR_BI) {
 491                 flag = TTY_BREAK;
 492                 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
 493                 up->port.icount.brk++;
 494                 /*
 495                  * We do the SysRQ and SAK checking
 496                  * here because otherwise the break
 497                  * may get masked by ignore_status_mask
 498                  * or read_status_mask.
 499                  */
 500                 if (uart_handle_break(&up->port))
 501                         return;
 502
 503         }
 504
 505         if (lsr & UART_LSR_PE) {
 506                 flag = TTY_PARITY;
 507                 up->port.icount.parity++;
 508         }
 509
 510         if (lsr & UART_LSR_FE) {
 511                 flag = TTY_FRAME;
 512                 up->port.icount.frame++;
 513         }
 514
 515         if (lsr & UART_LSR_OE)
 516                 up->port.icount.overrun++;
 517
 518 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
 519         if (up->port.line == up->port.cons->index) {
 520                 /* Recover the break flag from console xmit */
 521                 lsr |= up->lsr_break_flag;
 522         }
 523 #endif
 524         uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);
 525 }
 526
 527 static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
 528 {
 529         unsigned char ch = 0;
 530         unsigned int flag;
 531
 532         if (!(lsr & UART_LSR_DR))
 533                 return;
 534
 535         ch = serial_in(up, UART_RX);
 536         flag = TTY_NORMAL;
 537         up->port.icount.rx++;
 538
 539         if (uart_handle_sysrq_char(&up->port, ch))
 540                 return;
 541
 542         uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
 543 }
 544
 545 /**
 546  * serial_omap_irq() - This handles the interrupt from one port
 547  * @irq: uart port irq number
 548  * @dev_id: uart port info
 549  */
 550 static irqreturn_t serial_omap_irq(int irq, void *dev_id)
 551 {
 552         struct uart_omap_port *up = dev_id;
 553         unsigned int iir, lsr;
 554         unsigned int type;
 555         irqreturn_t ret = IRQ_NONE;
 556         int max_count = 256;
 557
 558         spin_lock(&up->port.lock);
 559         pm_runtime_get_sync(up->dev);
 560
 561         do {
 562                 iir = serial_in(up, UART_IIR);
 563                 if (iir & UART_IIR_NO_INT)
 564                         break;
 565
 566                 ret = IRQ_HANDLED;
 567                 lsr = serial_in(up, UART_LSR);
 568
 569                 /* extract IRQ type from IIR register */
 570                 type = iir & 0x3e;
 571
 572                 switch (type) {
 573                 case UART_IIR_MSI:
 574                         check_modem_status(up);
 575                         break;
 576                 case UART_IIR_THRI:
 577                         transmit_chars(up, lsr);
 578                         break;
 579                 case UART_IIR_RX_TIMEOUT:
 580                         /* FALLTHROUGH */
 581                 case UART_IIR_RDI:
 582                         serial_omap_rdi(up, lsr);
 583                         break;
 584                 case UART_IIR_RLSI:
 585                         serial_omap_rlsi(up, lsr);
 586                         break;
 587                 case UART_IIR_CTS_RTS_DSR:
 588                         /* simply try again */
 589                         break;
 590                 case UART_IIR_XOFF:
 591                         /* FALLTHROUGH */
 592                 default:
 593                         break;
 594                 }
 595         } while (!(iir & UART_IIR_NO_INT) && max_count--);
 596
 597         spin_unlock(&up->port.lock);
 598
 599         tty_flip_buffer_push(&up->port.state->port);
 600
 601         pm_runtime_mark_last_busy(up->dev);
 602         pm_runtime_put_autosuspend(up->dev);
 603         up->port_activity = jiffies;
 604
 605         return ret;
 606 }
 607
 608 static unsigned int serial_omap_tx_empty(struct uart_port *port)
 609 {
 610         struct uart_omap_port *up = to_uart_omap_port(port);
 611         unsigned long flags = 0;
 612         unsigned int ret = 0;
 613
 614         pm_runtime_get_sync(up->dev);
 615         dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
 616         spin_lock_irqsave(&up->port.lock, flags);
 617         ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
 618         spin_unlock_irqrestore(&up->port.lock, flags);
 619         pm_runtime_mark_last_busy(up->dev);
 620         pm_runtime_put_autosuspend(up->dev);
 621         return ret;
 622 }
 623
 624 static unsigned int serial_omap_get_mctrl(struct uart_port *port)
 625 {
 626         struct uart_omap_port *up = to_uart_omap_port(port);
 627         unsigned int status;
 628         unsigned int ret = 0;
 629
 630         pm_runtime_get_sync(up->dev);
 631         status = check_modem_status(up);
 632         pm_runtime_mark_last_busy(up->dev);
 633         pm_runtime_put_autosuspend(up->dev);
 634
 635         dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
 636
 637         if (status & UART_MSR_DCD)
 638                 ret |= TIOCM_CAR;
 639         if (status & UART_MSR_RI)
 640                 ret |= TIOCM_RNG;
 641         if (status & UART_MSR_DSR)
 642                 ret |= TIOCM_DSR;
 643         if (status & UART_MSR_CTS)
 644                 ret |= TIOCM_CTS;
 645         return ret;
 646 }
 647
 648 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
 649 {
 650         struct uart_omap_port *up = to_uart_omap_port(port);
 651         unsigned char mcr = 0, old_mcr;
 652
 653         dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
 654         if (mctrl & TIOCM_RTS)
 655                 mcr |= UART_MCR_RTS;
 656         if (mctrl & TIOCM_DTR)
 657                 mcr |= UART_MCR_DTR;
 658         if (mctrl & TIOCM_OUT1)
 659                 mcr |= UART_MCR_OUT1;
 660         if (mctrl & TIOCM_OUT2)
 661                 mcr |= UART_MCR_OUT2;
 662         if (mctrl & TIOCM_LOOP)
 663                 mcr |= UART_MCR_LOOP;
 664
 665         pm_runtime_get_sync(up->dev);
 666         old_mcr = serial_in(up, UART_MCR);
 667         old_mcr &= ~(UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_OUT1 |
 668                      UART_MCR_DTR | UART_MCR_RTS);
 669         up->mcr = old_mcr | mcr;
 670         serial_out(up, UART_MCR, up->mcr);
 671         pm_runtime_mark_last_busy(up->dev);
 672         pm_runtime_put_autosuspend(up->dev);
 673
 674         if (gpio_is_valid(up->DTR_gpio) &&
 675             !!(mctrl & TIOCM_DTR) != up->DTR_active) {
 676                 up->DTR_active = !up->DTR_active;
 677                 if (gpio_cansleep(up->DTR_gpio))
 678                         schedule_work(&up->qos_work);
 679                 else
 680                         gpio_set_value(up->DTR_gpio,
 681                                        up->DTR_active != up->DTR_inverted);
 682         }
 683 }
 684
 685 static void serial_omap_break_ctl(struct uart_port *port, int break_state)
 686 {
 687         struct uart_omap_port *up = to_uart_omap_port(port);
 688         unsigned long flags = 0;
 689
 690         dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
 691         pm_runtime_get_sync(up->dev);
 692         spin_lock_irqsave(&up->port.lock, flags);
 693         if (break_state == -1)
 694                 up->lcr |= UART_LCR_SBC;
 695         else
 696                 up->lcr &= ~UART_LCR_SBC;
 697         serial_out(up, UART_LCR, up->lcr);
 698         spin_unlock_irqrestore(&up->port.lock, flags);
 699         pm_runtime_mark_last_busy(up->dev);
 700         pm_runtime_put_autosuspend(up->dev);
 701 }
 702
 703 static int serial_omap_startup(struct uart_port *port)
 704 {
 705         struct uart_omap_port *up = to_uart_omap_port(port);
 706         unsigned long flags = 0;
 707         int retval;
 708
 709         /*
 710          * Allocate the IRQ
 711          */
 712         retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
 713                                 up->name, up);
 714         if (retval)
 715                 return retval;
 716
 717         /* Optional wake-up IRQ */
 718         if (up->wakeirq) {
 719                 retval = request_irq(up->wakeirq, serial_omap_irq,
 720                                      up->port.irqflags, up->name, up);
 721                 if (retval) {
 722                         free_irq(up->port.irq, up);
 723                         return retval;
 724                 }
 725                 disable_irq(up->wakeirq);
 726         } else {
 727                 dev_info(up->port.dev, "no wakeirq for uart%d\n",
 728                          up->port.line);
 729         }
 730
 731         dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
 732
 733         pm_runtime_get_sync(up->dev);
 734         /*
 735          * Clear the FIFO buffers and disable them.
 736          * (they will be reenabled in set_termios())
 737          */
 738         serial_omap_clear_fifos(up);
 739         /* For Hardware flow control */
 740         serial_out(up, UART_MCR, UART_MCR_RTS);
 741
 742         /*
 743          * Clear the interrupt registers.
 744          */
 745         (void) serial_in(up, UART_LSR);
 746         if (serial_in(up, UART_LSR) & UART_LSR_DR)
 747                 (void) serial_in(up, UART_RX);
 748         (void) serial_in(up, UART_IIR);
 749         (void) serial_in(up, UART_MSR);
 750
 751         /*
 752          * Now, initialize the UART
 753          */
 754         serial_out(up, UART_LCR, UART_LCR_WLEN8);
 755         spin_lock_irqsave(&up->port.lock, flags);
 756         /*
 757          * Most PC uarts need OUT2 raised to enable interrupts.
 758          */
 759         up->port.mctrl |= TIOCM_OUT2;
 760         serial_omap_set_mctrl(&up->port, up->port.mctrl);
 761         spin_unlock_irqrestore(&up->port.lock, flags);
 762
 763         up->msr_saved_flags = 0;
 764         /*
 765          * Finally, enable interrupts. Note: Modem status interrupts
 766          * are set via set_termios(), which will be occurring imminently
 767          * anyway, so we don't enable them here.
 768          */
 769         up->ier = UART_IER_RLSI | UART_IER_RDI;
 770         serial_out(up, UART_IER, up->ier);
 771
 772         /* Enable module level wake up */
 773         up->wer = OMAP_UART_WER_MOD_WKUP;
 774         if (up->features & OMAP_UART_WER_HAS_TX_WAKEUP)
 775                 up->wer |= OMAP_UART_TX_WAKEUP_EN;
 776
 777         serial_out(up, UART_OMAP_WER, up->wer);
 778
 779         pm_runtime_mark_last_busy(up->dev);
 780         pm_runtime_put_autosuspend(up->dev);
 781         up->port_activity = jiffies;
 782         return 0;
 783 }
 784
 785 static void serial_omap_shutdown(struct uart_port *port)
 786 {
 787         struct uart_omap_port *up = to_uart_omap_port(port);
 788         unsigned long flags = 0;
 789
 790         dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
 791
 792         pm_runtime_get_sync(up->dev);
 793         /*
 794          * Disable interrupts from this port
 795          */
 796         up->ier = 0;
 797         serial_out(up, UART_IER, 0);
 798
 799         spin_lock_irqsave(&up->port.lock, flags);
 800         up->port.mctrl &= ~TIOCM_OUT2;
 801         serial_omap_set_mctrl(&up->port, up->port.mctrl);
 802         spin_unlock_irqrestore(&up->port.lock, flags);
 803
 804         /*
 805          * Disable break condition and FIFOs
 806          */
 807         serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
 808         serial_omap_clear_fifos(up);
 809
 810         /*
 811          * Read data port to reset things, and then free the irq
 812          */
 813         if (serial_in(up, UART_LSR) & UART_LSR_DR)
 814                 (void) serial_in(up, UART_RX);
 815
 816         pm_runtime_mark_last_busy(up->dev);
 817         pm_runtime_put_autosuspend(up->dev);
 818         free_irq(up->port.irq, up);
 819         if (up->wakeirq)
 820                 free_irq(up->wakeirq, up);
 821 }
 822
 823 static void serial_omap_uart_qos_work(struct work_struct *work)
 824 {
 825         struct uart_omap_port *up = container_of(work, struct uart_omap_port,
 826                                                 qos_work);
 827
 828         pm_qos_update_request(&up->pm_qos_request, up->latency);
 829         if (gpio_is_valid(up->DTR_gpio))
 830                 gpio_set_value_cansleep(up->DTR_gpio,
 831                                         up->DTR_active != up->DTR_inverted);
 832 }
 833
 834 static void
 835 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
 836                         struct ktermios *old)
 837 {
 838         struct uart_omap_port *up = to_uart_omap_port(port);
 839         unsigned char cval = 0;
 840         unsigned long flags = 0;
 841         unsigned int baud, quot;
 842
 843         switch (termios->c_cflag & CSIZE) {
 844         case CS5:
 845                 cval = UART_LCR_WLEN5;
 846                 break;
 847         case CS6:
 848                 cval = UART_LCR_WLEN6;
 849                 break;
 850         case CS7:
 851                 cval = UART_LCR_WLEN7;
 852                 break;
 853         default:
 854         case CS8:
 855                 cval = UART_LCR_WLEN8;
 856                 break;
 857         }
 858
 859         if (termios->c_cflag & CSTOPB)
 860                 cval |= UART_LCR_STOP;
 861         if (termios->c_cflag & PARENB)
 862                 cval |= UART_LCR_PARITY;
 863         if (!(termios->c_cflag & PARODD))
 864                 cval |= UART_LCR_EPAR;
 865         if (termios->c_cflag & CMSPAR)
 866                 cval |= UART_LCR_SPAR;
 867
 868         /*
 869          * Ask the core to calculate the divisor for us.
 870          */
 871
 872         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
 873         quot = serial_omap_get_divisor(port, baud);
 874
 875         /* calculate wakeup latency constraint */
 876         up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8);
 877         up->latency = up->calc_latency;
 878         schedule_work(&up->qos_work);
 879
 880         up->dll = quot & 0xff;
 881         up->dlh = quot >> 8;
 882         up->mdr1 = UART_OMAP_MDR1_DISABLE;
 883
 884         up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
 885                         UART_FCR_ENABLE_FIFO;
 886
 887         /*
 888          * Ok, we're now changing the port state. Do it with
 889          * interrupts disabled.
 890          */
 891         pm_runtime_get_sync(up->dev);
 892         spin_lock_irqsave(&up->port.lock, flags);
 893
 894         /*
 895          * Update the per-port timeout.
 896          */
 897         uart_update_timeout(port, termios->c_cflag, baud);
 898
 899         up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
 900         if (termios->c_iflag & INPCK)
 901                 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
 902         if (termios->c_iflag & (BRKINT | PARMRK))
 903                 up->port.read_status_mask |= UART_LSR_BI;
 904
 905         /*
 906          * Characters to ignore
 907          */
 908         up->port.ignore_status_mask = 0;
 909         if (termios->c_iflag & IGNPAR)
 910                 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
 911         if (termios->c_iflag & IGNBRK) {
 912                 up->port.ignore_status_mask |= UART_LSR_BI;
 913                 /*
 914                  * If we're ignoring parity and break indicators,
 915                  * ignore overruns too (for real raw support).
 916                  */
 917                 if (termios->c_iflag & IGNPAR)
 918                         up->port.ignore_status_mask |= UART_LSR_OE;
 919         }
 920
 921         /*
 922          * ignore all characters if CREAD is not set
 923          */
 924         if ((termios->c_cflag & CREAD) == 0)
 925                 up->port.ignore_status_mask |= UART_LSR_DR;
 926
 927         /*
 928          * Modem status interrupts
 929          */
 930         up->ier &= ~UART_IER_MSI;
 931         if (UART_ENABLE_MS(&up->port, termios->c_cflag))
 932                 up->ier |= UART_IER_MSI;
 933         serial_out(up, UART_IER, up->ier);
 934         serial_out(up, UART_LCR, cval);         /* reset DLAB */
 935         up->lcr = cval;
 936         up->scr = 0;
 937
 938         /* FIFOs and DMA Settings */
 939
 940         /* FCR can be changed only when the
 941          * baud clock is not running
 942          * DLL_REG and DLH_REG set to 0.
 943          */
 944         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 945         serial_out(up, UART_DLL, 0);
 946         serial_out(up, UART_DLM, 0);
 947         serial_out(up, UART_LCR, 0);
 948
 949         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 950
 951         up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB;
 952         up->efr &= ~UART_EFR_SCD;
 953         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 954
 955         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 956         up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR;
 957         serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
 958         /* FIFO ENABLE, DMA MODE */
 959
 960         up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
 961         /*
 962          * NOTE: Setting OMAP_UART_SCR_RX_TRIG_GRANU1_MASK
 963          * sets Enables the granularity of 1 for TRIGGER RX
 964          * level. Along with setting RX FIFO trigger level
 965          * to 1 (as noted below, 16 characters) and TLR[3:0]
 966          * to zero this will result RX FIFO threshold level
 967          * to 1 character, instead of 16 as noted in comment
 968          * below.
 969          */
 970
 971         /* Set receive FIFO threshold to 16 characters and
 972          * transmit FIFO threshold to 16 spaces
 973          */
 974         up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
 975         up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK;
 976         up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 |
 977                 UART_FCR_ENABLE_FIFO;
 978
 979         serial_out(up, UART_FCR, up->fcr);
 980         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 981
 982         serial_out(up, UART_OMAP_SCR, up->scr);
 983
 984         /* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */
 985         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 986         serial_out(up, UART_MCR, up->mcr);
 987         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 988         serial_out(up, UART_EFR, up->efr);
 989         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 990
 991         /* Protocol, Baud Rate, and Interrupt Settings */
 992
 993         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
 994                 serial_omap_mdr1_errataset(up, up->mdr1);
 995         else
 996                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
 997
 998         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 999         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
1000
1001         serial_out(up, UART_LCR, 0);
1002         serial_out(up, UART_IER, 0);
1003         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1004
1005         serial_out(up, UART_DLL, up->dll);      /* LS of divisor */
1006         serial_out(up, UART_DLM, up->dlh);      /* MS of divisor */
1007
1008         serial_out(up, UART_LCR, 0);
1009         serial_out(up, UART_IER, up->ier);
1010         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1011
1012         serial_out(up, UART_EFR, up->efr);
1013         serial_out(up, UART_LCR, cval);
1014
1015         if (!serial_omap_baud_is_mode16(port, baud))
1016                 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
1017         else
1018                 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
1019
1020         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1021                 serial_omap_mdr1_errataset(up, up->mdr1);
1022         else
1023                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1024
1025         /* Configure flow control */
1026         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1027
1028         /* XON1/XOFF1 accessible mode B, TCRTLR=0, ECB=0 */
1029         serial_out(up, UART_XON1, termios->c_cc[VSTART]);
1030         serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
1031
1032         /* Enable access to TCR/TLR */
1033         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
1034         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1035         serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
1036
1037         serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
1038
1039         if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
1040                 /* Enable AUTORTS and AUTOCTS */
1041                 up->efr |= UART_EFR_CTS | UART_EFR_RTS;
1042
1043                 /* Ensure MCR RTS is asserted */
1044                 up->mcr |= UART_MCR_RTS;
1045         } else {
1046                 /* Disable AUTORTS and AUTOCTS */
1047                 up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS);
1048         }
1049
1050         if (up->port.flags & UPF_SOFT_FLOW) {
1051                 /* clear SW control mode bits */
1052                 up->efr &= OMAP_UART_SW_CLR;
1053
1054                 /*
1055                  * IXON Flag:
1056                  * Enable XON/XOFF flow control on input.
1057                  * Receiver compares XON1, XOFF1.
1058                  */
1059                 if (termios->c_iflag & IXON)
1060                         up->efr |= OMAP_UART_SW_RX;
1061
1062                 /*
1063                  * IXOFF Flag:
1064                  * Enable XON/XOFF flow control on output.
1065                  * Transmit XON1, XOFF1
1066                  */
1067                 if (termios->c_iflag & IXOFF)
1068                         up->efr |= OMAP_UART_SW_TX;
1069
1070                 /*
1071                  * IXANY Flag:
1072                  * Enable any character to restart output.
1073                  * Operation resumes after receiving any
1074                  * character after recognition of the XOFF character
1075                  */
1076                 if (termios->c_iflag & IXANY)
1077                         up->mcr |= UART_MCR_XONANY;
1078                 else
1079                         up->mcr &= ~UART_MCR_XONANY;
1080         }
1081         serial_out(up, UART_MCR, up->mcr);
1082         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1083         serial_out(up, UART_EFR, up->efr);
1084         serial_out(up, UART_LCR, up->lcr);
1085
1086         serial_omap_set_mctrl(&up->port, up->port.mctrl);
1087
1088         spin_unlock_irqrestore(&up->port.lock, flags);
1089         pm_runtime_mark_last_busy(up->dev);
1090         pm_runtime_put_autosuspend(up->dev);
1091         dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
1092 }
1093
1094 static void
1095 serial_omap_pm(struct uart_port *port, unsigned int state,
1096                unsigned int oldstate)
1097 {
1098         struct uart_omap_port *up = to_uart_omap_port(port);
1099         unsigned char efr;
1100
1101         dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
1102
1103         pm_runtime_get_sync(up->dev);
1104         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1105         efr = serial_in(up, UART_EFR);
1106         serial_out(up, UART_EFR, efr | UART_EFR_ECB);
1107         serial_out(up, UART_LCR, 0);
1108
1109         serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
1110         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1111         serial_out(up, UART_EFR, efr);
1112         serial_out(up, UART_LCR, 0);
1113
1114         if (!device_may_wakeup(up->dev)) {
1115                 if (!state)
1116                         pm_runtime_forbid(up->dev);
1117                 else
1118                         pm_runtime_allow(up->dev);
1119         }
1120
1121         pm_runtime_mark_last_busy(up->dev);
1122         pm_runtime_put_autosuspend(up->dev);
1123 }
1124
1125 static void serial_omap_release_port(struct uart_port *port)
1126 {
1127         dev_dbg(port->dev, "serial_omap_release_port+\n");
1128 }
1129
1130 static int serial_omap_request_port(struct uart_port *port)
1131 {
1132         dev_dbg(port->dev, "serial_omap_request_port+\n");
1133         return 0;
1134 }
1135
1136 static void serial_omap_config_port(struct uart_port *port, int flags)
1137 {
1138         struct uart_omap_port *up = to_uart_omap_port(port);
1139
1140         dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
1141                                                         up->port.line);
1142         up->port.type = PORT_OMAP;
1143         up->port.flags |= UPF_SOFT_FLOW | UPF_HARD_FLOW;
1144 }
1145
1146 static int
1147 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
1148 {
1149         /* we don't want the core code to modify any port params */
1150         dev_dbg(port->dev, "serial_omap_verify_port+\n");
1151         return -EINVAL;
1152 }
1153
1154 static const char *
1155 serial_omap_type(struct uart_port *port)
1156 {
1157         struct uart_omap_port *up = to_uart_omap_port(port);
1158
1159         dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
1160         return up->name;
1161 }
1162
1163 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1164
1165 static inline void wait_for_xmitr(struct uart_omap_port *up)
1166 {
1167         unsigned int status, tmout = 10000;
1168
1169         /* Wait up to 10ms for the character(s) to be sent. */
1170         do {
1171                 status = serial_in(up, UART_LSR);
1172
1173                 if (status & UART_LSR_BI)
1174                         up->lsr_break_flag = UART_LSR_BI;
1175
1176                 if (--tmout == 0)
1177                         break;
1178                 udelay(1);
1179         } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
1180
1181         /* Wait up to 1s for flow control if necessary */
1182         if (up->port.flags & UPF_CONS_FLOW) {
1183                 tmout = 1000000;
1184                 for (tmout = 1000000; tmout; tmout--) {
1185                         unsigned int msr = serial_in(up, UART_MSR);
1186
1187                         up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1188                         if (msr & UART_MSR_CTS)
1189                                 break;
1190
1191                         udelay(1);
1192                 }
1193         }
1194 }
1195
1196 #ifdef CONFIG_CONSOLE_POLL
1197
1198 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
1199 {
1200         struct uart_omap_port *up = to_uart_omap_port(port);
1201
1202         pm_runtime_get_sync(up->dev);
1203         wait_for_xmitr(up);
1204         serial_out(up, UART_TX, ch);
1205         pm_runtime_mark_last_busy(up->dev);
1206         pm_runtime_put_autosuspend(up->dev);
1207 }
1208
1209 static int serial_omap_poll_get_char(struct uart_port *port)
1210 {
1211         struct uart_omap_port *up = to_uart_omap_port(port);
1212         unsigned int status;
1213
1214         pm_runtime_get_sync(up->dev);
1215         status = serial_in(up, UART_LSR);
1216         if (!(status & UART_LSR_DR)) {
1217                 status = NO_POLL_CHAR;
1218                 goto out;
1219         }
1220
1221         status = serial_in(up, UART_RX);
1222
1223 out:
1224         pm_runtime_mark_last_busy(up->dev);
1225         pm_runtime_put_autosuspend(up->dev);
1226
1227         return status;
1228 }
1229
1230 #endif /* CONFIG_CONSOLE_POLL */
1231
1232 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
1233
1234 static struct uart_omap_port *serial_omap_console_ports[OMAP_MAX_HSUART_PORTS];
1235
1236 static struct uart_driver serial_omap_reg;
1237
1238 static void serial_omap_console_putchar(struct uart_port *port, int ch)
1239 {
1240         struct uart_omap_port *up = to_uart_omap_port(port);
1241
1242         wait_for_xmitr(up);
1243         serial_out(up, UART_TX, ch);
1244 }
1245
1246 static void
1247 serial_omap_console_write(struct console *co, const char *s,
1248                 unsigned int count)
1249 {
1250         struct uart_omap_port *up = serial_omap_console_ports[co->index];
1251         unsigned long flags;
1252         unsigned int ier;
1253         int locked = 1;
1254
1255         pm_runtime_get_sync(up->dev);
1256
1257         local_irq_save(flags);
1258         if (up->port.sysrq)
1259                 locked = 0;
1260         else if (oops_in_progress)
1261                 locked = spin_trylock(&up->port.lock);
1262         else
1263                 spin_lock(&up->port.lock);
1264
1265         /*
1266          * First save the IER then disable the interrupts
1267          */
1268         ier = serial_in(up, UART_IER);
1269         serial_out(up, UART_IER, 0);
1270
1271         uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1272
1273         /*
1274          * Finally, wait for transmitter to become empty
1275          * and restore the IER
1276          */
1277         wait_for_xmitr(up);
1278         serial_out(up, UART_IER, ier);
1279         /*
1280          * The receive handling will happen properly because the
1281          * receive ready bit will still be set; it is not cleared
1282          * on read.  However, modem control will not, we must
1283          * call it if we have saved something in the saved flags
1284          * while processing with interrupts off.
1285          */
1286         if (up->msr_saved_flags)
1287                 check_modem_status(up);
1288
1289         pm_runtime_mark_last_busy(up->dev);
1290         pm_runtime_put_autosuspend(up->dev);
1291         if (locked)
1292                 spin_unlock(&up->port.lock);
1293         local_irq_restore(flags);
1294 }
1295
1296 static int __init
1297 serial_omap_console_setup(struct console *co, char *options)
1298 {
1299         struct uart_omap_port *up;
1300         int baud = 115200;
1301         int bits = 8;
1302         int parity = 'n';
1303         int flow = 'n';
1304
1305         if (serial_omap_console_ports[co->index] == NULL)
1306                 return -ENODEV;
1307         up = serial_omap_console_ports[co->index];
1308
1309         if (options)
1310                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1311
1312         return uart_set_options(&up->port, co, baud, parity, bits, flow);
1313 }
1314
1315 static struct console serial_omap_console = {
1316         .name           = OMAP_SERIAL_NAME,
1317         .write          = serial_omap_console_write,
1318         .device         = uart_console_device,
1319         .setup          = serial_omap_console_setup,
1320         .flags          = CON_PRINTBUFFER,
1321         .index          = -1,
1322         .data           = &serial_omap_reg,
1323 };
1324
1325 static void serial_omap_add_console_port(struct uart_omap_port *up)
1326 {
1327         serial_omap_console_ports[up->port.line] = up;
1328 }
1329
1330 #define OMAP_CONSOLE    (&serial_omap_console)
1331
1332 #else
1333
1334 #define OMAP_CONSOLE    NULL
1335
1336 static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1337 {}
1338
1339 #endif
1340
1341 /* Enable or disable the rs485 support */
1342 static void
1343 serial_omap_config_rs485(struct uart_port *port, struct serial_rs485 *rs485conf)
1344 {
1345         struct uart_omap_port *up = to_uart_omap_port(port);
1346         unsigned long flags;
1347         unsigned int mode;
1348         int val;
1349
1350         pm_runtime_get_sync(up->dev);
1351         spin_lock_irqsave(&up->port.lock, flags);
1352
1353         /* Disable interrupts from this port */
1354         mode = up->ier;
1355         up->ier = 0;
1356         serial_out(up, UART_IER, 0);
1357
1358         /* store new config */
1359         up->rs485 = *rs485conf;
1360
1361         /*
1362          * Just as a precaution, only allow rs485
1363          * to be enabled if the gpio pin is valid
1364          */
1365         if (gpio_is_valid(up->rts_gpio)) {
1366                 /* enable / disable rts */
1367                 val = (up->rs485.flags & SER_RS485_ENABLED) ?
1368                         SER_RS485_RTS_AFTER_SEND : SER_RS485_RTS_ON_SEND;
1369                 val = (up->rs485.flags & val) ? 1 : 0;
1370                 gpio_set_value(up->rts_gpio, val);
1371         } else
1372                 up->rs485.flags &= ~SER_RS485_ENABLED;
1373
1374         /* Enable interrupts */
1375         up->ier = mode;
1376         serial_out(up, UART_IER, up->ier);
1377
1378         spin_unlock_irqrestore(&up->port.lock, flags);
1379         pm_runtime_mark_last_busy(up->dev);
1380         pm_runtime_put_autosuspend(up->dev);
1381 }
1382
1383 static int
1384 serial_omap_ioctl(struct uart_port *port, unsigned int cmd, unsigned long arg)
1385 {
1386         struct serial_rs485 rs485conf;
1387
1388         switch (cmd) {
1389         case TIOCSRS485:
1390                 if (copy_from_user(&rs485conf, (struct serial_rs485 *) arg,
1391                                         sizeof(rs485conf)))
1392                         return -EFAULT;
1393
1394                 serial_omap_config_rs485(port, &rs485conf);
1395                 break;
1396
1397         case TIOCGRS485:
1398                 if (copy_to_user((struct serial_rs485 *) arg,
1399                                         &(to_uart_omap_port(port)->rs485),
1400                                         sizeof(rs485conf)))
1401                         return -EFAULT;
1402                 break;
1403
1404         default:
1405                 return -ENOIOCTLCMD;
1406         }
1407         return 0;
1408 }
1409
1410
1411 static struct uart_ops serial_omap_pops = {
1412         .tx_empty       = serial_omap_tx_empty,
1413         .set_mctrl      = serial_omap_set_mctrl,
1414         .get_mctrl      = serial_omap_get_mctrl,
1415         .stop_tx        = serial_omap_stop_tx,
1416         .start_tx       = serial_omap_start_tx,
1417         .throttle       = serial_omap_throttle,
1418         .unthrottle     = serial_omap_unthrottle,
1419         .stop_rx        = serial_omap_stop_rx,
1420         .enable_ms      = serial_omap_enable_ms,
1421         .break_ctl      = serial_omap_break_ctl,
1422         .startup        = serial_omap_startup,
1423         .shutdown       = serial_omap_shutdown,
1424         .set_termios    = serial_omap_set_termios,
1425         .pm             = serial_omap_pm,
1426         .type           = serial_omap_type,
1427         .release_port   = serial_omap_release_port,
1428         .request_port   = serial_omap_request_port,
1429         .config_port    = serial_omap_config_port,
1430         .verify_port    = serial_omap_verify_port,
1431         .ioctl          = serial_omap_ioctl,
1432 #ifdef CONFIG_CONSOLE_POLL
1433         .poll_put_char  = serial_omap_poll_put_char,
1434         .poll_get_char  = serial_omap_poll_get_char,
1435 #endif
1436 };
1437
1438 static struct uart_driver serial_omap_reg = {
1439         .owner          = THIS_MODULE,
1440         .driver_name    = "OMAP-SERIAL",
1441         .dev_name       = OMAP_SERIAL_NAME,
1442         .nr             = OMAP_MAX_HSUART_PORTS,
1443         .cons           = OMAP_CONSOLE,
1444 };
1445
1446 #ifdef CONFIG_PM_SLEEP
1447 static int serial_omap_prepare(struct device *dev)
1448 {
1449         struct uart_omap_port *up = dev_get_drvdata(dev);
1450
1451         up->is_suspending = true;
1452
1453         return 0;
1454 }
1455
1456 static void serial_omap_complete(struct device *dev)
1457 {
1458         struct uart_omap_port *up = dev_get_drvdata(dev);
1459
1460         up->is_suspending = false;
1461 }
1462
1463 static int serial_omap_suspend(struct device *dev)
1464 {
1465         struct uart_omap_port *up = dev_get_drvdata(dev);
1466
1467         uart_suspend_port(&serial_omap_reg, &up->port);
1468         flush_work(&up->qos_work);
1469
1470         return 0;
1471 }
1472
1473 static int serial_omap_resume(struct device *dev)
1474 {
1475         struct uart_omap_port *up = dev_get_drvdata(dev);
1476
1477         uart_resume_port(&serial_omap_reg, &up->port);
1478
1479         return 0;
1480 }
1481 #else
1482 #define serial_omap_prepare NULL
1483 #define serial_omap_complete NULL
1484 #endif /* CONFIG_PM_SLEEP */
1485
1486 static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
1487 {
1488         u32 mvr, scheme;
1489         u16 revision, major, minor;
1490
1491         mvr = readl(up->port.membase + (UART_OMAP_MVER << up->port.regshift));
1492
1493         /* Check revision register scheme */
1494         scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
1495
1496         switch (scheme) {
1497         case 0: /* Legacy Scheme: OMAP2/3 */
1498                 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
1499                 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
1500                                         OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
1501                 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
1502                 break;
1503         case 1:
1504                 /* New Scheme: OMAP4+ */
1505                 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
1506                 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
1507                                         OMAP_UART_MVR_MAJ_SHIFT;
1508                 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
1509                 break;
1510         default:
1511                 dev_warn(up->dev,
1512                         "Unknown %s revision, defaulting to highest\n",
1513                         up->name);
1514                 /* highest possible revision */
1515                 major = 0xff;
1516                 minor = 0xff;
1517         }
1518
1519         /* normalize revision for the driver */
1520         revision = UART_BUILD_REVISION(major, minor);
1521
1522         switch (revision) {
1523         case OMAP_UART_REV_46:
1524                 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1525                                 UART_ERRATA_i291_DMA_FORCEIDLE);
1526                 break;
1527         case OMAP_UART_REV_52:
1528                 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1529                                 UART_ERRATA_i291_DMA_FORCEIDLE);
1530                 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1531                 break;
1532         case OMAP_UART_REV_63:
1533                 up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
1534                 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1535                 break;
1536         default:
1537                 break;
1538         }
1539 }
1540
1541 static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
1542 {
1543         struct omap_uart_port_info *omap_up_info;
1544
1545         omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
1546         if (!omap_up_info)
1547                 return NULL; /* out of memory */
1548
1549         of_property_read_u32(dev->of_node, "clock-frequency",
1550                                          &omap_up_info->uartclk);
1551         return omap_up_info;
1552 }
1553
1554 static int serial_omap_probe_rs485(struct uart_omap_port *up,
1555                                    struct device_node *np)
1556 {
1557         struct serial_rs485 *rs485conf = &up->rs485;
1558         u32 rs485_delay[2];
1559         enum of_gpio_flags flags;
1560         int ret;
1561
1562         rs485conf->flags = 0;
1563         up->rts_gpio = -EINVAL;
1564
1565         if (!np)
1566                 return 0;
1567
1568         if (of_property_read_bool(np, "rs485-rts-active-high"))
1569                 rs485conf->flags |= SER_RS485_RTS_ON_SEND;
1570         else
1571                 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
1572
1573         /* check for tx enable gpio */
1574         up->rts_gpio = of_get_named_gpio_flags(np, "rts-gpio", 0, &flags);
1575         if (gpio_is_valid(up->rts_gpio)) {
1576                 ret = gpio_request(up->rts_gpio, "omap-serial");
1577                 if (ret < 0)
1578                         return ret;
1579                 ret = gpio_direction_output(up->rts_gpio,
1580                                             flags & SER_RS485_RTS_AFTER_SEND);
1581                 if (ret < 0)
1582                         return ret;
1583         } else
1584                 up->rts_gpio = -EINVAL;
1585
1586         if (of_property_read_u32_array(np, "rs485-rts-delay",
1587                                     rs485_delay, 2) == 0) {
1588                 rs485conf->delay_rts_before_send = rs485_delay[0];
1589                 rs485conf->delay_rts_after_send = rs485_delay[1];
1590         }
1591
1592         if (of_property_read_bool(np, "rs485-rx-during-tx"))
1593                 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1594
1595         if (of_property_read_bool(np, "linux,rs485-enabled-at-boot-time"))
1596                 rs485conf->flags |= SER_RS485_ENABLED;
1597
1598         return 0;
1599 }
1600
1601 static int serial_omap_probe(struct platform_device *pdev)
1602 {
1603         struct uart_omap_port   *up;
1604         struct resource         *mem, *irq;
1605         struct omap_uart_port_info *omap_up_info = dev_get_platdata(&pdev->dev);
1606         int ret, uartirq = 0, wakeirq = 0;
1607
1608         /* The optional wakeirq may be specified in the board dts file */
1609         if (pdev->dev.of_node) {
1610                 uartirq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1611                 if (!uartirq)
1612                         return -EPROBE_DEFER;
1613                 wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1);
1614                 omap_up_info = of_get_uart_port_info(&pdev->dev);
1615                 pdev->dev.platform_data = omap_up_info;
1616         } else {
1617                 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1618                 if (!irq) {
1619                         dev_err(&pdev->dev, "no irq resource?\n");
1620                         return -ENODEV;
1621                 }
1622                 uartirq = irq->start;
1623         }
1624
1625         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1626         if (!mem) {
1627                 dev_err(&pdev->dev, "no mem resource?\n");
1628                 return -ENODEV;
1629         }
1630
1631         if (!devm_request_mem_region(&pdev->dev, mem->start, resource_size(mem),
1632                                 pdev->dev.driver->name)) {
1633                 dev_err(&pdev->dev, "memory region already claimed\n");
1634                 return -EBUSY;
1635         }
1636
1637         if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1638             omap_up_info->DTR_present) {
1639                 ret = gpio_request(omap_up_info->DTR_gpio, "omap-serial");
1640                 if (ret < 0)
1641                         return ret;
1642                 ret = gpio_direction_output(omap_up_info->DTR_gpio,
1643                                             omap_up_info->DTR_inverted);
1644                 if (ret < 0)
1645                         return ret;
1646         }
1647
1648         up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
1649         if (!up)
1650                 return -ENOMEM;
1651
1652         if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1653             omap_up_info->DTR_present) {
1654                 up->DTR_gpio = omap_up_info->DTR_gpio;
1655                 up->DTR_inverted = omap_up_info->DTR_inverted;
1656         } else
1657                 up->DTR_gpio = -EINVAL;
1658         up->DTR_active = 0;
1659
1660         up->dev = &pdev->dev;
1661         up->port.dev = &pdev->dev;
1662         up->port.type = PORT_OMAP;
1663         up->port.iotype = UPIO_MEM;
1664         up->port.irq = uartirq;
1665         up->wakeirq = wakeirq;
1666
1667         up->port.regshift = 2;
1668         up->port.fifosize = 64;
1669         up->port.ops = &serial_omap_pops;
1670
1671         if (pdev->dev.of_node)
1672                 up->port.line = of_alias_get_id(pdev->dev.of_node, "serial");
1673         else
1674                 up->port.line = pdev->id;
1675
1676         if (up->port.line < 0) {
1677                 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
1678                                                                 up->port.line);
1679                 ret = -ENODEV;
1680                 goto err_port_line;
1681         }
1682
1683         ret = serial_omap_probe_rs485(up, pdev->dev.of_node);
1684         if (ret < 0)
1685                 goto err_rs485;
1686
1687         sprintf(up->name, "OMAP UART%d", up->port.line);
1688         up->port.mapbase = mem->start;
1689         up->port.membase = devm_ioremap(&pdev->dev, mem->start,
1690                                                 resource_size(mem));
1691         if (!up->port.membase) {
1692                 dev_err(&pdev->dev, "can't ioremap UART\n");
1693                 ret = -ENOMEM;
1694                 goto err_ioremap;
1695         }
1696
1697         up->port.flags = omap_up_info->flags;
1698         up->port.uartclk = omap_up_info->uartclk;
1699         if (!up->port.uartclk) {
1700                 up->port.uartclk = DEFAULT_CLK_SPEED;
1701                 dev_warn(&pdev->dev, "No clock speed specified: using default:"
1702                                                 "%d\n", DEFAULT_CLK_SPEED);
1703         }
1704
1705         up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1706         up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1707         pm_qos_add_request(&up->pm_qos_request,
1708                 PM_QOS_CPU_DMA_LATENCY, up->latency);
1709         serial_omap_uart_wq = create_singlethread_workqueue(up->name);
1710         INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1711
1712         platform_set_drvdata(pdev, up);
1713         if (omap_up_info->autosuspend_timeout == 0)
1714                 omap_up_info->autosuspend_timeout = -1;
1715         device_init_wakeup(up->dev, true);
1716         pm_runtime_use_autosuspend(&pdev->dev);
1717         pm_runtime_set_autosuspend_delay(&pdev->dev,
1718                         omap_up_info->autosuspend_timeout);
1719
1720         pm_runtime_irq_safe(&pdev->dev);
1721         pm_runtime_enable(&pdev->dev);
1722
1723         pm_runtime_get_sync(&pdev->dev);
1724
1725         omap_serial_fill_features_erratas(up);
1726
1727         ui[up->port.line] = up;
1728         serial_omap_add_console_port(up);
1729
1730         ret = uart_add_one_port(&serial_omap_reg, &up->port);
1731         if (ret != 0)
1732                 goto err_add_port;
1733
1734         pm_runtime_mark_last_busy(up->dev);
1735         pm_runtime_put_autosuspend(up->dev);
1736         return 0;
1737
1738 err_add_port:
1739         pm_runtime_put(&pdev->dev);
1740         pm_runtime_disable(&pdev->dev);
1741 err_ioremap:
1742 err_rs485:
1743 err_port_line:
1744         dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n",
1745                                 pdev->id, __func__, ret);
1746         return ret;
1747 }
1748
1749 static int serial_omap_remove(struct platform_device *dev)
1750 {
1751         struct uart_omap_port *up = platform_get_drvdata(dev);
1752
1753         pm_runtime_put_sync(up->dev);
1754         pm_runtime_disable(up->dev);
1755         uart_remove_one_port(&serial_omap_reg, &up->port);
1756         pm_qos_remove_request(&up->pm_qos_request);
1757
1758         return 0;
1759 }
1760
1761 /*
1762  * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1763  * The access to uart register after MDR1 Access
1764  * causes UART to corrupt data.
1765  *
1766  * Need a delay =
1767  * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1768  * give 10 times as much
1769  */
1770 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1771 {
1772         u8 timeout = 255;
1773
1774         serial_out(up, UART_OMAP_MDR1, mdr1);
1775         udelay(2);
1776         serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1777                         UART_FCR_CLEAR_RCVR);
1778         /*
1779          * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1780          * TX_FIFO_E bit is 1.
1781          */
1782         while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1783                                 (UART_LSR_THRE | UART_LSR_DR))) {
1784                 timeout--;
1785                 if (!timeout) {
1786                         /* Should *never* happen. we warn and carry on */
1787                         dev_crit(up->dev, "Errata i202: timedout %x\n",
1788                                                 serial_in(up, UART_LSR));
1789                         break;
1790                 }
1791                 udelay(1);
1792         }
1793 }
1794
1795 #ifdef CONFIG_PM_RUNTIME
1796 static void serial_omap_restore_context(struct uart_omap_port *up)
1797 {
1798         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1799                 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1800         else
1801                 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1802
1803         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1804         serial_out(up, UART_EFR, UART_EFR_ECB);
1805         serial_out(up, UART_LCR, 0x0); /* Operational mode */
1806         serial_out(up, UART_IER, 0x0);
1807         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1808         serial_out(up, UART_DLL, up->dll);
1809         serial_out(up, UART_DLM, up->dlh);
1810         serial_out(up, UART_LCR, 0x0); /* Operational mode */
1811         serial_out(up, UART_IER, up->ier);
1812         serial_out(up, UART_FCR, up->fcr);
1813         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1814         serial_out(up, UART_MCR, up->mcr);
1815         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1816         serial_out(up, UART_OMAP_SCR, up->scr);
1817         serial_out(up, UART_EFR, up->efr);
1818         serial_out(up, UART_LCR, up->lcr);
1819         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1820                 serial_omap_mdr1_errataset(up, up->mdr1);
1821         else
1822                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1823         serial_out(up, UART_OMAP_WER, up->wer);
1824 }
1825
1826 static int serial_omap_runtime_suspend(struct device *dev)
1827 {
1828         struct uart_omap_port *up = dev_get_drvdata(dev);
1829
1830         if (!up)
1831                 return -EINVAL;
1832
1833         /*
1834         * When using 'no_console_suspend', the console UART must not be
1835         * suspended. Since driver suspend is managed by runtime suspend,
1836         * preventing runtime suspend (by returning error) will keep device
1837         * active during suspend.
1838         */
1839         if (up->is_suspending && !console_suspend_enabled &&
1840             uart_console(&up->port))
1841                 return -EBUSY;
1842
1843         up->context_loss_cnt = serial_omap_get_context_loss_count(up);
1844
1845         if (device_may_wakeup(dev)) {
1846                 if (!up->wakeups_enabled) {
1847                         serial_omap_enable_wakeup(up, true);
1848                         up->wakeups_enabled = true;
1849                 }
1850         } else {
1851                 if (up->wakeups_enabled) {
1852                         serial_omap_enable_wakeup(up, false);
1853                         up->wakeups_enabled = false;
1854                 }
1855         }
1856
1857         up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1858         schedule_work(&up->qos_work);
1859
1860         return 0;
1861 }
1862
1863 static int serial_omap_runtime_resume(struct device *dev)
1864 {
1865         struct uart_omap_port *up = dev_get_drvdata(dev);
1866
1867         int loss_cnt = serial_omap_get_context_loss_count(up);
1868
1869         if (loss_cnt < 0) {
1870                 dev_dbg(dev, "serial_omap_get_context_loss_count failed : %d\n",
1871                         loss_cnt);
1872                 serial_omap_restore_context(up);
1873         } else if (up->context_loss_cnt != loss_cnt) {
1874                 serial_omap_restore_context(up);
1875         }
1876         up->latency = up->calc_latency;
1877         schedule_work(&up->qos_work);
1878
1879         return 0;
1880 }
1881 #endif
1882
1883 static const struct dev_pm_ops serial_omap_dev_pm_ops = {
1884         SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
1885         SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
1886                                 serial_omap_runtime_resume, NULL)
1887         .prepare        = serial_omap_prepare,
1888         .complete       = serial_omap_complete,
1889 };
1890
1891 #if defined(CONFIG_OF)
1892 static const struct of_device_id omap_serial_of_match[] = {
1893         { .compatible = "ti,omap2-uart" },
1894         { .compatible = "ti,omap3-uart" },
1895         { .compatible = "ti,omap4-uart" },
1896         {},
1897 };
1898 MODULE_DEVICE_TABLE(of, omap_serial_of_match);
1899 #endif
1900
1901 static struct platform_driver serial_omap_driver = {
1902         .probe          = serial_omap_probe,
1903         .remove         = serial_omap_remove,
1904         .driver         = {
1905                 .name   = DRIVER_NAME,
1906                 .pm     = &serial_omap_dev_pm_ops,
1907                 .of_match_table = of_match_ptr(omap_serial_of_match),
1908         },
1909 };
1910
1911 static int __init serial_omap_init(void)
1912 {
1913         int ret;
1914
1915         ret = uart_register_driver(&serial_omap_reg);
1916         if (ret != 0)
1917                 return ret;
1918         ret = platform_driver_register(&serial_omap_driver);
1919         if (ret != 0)
1920                 uart_unregister_driver(&serial_omap_reg);
1921         return ret;
1922 }
1923
1924 static void __exit serial_omap_exit(void)
1925 {
1926         platform_driver_unregister(&serial_omap_driver);
1927         uart_unregister_driver(&serial_omap_reg);
1928 }
1929
1930 module_init(serial_omap_init);
1931 module_exit(serial_omap_exit);
1932
1933 MODULE_DESCRIPTION("OMAP High Speed UART driver");
1934 MODULE_LICENSE("GPL");
1935 MODULE_AUTHOR("Texas Instruments Inc");