drivers/tty/serial/omap-serial.c

   1 /*
   2  * Driver for OMAP-UART controller.
   3  * Based on drivers/serial/8250.c
   4  *
   5  * Copyright (C) 2010 Texas Instruments.
   6  *
   7  * Authors:
   8  *      Govindraj R     <govindraj.raja@ti.com>
   9  *      Thara Gopinath  <thara@ti.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * Note: This driver is made separate from 8250 driver as we cannot
  17  * over load 8250 driver with omap platform specific configuration for
  18  * features like DMA, it makes easier to implement features like DMA and
  19  * hardware flow control and software flow control configuration with
  20  * this driver as required for the omap-platform.
  21  */
  22
  23 #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  24 #define SUPPORT_SYSRQ
  25 #endif
  26
  27 #include <linux/module.h>
  28 #include <linux/init.h>
  29 #include <linux/console.h>
  30 #include <linux/serial_reg.h>
  31 #include <linux/delay.h>
  32 #include <linux/slab.h>
  33 #include <linux/tty.h>
  34 #include <linux/tty_flip.h>
  35 #include <linux/platform_device.h>
  36 #include <linux/io.h>
  37 #include <linux/clk.h>
  38 #include <linux/serial_core.h>
  39 #include <linux/irq.h>
  40 #include <linux/pm_runtime.h>
  41 #include <linux/of.h>
  42 #include <linux/gpio.h>
  43 #include <linux/pinctrl/consumer.h>
  44
  45 #include <plat/omap-serial.h>
  46
  47 #define UART_BUILD_REVISION(x, y)       (((x) << 8) | (y))
  48
  49 #define OMAP_UART_REV_42 0x0402
  50 #define OMAP_UART_REV_46 0x0406
  51 #define OMAP_UART_REV_52 0x0502
  52 #define OMAP_UART_REV_63 0x0603
  53
  54 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
  55
  56 /* SCR register bitmasks */
  57 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK               (1 << 7)
  58
  59 /* FCR register bitmasks */
  60 #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK                 (0x3 << 6)
  61 #define OMAP_UART_FCR_TX_FIFO_TRIG_MASK                 (0x3 << 4)
  62
  63 /* MVR register bitmasks */
  64 #define OMAP_UART_MVR_SCHEME_SHIFT      30
  65
  66 #define OMAP_UART_LEGACY_MVR_MAJ_MASK   0xf0
  67 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT  4
  68 #define OMAP_UART_LEGACY_MVR_MIN_MASK   0x0f
  69
  70 #define OMAP_UART_MVR_MAJ_MASK          0x700
  71 #define OMAP_UART_MVR_MAJ_SHIFT         8
  72 #define OMAP_UART_MVR_MIN_MASK          0x3f
  73
  74 struct uart_omap_port {
  75         struct uart_port        port;
  76         struct uart_omap_dma    uart_dma;
  77         struct device           *dev;
  78
  79         unsigned char           ier;
  80         unsigned char           lcr;
  81         unsigned char           mcr;
  82         unsigned char           fcr;
  83         unsigned char           efr;
  84         unsigned char           dll;
  85         unsigned char           dlh;
  86         unsigned char           mdr1;
  87         unsigned char           scr;
  88
  89         int                     use_dma;
  90         /*
  91          * Some bits in registers are cleared on a read, so they must
  92          * be saved whenever the register is read but the bits will not
  93          * be immediately processed.
  94          */
  95         unsigned int            lsr_break_flag;
  96         unsigned char           msr_saved_flags;
  97         char                    name[20];
  98         unsigned long           port_activity;
  99         u32                     context_loss_cnt;
 100         u32                     errata;
 101         u8                      wakeups_enabled;
 102
 103         int                     DTR_gpio;
 104         int                     DTR_inverted;
 105         int                     DTR_active;
 106
 107         struct pm_qos_request   pm_qos_request;
 108         u32                     latency;
 109         u32                     calc_latency;
 110         struct work_struct      qos_work;
 111         struct pinctrl          *pins;
 112 };
 113
 114 #define to_uart_omap_port(p)    ((container_of((p), struct uart_omap_port, port)))
 115
 116 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
 117
 118 /* Forward declaration of functions */
 119 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
 120
 121 static struct workqueue_struct *serial_omap_uart_wq;
 122
 123 static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
 124 {
 125         offset <<= up->port.regshift;
 126         return readw(up->port.membase + offset);
 127 }
 128
 129 static inline void serial_out(struct uart_omap_port *up, int offset, int value)
 130 {
 131         offset <<= up->port.regshift;
 132         writew(value, up->port.membase + offset);
 133 }
 134
 135 static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
 136 {
 137         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
 138         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
 139                        UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
 140         serial_out(up, UART_FCR, 0);
 141 }
 142
 143 static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
 144 {
 145         struct omap_uart_port_info *pdata = up->dev->platform_data;
 146
 147         if (!pdata || !pdata->get_context_loss_count)
 148                 return 0;
 149
 150         return pdata->get_context_loss_count(up->dev);
 151 }
 152
 153 static void serial_omap_set_forceidle(struct uart_omap_port *up)
 154 {
 155         struct omap_uart_port_info *pdata = up->dev->platform_data;
 156
 157         if (!pdata || !pdata->set_forceidle)
 158                 return;
 159
 160         pdata->set_forceidle(up->dev);
 161 }
 162
 163 static void serial_omap_set_noidle(struct uart_omap_port *up)
 164 {
 165         struct omap_uart_port_info *pdata = up->dev->platform_data;
 166
 167         if (!pdata || !pdata->set_noidle)
 168                 return;
 169
 170         pdata->set_noidle(up->dev);
 171 }
 172
 173 static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
 174 {
 175         struct omap_uart_port_info *pdata = up->dev->platform_data;
 176
 177         if (!pdata || !pdata->enable_wakeup)
 178                 return;
 179
 180         pdata->enable_wakeup(up->dev, enable);
 181 }
 182
 183 /*
 184  * serial_omap_get_divisor - calculate divisor value
 185  * @port: uart port info
 186  * @baud: baudrate for which divisor needs to be calculated.
 187  *
 188  * We have written our own function to get the divisor so as to support
 189  * 13x mode. 3Mbps Baudrate as an different divisor.
 190  * Reference OMAP TRM Chapter 17:
 191  * Table 17-1. UART Mode Baud Rates, Divisor Values, and Error Rates
 192  * referring to oversampling - divisor value
 193  * baudrate 460,800 to 3,686,400 all have divisor 13
 194  * except 3,000,000 which has divisor value 16
 195  */
 196 static unsigned int
 197 serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
 198 {
 199         unsigned int divisor;
 200
 201         if (baud > OMAP_MODE13X_SPEED && baud != 3000000)
 202                 divisor = 13;
 203         else
 204                 divisor = 16;
 205         return port->uartclk/(baud * divisor);
 206 }
 207
 208 static void serial_omap_enable_ms(struct uart_port *port)
 209 {
 210         struct uart_omap_port *up = to_uart_omap_port(port);
 211
 212         dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
 213
 214         pm_runtime_get_sync(up->dev);
 215         up->ier |= UART_IER_MSI;
 216         serial_out(up, UART_IER, up->ier);
 217         pm_runtime_mark_last_busy(up->dev);
 218         pm_runtime_put_autosuspend(up->dev);
 219 }
 220
 221 static void serial_omap_stop_tx(struct uart_port *port)
 222 {
 223         struct uart_omap_port *up = to_uart_omap_port(port);
 224
 225         pm_runtime_get_sync(up->dev);
 226         if (up->ier & UART_IER_THRI) {
 227                 up->ier &= ~UART_IER_THRI;
 228                 serial_out(up, UART_IER, up->ier);
 229         }
 230
 231         serial_omap_set_forceidle(up);
 232
 233         pm_runtime_mark_last_busy(up->dev);
 234         pm_runtime_put_autosuspend(up->dev);
 235 }
 236
 237 static void serial_omap_stop_rx(struct uart_port *port)
 238 {
 239         struct uart_omap_port *up = to_uart_omap_port(port);
 240
 241         pm_runtime_get_sync(up->dev);
 242         up->ier &= ~UART_IER_RLSI;
 243         up->port.read_status_mask &= ~UART_LSR_DR;
 244         serial_out(up, UART_IER, up->ier);
 245         pm_runtime_mark_last_busy(up->dev);
 246         pm_runtime_put_autosuspend(up->dev);
 247 }
 248
 249 static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
 250 {
 251         struct circ_buf *xmit = &up->port.state->xmit;
 252         int count;
 253
 254         if (!(lsr & UART_LSR_THRE))
 255                 return;
 256
 257         if (up->port.x_char) {
 258                 serial_out(up, UART_TX, up->port.x_char);
 259                 up->port.icount.tx++;
 260                 up->port.x_char = 0;
 261                 return;
 262         }
 263         if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
 264                 serial_omap_stop_tx(&up->port);
 265                 return;
 266         }
 267         count = up->port.fifosize / 4;
 268         do {
 269                 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
 270                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 271                 up->port.icount.tx++;
 272                 if (uart_circ_empty(xmit))
 273                         break;
 274         } while (--count > 0);
 275
 276         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
 277                 spin_unlock(&up->port.lock);
 278                 uart_write_wakeup(&up->port);
 279                 spin_lock(&up->port.lock);
 280         }
 281
 282         if (uart_circ_empty(xmit))
 283                 serial_omap_stop_tx(&up->port);
 284 }
 285
 286 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
 287 {
 288         if (!(up->ier & UART_IER_THRI)) {
 289                 up->ier |= UART_IER_THRI;
 290                 serial_out(up, UART_IER, up->ier);
 291         }
 292 }
 293
 294 static void serial_omap_start_tx(struct uart_port *port)
 295 {
 296         struct uart_omap_port *up = to_uart_omap_port(port);
 297
 298         pm_runtime_get_sync(up->dev);
 299         serial_omap_enable_ier_thri(up);
 300         serial_omap_set_noidle(up);
 301         pm_runtime_mark_last_busy(up->dev);
 302         pm_runtime_put_autosuspend(up->dev);
 303 }
 304
 305 static unsigned int check_modem_status(struct uart_omap_port *up)
 306 {
 307         unsigned int status;
 308
 309         status = serial_in(up, UART_MSR);
 310         status |= up->msr_saved_flags;
 311         up->msr_saved_flags = 0;
 312         if ((status & UART_MSR_ANY_DELTA) == 0)
 313                 return status;
 314
 315         if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
 316             up->port.state != NULL) {
 317                 if (status & UART_MSR_TERI)
 318                         up->port.icount.rng++;
 319                 if (status & UART_MSR_DDSR)
 320                         up->port.icount.dsr++;
 321                 if (status & UART_MSR_DDCD)
 322                         uart_handle_dcd_change
 323                                 (&up->port, status & UART_MSR_DCD);
 324                 if (status & UART_MSR_DCTS)
 325                         uart_handle_cts_change
 326                                 (&up->port, status & UART_MSR_CTS);
 327                 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
 328         }
 329
 330         return status;
 331 }
 332
 333 static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)
 334 {
 335         unsigned int flag;
 336         unsigned char ch = 0;
 337
 338         if (likely(lsr & UART_LSR_DR))
 339                 ch = serial_in(up, UART_RX);
 340
 341         up->port.icount.rx++;
 342         flag = TTY_NORMAL;
 343
 344         if (lsr & UART_LSR_BI) {
 345                 flag = TTY_BREAK;
 346                 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
 347                 up->port.icount.brk++;
 348                 /*
 349                  * We do the SysRQ and SAK checking
 350                  * here because otherwise the break
 351                  * may get masked by ignore_status_mask
 352                  * or read_status_mask.
 353                  */
 354                 if (uart_handle_break(&up->port))
 355                         return;
 356
 357         }
 358
 359         if (lsr & UART_LSR_PE) {
 360                 flag = TTY_PARITY;
 361                 up->port.icount.parity++;
 362         }
 363
 364         if (lsr & UART_LSR_FE) {
 365                 flag = TTY_FRAME;
 366                 up->port.icount.frame++;
 367         }
 368
 369         if (lsr & UART_LSR_OE)
 370                 up->port.icount.overrun++;
 371
 372 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
 373         if (up->port.line == up->port.cons->index) {
 374                 /* Recover the break flag from console xmit */
 375                 lsr |= up->lsr_break_flag;
 376         }
 377 #endif
 378         uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);
 379 }
 380
 381 static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
 382 {
 383         unsigned char ch = 0;
 384         unsigned int flag;
 385
 386         if (!(lsr & UART_LSR_DR))
 387                 return;
 388
 389         ch = serial_in(up, UART_RX);
 390         flag = TTY_NORMAL;
 391         up->port.icount.rx++;
 392
 393         if (uart_handle_sysrq_char(&up->port, ch))
 394                 return;
 395
 396         uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
 397 }
 398
 399 /**
 400  * serial_omap_irq() - This handles the interrupt from one port
 401  * @irq: uart port irq number
 402  * @dev_id: uart port info
 403  */
 404 static irqreturn_t serial_omap_irq(int irq, void *dev_id)
 405 {
 406         struct uart_omap_port *up = dev_id;
 407         struct tty_struct *tty = up->port.state->port.tty;
 408         unsigned int iir, lsr;
 409         unsigned int type;
 410         irqreturn_t ret = IRQ_NONE;
 411         int max_count = 256;
 412
 413         spin_lock(&up->port.lock);
 414         pm_runtime_get_sync(up->dev);
 415
 416         do {
 417                 iir = serial_in(up, UART_IIR);
 418                 if (iir & UART_IIR_NO_INT)
 419                         break;
 420
 421                 ret = IRQ_HANDLED;
 422                 lsr = serial_in(up, UART_LSR);
 423
 424                 /* extract IRQ type from IIR register */
 425                 type = iir & 0x3e;
 426
 427                 switch (type) {
 428                 case UART_IIR_MSI:
 429                         check_modem_status(up);
 430                         break;
 431                 case UART_IIR_THRI:
 432                         transmit_chars(up, lsr);
 433                         break;
 434                 case UART_IIR_RX_TIMEOUT:
 435                         /* FALLTHROUGH */
 436                 case UART_IIR_RDI:
 437                         serial_omap_rdi(up, lsr);
 438                         break;
 439                 case UART_IIR_RLSI:
 440                         serial_omap_rlsi(up, lsr);
 441                         break;
 442                 case UART_IIR_CTS_RTS_DSR:
 443                         /* simply try again */
 444                         break;
 445                 case UART_IIR_XOFF:
 446                         /* FALLTHROUGH */
 447                 default:
 448                         break;
 449                 }
 450         } while (!(iir & UART_IIR_NO_INT) && max_count--);
 451
 452         spin_unlock(&up->port.lock);
 453
 454         tty_flip_buffer_push(tty);
 455
 456         pm_runtime_mark_last_busy(up->dev);
 457         pm_runtime_put_autosuspend(up->dev);
 458         up->port_activity = jiffies;
 459
 460         return ret;
 461 }
 462
 463 static unsigned int serial_omap_tx_empty(struct uart_port *port)
 464 {
 465         struct uart_omap_port *up = to_uart_omap_port(port);
 466         unsigned long flags = 0;
 467         unsigned int ret = 0;
 468
 469         pm_runtime_get_sync(up->dev);
 470         dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
 471         spin_lock_irqsave(&up->port.lock, flags);
 472         ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
 473         spin_unlock_irqrestore(&up->port.lock, flags);
 474         pm_runtime_mark_last_busy(up->dev);
 475         pm_runtime_put_autosuspend(up->dev);
 476         return ret;
 477 }
 478
 479 static unsigned int serial_omap_get_mctrl(struct uart_port *port)
 480 {
 481         struct uart_omap_port *up = to_uart_omap_port(port);
 482         unsigned int status;
 483         unsigned int ret = 0;
 484
 485         pm_runtime_get_sync(up->dev);
 486         status = check_modem_status(up);
 487         pm_runtime_mark_last_busy(up->dev);
 488         pm_runtime_put_autosuspend(up->dev);
 489
 490         dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
 491
 492         if (status & UART_MSR_DCD)
 493                 ret |= TIOCM_CAR;
 494         if (status & UART_MSR_RI)
 495                 ret |= TIOCM_RNG;
 496         if (status & UART_MSR_DSR)
 497                 ret |= TIOCM_DSR;
 498         if (status & UART_MSR_CTS)
 499                 ret |= TIOCM_CTS;
 500         return ret;
 501 }
 502
 503 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
 504 {
 505         struct uart_omap_port *up = to_uart_omap_port(port);
 506         unsigned char mcr = 0, old_mcr;
 507
 508         dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
 509         if (mctrl & TIOCM_RTS)
 510                 mcr |= UART_MCR_RTS;
 511         if (mctrl & TIOCM_DTR)
 512                 mcr |= UART_MCR_DTR;
 513         if (mctrl & TIOCM_OUT1)
 514                 mcr |= UART_MCR_OUT1;
 515         if (mctrl & TIOCM_OUT2)
 516                 mcr |= UART_MCR_OUT2;
 517         if (mctrl & TIOCM_LOOP)
 518                 mcr |= UART_MCR_LOOP;
 519
 520         pm_runtime_get_sync(up->dev);
 521         old_mcr = serial_in(up, UART_MCR);
 522         old_mcr &= ~(UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_OUT1 |
 523                      UART_MCR_DTR | UART_MCR_RTS);
 524         up->mcr = old_mcr | mcr;
 525         serial_out(up, UART_MCR, up->mcr);
 526         pm_runtime_mark_last_busy(up->dev);
 527         pm_runtime_put_autosuspend(up->dev);
 528
 529         if (gpio_is_valid(up->DTR_gpio) &&
 530             !!(mctrl & TIOCM_DTR) != up->DTR_active) {
 531                 up->DTR_active = !up->DTR_active;
 532                 if (gpio_cansleep(up->DTR_gpio))
 533                         schedule_work(&up->qos_work);
 534                 else
 535                         gpio_set_value(up->DTR_gpio,
 536                                        up->DTR_active != up->DTR_inverted);
 537         }
 538 }
 539
 540 static void serial_omap_break_ctl(struct uart_port *port, int break_state)
 541 {
 542         struct uart_omap_port *up = to_uart_omap_port(port);
 543         unsigned long flags = 0;
 544
 545         dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
 546         pm_runtime_get_sync(up->dev);
 547         spin_lock_irqsave(&up->port.lock, flags);
 548         if (break_state == -1)
 549                 up->lcr |= UART_LCR_SBC;
 550         else
 551                 up->lcr &= ~UART_LCR_SBC;
 552         serial_out(up, UART_LCR, up->lcr);
 553         spin_unlock_irqrestore(&up->port.lock, flags);
 554         pm_runtime_mark_last_busy(up->dev);
 555         pm_runtime_put_autosuspend(up->dev);
 556 }
 557
 558 static int serial_omap_startup(struct uart_port *port)
 559 {
 560         struct uart_omap_port *up = to_uart_omap_port(port);
 561         unsigned long flags = 0;
 562         int retval;
 563
 564         /*
 565          * Allocate the IRQ
 566          */
 567         retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
 568                                 up->name, up);
 569         if (retval)
 570                 return retval;
 571
 572         dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
 573
 574         pm_runtime_get_sync(up->dev);
 575         /*
 576          * Clear the FIFO buffers and disable them.
 577          * (they will be reenabled in set_termios())
 578          */
 579         serial_omap_clear_fifos(up);
 580         /* For Hardware flow control */
 581         serial_out(up, UART_MCR, UART_MCR_RTS);
 582
 583         /*
 584          * Clear the interrupt registers.
 585          */
 586         (void) serial_in(up, UART_LSR);
 587         if (serial_in(up, UART_LSR) & UART_LSR_DR)
 588                 (void) serial_in(up, UART_RX);
 589         (void) serial_in(up, UART_IIR);
 590         (void) serial_in(up, UART_MSR);
 591
 592         /*
 593          * Now, initialize the UART
 594          */
 595         serial_out(up, UART_LCR, UART_LCR_WLEN8);
 596         spin_lock_irqsave(&up->port.lock, flags);
 597         /*
 598          * Most PC uarts need OUT2 raised to enable interrupts.
 599          */
 600         up->port.mctrl |= TIOCM_OUT2;
 601         serial_omap_set_mctrl(&up->port, up->port.mctrl);
 602         spin_unlock_irqrestore(&up->port.lock, flags);
 603
 604         up->msr_saved_flags = 0;
 605         /*
 606          * Finally, enable interrupts. Note: Modem status interrupts
 607          * are set via set_termios(), which will be occurring imminently
 608          * anyway, so we don't enable them here.
 609          */
 610         up->ier = UART_IER_RLSI | UART_IER_RDI;
 611         serial_out(up, UART_IER, up->ier);
 612
 613         /* Enable module level wake up */
 614         serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP);
 615
 616         pm_runtime_mark_last_busy(up->dev);
 617         pm_runtime_put_autosuspend(up->dev);
 618         up->port_activity = jiffies;
 619         return 0;
 620 }
 621
 622 static void serial_omap_shutdown(struct uart_port *port)
 623 {
 624         struct uart_omap_port *up = to_uart_omap_port(port);
 625         unsigned long flags = 0;
 626
 627         dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
 628
 629         pm_runtime_get_sync(up->dev);
 630         /*
 631          * Disable interrupts from this port
 632          */
 633         up->ier = 0;
 634         serial_out(up, UART_IER, 0);
 635
 636         spin_lock_irqsave(&up->port.lock, flags);
 637         up->port.mctrl &= ~TIOCM_OUT2;
 638         serial_omap_set_mctrl(&up->port, up->port.mctrl);
 639         spin_unlock_irqrestore(&up->port.lock, flags);
 640
 641         /*
 642          * Disable break condition and FIFOs
 643          */
 644         serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
 645         serial_omap_clear_fifos(up);
 646
 647         /*
 648          * Read data port to reset things, and then free the irq
 649          */
 650         if (serial_in(up, UART_LSR) & UART_LSR_DR)
 651                 (void) serial_in(up, UART_RX);
 652
 653         pm_runtime_mark_last_busy(up->dev);
 654         pm_runtime_put_autosuspend(up->dev);
 655         free_irq(up->port.irq, up);
 656 }
 657
 658 static inline void
 659 serial_omap_configure_xonxoff
 660                 (struct uart_omap_port *up, struct ktermios *termios)
 661 {
 662         up->lcr = serial_in(up, UART_LCR);
 663         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 664         up->efr = serial_in(up, UART_EFR);
 665         serial_out(up, UART_EFR, up->efr & ~UART_EFR_ECB);
 666
 667         serial_out(up, UART_XON1, termios->c_cc[VSTART]);
 668         serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
 669
 670         /* clear SW control mode bits */
 671         up->efr &= OMAP_UART_SW_CLR;
 672
 673         /*
 674          * IXON Flag:
 675          * Enable XON/XOFF flow control on output.
 676          * Transmit XON1, XOFF1
 677          */
 678         if (termios->c_iflag & IXON)
 679                 up->efr |= OMAP_UART_SW_TX;
 680
 681         /*
 682          * IXOFF Flag:
 683          * Enable XON/XOFF flow control on input.
 684          * Receiver compares XON1, XOFF1.
 685          */
 686         if (termios->c_iflag & IXOFF)
 687                 up->efr |= OMAP_UART_SW_RX;
 688
 689         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 690         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 691
 692         up->mcr = serial_in(up, UART_MCR);
 693
 694         /*
 695          * IXANY Flag:
 696          * Enable any character to restart output.
 697          * Operation resumes after receiving any
 698          * character after recognition of the XOFF character
 699          */
 700         if (termios->c_iflag & IXANY)
 701                 up->mcr |= UART_MCR_XONANY;
 702         else
 703                 up->mcr &= ~UART_MCR_XONANY;
 704
 705         serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
 706         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 707         serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
 708         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 709         serial_out(up, UART_MCR, up->mcr & ~UART_MCR_TCRTLR);
 710         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 711         serial_out(up, UART_EFR, up->efr);
 712         serial_out(up, UART_LCR, up->lcr);
 713 }
 714
 715 static void serial_omap_uart_qos_work(struct work_struct *work)
 716 {
 717         struct uart_omap_port *up = container_of(work, struct uart_omap_port,
 718                                                 qos_work);
 719
 720         pm_qos_update_request(&up->pm_qos_request, up->latency);
 721         if (gpio_is_valid(up->DTR_gpio))
 722                 gpio_set_value_cansleep(up->DTR_gpio,
 723                                         up->DTR_active != up->DTR_inverted);
 724 }
 725
 726 static void
 727 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
 728                         struct ktermios *old)
 729 {
 730         struct uart_omap_port *up = to_uart_omap_port(port);
 731         unsigned char cval = 0;
 732         unsigned long flags = 0;
 733         unsigned int baud, quot;
 734
 735         switch (termios->c_cflag & CSIZE) {
 736         case CS5:
 737                 cval = UART_LCR_WLEN5;
 738                 break;
 739         case CS6:
 740                 cval = UART_LCR_WLEN6;
 741                 break;
 742         case CS7:
 743                 cval = UART_LCR_WLEN7;
 744                 break;
 745         default:
 746         case CS8:
 747                 cval = UART_LCR_WLEN8;
 748                 break;
 749         }
 750
 751         if (termios->c_cflag & CSTOPB)
 752                 cval |= UART_LCR_STOP;
 753         if (termios->c_cflag & PARENB)
 754                 cval |= UART_LCR_PARITY;
 755         if (!(termios->c_cflag & PARODD))
 756                 cval |= UART_LCR_EPAR;
 757
 758         /*
 759          * Ask the core to calculate the divisor for us.
 760          */
 761
 762         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
 763         quot = serial_omap_get_divisor(port, baud);
 764
 765         /* calculate wakeup latency constraint */
 766         up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8);
 767         up->latency = up->calc_latency;
 768         schedule_work(&up->qos_work);
 769
 770         up->dll = quot & 0xff;
 771         up->dlh = quot >> 8;
 772         up->mdr1 = UART_OMAP_MDR1_DISABLE;
 773
 774         up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
 775                         UART_FCR_ENABLE_FIFO;
 776
 777         /*
 778          * Ok, we're now changing the port state. Do it with
 779          * interrupts disabled.
 780          */
 781         pm_runtime_get_sync(up->dev);
 782         spin_lock_irqsave(&up->port.lock, flags);
 783
 784         /*
 785          * Update the per-port timeout.
 786          */
 787         uart_update_timeout(port, termios->c_cflag, baud);
 788
 789         up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
 790         if (termios->c_iflag & INPCK)
 791                 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
 792         if (termios->c_iflag & (BRKINT | PARMRK))
 793                 up->port.read_status_mask |= UART_LSR_BI;
 794
 795         /*
 796          * Characters to ignore
 797          */
 798         up->port.ignore_status_mask = 0;
 799         if (termios->c_iflag & IGNPAR)
 800                 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
 801         if (termios->c_iflag & IGNBRK) {
 802                 up->port.ignore_status_mask |= UART_LSR_BI;
 803                 /*
 804                  * If we're ignoring parity and break indicators,
 805                  * ignore overruns too (for real raw support).
 806                  */
 807                 if (termios->c_iflag & IGNPAR)
 808                         up->port.ignore_status_mask |= UART_LSR_OE;
 809         }
 810
 811         /*
 812          * ignore all characters if CREAD is not set
 813          */
 814         if ((termios->c_cflag & CREAD) == 0)
 815                 up->port.ignore_status_mask |= UART_LSR_DR;
 816
 817         /*
 818          * Modem status interrupts
 819          */
 820         up->ier &= ~UART_IER_MSI;
 821         if (UART_ENABLE_MS(&up->port, termios->c_cflag))
 822                 up->ier |= UART_IER_MSI;
 823         serial_out(up, UART_IER, up->ier);
 824         serial_out(up, UART_LCR, cval);         /* reset DLAB */
 825         up->lcr = cval;
 826         up->scr = OMAP_UART_SCR_TX_EMPTY;
 827
 828         /* FIFOs and DMA Settings */
 829
 830         /* FCR can be changed only when the
 831          * baud clock is not running
 832          * DLL_REG and DLH_REG set to 0.
 833          */
 834         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 835         serial_out(up, UART_DLL, 0);
 836         serial_out(up, UART_DLM, 0);
 837         serial_out(up, UART_LCR, 0);
 838
 839         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 840
 841         up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB;
 842         up->efr &= ~UART_EFR_SCD;
 843         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 844
 845         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 846         up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR;
 847         serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
 848         /* FIFO ENABLE, DMA MODE */
 849
 850         up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
 851
 852         /* Set receive FIFO threshold to 16 characters and
 853          * transmit FIFO threshold to 16 spaces
 854          */
 855         up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
 856         up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK;
 857         up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 |
 858                 UART_FCR_ENABLE_FIFO;
 859
 860         serial_out(up, UART_FCR, up->fcr);
 861         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 862
 863         serial_out(up, UART_OMAP_SCR, up->scr);
 864
 865         /* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */
 866         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 867         serial_out(up, UART_MCR, up->mcr);
 868         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 869         serial_out(up, UART_EFR, up->efr);
 870         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 871
 872         /* Protocol, Baud Rate, and Interrupt Settings */
 873
 874         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
 875                 serial_omap_mdr1_errataset(up, up->mdr1);
 876         else
 877                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
 878
 879         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 880         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 881
 882         serial_out(up, UART_LCR, 0);
 883         serial_out(up, UART_IER, 0);
 884         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 885
 886         serial_out(up, UART_DLL, up->dll);      /* LS of divisor */
 887         serial_out(up, UART_DLM, up->dlh);      /* MS of divisor */
 888
 889         serial_out(up, UART_LCR, 0);
 890         serial_out(up, UART_IER, up->ier);
 891         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 892
 893         serial_out(up, UART_EFR, up->efr);
 894         serial_out(up, UART_LCR, cval);
 895
 896         if (baud > 230400 && baud != 3000000)
 897                 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
 898         else
 899                 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
 900
 901         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
 902                 serial_omap_mdr1_errataset(up, up->mdr1);
 903         else
 904                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
 905
 906         /* Hardware Flow Control Configuration */
 907
 908         if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
 909                 /* Enable access to TCR/TLR */
 910                 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 911                 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 912                 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 913                 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
 914
 915                 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
 916
 917                 /* Enable AUTORTS and AUTOCTS */
 918                 up->efr |= UART_EFR_CTS | UART_EFR_RTS;
 919
 920                 /* Disable access to TCR/TLR */
 921                 serial_out(up, UART_MCR, up->mcr | UART_MCR_RTS);
 922                 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 923                 serial_out(up, UART_EFR, up->efr);
 924                 serial_out(up, UART_LCR, cval);
 925         } else {
 926                 /* Disable AUTORTS and AUTOCTS */
 927                 up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS);
 928
 929                 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 930                 serial_out(up, UART_EFR, up->efr);
 931                 serial_out(up, UART_LCR, cval);
 932         }
 933
 934         serial_omap_set_mctrl(&up->port, up->port.mctrl);
 935         /* Software Flow Control Configuration */
 936         if (up->port.flags & UPF_SOFT_FLOW)
 937                 serial_omap_configure_xonxoff(up, termios);
 938
 939         spin_unlock_irqrestore(&up->port.lock, flags);
 940         pm_runtime_mark_last_busy(up->dev);
 941         pm_runtime_put_autosuspend(up->dev);
 942         dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
 943 }
 944
 945 static int serial_omap_set_wake(struct uart_port *port, unsigned int state)
 946 {
 947         struct uart_omap_port *up = to_uart_omap_port(port);
 948
 949         serial_omap_enable_wakeup(up, state);
 950
 951         return 0;
 952 }
 953
 954 static void
 955 serial_omap_pm(struct uart_port *port, unsigned int state,
 956                unsigned int oldstate)
 957 {
 958         struct uart_omap_port *up = to_uart_omap_port(port);
 959         unsigned char efr;
 960
 961         dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
 962
 963         pm_runtime_get_sync(up->dev);
 964         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 965         efr = serial_in(up, UART_EFR);
 966         serial_out(up, UART_EFR, efr | UART_EFR_ECB);
 967         serial_out(up, UART_LCR, 0);
 968
 969         serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
 970         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 971         serial_out(up, UART_EFR, efr);
 972         serial_out(up, UART_LCR, 0);
 973
 974         if (!device_may_wakeup(up->dev)) {
 975                 if (!state)
 976                         pm_runtime_forbid(up->dev);
 977                 else
 978                         pm_runtime_allow(up->dev);
 979         }
 980
 981         pm_runtime_mark_last_busy(up->dev);
 982         pm_runtime_put_autosuspend(up->dev);
 983 }
 984
 985 static void serial_omap_release_port(struct uart_port *port)
 986 {
 987         dev_dbg(port->dev, "serial_omap_release_port+\n");
 988 }
 989
 990 static int serial_omap_request_port(struct uart_port *port)
 991 {
 992         dev_dbg(port->dev, "serial_omap_request_port+\n");
 993         return 0;
 994 }
 995
 996 static void serial_omap_config_port(struct uart_port *port, int flags)
 997 {
 998         struct uart_omap_port *up = to_uart_omap_port(port);
 999
1000         dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
1001                                                         up->port.line);
1002         up->port.type = PORT_OMAP;
1003 }
1004
1005 static int
1006 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
1007 {
1008         /* we don't want the core code to modify any port params */
1009         dev_dbg(port->dev, "serial_omap_verify_port+\n");
1010         return -EINVAL;
1011 }
1012
1013 static const char *
1014 serial_omap_type(struct uart_port *port)
1015 {
1016         struct uart_omap_port *up = to_uart_omap_port(port);
1017
1018         dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
1019         return up->name;
1020 }
1021
1022 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1023
1024 static inline void wait_for_xmitr(struct uart_omap_port *up)
1025 {
1026         unsigned int status, tmout = 10000;
1027
1028         /* Wait up to 10ms for the character(s) to be sent. */
1029         do {
1030                 status = serial_in(up, UART_LSR);
1031
1032                 if (status & UART_LSR_BI)
1033                         up->lsr_break_flag = UART_LSR_BI;
1034
1035                 if (--tmout == 0)
1036                         break;
1037                 udelay(1);
1038         } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
1039
1040         /* Wait up to 1s for flow control if necessary */
1041         if (up->port.flags & UPF_CONS_FLOW) {
1042                 tmout = 1000000;
1043                 for (tmout = 1000000; tmout; tmout--) {
1044                         unsigned int msr = serial_in(up, UART_MSR);
1045
1046                         up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1047                         if (msr & UART_MSR_CTS)
1048                                 break;
1049
1050                         udelay(1);
1051                 }
1052         }
1053 }
1054
1055 #ifdef CONFIG_CONSOLE_POLL
1056
1057 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
1058 {
1059         struct uart_omap_port *up = to_uart_omap_port(port);
1060
1061         pm_runtime_get_sync(up->dev);
1062         wait_for_xmitr(up);
1063         serial_out(up, UART_TX, ch);
1064         pm_runtime_mark_last_busy(up->dev);
1065         pm_runtime_put_autosuspend(up->dev);
1066 }
1067
1068 static int serial_omap_poll_get_char(struct uart_port *port)
1069 {
1070         struct uart_omap_port *up = to_uart_omap_port(port);
1071         unsigned int status;
1072
1073         pm_runtime_get_sync(up->dev);
1074         status = serial_in(up, UART_LSR);
1075         if (!(status & UART_LSR_DR)) {
1076                 status = NO_POLL_CHAR;
1077                 goto out;
1078         }
1079
1080         status = serial_in(up, UART_RX);
1081
1082 out:
1083         pm_runtime_mark_last_busy(up->dev);
1084         pm_runtime_put_autosuspend(up->dev);
1085
1086         return status;
1087 }
1088
1089 #endif /* CONFIG_CONSOLE_POLL */
1090
1091 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
1092
1093 static struct uart_omap_port *serial_omap_console_ports[4];
1094
1095 static struct uart_driver serial_omap_reg;
1096
1097 static void serial_omap_console_putchar(struct uart_port *port, int ch)
1098 {
1099         struct uart_omap_port *up = to_uart_omap_port(port);
1100
1101         wait_for_xmitr(up);
1102         serial_out(up, UART_TX, ch);
1103 }
1104
1105 static void
1106 serial_omap_console_write(struct console *co, const char *s,
1107                 unsigned int count)
1108 {
1109         struct uart_omap_port *up = serial_omap_console_ports[co->index];
1110         unsigned long flags;
1111         unsigned int ier;
1112         int locked = 1;
1113
1114         pm_runtime_get_sync(up->dev);
1115
1116         local_irq_save(flags);
1117         if (up->port.sysrq)
1118                 locked = 0;
1119         else if (oops_in_progress)
1120                 locked = spin_trylock(&up->port.lock);
1121         else
1122                 spin_lock(&up->port.lock);
1123
1124         /*
1125          * First save the IER then disable the interrupts
1126          */
1127         ier = serial_in(up, UART_IER);
1128         serial_out(up, UART_IER, 0);
1129
1130         uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1131
1132         /*
1133          * Finally, wait for transmitter to become empty
1134          * and restore the IER
1135          */
1136         wait_for_xmitr(up);
1137         serial_out(up, UART_IER, ier);
1138         /*
1139          * The receive handling will happen properly because the
1140          * receive ready bit will still be set; it is not cleared
1141          * on read.  However, modem control will not, we must
1142          * call it if we have saved something in the saved flags
1143          * while processing with interrupts off.
1144          */
1145         if (up->msr_saved_flags)
1146                 check_modem_status(up);
1147
1148         pm_runtime_mark_last_busy(up->dev);
1149         pm_runtime_put_autosuspend(up->dev);
1150         if (locked)
1151                 spin_unlock(&up->port.lock);
1152         local_irq_restore(flags);
1153 }
1154
1155 static int __init
1156 serial_omap_console_setup(struct console *co, char *options)
1157 {
1158         struct uart_omap_port *up;
1159         int baud = 115200;
1160         int bits = 8;
1161         int parity = 'n';
1162         int flow = 'n';
1163
1164         if (serial_omap_console_ports[co->index] == NULL)
1165                 return -ENODEV;
1166         up = serial_omap_console_ports[co->index];
1167
1168         if (options)
1169                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1170
1171         return uart_set_options(&up->port, co, baud, parity, bits, flow);
1172 }
1173
1174 static struct console serial_omap_console = {
1175         .name           = OMAP_SERIAL_NAME,
1176         .write          = serial_omap_console_write,
1177         .device         = uart_console_device,
1178         .setup          = serial_omap_console_setup,
1179         .flags          = CON_PRINTBUFFER,
1180         .index          = -1,
1181         .data           = &serial_omap_reg,
1182 };
1183
1184 static void serial_omap_add_console_port(struct uart_omap_port *up)
1185 {
1186         serial_omap_console_ports[up->port.line] = up;
1187 }
1188
1189 #define OMAP_CONSOLE    (&serial_omap_console)
1190
1191 #else
1192
1193 #define OMAP_CONSOLE    NULL
1194
1195 static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1196 {}
1197
1198 #endif
1199
1200 static struct uart_ops serial_omap_pops = {
1201         .tx_empty       = serial_omap_tx_empty,
1202         .set_mctrl      = serial_omap_set_mctrl,
1203         .get_mctrl      = serial_omap_get_mctrl,
1204         .stop_tx        = serial_omap_stop_tx,
1205         .start_tx       = serial_omap_start_tx,
1206         .stop_rx        = serial_omap_stop_rx,
1207         .enable_ms      = serial_omap_enable_ms,
1208         .break_ctl      = serial_omap_break_ctl,
1209         .startup        = serial_omap_startup,
1210         .shutdown       = serial_omap_shutdown,
1211         .set_termios    = serial_omap_set_termios,
1212         .pm             = serial_omap_pm,
1213         .set_wake       = serial_omap_set_wake,
1214         .type           = serial_omap_type,
1215         .release_port   = serial_omap_release_port,
1216         .request_port   = serial_omap_request_port,
1217         .config_port    = serial_omap_config_port,
1218         .verify_port    = serial_omap_verify_port,
1219 #ifdef CONFIG_CONSOLE_POLL
1220         .poll_put_char  = serial_omap_poll_put_char,
1221         .poll_get_char  = serial_omap_poll_get_char,
1222 #endif
1223 };
1224
1225 static struct uart_driver serial_omap_reg = {
1226         .owner          = THIS_MODULE,
1227         .driver_name    = "OMAP-SERIAL",
1228         .dev_name       = OMAP_SERIAL_NAME,
1229         .nr             = OMAP_MAX_HSUART_PORTS,
1230         .cons           = OMAP_CONSOLE,
1231 };
1232
1233 #ifdef CONFIG_PM_SLEEP
1234 static int serial_omap_suspend(struct device *dev)
1235 {
1236         struct uart_omap_port *up = dev_get_drvdata(dev);
1237
1238         uart_suspend_port(&serial_omap_reg, &up->port);
1239         flush_work(&up->qos_work);
1240
1241         return 0;
1242 }
1243
1244 static int serial_omap_resume(struct device *dev)
1245 {
1246         struct uart_omap_port *up = dev_get_drvdata(dev);
1247
1248         uart_resume_port(&serial_omap_reg, &up->port);
1249
1250         return 0;
1251 }
1252 #endif
1253
1254 static void __devinit omap_serial_fill_features_erratas(struct uart_omap_port *up)
1255 {
1256         u32 mvr, scheme;
1257         u16 revision, major, minor;
1258
1259         mvr = serial_in(up, UART_OMAP_MVER);
1260
1261         /* Check revision register scheme */
1262         scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
1263
1264         switch (scheme) {
1265         case 0: /* Legacy Scheme: OMAP2/3 */
1266                 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
1267                 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
1268                                         OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
1269                 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
1270                 break;
1271         case 1:
1272                 /* New Scheme: OMAP4+ */
1273                 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
1274                 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
1275                                         OMAP_UART_MVR_MAJ_SHIFT;
1276                 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
1277                 break;
1278         default:
1279                 dev_warn(up->dev,
1280                         "Unknown %s revision, defaulting to highest\n",
1281                         up->name);
1282                 /* highest possible revision */
1283                 major = 0xff;
1284                 minor = 0xff;
1285         }
1286
1287         /* normalize revision for the driver */
1288         revision = UART_BUILD_REVISION(major, minor);
1289
1290         switch (revision) {
1291         case OMAP_UART_REV_46:
1292                 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1293                                 UART_ERRATA_i291_DMA_FORCEIDLE);
1294                 break;
1295         case OMAP_UART_REV_52:
1296                 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1297                                 UART_ERRATA_i291_DMA_FORCEIDLE);
1298                 break;
1299         case OMAP_UART_REV_63:
1300                 up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
1301                 break;
1302         default:
1303                 break;
1304         }
1305 }
1306
1307 static __devinit struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
1308 {
1309         struct omap_uart_port_info *omap_up_info;
1310
1311         omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
1312         if (!omap_up_info)
1313                 return NULL; /* out of memory */
1314
1315         of_property_read_u32(dev->of_node, "clock-frequency",
1316                                          &omap_up_info->uartclk);
1317         return omap_up_info;
1318 }
1319
1320 static int __devinit serial_omap_probe(struct platform_device *pdev)
1321 {
1322         struct uart_omap_port   *up;
1323         struct resource         *mem, *irq;
1324         struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data;
1325         int ret;
1326
1327         if (pdev->dev.of_node)
1328                 omap_up_info = of_get_uart_port_info(&pdev->dev);
1329
1330         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1331         if (!mem) {
1332                 dev_err(&pdev->dev, "no mem resource?\n");
1333                 return -ENODEV;
1334         }
1335
1336         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1337         if (!irq) {
1338                 dev_err(&pdev->dev, "no irq resource?\n");
1339                 return -ENODEV;
1340         }
1341
1342         if (!devm_request_mem_region(&pdev->dev, mem->start, resource_size(mem),
1343                                 pdev->dev.driver->name)) {
1344                 dev_err(&pdev->dev, "memory region already claimed\n");
1345                 return -EBUSY;
1346         }
1347
1348         if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1349             omap_up_info->DTR_present) {
1350                 ret = gpio_request(omap_up_info->DTR_gpio, "omap-serial");
1351                 if (ret < 0)
1352                         return ret;
1353                 ret = gpio_direction_output(omap_up_info->DTR_gpio,
1354                                             omap_up_info->DTR_inverted);
1355                 if (ret < 0)
1356                         return ret;
1357         }
1358
1359         up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
1360         if (!up)
1361                 return -ENOMEM;
1362
1363         if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1364             omap_up_info->DTR_present) {
1365                 up->DTR_gpio = omap_up_info->DTR_gpio;
1366                 up->DTR_inverted = omap_up_info->DTR_inverted;
1367         } else
1368                 up->DTR_gpio = -EINVAL;
1369         up->DTR_active = 0;
1370
1371         up->dev = &pdev->dev;
1372         up->port.dev = &pdev->dev;
1373         up->port.type = PORT_OMAP;
1374         up->port.iotype = UPIO_MEM;
1375         up->port.irq = irq->start;
1376
1377         up->port.regshift = 2;
1378         up->port.fifosize = 64;
1379         up->port.ops = &serial_omap_pops;
1380
1381         if (pdev->dev.of_node)
1382                 up->port.line = of_alias_get_id(pdev->dev.of_node, "serial");
1383         else
1384                 up->port.line = pdev->id;
1385
1386         if (up->port.line < 0) {
1387                 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
1388                                                                 up->port.line);
1389                 ret = -ENODEV;
1390                 goto err_port_line;
1391         }
1392
1393         up->pins = devm_pinctrl_get_select_default(&pdev->dev);
1394         if (IS_ERR(up->pins)) {
1395                 dev_warn(&pdev->dev, "did not get pins for uart%i error: %li\n",
1396                          up->port.line, PTR_ERR(up->pins));
1397                 up->pins = NULL;
1398         }
1399
1400         sprintf(up->name, "OMAP UART%d", up->port.line);
1401         up->port.mapbase = mem->start;
1402         up->port.membase = devm_ioremap(&pdev->dev, mem->start,
1403                                                 resource_size(mem));
1404         if (!up->port.membase) {
1405                 dev_err(&pdev->dev, "can't ioremap UART\n");
1406                 ret = -ENOMEM;
1407                 goto err_ioremap;
1408         }
1409
1410         up->port.flags = omap_up_info->flags;
1411         up->port.uartclk = omap_up_info->uartclk;
1412         if (!up->port.uartclk) {
1413                 up->port.uartclk = DEFAULT_CLK_SPEED;
1414                 dev_warn(&pdev->dev, "No clock speed specified: using default:"
1415                                                 "%d\n", DEFAULT_CLK_SPEED);
1416         }
1417
1418         up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1419         up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1420         pm_qos_add_request(&up->pm_qos_request,
1421                 PM_QOS_CPU_DMA_LATENCY, up->latency);
1422         serial_omap_uart_wq = create_singlethread_workqueue(up->name);
1423         INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1424
1425         platform_set_drvdata(pdev, up);
1426         pm_runtime_enable(&pdev->dev);
1427         pm_runtime_use_autosuspend(&pdev->dev);
1428         pm_runtime_set_autosuspend_delay(&pdev->dev,
1429                         omap_up_info->autosuspend_timeout);
1430
1431         pm_runtime_irq_safe(&pdev->dev);
1432         pm_runtime_get_sync(&pdev->dev);
1433
1434         omap_serial_fill_features_erratas(up);
1435
1436         ui[up->port.line] = up;
1437         serial_omap_add_console_port(up);
1438
1439         ret = uart_add_one_port(&serial_omap_reg, &up->port);
1440         if (ret != 0)
1441                 goto err_add_port;
1442
1443         pm_runtime_mark_last_busy(up->dev);
1444         pm_runtime_put_autosuspend(up->dev);
1445         return 0;
1446
1447 err_add_port:
1448         pm_runtime_put(&pdev->dev);
1449         pm_runtime_disable(&pdev->dev);
1450 err_ioremap:
1451 err_port_line:
1452         dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n",
1453                                 pdev->id, __func__, ret);
1454         return ret;
1455 }
1456
1457 static int __devexit serial_omap_remove(struct platform_device *dev)
1458 {
1459         struct uart_omap_port *up = platform_get_drvdata(dev);
1460
1461         pm_runtime_put_sync(up->dev);
1462         pm_runtime_disable(up->dev);
1463         uart_remove_one_port(&serial_omap_reg, &up->port);
1464         pm_qos_remove_request(&up->pm_qos_request);
1465
1466         return 0;
1467 }
1468
1469 /*
1470  * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1471  * The access to uart register after MDR1 Access
1472  * causes UART to corrupt data.
1473  *
1474  * Need a delay =
1475  * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1476  * give 10 times as much
1477  */
1478 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1479 {
1480         u8 timeout = 255;
1481
1482         serial_out(up, UART_OMAP_MDR1, mdr1);
1483         udelay(2);
1484         serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1485                         UART_FCR_CLEAR_RCVR);
1486         /*
1487          * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1488          * TX_FIFO_E bit is 1.
1489          */
1490         while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1491                                 (UART_LSR_THRE | UART_LSR_DR))) {
1492                 timeout--;
1493                 if (!timeout) {
1494                         /* Should *never* happen. we warn and carry on */
1495                         dev_crit(up->dev, "Errata i202: timedout %x\n",
1496                                                 serial_in(up, UART_LSR));
1497                         break;
1498                 }
1499                 udelay(1);
1500         }
1501 }
1502
1503 #ifdef CONFIG_PM_RUNTIME
1504 static void serial_omap_restore_context(struct uart_omap_port *up)
1505 {
1506         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1507                 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1508         else
1509                 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1510
1511         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1512         serial_out(up, UART_EFR, UART_EFR_ECB);
1513         serial_out(up, UART_LCR, 0x0); /* Operational mode */
1514         serial_out(up, UART_IER, 0x0);
1515         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1516         serial_out(up, UART_DLL, up->dll);
1517         serial_out(up, UART_DLM, up->dlh);
1518         serial_out(up, UART_LCR, 0x0); /* Operational mode */
1519         serial_out(up, UART_IER, up->ier);
1520         serial_out(up, UART_FCR, up->fcr);
1521         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1522         serial_out(up, UART_MCR, up->mcr);
1523         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1524         serial_out(up, UART_OMAP_SCR, up->scr);
1525         serial_out(up, UART_EFR, up->efr);
1526         serial_out(up, UART_LCR, up->lcr);
1527         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1528                 serial_omap_mdr1_errataset(up, up->mdr1);
1529         else
1530                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1531 }
1532
1533 static int serial_omap_runtime_suspend(struct device *dev)
1534 {
1535         struct uart_omap_port *up = dev_get_drvdata(dev);
1536         struct omap_uart_port_info *pdata = dev->platform_data;
1537
1538         if (!up)
1539                 return -EINVAL;
1540
1541         if (!pdata)
1542                 return 0;
1543
1544         up->context_loss_cnt = serial_omap_get_context_loss_count(up);
1545
1546         if (device_may_wakeup(dev)) {
1547                 if (!up->wakeups_enabled) {
1548                         serial_omap_enable_wakeup(up, true);
1549                         up->wakeups_enabled = true;
1550                 }
1551         } else {
1552                 if (up->wakeups_enabled) {
1553                         serial_omap_enable_wakeup(up, false);
1554                         up->wakeups_enabled = false;
1555                 }
1556         }
1557
1558         up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1559         schedule_work(&up->qos_work);
1560
1561         return 0;
1562 }
1563
1564 static int serial_omap_runtime_resume(struct device *dev)
1565 {
1566         struct uart_omap_port *up = dev_get_drvdata(dev);
1567
1568         u32 loss_cnt = serial_omap_get_context_loss_count(up);
1569
1570         if (up->context_loss_cnt != loss_cnt)
1571                 serial_omap_restore_context(up);
1572
1573         up->latency = up->calc_latency;
1574         schedule_work(&up->qos_work);
1575
1576         return 0;
1577 }
1578 #endif
1579
1580 static const struct dev_pm_ops serial_omap_dev_pm_ops = {
1581         SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
1582         SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
1583                                 serial_omap_runtime_resume, NULL)
1584 };
1585
1586 #if defined(CONFIG_OF)
1587 static const struct of_device_id omap_serial_of_match[] = {
1588         { .compatible = "ti,omap2-uart" },
1589         { .compatible = "ti,omap3-uart" },
1590         { .compatible = "ti,omap4-uart" },
1591         {},
1592 };
1593 MODULE_DEVICE_TABLE(of, omap_serial_of_match);
1594 #endif
1595
1596 static struct platform_driver serial_omap_driver = {
1597         .probe          = serial_omap_probe,
1598         .remove         = __devexit_p(serial_omap_remove),
1599         .driver         = {
1600                 .name   = DRIVER_NAME,
1601                 .pm     = &serial_omap_dev_pm_ops,
1602                 .of_match_table = of_match_ptr(omap_serial_of_match),
1603         },
1604 };
1605
1606 static int __init serial_omap_init(void)
1607 {
1608         int ret;
1609
1610         ret = uart_register_driver(&serial_omap_reg);
1611         if (ret != 0)
1612                 return ret;
1613         ret = platform_driver_register(&serial_omap_driver);
1614         if (ret != 0)
1615                 uart_unregister_driver(&serial_omap_reg);
1616         return ret;
1617 }
1618
1619 static void __exit serial_omap_exit(void)
1620 {
1621         platform_driver_unregister(&serial_omap_driver);
1622         uart_unregister_driver(&serial_omap_reg);
1623 }
1624
1625 module_init(serial_omap_init);
1626 module_exit(serial_omap_exit);
1627
1628 MODULE_DESCRIPTION("OMAP High Speed UART driver");
1629 MODULE_LICENSE("GPL");
1630 MODULE_AUTHOR("Texas Instruments Inc");