drivers/tty/serial/omap-serial.c

   1 /*
   2  * Driver for OMAP-UART controller.
   3  * Based on drivers/serial/8250.c
   4  *
   5  * Copyright (C) 2010 Texas Instruments.
   6  *
   7  * Authors:
   8  *      Govindraj R     <govindraj.raja@ti.com>
   9  *      Thara Gopinath  <thara@ti.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * Note: This driver is made separate from 8250 driver as we cannot
  17  * over load 8250 driver with omap platform specific configuration for
  18  * features like DMA, it makes easier to implement features like DMA and
  19  * hardware flow control and software flow control configuration with
  20  * this driver as required for the omap-platform.
  21  */
  22
  23 #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  24 #define SUPPORT_SYSRQ
  25 #endif
  26
  27 #include <linux/module.h>
  28 #include <linux/init.h>
  29 #include <linux/console.h>
  30 #include <linux/serial_reg.h>
  31 #include <linux/delay.h>
  32 #include <linux/slab.h>
  33 #include <linux/tty.h>
  34 #include <linux/tty_flip.h>
  35 #include <linux/platform_device.h>
  36 #include <linux/io.h>
  37 #include <linux/clk.h>
  38 #include <linux/serial_core.h>
  39 #include <linux/irq.h>
  40 #include <linux/pm_runtime.h>
  41 #include <linux/of.h>
  42 #include <linux/of_irq.h>
  43 #include <linux/gpio.h>
  44 #include <linux/of_gpio.h>
  45 #include <linux/platform_data/serial-omap.h>
  46
  47 #include <dt-bindings/gpio/gpio.h>
  48
  49 #define OMAP_MAX_HSUART_PORTS   6
  50
  51 #define UART_BUILD_REVISION(x, y)       (((x) << 8) | (y))
  52
  53 #define OMAP_UART_REV_42 0x0402
  54 #define OMAP_UART_REV_46 0x0406
  55 #define OMAP_UART_REV_52 0x0502
  56 #define OMAP_UART_REV_63 0x0603
  57
  58 #define OMAP_UART_TX_WAKEUP_EN          BIT(7)
  59
  60 /* Feature flags */
  61 #define OMAP_UART_WER_HAS_TX_WAKEUP     BIT(0)
  62
  63 #define UART_ERRATA_i202_MDR1_ACCESS    BIT(0)
  64 #define UART_ERRATA_i291_DMA_FORCEIDLE  BIT(1)
  65
  66 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
  67
  68 /* SCR register bitmasks */
  69 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK               (1 << 7)
  70 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK               (1 << 6)
  71 #define OMAP_UART_SCR_TX_EMPTY                  (1 << 3)
  72
  73 /* FCR register bitmasks */
  74 #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK                 (0x3 << 6)
  75 #define OMAP_UART_FCR_TX_FIFO_TRIG_MASK                 (0x3 << 4)
  76
  77 /* MVR register bitmasks */
  78 #define OMAP_UART_MVR_SCHEME_SHIFT      30
  79
  80 #define OMAP_UART_LEGACY_MVR_MAJ_MASK   0xf0
  81 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT  4
  82 #define OMAP_UART_LEGACY_MVR_MIN_MASK   0x0f
  83
  84 #define OMAP_UART_MVR_MAJ_MASK          0x700
  85 #define OMAP_UART_MVR_MAJ_SHIFT         8
  86 #define OMAP_UART_MVR_MIN_MASK          0x3f
  87
  88 #define OMAP_UART_DMA_CH_FREE   -1
  89
  90 #define MSR_SAVE_FLAGS          UART_MSR_ANY_DELTA
  91 #define OMAP_MODE13X_SPEED      230400
  92
  93 /* WER = 0x7F
  94  * Enable module level wakeup in WER reg
  95  */
  96 #define OMAP_UART_WER_MOD_WKUP  0X7F
  97
  98 /* Enable XON/XOFF flow control on output */
  99 #define OMAP_UART_SW_TX         0x08
 100
 101 /* Enable XON/XOFF flow control on input */
 102 #define OMAP_UART_SW_RX         0x02
 103
 104 #define OMAP_UART_SW_CLR        0xF0
 105
 106 #define OMAP_UART_TCR_TRIG      0x0F
 107
 108 struct uart_omap_dma {
 109         u8                      uart_dma_tx;
 110         u8                      uart_dma_rx;
 111         int                     rx_dma_channel;
 112         int                     tx_dma_channel;
 113         dma_addr_t              rx_buf_dma_phys;
 114         dma_addr_t              tx_buf_dma_phys;
 115         unsigned int            uart_base;
 116         /*
 117          * Buffer for rx dma.It is not required for tx because the buffer
 118          * comes from port structure.
 119          */
 120         unsigned char           *rx_buf;
 121         unsigned int            prev_rx_dma_pos;
 122         int                     tx_buf_size;
 123         int                     tx_dma_used;
 124         int                     rx_dma_used;
 125         spinlock_t              tx_lock;
 126         spinlock_t              rx_lock;
 127         /* timer to poll activity on rx dma */
 128         struct timer_list       rx_timer;
 129         unsigned int            rx_buf_size;
 130         unsigned int            rx_poll_rate;
 131         unsigned int            rx_timeout;
 132 };
 133
 134 struct uart_omap_port {
 135         struct uart_port        port;
 136         struct uart_omap_dma    uart_dma;
 137         struct device           *dev;
 138         int                     wakeirq;
 139
 140         unsigned char           ier;
 141         unsigned char           lcr;
 142         unsigned char           mcr;
 143         unsigned char           fcr;
 144         unsigned char           efr;
 145         unsigned char           dll;
 146         unsigned char           dlh;
 147         unsigned char           mdr1;
 148         unsigned char           scr;
 149         unsigned char           wer;
 150
 151         int                     use_dma;
 152         /*
 153          * Some bits in registers are cleared on a read, so they must
 154          * be saved whenever the register is read but the bits will not
 155          * be immediately processed.
 156          */
 157         unsigned int            lsr_break_flag;
 158         unsigned char           msr_saved_flags;
 159         char                    name[20];
 160         unsigned long           port_activity;
 161         int                     context_loss_cnt;
 162         u32                     errata;
 163         u8                      wakeups_enabled;
 164         u32                     features;
 165
 166         int                     DTR_gpio;
 167         int                     DTR_inverted;
 168         int                     DTR_active;
 169
 170         struct serial_rs485     rs485;
 171         int                     rts_gpio;
 172
 173         struct pm_qos_request   pm_qos_request;
 174         u32                     latency;
 175         u32                     calc_latency;
 176         struct work_struct      qos_work;
 177         bool                    is_suspending;
 178 };
 179
 180 #define to_uart_omap_port(p)    ((container_of((p), struct uart_omap_port, port)))
 181
 182 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
 183
 184 /* Forward declaration of functions */
 185 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
 186
 187 static struct workqueue_struct *serial_omap_uart_wq;
 188
 189 static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
 190 {
 191         offset <<= up->port.regshift;
 192         return readw(up->port.membase + offset);
 193 }
 194
 195 static inline void serial_out(struct uart_omap_port *up, int offset, int value)
 196 {
 197         offset <<= up->port.regshift;
 198         writew(value, up->port.membase + offset);
 199 }
 200
 201 static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
 202 {
 203         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
 204         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
 205                        UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
 206         serial_out(up, UART_FCR, 0);
 207 }
 208
 209 static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
 210 {
 211         struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
 212
 213         if (!pdata || !pdata->get_context_loss_count)
 214                 return -EINVAL;
 215
 216         return pdata->get_context_loss_count(up->dev);
 217 }
 218
 219 static inline void serial_omap_enable_wakeirq(struct uart_omap_port *up,
 220                                        bool enable)
 221 {
 222         if (!up->wakeirq)
 223                 return;
 224
 225         if (enable)
 226                 enable_irq(up->wakeirq);
 227         else
 228                 disable_irq(up->wakeirq);
 229 }
 230
 231 static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
 232 {
 233         struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
 234
 235         serial_omap_enable_wakeirq(up, enable);
 236         if (!pdata || !pdata->enable_wakeup)
 237                 return;
 238
 239         pdata->enable_wakeup(up->dev, enable);
 240 }
 241
 242 /*
 243  * serial_omap_baud_is_mode16 - check if baud rate is MODE16X
 244  * @port: uart port info
 245  * @baud: baudrate for which mode needs to be determined
 246  *
 247  * Returns true if baud rate is MODE16X and false if MODE13X
 248  * Original table in OMAP TRM named "UART Mode Baud Rates, Divisor Values,
 249  * and Error Rates" determines modes not for all common baud rates.
 250  * E.g. for 1000000 baud rate mode must be 16x, but according to that
 251  * table it's determined as 13x.
 252  */
 253 static bool
 254 serial_omap_baud_is_mode16(struct uart_port *port, unsigned int baud)
 255 {
 256         unsigned int n13 = port->uartclk / (13 * baud);
 257         unsigned int n16 = port->uartclk / (16 * baud);
 258         int baudAbsDiff13 = baud - (port->uartclk / (13 * n13));
 259         int baudAbsDiff16 = baud - (port->uartclk / (16 * n16));
 260         if(baudAbsDiff13 < 0)
 261                 baudAbsDiff13 = -baudAbsDiff13;
 262         if(baudAbsDiff16 < 0)
 263                 baudAbsDiff16 = -baudAbsDiff16;
 264
 265         return (baudAbsDiff13 >= baudAbsDiff16);
 266 }
 267
 268 /*
 269  * serial_omap_get_divisor - calculate divisor value
 270  * @port: uart port info
 271  * @baud: baudrate for which divisor needs to be calculated.
 272  */
 273 static unsigned int
 274 serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
 275 {
 276         unsigned int mode;
 277
 278         if (!serial_omap_baud_is_mode16(port, baud))
 279                 mode = 13;
 280         else
 281                 mode = 16;
 282         return port->uartclk/(mode * baud);
 283 }
 284
 285 static void serial_omap_enable_ms(struct uart_port *port)
 286 {
 287         struct uart_omap_port *up = to_uart_omap_port(port);
 288
 289         dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
 290
 291         pm_runtime_get_sync(up->dev);
 292         up->ier |= UART_IER_MSI;
 293         serial_out(up, UART_IER, up->ier);
 294         pm_runtime_mark_last_busy(up->dev);
 295         pm_runtime_put_autosuspend(up->dev);
 296 }
 297
 298 static void serial_omap_stop_tx(struct uart_port *port)
 299 {
 300         struct uart_omap_port *up = to_uart_omap_port(port);
 301         int res;
 302
 303         pm_runtime_get_sync(up->dev);
 304
 305         /* Handle RS-485 */
 306         if (up->rs485.flags & SER_RS485_ENABLED) {
 307                 if (up->scr & OMAP_UART_SCR_TX_EMPTY) {
 308                         /* THR interrupt is fired when both TX FIFO and TX
 309                          * shift register are empty. This means there's nothing
 310                          * left to transmit now, so make sure the THR interrupt
 311                          * is fired when TX FIFO is below the trigger level,
 312                          * disable THR interrupts and toggle the RS-485 GPIO
 313                          * data direction pin if needed.
 314                          */
 315                         up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
 316                         serial_out(up, UART_OMAP_SCR, up->scr);
 317                         res = (up->rs485.flags & SER_RS485_RTS_AFTER_SEND) ? 1 : 0;
 318                         if (gpio_get_value(up->rts_gpio) != res) {
 319                                 if (up->rs485.delay_rts_after_send > 0) {
 320                                         mdelay(up->rs485.delay_rts_after_send);
 321                                 }
 322                                 gpio_set_value(up->rts_gpio, res);
 323                         }
 324                 } else {
 325                         /* We're asked to stop, but there's still stuff in the
 326                          * UART FIFO, so make sure the THR interrupt is fired
 327                          * when both TX FIFO and TX shift register are empty.
 328                          * The next THR interrupt (if no transmission is started
 329                          * in the meantime) will indicate the end of a
 330                          * transmission. Therefore we _don't_ disable THR
 331                          * interrupts in this situation.
 332                          */
 333                         up->scr |= OMAP_UART_SCR_TX_EMPTY;
 334                         serial_out(up, UART_OMAP_SCR, up->scr);
 335                         return;
 336                 }
 337         }
 338
 339         if (up->ier & UART_IER_THRI) {
 340                 up->ier &= ~UART_IER_THRI;
 341                 serial_out(up, UART_IER, up->ier);
 342         }
 343
 344         if ((up->rs485.flags & SER_RS485_ENABLED) &&
 345             !(up->rs485.flags & SER_RS485_RX_DURING_TX)) {
 346                 up->ier = UART_IER_RLSI | UART_IER_RDI;
 347                 serial_out(up, UART_IER, up->ier);
 348         }
 349
 350         pm_runtime_mark_last_busy(up->dev);
 351         pm_runtime_put_autosuspend(up->dev);
 352 }
 353
 354 static void serial_omap_stop_rx(struct uart_port *port)
 355 {
 356         struct uart_omap_port *up = to_uart_omap_port(port);
 357
 358         pm_runtime_get_sync(up->dev);
 359         up->ier &= ~UART_IER_RLSI;
 360         up->port.read_status_mask &= ~UART_LSR_DR;
 361         serial_out(up, UART_IER, up->ier);
 362         pm_runtime_mark_last_busy(up->dev);
 363         pm_runtime_put_autosuspend(up->dev);
 364 }
 365
 366 static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
 367 {
 368         struct circ_buf *xmit = &up->port.state->xmit;
 369         int count;
 370
 371         if (up->port.x_char) {
 372                 serial_out(up, UART_TX, up->port.x_char);
 373                 up->port.icount.tx++;
 374                 up->port.x_char = 0;
 375                 return;
 376         }
 377         if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
 378                 serial_omap_stop_tx(&up->port);
 379                 return;
 380         }
 381         count = up->port.fifosize / 4;
 382         do {
 383                 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
 384                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 385                 up->port.icount.tx++;
 386                 if (uart_circ_empty(xmit))
 387                         break;
 388         } while (--count > 0);
 389
 390         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
 391                 spin_unlock(&up->port.lock);
 392                 uart_write_wakeup(&up->port);
 393                 spin_lock(&up->port.lock);
 394         }
 395
 396         if (uart_circ_empty(xmit))
 397                 serial_omap_stop_tx(&up->port);
 398 }
 399
 400 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
 401 {
 402         if (!(up->ier & UART_IER_THRI)) {
 403                 up->ier |= UART_IER_THRI;
 404                 serial_out(up, UART_IER, up->ier);
 405         }
 406 }
 407
 408 static void serial_omap_start_tx(struct uart_port *port)
 409 {
 410         struct uart_omap_port *up = to_uart_omap_port(port);
 411         int res;
 412
 413         pm_runtime_get_sync(up->dev);
 414
 415         /* Handle RS-485 */
 416         if (up->rs485.flags & SER_RS485_ENABLED) {
 417                 /* Fire THR interrupts when FIFO is below trigger level */
 418                 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
 419                 serial_out(up, UART_OMAP_SCR, up->scr);
 420
 421                 /* if rts not already enabled */
 422                 res = (up->rs485.flags & SER_RS485_RTS_ON_SEND) ? 1 : 0;
 423                 if (gpio_get_value(up->rts_gpio) != res) {
 424                         gpio_set_value(up->rts_gpio, res);
 425                         if (up->rs485.delay_rts_before_send > 0) {
 426                                 mdelay(up->rs485.delay_rts_before_send);
 427                         }
 428                 }
 429         }
 430
 431         if ((up->rs485.flags & SER_RS485_ENABLED) &&
 432             !(up->rs485.flags & SER_RS485_RX_DURING_TX))
 433                 serial_omap_stop_rx(port);
 434
 435         serial_omap_enable_ier_thri(up);
 436         pm_runtime_mark_last_busy(up->dev);
 437         pm_runtime_put_autosuspend(up->dev);
 438 }
 439
 440 static void serial_omap_throttle(struct uart_port *port)
 441 {
 442         struct uart_omap_port *up = to_uart_omap_port(port);
 443         unsigned long flags;
 444
 445         pm_runtime_get_sync(up->dev);
 446         spin_lock_irqsave(&up->port.lock, flags);
 447         up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
 448         serial_out(up, UART_IER, up->ier);
 449         spin_unlock_irqrestore(&up->port.lock, flags);
 450         pm_runtime_mark_last_busy(up->dev);
 451         pm_runtime_put_autosuspend(up->dev);
 452 }
 453
 454 static void serial_omap_unthrottle(struct uart_port *port)
 455 {
 456         struct uart_omap_port *up = to_uart_omap_port(port);
 457         unsigned long flags;
 458
 459         pm_runtime_get_sync(up->dev);
 460         spin_lock_irqsave(&up->port.lock, flags);
 461         up->ier |= UART_IER_RLSI | UART_IER_RDI;
 462         serial_out(up, UART_IER, up->ier);
 463         spin_unlock_irqrestore(&up->port.lock, flags);
 464         pm_runtime_mark_last_busy(up->dev);
 465         pm_runtime_put_autosuspend(up->dev);
 466 }
 467
 468 static unsigned int check_modem_status(struct uart_omap_port *up)
 469 {
 470         unsigned int status;
 471
 472         status = serial_in(up, UART_MSR);
 473         status |= up->msr_saved_flags;
 474         up->msr_saved_flags = 0;
 475         if ((status & UART_MSR_ANY_DELTA) == 0)
 476                 return status;
 477
 478         if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
 479             up->port.state != NULL) {
 480                 if (status & UART_MSR_TERI)
 481                         up->port.icount.rng++;
 482                 if (status & UART_MSR_DDSR)
 483                         up->port.icount.dsr++;
 484                 if (status & UART_MSR_DDCD)
 485                         uart_handle_dcd_change
 486                                 (&up->port, status & UART_MSR_DCD);
 487                 if (status & UART_MSR_DCTS)
 488                         uart_handle_cts_change
 489                                 (&up->port, status & UART_MSR_CTS);
 490                 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
 491         }
 492
 493         return status;
 494 }
 495
 496 static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)
 497 {
 498         unsigned int flag;
 499         unsigned char ch = 0;
 500
 501         if (likely(lsr & UART_LSR_DR))
 502                 ch = serial_in(up, UART_RX);
 503
 504         up->port.icount.rx++;
 505         flag = TTY_NORMAL;
 506
 507         if (lsr & UART_LSR_BI) {
 508                 flag = TTY_BREAK;
 509                 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
 510                 up->port.icount.brk++;
 511                 /*
 512                  * We do the SysRQ and SAK checking
 513                  * here because otherwise the break
 514                  * may get masked by ignore_status_mask
 515                  * or read_status_mask.
 516                  */
 517                 if (uart_handle_break(&up->port))
 518                         return;
 519
 520         }
 521
 522         if (lsr & UART_LSR_PE) {
 523                 flag = TTY_PARITY;
 524                 up->port.icount.parity++;
 525         }
 526
 527         if (lsr & UART_LSR_FE) {
 528                 flag = TTY_FRAME;
 529                 up->port.icount.frame++;
 530         }
 531
 532         if (lsr & UART_LSR_OE)
 533                 up->port.icount.overrun++;
 534
 535 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
 536         if (up->port.line == up->port.cons->index) {
 537                 /* Recover the break flag from console xmit */
 538                 lsr |= up->lsr_break_flag;
 539         }
 540 #endif
 541         uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);
 542 }
 543
 544 static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
 545 {
 546         unsigned char ch = 0;
 547         unsigned int flag;
 548
 549         if (!(lsr & UART_LSR_DR))
 550                 return;
 551
 552         ch = serial_in(up, UART_RX);
 553         flag = TTY_NORMAL;
 554         up->port.icount.rx++;
 555
 556         if (uart_handle_sysrq_char(&up->port, ch))
 557                 return;
 558
 559         uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
 560 }
 561
 562 /**
 563  * serial_omap_irq() - This handles the interrupt from one port
 564  * @irq: uart port irq number
 565  * @dev_id: uart port info
 566  */
 567 static irqreturn_t serial_omap_irq(int irq, void *dev_id)
 568 {
 569         struct uart_omap_port *up = dev_id;
 570         unsigned int iir, lsr;
 571         unsigned int type;
 572         irqreturn_t ret = IRQ_NONE;
 573         int max_count = 256;
 574
 575         spin_lock(&up->port.lock);
 576         pm_runtime_get_sync(up->dev);
 577
 578         do {
 579                 iir = serial_in(up, UART_IIR);
 580                 if (iir & UART_IIR_NO_INT)
 581                         break;
 582
 583                 ret = IRQ_HANDLED;
 584                 lsr = serial_in(up, UART_LSR);
 585
 586                 /* extract IRQ type from IIR register */
 587                 type = iir & 0x3e;
 588
 589                 switch (type) {
 590                 case UART_IIR_MSI:
 591                         check_modem_status(up);
 592                         break;
 593                 case UART_IIR_THRI:
 594                         transmit_chars(up, lsr);
 595                         break;
 596                 case UART_IIR_RX_TIMEOUT:
 597                         /* FALLTHROUGH */
 598                 case UART_IIR_RDI:
 599                         serial_omap_rdi(up, lsr);
 600                         break;
 601                 case UART_IIR_RLSI:
 602                         serial_omap_rlsi(up, lsr);
 603                         break;
 604                 case UART_IIR_CTS_RTS_DSR:
 605                         /* simply try again */
 606                         break;
 607                 case UART_IIR_XOFF:
 608                         /* FALLTHROUGH */
 609                 default:
 610                         break;
 611                 }
 612         } while (!(iir & UART_IIR_NO_INT) && max_count--);
 613
 614         spin_unlock(&up->port.lock);
 615
 616         tty_flip_buffer_push(&up->port.state->port);
 617
 618         pm_runtime_mark_last_busy(up->dev);
 619         pm_runtime_put_autosuspend(up->dev);
 620         up->port_activity = jiffies;
 621
 622         return ret;
 623 }
 624
 625 static unsigned int serial_omap_tx_empty(struct uart_port *port)
 626 {
 627         struct uart_omap_port *up = to_uart_omap_port(port);
 628         unsigned long flags = 0;
 629         unsigned int ret = 0;
 630
 631         pm_runtime_get_sync(up->dev);
 632         dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
 633         spin_lock_irqsave(&up->port.lock, flags);
 634         ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
 635         spin_unlock_irqrestore(&up->port.lock, flags);
 636         pm_runtime_mark_last_busy(up->dev);
 637         pm_runtime_put_autosuspend(up->dev);
 638         return ret;
 639 }
 640
 641 static unsigned int serial_omap_get_mctrl(struct uart_port *port)
 642 {
 643         struct uart_omap_port *up = to_uart_omap_port(port);
 644         unsigned int status;
 645         unsigned int ret = 0;
 646
 647         pm_runtime_get_sync(up->dev);
 648         status = check_modem_status(up);
 649         pm_runtime_mark_last_busy(up->dev);
 650         pm_runtime_put_autosuspend(up->dev);
 651
 652         dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
 653
 654         if (status & UART_MSR_DCD)
 655                 ret |= TIOCM_CAR;
 656         if (status & UART_MSR_RI)
 657                 ret |= TIOCM_RNG;
 658         if (status & UART_MSR_DSR)
 659                 ret |= TIOCM_DSR;
 660         if (status & UART_MSR_CTS)
 661                 ret |= TIOCM_CTS;
 662         return ret;
 663 }
 664
 665 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
 666 {
 667         struct uart_omap_port *up = to_uart_omap_port(port);
 668         unsigned char mcr = 0, old_mcr;
 669
 670         dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
 671         if (mctrl & TIOCM_RTS)
 672                 mcr |= UART_MCR_RTS;
 673         if (mctrl & TIOCM_DTR)
 674                 mcr |= UART_MCR_DTR;
 675         if (mctrl & TIOCM_OUT1)
 676                 mcr |= UART_MCR_OUT1;
 677         if (mctrl & TIOCM_OUT2)
 678                 mcr |= UART_MCR_OUT2;
 679         if (mctrl & TIOCM_LOOP)
 680                 mcr |= UART_MCR_LOOP;
 681
 682         pm_runtime_get_sync(up->dev);
 683         old_mcr = serial_in(up, UART_MCR);
 684         old_mcr &= ~(UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_OUT1 |
 685                      UART_MCR_DTR | UART_MCR_RTS);
 686         up->mcr = old_mcr | mcr;
 687         serial_out(up, UART_MCR, up->mcr);
 688         pm_runtime_mark_last_busy(up->dev);
 689         pm_runtime_put_autosuspend(up->dev);
 690
 691         if (gpio_is_valid(up->DTR_gpio) &&
 692             !!(mctrl & TIOCM_DTR) != up->DTR_active) {
 693                 up->DTR_active = !up->DTR_active;
 694                 if (gpio_cansleep(up->DTR_gpio))
 695                         schedule_work(&up->qos_work);
 696                 else
 697                         gpio_set_value(up->DTR_gpio,
 698                                        up->DTR_active != up->DTR_inverted);
 699         }
 700 }
 701
 702 static void serial_omap_break_ctl(struct uart_port *port, int break_state)
 703 {
 704         struct uart_omap_port *up = to_uart_omap_port(port);
 705         unsigned long flags = 0;
 706
 707         dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
 708         pm_runtime_get_sync(up->dev);
 709         spin_lock_irqsave(&up->port.lock, flags);
 710         if (break_state == -1)
 711                 up->lcr |= UART_LCR_SBC;
 712         else
 713                 up->lcr &= ~UART_LCR_SBC;
 714         serial_out(up, UART_LCR, up->lcr);
 715         spin_unlock_irqrestore(&up->port.lock, flags);
 716         pm_runtime_mark_last_busy(up->dev);
 717         pm_runtime_put_autosuspend(up->dev);
 718 }
 719
 720 static int serial_omap_startup(struct uart_port *port)
 721 {
 722         struct uart_omap_port *up = to_uart_omap_port(port);
 723         unsigned long flags = 0;
 724         int retval;
 725
 726         /*
 727          * Allocate the IRQ
 728          */
 729         retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
 730                                 up->name, up);
 731         if (retval)
 732                 return retval;
 733
 734         /* Optional wake-up IRQ */
 735         if (up->wakeirq) {
 736                 retval = request_irq(up->wakeirq, serial_omap_irq,
 737                                      up->port.irqflags, up->name, up);
 738                 if (retval) {
 739                         free_irq(up->port.irq, up);
 740                         return retval;
 741                 }
 742                 disable_irq(up->wakeirq);
 743         } else {
 744                 dev_info(up->port.dev, "no wakeirq for uart%d\n",
 745                          up->port.line);
 746         }
 747
 748         dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
 749
 750         pm_runtime_get_sync(up->dev);
 751         /*
 752          * Clear the FIFO buffers and disable them.
 753          * (they will be reenabled in set_termios())
 754          */
 755         serial_omap_clear_fifos(up);
 756         /* For Hardware flow control */
 757         serial_out(up, UART_MCR, UART_MCR_RTS);
 758
 759         /*
 760          * Clear the interrupt registers.
 761          */
 762         (void) serial_in(up, UART_LSR);
 763         if (serial_in(up, UART_LSR) & UART_LSR_DR)
 764                 (void) serial_in(up, UART_RX);
 765         (void) serial_in(up, UART_IIR);
 766         (void) serial_in(up, UART_MSR);
 767
 768         /*
 769          * Now, initialize the UART
 770          */
 771         serial_out(up, UART_LCR, UART_LCR_WLEN8);
 772         spin_lock_irqsave(&up->port.lock, flags);
 773         /*
 774          * Most PC uarts need OUT2 raised to enable interrupts.
 775          */
 776         up->port.mctrl |= TIOCM_OUT2;
 777         serial_omap_set_mctrl(&up->port, up->port.mctrl);
 778         spin_unlock_irqrestore(&up->port.lock, flags);
 779
 780         up->msr_saved_flags = 0;
 781         /*
 782          * Finally, enable interrupts. Note: Modem status interrupts
 783          * are set via set_termios(), which will be occurring imminently
 784          * anyway, so we don't enable them here.
 785          */
 786         up->ier = UART_IER_RLSI | UART_IER_RDI;
 787         serial_out(up, UART_IER, up->ier);
 788
 789         /* Enable module level wake up */
 790         up->wer = OMAP_UART_WER_MOD_WKUP;
 791         if (up->features & OMAP_UART_WER_HAS_TX_WAKEUP)
 792                 up->wer |= OMAP_UART_TX_WAKEUP_EN;
 793
 794         serial_out(up, UART_OMAP_WER, up->wer);
 795
 796         pm_runtime_mark_last_busy(up->dev);
 797         pm_runtime_put_autosuspend(up->dev);
 798         up->port_activity = jiffies;
 799         return 0;
 800 }
 801
 802 static void serial_omap_shutdown(struct uart_port *port)
 803 {
 804         struct uart_omap_port *up = to_uart_omap_port(port);
 805         unsigned long flags = 0;
 806
 807         dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
 808
 809         pm_runtime_get_sync(up->dev);
 810         /*
 811          * Disable interrupts from this port
 812          */
 813         up->ier = 0;
 814         serial_out(up, UART_IER, 0);
 815
 816         spin_lock_irqsave(&up->port.lock, flags);
 817         up->port.mctrl &= ~TIOCM_OUT2;
 818         serial_omap_set_mctrl(&up->port, up->port.mctrl);
 819         spin_unlock_irqrestore(&up->port.lock, flags);
 820
 821         /*
 822          * Disable break condition and FIFOs
 823          */
 824         serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
 825         serial_omap_clear_fifos(up);
 826
 827         /*
 828          * Read data port to reset things, and then free the irq
 829          */
 830         if (serial_in(up, UART_LSR) & UART_LSR_DR)
 831                 (void) serial_in(up, UART_RX);
 832
 833         pm_runtime_mark_last_busy(up->dev);
 834         pm_runtime_put_autosuspend(up->dev);
 835         free_irq(up->port.irq, up);
 836         if (up->wakeirq)
 837                 free_irq(up->wakeirq, up);
 838 }
 839
 840 static void serial_omap_uart_qos_work(struct work_struct *work)
 841 {
 842         struct uart_omap_port *up = container_of(work, struct uart_omap_port,
 843                                                 qos_work);
 844
 845         pm_qos_update_request(&up->pm_qos_request, up->latency);
 846         if (gpio_is_valid(up->DTR_gpio))
 847                 gpio_set_value_cansleep(up->DTR_gpio,
 848                                         up->DTR_active != up->DTR_inverted);
 849 }
 850
 851 static void
 852 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
 853                         struct ktermios *old)
 854 {
 855         struct uart_omap_port *up = to_uart_omap_port(port);
 856         unsigned char cval = 0;
 857         unsigned long flags = 0;
 858         unsigned int baud, quot;
 859
 860         switch (termios->c_cflag & CSIZE) {
 861         case CS5:
 862                 cval = UART_LCR_WLEN5;
 863                 break;
 864         case CS6:
 865                 cval = UART_LCR_WLEN6;
 866                 break;
 867         case CS7:
 868                 cval = UART_LCR_WLEN7;
 869                 break;
 870         default:
 871         case CS8:
 872                 cval = UART_LCR_WLEN8;
 873                 break;
 874         }
 875
 876         if (termios->c_cflag & CSTOPB)
 877                 cval |= UART_LCR_STOP;
 878         if (termios->c_cflag & PARENB)
 879                 cval |= UART_LCR_PARITY;
 880         if (!(termios->c_cflag & PARODD))
 881                 cval |= UART_LCR_EPAR;
 882         if (termios->c_cflag & CMSPAR)
 883                 cval |= UART_LCR_SPAR;
 884
 885         /*
 886          * Ask the core to calculate the divisor for us.
 887          */
 888
 889         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
 890         quot = serial_omap_get_divisor(port, baud);
 891
 892         /* calculate wakeup latency constraint */
 893         up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8);
 894         up->latency = up->calc_latency;
 895         schedule_work(&up->qos_work);
 896
 897         up->dll = quot & 0xff;
 898         up->dlh = quot >> 8;
 899         up->mdr1 = UART_OMAP_MDR1_DISABLE;
 900
 901         up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
 902                         UART_FCR_ENABLE_FIFO;
 903
 904         /*
 905          * Ok, we're now changing the port state. Do it with
 906          * interrupts disabled.
 907          */
 908         pm_runtime_get_sync(up->dev);
 909         spin_lock_irqsave(&up->port.lock, flags);
 910
 911         /*
 912          * Update the per-port timeout.
 913          */
 914         uart_update_timeout(port, termios->c_cflag, baud);
 915
 916         up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
 917         if (termios->c_iflag & INPCK)
 918                 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
 919         if (termios->c_iflag & (BRKINT | PARMRK))
 920                 up->port.read_status_mask |= UART_LSR_BI;
 921
 922         /*
 923          * Characters to ignore
 924          */
 925         up->port.ignore_status_mask = 0;
 926         if (termios->c_iflag & IGNPAR)
 927                 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
 928         if (termios->c_iflag & IGNBRK) {
 929                 up->port.ignore_status_mask |= UART_LSR_BI;
 930                 /*
 931                  * If we're ignoring parity and break indicators,
 932                  * ignore overruns too (for real raw support).
 933                  */
 934                 if (termios->c_iflag & IGNPAR)
 935                         up->port.ignore_status_mask |= UART_LSR_OE;
 936         }
 937
 938         /*
 939          * ignore all characters if CREAD is not set
 940          */
 941         if ((termios->c_cflag & CREAD) == 0)
 942                 up->port.ignore_status_mask |= UART_LSR_DR;
 943
 944         /*
 945          * Modem status interrupts
 946          */
 947         up->ier &= ~UART_IER_MSI;
 948         if (UART_ENABLE_MS(&up->port, termios->c_cflag))
 949                 up->ier |= UART_IER_MSI;
 950         serial_out(up, UART_IER, up->ier);
 951         serial_out(up, UART_LCR, cval);         /* reset DLAB */
 952         up->lcr = cval;
 953         up->scr = 0;
 954
 955         /* FIFOs and DMA Settings */
 956
 957         /* FCR can be changed only when the
 958          * baud clock is not running
 959          * DLL_REG and DLH_REG set to 0.
 960          */
 961         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 962         serial_out(up, UART_DLL, 0);
 963         serial_out(up, UART_DLM, 0);
 964         serial_out(up, UART_LCR, 0);
 965
 966         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 967
 968         up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB;
 969         up->efr &= ~UART_EFR_SCD;
 970         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 971
 972         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 973         up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR;
 974         serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
 975         /* FIFO ENABLE, DMA MODE */
 976
 977         up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
 978         /*
 979          * NOTE: Setting OMAP_UART_SCR_RX_TRIG_GRANU1_MASK
 980          * sets Enables the granularity of 1 for TRIGGER RX
 981          * level. Along with setting RX FIFO trigger level
 982          * to 1 (as noted below, 16 characters) and TLR[3:0]
 983          * to zero this will result RX FIFO threshold level
 984          * to 1 character, instead of 16 as noted in comment
 985          * below.
 986          */
 987
 988         /* Set receive FIFO threshold to 16 characters and
 989          * transmit FIFO threshold to 32 spaces
 990          */
 991         up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
 992         up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK;
 993         up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 |
 994                 UART_FCR_ENABLE_FIFO;
 995
 996         serial_out(up, UART_FCR, up->fcr);
 997         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 998
 999         serial_out(up, UART_OMAP_SCR, up->scr);
1000
1001         /* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */
1002         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1003         serial_out(up, UART_MCR, up->mcr);
1004         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1005         serial_out(up, UART_EFR, up->efr);
1006         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1007
1008         /* Protocol, Baud Rate, and Interrupt Settings */
1009
1010         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1011                 serial_omap_mdr1_errataset(up, up->mdr1);
1012         else
1013                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1014
1015         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1016         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
1017
1018         serial_out(up, UART_LCR, 0);
1019         serial_out(up, UART_IER, 0);
1020         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1021
1022         serial_out(up, UART_DLL, up->dll);      /* LS of divisor */
1023         serial_out(up, UART_DLM, up->dlh);      /* MS of divisor */
1024
1025         serial_out(up, UART_LCR, 0);
1026         serial_out(up, UART_IER, up->ier);
1027         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1028
1029         serial_out(up, UART_EFR, up->efr);
1030         serial_out(up, UART_LCR, cval);
1031
1032         if (!serial_omap_baud_is_mode16(port, baud))
1033                 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
1034         else
1035                 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
1036
1037         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1038                 serial_omap_mdr1_errataset(up, up->mdr1);
1039         else
1040                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1041
1042         /* Configure flow control */
1043         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1044
1045         /* XON1/XOFF1 accessible mode B, TCRTLR=0, ECB=0 */
1046         serial_out(up, UART_XON1, termios->c_cc[VSTART]);
1047         serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
1048
1049         /* Enable access to TCR/TLR */
1050         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
1051         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1052         serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
1053
1054         serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
1055
1056         if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
1057                 /* Enable AUTORTS and AUTOCTS */
1058                 up->efr |= UART_EFR_CTS | UART_EFR_RTS;
1059
1060                 /* Ensure MCR RTS is asserted */
1061                 up->mcr |= UART_MCR_RTS;
1062         } else {
1063                 /* Disable AUTORTS and AUTOCTS */
1064                 up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS);
1065         }
1066
1067         if (up->port.flags & UPF_SOFT_FLOW) {
1068                 /* clear SW control mode bits */
1069                 up->efr &= OMAP_UART_SW_CLR;
1070
1071                 /*
1072                  * IXON Flag:
1073                  * Enable XON/XOFF flow control on input.
1074                  * Receiver compares XON1, XOFF1.
1075                  */
1076                 if (termios->c_iflag & IXON)
1077                         up->efr |= OMAP_UART_SW_RX;
1078
1079                 /*
1080                  * IXOFF Flag:
1081                  * Enable XON/XOFF flow control on output.
1082                  * Transmit XON1, XOFF1
1083                  */
1084                 if (termios->c_iflag & IXOFF)
1085                         up->efr |= OMAP_UART_SW_TX;
1086
1087                 /*
1088                  * IXANY Flag:
1089                  * Enable any character to restart output.
1090                  * Operation resumes after receiving any
1091                  * character after recognition of the XOFF character
1092                  */
1093                 if (termios->c_iflag & IXANY)
1094                         up->mcr |= UART_MCR_XONANY;
1095                 else
1096                         up->mcr &= ~UART_MCR_XONANY;
1097         }
1098         serial_out(up, UART_MCR, up->mcr);
1099         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1100         serial_out(up, UART_EFR, up->efr);
1101         serial_out(up, UART_LCR, up->lcr);
1102
1103         serial_omap_set_mctrl(&up->port, up->port.mctrl);
1104
1105         spin_unlock_irqrestore(&up->port.lock, flags);
1106         pm_runtime_mark_last_busy(up->dev);
1107         pm_runtime_put_autosuspend(up->dev);
1108         dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
1109 }
1110
1111 static void
1112 serial_omap_pm(struct uart_port *port, unsigned int state,
1113                unsigned int oldstate)
1114 {
1115         struct uart_omap_port *up = to_uart_omap_port(port);
1116         unsigned char efr;
1117
1118         dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
1119
1120         pm_runtime_get_sync(up->dev);
1121         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1122         efr = serial_in(up, UART_EFR);
1123         serial_out(up, UART_EFR, efr | UART_EFR_ECB);
1124         serial_out(up, UART_LCR, 0);
1125
1126         serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
1127         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1128         serial_out(up, UART_EFR, efr);
1129         serial_out(up, UART_LCR, 0);
1130
1131         if (!device_may_wakeup(up->dev)) {
1132                 if (!state)
1133                         pm_runtime_forbid(up->dev);
1134                 else
1135                         pm_runtime_allow(up->dev);
1136         }
1137
1138         pm_runtime_mark_last_busy(up->dev);
1139         pm_runtime_put_autosuspend(up->dev);
1140 }
1141
1142 static void serial_omap_release_port(struct uart_port *port)
1143 {
1144         dev_dbg(port->dev, "serial_omap_release_port+\n");
1145 }
1146
1147 static int serial_omap_request_port(struct uart_port *port)
1148 {
1149         dev_dbg(port->dev, "serial_omap_request_port+\n");
1150         return 0;
1151 }
1152
1153 static void serial_omap_config_port(struct uart_port *port, int flags)
1154 {
1155         struct uart_omap_port *up = to_uart_omap_port(port);
1156
1157         dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
1158                                                         up->port.line);
1159         up->port.type = PORT_OMAP;
1160         up->port.flags |= UPF_SOFT_FLOW | UPF_HARD_FLOW;
1161 }
1162
1163 static int
1164 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
1165 {
1166         /* we don't want the core code to modify any port params */
1167         dev_dbg(port->dev, "serial_omap_verify_port+\n");
1168         return -EINVAL;
1169 }
1170
1171 static const char *
1172 serial_omap_type(struct uart_port *port)
1173 {
1174         struct uart_omap_port *up = to_uart_omap_port(port);
1175
1176         dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
1177         return up->name;
1178 }
1179
1180 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1181
1182 static inline void wait_for_xmitr(struct uart_omap_port *up)
1183 {
1184         unsigned int status, tmout = 10000;
1185
1186         /* Wait up to 10ms for the character(s) to be sent. */
1187         do {
1188                 status = serial_in(up, UART_LSR);
1189
1190                 if (status & UART_LSR_BI)
1191                         up->lsr_break_flag = UART_LSR_BI;
1192
1193                 if (--tmout == 0)
1194                         break;
1195                 udelay(1);
1196         } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
1197
1198         /* Wait up to 1s for flow control if necessary */
1199         if (up->port.flags & UPF_CONS_FLOW) {
1200                 tmout = 1000000;
1201                 for (tmout = 1000000; tmout; tmout--) {
1202                         unsigned int msr = serial_in(up, UART_MSR);
1203
1204                         up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1205                         if (msr & UART_MSR_CTS)
1206                                 break;
1207
1208                         udelay(1);
1209                 }
1210         }
1211 }
1212
1213 #ifdef CONFIG_CONSOLE_POLL
1214
1215 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
1216 {
1217         struct uart_omap_port *up = to_uart_omap_port(port);
1218
1219         pm_runtime_get_sync(up->dev);
1220         wait_for_xmitr(up);
1221         serial_out(up, UART_TX, ch);
1222         pm_runtime_mark_last_busy(up->dev);
1223         pm_runtime_put_autosuspend(up->dev);
1224 }
1225
1226 static int serial_omap_poll_get_char(struct uart_port *port)
1227 {
1228         struct uart_omap_port *up = to_uart_omap_port(port);
1229         unsigned int status;
1230
1231         pm_runtime_get_sync(up->dev);
1232         status = serial_in(up, UART_LSR);
1233         if (!(status & UART_LSR_DR)) {
1234                 status = NO_POLL_CHAR;
1235                 goto out;
1236         }
1237
1238         status = serial_in(up, UART_RX);
1239
1240 out:
1241         pm_runtime_mark_last_busy(up->dev);
1242         pm_runtime_put_autosuspend(up->dev);
1243
1244         return status;
1245 }
1246
1247 #endif /* CONFIG_CONSOLE_POLL */
1248
1249 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
1250
1251 static struct uart_omap_port *serial_omap_console_ports[OMAP_MAX_HSUART_PORTS];
1252
1253 static struct uart_driver serial_omap_reg;
1254
1255 static void serial_omap_console_putchar(struct uart_port *port, int ch)
1256 {
1257         struct uart_omap_port *up = to_uart_omap_port(port);
1258
1259         wait_for_xmitr(up);
1260         serial_out(up, UART_TX, ch);
1261 }
1262
1263 static void
1264 serial_omap_console_write(struct console *co, const char *s,
1265                 unsigned int count)
1266 {
1267         struct uart_omap_port *up = serial_omap_console_ports[co->index];
1268         unsigned long flags;
1269         unsigned int ier;
1270         int locked = 1;
1271
1272         pm_runtime_get_sync(up->dev);
1273
1274         local_irq_save(flags);
1275         if (up->port.sysrq)
1276                 locked = 0;
1277         else if (oops_in_progress)
1278                 locked = spin_trylock(&up->port.lock);
1279         else
1280                 spin_lock(&up->port.lock);
1281
1282         /*
1283          * First save the IER then disable the interrupts
1284          */
1285         ier = serial_in(up, UART_IER);
1286         serial_out(up, UART_IER, 0);
1287
1288         uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1289
1290         /*
1291          * Finally, wait for transmitter to become empty
1292          * and restore the IER
1293          */
1294         wait_for_xmitr(up);
1295         serial_out(up, UART_IER, ier);
1296         /*
1297          * The receive handling will happen properly because the
1298          * receive ready bit will still be set; it is not cleared
1299          * on read.  However, modem control will not, we must
1300          * call it if we have saved something in the saved flags
1301          * while processing with interrupts off.
1302          */
1303         if (up->msr_saved_flags)
1304                 check_modem_status(up);
1305
1306         pm_runtime_mark_last_busy(up->dev);
1307         pm_runtime_put_autosuspend(up->dev);
1308         if (locked)
1309                 spin_unlock(&up->port.lock);
1310         local_irq_restore(flags);
1311 }
1312
1313 static int __init
1314 serial_omap_console_setup(struct console *co, char *options)
1315 {
1316         struct uart_omap_port *up;
1317         int baud = 115200;
1318         int bits = 8;
1319         int parity = 'n';
1320         int flow = 'n';
1321
1322         if (serial_omap_console_ports[co->index] == NULL)
1323                 return -ENODEV;
1324         up = serial_omap_console_ports[co->index];
1325
1326         if (options)
1327                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1328
1329         return uart_set_options(&up->port, co, baud, parity, bits, flow);
1330 }
1331
1332 static struct console serial_omap_console = {
1333         .name           = OMAP_SERIAL_NAME,
1334         .write          = serial_omap_console_write,
1335         .device         = uart_console_device,
1336         .setup          = serial_omap_console_setup,
1337         .flags          = CON_PRINTBUFFER,
1338         .index          = -1,
1339         .data           = &serial_omap_reg,
1340 };
1341
1342 static void serial_omap_add_console_port(struct uart_omap_port *up)
1343 {
1344         serial_omap_console_ports[up->port.line] = up;
1345 }
1346
1347 #define OMAP_CONSOLE    (&serial_omap_console)
1348
1349 #else
1350
1351 #define OMAP_CONSOLE    NULL
1352
1353 static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1354 {}
1355
1356 #endif
1357
1358 /* Enable or disable the rs485 support */
1359 static void
1360 serial_omap_config_rs485(struct uart_port *port, struct serial_rs485 *rs485conf)
1361 {
1362         struct uart_omap_port *up = to_uart_omap_port(port);
1363         unsigned long flags;
1364         unsigned int mode;
1365         int val;
1366
1367         pm_runtime_get_sync(up->dev);
1368         spin_lock_irqsave(&up->port.lock, flags);
1369
1370         /* Disable interrupts from this port */
1371         mode = up->ier;
1372         up->ier = 0;
1373         serial_out(up, UART_IER, 0);
1374
1375         /* store new config */
1376         up->rs485 = *rs485conf;
1377
1378         /*
1379          * Just as a precaution, only allow rs485
1380          * to be enabled if the gpio pin is valid
1381          */
1382         if (gpio_is_valid(up->rts_gpio)) {
1383                 /* enable / disable rts */
1384                 val = (up->rs485.flags & SER_RS485_ENABLED) ?
1385                         SER_RS485_RTS_AFTER_SEND : SER_RS485_RTS_ON_SEND;
1386                 val = (up->rs485.flags & val) ? 1 : 0;
1387                 gpio_set_value(up->rts_gpio, val);
1388         } else
1389                 up->rs485.flags &= ~SER_RS485_ENABLED;
1390
1391         /* Enable interrupts */
1392         up->ier = mode;
1393         serial_out(up, UART_IER, up->ier);
1394
1395         /* If RS-485 is disabled, make sure the THR interrupt is fired when
1396          * TX FIFO is below the trigger level.
1397          */
1398         if (!(up->rs485.flags & SER_RS485_ENABLED) &&
1399             (up->scr & OMAP_UART_SCR_TX_EMPTY)) {
1400                 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
1401                 serial_out(up, UART_OMAP_SCR, up->scr);
1402         }
1403
1404         spin_unlock_irqrestore(&up->port.lock, flags);
1405         pm_runtime_mark_last_busy(up->dev);
1406         pm_runtime_put_autosuspend(up->dev);
1407 }
1408
1409 static int
1410 serial_omap_ioctl(struct uart_port *port, unsigned int cmd, unsigned long arg)
1411 {
1412         struct serial_rs485 rs485conf;
1413
1414         switch (cmd) {
1415         case TIOCSRS485:
1416                 if (copy_from_user(&rs485conf, (struct serial_rs485 *) arg,
1417                                         sizeof(rs485conf)))
1418                         return -EFAULT;
1419
1420                 serial_omap_config_rs485(port, &rs485conf);
1421                 break;
1422
1423         case TIOCGRS485:
1424                 if (copy_to_user((struct serial_rs485 *) arg,
1425                                         &(to_uart_omap_port(port)->rs485),
1426                                         sizeof(rs485conf)))
1427                         return -EFAULT;
1428                 break;
1429
1430         default:
1431                 return -ENOIOCTLCMD;
1432         }
1433         return 0;
1434 }
1435
1436
1437 static struct uart_ops serial_omap_pops = {
1438         .tx_empty       = serial_omap_tx_empty,
1439         .set_mctrl      = serial_omap_set_mctrl,
1440         .get_mctrl      = serial_omap_get_mctrl,
1441         .stop_tx        = serial_omap_stop_tx,
1442         .start_tx       = serial_omap_start_tx,
1443         .throttle       = serial_omap_throttle,
1444         .unthrottle     = serial_omap_unthrottle,
1445         .stop_rx        = serial_omap_stop_rx,
1446         .enable_ms      = serial_omap_enable_ms,
1447         .break_ctl      = serial_omap_break_ctl,
1448         .startup        = serial_omap_startup,
1449         .shutdown       = serial_omap_shutdown,
1450         .set_termios    = serial_omap_set_termios,
1451         .pm             = serial_omap_pm,
1452         .type           = serial_omap_type,
1453         .release_port   = serial_omap_release_port,
1454         .request_port   = serial_omap_request_port,
1455         .config_port    = serial_omap_config_port,
1456         .verify_port    = serial_omap_verify_port,
1457         .ioctl          = serial_omap_ioctl,
1458 #ifdef CONFIG_CONSOLE_POLL
1459         .poll_put_char  = serial_omap_poll_put_char,
1460         .poll_get_char  = serial_omap_poll_get_char,
1461 #endif
1462 };
1463
1464 static struct uart_driver serial_omap_reg = {
1465         .owner          = THIS_MODULE,
1466         .driver_name    = "OMAP-SERIAL",
1467         .dev_name       = OMAP_SERIAL_NAME,
1468         .nr             = OMAP_MAX_HSUART_PORTS,
1469         .cons           = OMAP_CONSOLE,
1470 };
1471
1472 #ifdef CONFIG_PM_SLEEP
1473 static int serial_omap_prepare(struct device *dev)
1474 {
1475         struct uart_omap_port *up = dev_get_drvdata(dev);
1476
1477         up->is_suspending = true;
1478
1479         return 0;
1480 }
1481
1482 static void serial_omap_complete(struct device *dev)
1483 {
1484         struct uart_omap_port *up = dev_get_drvdata(dev);
1485
1486         up->is_suspending = false;
1487 }
1488
1489 static int serial_omap_suspend(struct device *dev)
1490 {
1491         struct uart_omap_port *up = dev_get_drvdata(dev);
1492
1493         uart_suspend_port(&serial_omap_reg, &up->port);
1494         flush_work(&up->qos_work);
1495
1496         return 0;
1497 }
1498
1499 static int serial_omap_resume(struct device *dev)
1500 {
1501         struct uart_omap_port *up = dev_get_drvdata(dev);
1502
1503         uart_resume_port(&serial_omap_reg, &up->port);
1504
1505         return 0;
1506 }
1507 #else
1508 #define serial_omap_prepare NULL
1509 #define serial_omap_complete NULL
1510 #endif /* CONFIG_PM_SLEEP */
1511
1512 static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
1513 {
1514         u32 mvr, scheme;
1515         u16 revision, major, minor;
1516
1517         mvr = readl(up->port.membase + (UART_OMAP_MVER << up->port.regshift));
1518
1519         /* Check revision register scheme */
1520         scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
1521
1522         switch (scheme) {
1523         case 0: /* Legacy Scheme: OMAP2/3 */
1524                 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
1525                 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
1526                                         OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
1527                 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
1528                 break;
1529         case 1:
1530                 /* New Scheme: OMAP4+ */
1531                 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
1532                 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
1533                                         OMAP_UART_MVR_MAJ_SHIFT;
1534                 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
1535                 break;
1536         default:
1537                 dev_warn(up->dev,
1538                         "Unknown %s revision, defaulting to highest\n",
1539                         up->name);
1540                 /* highest possible revision */
1541                 major = 0xff;
1542                 minor = 0xff;
1543         }
1544
1545         /* normalize revision for the driver */
1546         revision = UART_BUILD_REVISION(major, minor);
1547
1548         switch (revision) {
1549         case OMAP_UART_REV_46:
1550                 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1551                                 UART_ERRATA_i291_DMA_FORCEIDLE);
1552                 break;
1553         case OMAP_UART_REV_52:
1554                 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1555                                 UART_ERRATA_i291_DMA_FORCEIDLE);
1556                 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1557                 break;
1558         case OMAP_UART_REV_63:
1559                 up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
1560                 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1561                 break;
1562         default:
1563                 break;
1564         }
1565 }
1566
1567 static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
1568 {
1569         struct omap_uart_port_info *omap_up_info;
1570
1571         omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
1572         if (!omap_up_info)
1573                 return NULL; /* out of memory */
1574
1575         of_property_read_u32(dev->of_node, "clock-frequency",
1576                                          &omap_up_info->uartclk);
1577         return omap_up_info;
1578 }
1579
1580 static int serial_omap_probe_rs485(struct uart_omap_port *up,
1581                                    struct device_node *np)
1582 {
1583         struct serial_rs485 *rs485conf = &up->rs485;
1584         u32 rs485_delay[2];
1585         enum of_gpio_flags flags;
1586         int ret;
1587
1588         rs485conf->flags = 0;
1589         up->rts_gpio = -EINVAL;
1590
1591         if (!np)
1592                 return 0;
1593
1594         if (of_property_read_bool(np, "rs485-rts-active-high"))
1595                 rs485conf->flags |= SER_RS485_RTS_ON_SEND;
1596         else
1597                 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
1598
1599         /* check for tx enable gpio */
1600         up->rts_gpio = of_get_named_gpio_flags(np, "rts-gpio", 0, &flags);
1601         if (gpio_is_valid(up->rts_gpio)) {
1602                 ret = gpio_request(up->rts_gpio, "omap-serial");
1603                 if (ret < 0)
1604                         return ret;
1605                 ret = gpio_direction_output(up->rts_gpio,
1606                                             flags & SER_RS485_RTS_AFTER_SEND);
1607                 if (ret < 0)
1608                         return ret;
1609         } else
1610                 up->rts_gpio = -EINVAL;
1611
1612         if (of_property_read_u32_array(np, "rs485-rts-delay",
1613                                     rs485_delay, 2) == 0) {
1614                 rs485conf->delay_rts_before_send = rs485_delay[0];
1615                 rs485conf->delay_rts_after_send = rs485_delay[1];
1616         }
1617
1618         if (of_property_read_bool(np, "rs485-rx-during-tx"))
1619                 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1620
1621         if (of_property_read_bool(np, "linux,rs485-enabled-at-boot-time"))
1622                 rs485conf->flags |= SER_RS485_ENABLED;
1623
1624         return 0;
1625 }
1626
1627 static int serial_omap_probe(struct platform_device *pdev)
1628 {
1629         struct uart_omap_port   *up;
1630         struct resource         *mem, *irq;
1631         struct omap_uart_port_info *omap_up_info = dev_get_platdata(&pdev->dev);
1632         int ret, uartirq = 0, wakeirq = 0;
1633
1634         /* The optional wakeirq may be specified in the board dts file */
1635         if (pdev->dev.of_node) {
1636                 uartirq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1637                 if (!uartirq)
1638                         return -EPROBE_DEFER;
1639                 wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1);
1640                 omap_up_info = of_get_uart_port_info(&pdev->dev);
1641                 pdev->dev.platform_data = omap_up_info;
1642         } else {
1643                 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1644                 if (!irq) {
1645                         dev_err(&pdev->dev, "no irq resource?\n");
1646                         return -ENODEV;
1647                 }
1648                 uartirq = irq->start;
1649         }
1650
1651         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1652         if (!mem) {
1653                 dev_err(&pdev->dev, "no mem resource?\n");
1654                 return -ENODEV;
1655         }
1656
1657         if (!devm_request_mem_region(&pdev->dev, mem->start, resource_size(mem),
1658                                 pdev->dev.driver->name)) {
1659                 dev_err(&pdev->dev, "memory region already claimed\n");
1660                 return -EBUSY;
1661         }
1662
1663         if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1664             omap_up_info->DTR_present) {
1665                 ret = gpio_request(omap_up_info->DTR_gpio, "omap-serial");
1666                 if (ret < 0)
1667                         return ret;
1668                 ret = gpio_direction_output(omap_up_info->DTR_gpio,
1669                                             omap_up_info->DTR_inverted);
1670                 if (ret < 0)
1671                         return ret;
1672         }
1673
1674         up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
1675         if (!up)
1676                 return -ENOMEM;
1677
1678         if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1679             omap_up_info->DTR_present) {
1680                 up->DTR_gpio = omap_up_info->DTR_gpio;
1681                 up->DTR_inverted = omap_up_info->DTR_inverted;
1682         } else
1683                 up->DTR_gpio = -EINVAL;
1684         up->DTR_active = 0;
1685
1686         up->dev = &pdev->dev;
1687         up->port.dev = &pdev->dev;
1688         up->port.type = PORT_OMAP;
1689         up->port.iotype = UPIO_MEM;
1690         up->port.irq = uartirq;
1691         up->wakeirq = wakeirq;
1692
1693         up->port.regshift = 2;
1694         up->port.fifosize = 64;
1695         up->port.ops = &serial_omap_pops;
1696
1697         if (pdev->dev.of_node)
1698                 up->port.line = of_alias_get_id(pdev->dev.of_node, "serial");
1699         else
1700                 up->port.line = pdev->id;
1701
1702         if (up->port.line < 0) {
1703                 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
1704                                                                 up->port.line);
1705                 ret = -ENODEV;
1706                 goto err_port_line;
1707         }
1708
1709         ret = serial_omap_probe_rs485(up, pdev->dev.of_node);
1710         if (ret < 0)
1711                 goto err_rs485;
1712
1713         sprintf(up->name, "OMAP UART%d", up->port.line);
1714         up->port.mapbase = mem->start;
1715         up->port.membase = devm_ioremap(&pdev->dev, mem->start,
1716                                                 resource_size(mem));
1717         if (!up->port.membase) {
1718                 dev_err(&pdev->dev, "can't ioremap UART\n");
1719                 ret = -ENOMEM;
1720                 goto err_ioremap;
1721         }
1722
1723         up->port.flags = omap_up_info->flags;
1724         up->port.uartclk = omap_up_info->uartclk;
1725         if (!up->port.uartclk) {
1726                 up->port.uartclk = DEFAULT_CLK_SPEED;
1727                 dev_warn(&pdev->dev, "No clock speed specified: using default:"
1728                                                 "%d\n", DEFAULT_CLK_SPEED);
1729         }
1730
1731         up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1732         up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1733         pm_qos_add_request(&up->pm_qos_request,
1734                 PM_QOS_CPU_DMA_LATENCY, up->latency);
1735         serial_omap_uart_wq = create_singlethread_workqueue(up->name);
1736         INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1737
1738         platform_set_drvdata(pdev, up);
1739         if (omap_up_info->autosuspend_timeout == 0)
1740                 omap_up_info->autosuspend_timeout = -1;
1741         device_init_wakeup(up->dev, true);
1742         pm_runtime_use_autosuspend(&pdev->dev);
1743         pm_runtime_set_autosuspend_delay(&pdev->dev,
1744                         omap_up_info->autosuspend_timeout);
1745
1746         pm_runtime_irq_safe(&pdev->dev);
1747         pm_runtime_enable(&pdev->dev);
1748
1749         pm_runtime_get_sync(&pdev->dev);
1750
1751         omap_serial_fill_features_erratas(up);
1752
1753         ui[up->port.line] = up;
1754         serial_omap_add_console_port(up);
1755
1756         ret = uart_add_one_port(&serial_omap_reg, &up->port);
1757         if (ret != 0)
1758                 goto err_add_port;
1759
1760         pm_runtime_mark_last_busy(up->dev);
1761         pm_runtime_put_autosuspend(up->dev);
1762         return 0;
1763
1764 err_add_port:
1765         pm_runtime_put(&pdev->dev);
1766         pm_runtime_disable(&pdev->dev);
1767 err_ioremap:
1768 err_rs485:
1769 err_port_line:
1770         dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n",
1771                                 pdev->id, __func__, ret);
1772         return ret;
1773 }
1774
1775 static int serial_omap_remove(struct platform_device *dev)
1776 {
1777         struct uart_omap_port *up = platform_get_drvdata(dev);
1778
1779         pm_runtime_put_sync(up->dev);
1780         pm_runtime_disable(up->dev);
1781         uart_remove_one_port(&serial_omap_reg, &up->port);
1782         pm_qos_remove_request(&up->pm_qos_request);
1783
1784         return 0;
1785 }
1786
1787 /*
1788  * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1789  * The access to uart register after MDR1 Access
1790  * causes UART to corrupt data.
1791  *
1792  * Need a delay =
1793  * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1794  * give 10 times as much
1795  */
1796 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1797 {
1798         u8 timeout = 255;
1799
1800         serial_out(up, UART_OMAP_MDR1, mdr1);
1801         udelay(2);
1802         serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1803                         UART_FCR_CLEAR_RCVR);
1804         /*
1805          * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1806          * TX_FIFO_E bit is 1.
1807          */
1808         while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1809                                 (UART_LSR_THRE | UART_LSR_DR))) {
1810                 timeout--;
1811                 if (!timeout) {
1812                         /* Should *never* happen. we warn and carry on */
1813                         dev_crit(up->dev, "Errata i202: timedout %x\n",
1814                                                 serial_in(up, UART_LSR));
1815                         break;
1816                 }
1817                 udelay(1);
1818         }
1819 }
1820
1821 #ifdef CONFIG_PM_RUNTIME
1822 static void serial_omap_restore_context(struct uart_omap_port *up)
1823 {
1824         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1825                 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1826         else
1827                 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1828
1829         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1830         serial_out(up, UART_EFR, UART_EFR_ECB);
1831         serial_out(up, UART_LCR, 0x0); /* Operational mode */
1832         serial_out(up, UART_IER, 0x0);
1833         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1834         serial_out(up, UART_DLL, up->dll);
1835         serial_out(up, UART_DLM, up->dlh);
1836         serial_out(up, UART_LCR, 0x0); /* Operational mode */
1837         serial_out(up, UART_IER, up->ier);
1838         serial_out(up, UART_FCR, up->fcr);
1839         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1840         serial_out(up, UART_MCR, up->mcr);
1841         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1842         serial_out(up, UART_OMAP_SCR, up->scr);
1843         serial_out(up, UART_EFR, up->efr);
1844         serial_out(up, UART_LCR, up->lcr);
1845         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1846                 serial_omap_mdr1_errataset(up, up->mdr1);
1847         else
1848                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1849         serial_out(up, UART_OMAP_WER, up->wer);
1850 }
1851
1852 static int serial_omap_runtime_suspend(struct device *dev)
1853 {
1854         struct uart_omap_port *up = dev_get_drvdata(dev);
1855
1856         if (!up)
1857                 return -EINVAL;
1858
1859         /*
1860         * When using 'no_console_suspend', the console UART must not be
1861         * suspended. Since driver suspend is managed by runtime suspend,
1862         * preventing runtime suspend (by returning error) will keep device
1863         * active during suspend.
1864         */
1865         if (up->is_suspending && !console_suspend_enabled &&
1866             uart_console(&up->port))
1867                 return -EBUSY;
1868
1869         up->context_loss_cnt = serial_omap_get_context_loss_count(up);
1870
1871         if (device_may_wakeup(dev)) {
1872                 if (!up->wakeups_enabled) {
1873                         serial_omap_enable_wakeup(up, true);
1874                         up->wakeups_enabled = true;
1875                 }
1876         } else {
1877                 if (up->wakeups_enabled) {
1878                         serial_omap_enable_wakeup(up, false);
1879                         up->wakeups_enabled = false;
1880                 }
1881         }
1882
1883         up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1884         schedule_work(&up->qos_work);
1885
1886         return 0;
1887 }
1888
1889 static int serial_omap_runtime_resume(struct device *dev)
1890 {
1891         struct uart_omap_port *up = dev_get_drvdata(dev);
1892
1893         int loss_cnt = serial_omap_get_context_loss_count(up);
1894
1895         if (loss_cnt < 0) {
1896                 dev_dbg(dev, "serial_omap_get_context_loss_count failed : %d\n",
1897                         loss_cnt);
1898                 serial_omap_restore_context(up);
1899         } else if (up->context_loss_cnt != loss_cnt) {
1900                 serial_omap_restore_context(up);
1901         }
1902         up->latency = up->calc_latency;
1903         schedule_work(&up->qos_work);
1904
1905         return 0;
1906 }
1907 #endif
1908
1909 static const struct dev_pm_ops serial_omap_dev_pm_ops = {
1910         SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
1911         SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
1912                                 serial_omap_runtime_resume, NULL)
1913         .prepare        = serial_omap_prepare,
1914         .complete       = serial_omap_complete,
1915 };
1916
1917 #if defined(CONFIG_OF)
1918 static const struct of_device_id omap_serial_of_match[] = {
1919         { .compatible = "ti,omap2-uart" },
1920         { .compatible = "ti,omap3-uart" },
1921         { .compatible = "ti,omap4-uart" },
1922         {},
1923 };
1924 MODULE_DEVICE_TABLE(of, omap_serial_of_match);
1925 #endif
1926
1927 static struct platform_driver serial_omap_driver = {
1928         .probe          = serial_omap_probe,
1929         .remove         = serial_omap_remove,
1930         .driver         = {
1931                 .name   = DRIVER_NAME,
1932                 .pm     = &serial_omap_dev_pm_ops,
1933                 .of_match_table = of_match_ptr(omap_serial_of_match),
1934         },
1935 };
1936
1937 static int __init serial_omap_init(void)
1938 {
1939         int ret;
1940
1941         ret = uart_register_driver(&serial_omap_reg);
1942         if (ret != 0)
1943                 return ret;
1944         ret = platform_driver_register(&serial_omap_driver);
1945         if (ret != 0)
1946                 uart_unregister_driver(&serial_omap_reg);
1947         return ret;
1948 }
1949
1950 static void __exit serial_omap_exit(void)
1951 {
1952         platform_driver_unregister(&serial_omap_driver);
1953         uart_unregister_driver(&serial_omap_reg);
1954 }
1955
1956 module_init(serial_omap_init);
1957 module_exit(serial_omap_exit);
1958
1959 MODULE_DESCRIPTION("OMAP High Speed UART driver");
1960 MODULE_LICENSE("GPL");
1961 MODULE_AUTHOR("Texas Instruments Inc");