2 * Driver for OMAP-UART controller.
3 * Based on drivers/serial/8250.c
5 * Copyright (C) 2010 Texas Instruments.
8 * Govindraj R <govindraj.raja@ti.com>
9 * Thara Gopinath <thara@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * Note: This driver is made separate from 8250 driver as we cannot
17 * over load 8250 driver with omap platform specific configuration for
18 * features like DMA, it makes easier to implement features like DMA and
19 * hardware flow control and software flow control configuration with
20 * this driver as required for the omap-platform.
23 #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/console.h>
30 #include <linux/serial_reg.h>
31 #include <linux/delay.h>
32 #include <linux/slab.h>
33 #include <linux/tty.h>
34 #include <linux/tty_flip.h>
36 #include <linux/dma-mapping.h>
37 #include <linux/clk.h>
38 #include <linux/serial_core.h>
39 #include <linux/irq.h>
40 #include <linux/pm_runtime.h>
43 #include <plat/dmtimer.h>
44 #include <plat/omap-serial.h>
46 #define OMAP_UART_AUTOSUSPEND_DELAY -1
48 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
50 /* Forward declaration of functions */
51 static void uart_tx_dma_callback(int lch, u16 ch_status, void *data);
52 static void serial_omap_rx_timeout(unsigned long uart_no);
53 static int serial_omap_start_rxdma(struct uart_omap_port *up);
55 static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
57 offset <<= up->port.regshift;
58 return readw(up->port.membase + offset);
61 static inline void serial_out(struct uart_omap_port *up, int offset, int value)
63 offset <<= up->port.regshift;
64 writew(value, up->port.membase + offset);
67 static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
69 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
70 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
71 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
72 serial_out(up, UART_FCR, 0);
76 * serial_omap_get_divisor - calculate divisor value
77 * @port: uart port info
78 * @baud: baudrate for which divisor needs to be calculated.
80 * We have written our own function to get the divisor so as to support
81 * 13x mode. 3Mbps Baudrate as an different divisor.
82 * Reference OMAP TRM Chapter 17:
83 * Table 17-1. UART Mode Baud Rates, Divisor Values, and Error Rates
84 * referring to oversampling - divisor value
85 * baudrate 460,800 to 3,686,400 all have divisor 13
86 * except 3,000,000 which has divisor value 16
89 serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
93 if (baud > OMAP_MODE13X_SPEED && baud != 3000000)
97 return port->uartclk/(baud * divisor);
100 static void serial_omap_stop_rxdma(struct uart_omap_port *up)
102 if (up->uart_dma.rx_dma_used) {
103 del_timer(&up->uart_dma.rx_timer);
104 omap_stop_dma(up->uart_dma.rx_dma_channel);
105 omap_free_dma(up->uart_dma.rx_dma_channel);
106 up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE;
107 up->uart_dma.rx_dma_used = false;
108 pm_runtime_mark_last_busy(&up->pdev->dev);
109 pm_runtime_put_autosuspend(&up->pdev->dev);
113 static void serial_omap_enable_ms(struct uart_port *port)
115 struct uart_omap_port *up = (struct uart_omap_port *)port;
117 dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->pdev->id);
119 pm_runtime_get_sync(&up->pdev->dev);
120 up->ier |= UART_IER_MSI;
121 serial_out(up, UART_IER, up->ier);
122 pm_runtime_put(&up->pdev->dev);
125 static void serial_omap_stop_tx(struct uart_port *port)
127 struct uart_omap_port *up = (struct uart_omap_port *)port;
130 up->uart_dma.tx_dma_channel != OMAP_UART_DMA_CH_FREE) {
132 * Check if dma is still active. If yes do nothing,
133 * return. Else stop dma
135 if (omap_get_dma_active_status(up->uart_dma.tx_dma_channel))
137 omap_stop_dma(up->uart_dma.tx_dma_channel);
138 omap_free_dma(up->uart_dma.tx_dma_channel);
139 up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE;
140 pm_runtime_mark_last_busy(&up->pdev->dev);
141 pm_runtime_put_autosuspend(&up->pdev->dev);
144 pm_runtime_get_sync(&up->pdev->dev);
145 if (up->ier & UART_IER_THRI) {
146 up->ier &= ~UART_IER_THRI;
147 serial_out(up, UART_IER, up->ier);
150 pm_runtime_mark_last_busy(&up->pdev->dev);
151 pm_runtime_put_autosuspend(&up->pdev->dev);
154 static void serial_omap_stop_rx(struct uart_port *port)
156 struct uart_omap_port *up = (struct uart_omap_port *)port;
158 pm_runtime_get_sync(&up->pdev->dev);
160 serial_omap_stop_rxdma(up);
161 up->ier &= ~UART_IER_RLSI;
162 up->port.read_status_mask &= ~UART_LSR_DR;
163 serial_out(up, UART_IER, up->ier);
164 pm_runtime_mark_last_busy(&up->pdev->dev);
165 pm_runtime_put_autosuspend(&up->pdev->dev);
168 static inline void receive_chars(struct uart_omap_port *up, int *status)
170 struct tty_struct *tty = up->port.state->port.tty;
172 unsigned char ch, lsr = *status;
176 if (likely(lsr & UART_LSR_DR))
177 ch = serial_in(up, UART_RX);
179 up->port.icount.rx++;
181 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
183 * For statistics only
185 if (lsr & UART_LSR_BI) {
186 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
187 up->port.icount.brk++;
189 * We do the SysRQ and SAK checking
190 * here because otherwise the break
191 * may get masked by ignore_status_mask
192 * or read_status_mask.
194 if (uart_handle_break(&up->port))
196 } else if (lsr & UART_LSR_PE) {
197 up->port.icount.parity++;
198 } else if (lsr & UART_LSR_FE) {
199 up->port.icount.frame++;
202 if (lsr & UART_LSR_OE)
203 up->port.icount.overrun++;
206 * Mask off conditions which should be ignored.
208 lsr &= up->port.read_status_mask;
210 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
211 if (up->port.line == up->port.cons->index) {
212 /* Recover the break flag from console xmit */
213 lsr |= up->lsr_break_flag;
216 if (lsr & UART_LSR_BI)
218 else if (lsr & UART_LSR_PE)
220 else if (lsr & UART_LSR_FE)
224 if (uart_handle_sysrq_char(&up->port, ch))
226 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
228 lsr = serial_in(up, UART_LSR);
229 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
230 spin_unlock(&up->port.lock);
231 tty_flip_buffer_push(tty);
232 spin_lock(&up->port.lock);
235 static void transmit_chars(struct uart_omap_port *up)
237 struct circ_buf *xmit = &up->port.state->xmit;
240 if (up->port.x_char) {
241 serial_out(up, UART_TX, up->port.x_char);
242 up->port.icount.tx++;
246 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
247 serial_omap_stop_tx(&up->port);
250 count = up->port.fifosize / 4;
252 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
253 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
254 up->port.icount.tx++;
255 if (uart_circ_empty(xmit))
257 } while (--count > 0);
259 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
260 uart_write_wakeup(&up->port);
262 if (uart_circ_empty(xmit))
263 serial_omap_stop_tx(&up->port);
266 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
268 if (!(up->ier & UART_IER_THRI)) {
269 up->ier |= UART_IER_THRI;
270 serial_out(up, UART_IER, up->ier);
274 static void serial_omap_start_tx(struct uart_port *port)
276 struct uart_omap_port *up = (struct uart_omap_port *)port;
277 struct circ_buf *xmit;
282 pm_runtime_get_sync(&up->pdev->dev);
283 serial_omap_enable_ier_thri(up);
284 pm_runtime_mark_last_busy(&up->pdev->dev);
285 pm_runtime_put_autosuspend(&up->pdev->dev);
289 if (up->uart_dma.tx_dma_used)
292 xmit = &up->port.state->xmit;
294 if (up->uart_dma.tx_dma_channel == OMAP_UART_DMA_CH_FREE) {
295 pm_runtime_get_sync(&up->pdev->dev);
296 ret = omap_request_dma(up->uart_dma.uart_dma_tx,
298 (void *)uart_tx_dma_callback, up,
299 &(up->uart_dma.tx_dma_channel));
302 serial_omap_enable_ier_thri(up);
306 spin_lock(&(up->uart_dma.tx_lock));
307 up->uart_dma.tx_dma_used = true;
308 spin_unlock(&(up->uart_dma.tx_lock));
310 start = up->uart_dma.tx_buf_dma_phys +
311 (xmit->tail & (UART_XMIT_SIZE - 1));
313 up->uart_dma.tx_buf_size = uart_circ_chars_pending(xmit);
315 * It is a circular buffer. See if the buffer has wounded back.
316 * If yes it will have to be transferred in two separate dma
319 if (start + up->uart_dma.tx_buf_size >=
320 up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE)
321 up->uart_dma.tx_buf_size =
322 (up->uart_dma.tx_buf_dma_phys +
323 UART_XMIT_SIZE) - start;
325 omap_set_dma_dest_params(up->uart_dma.tx_dma_channel, 0,
326 OMAP_DMA_AMODE_CONSTANT,
327 up->uart_dma.uart_base, 0, 0);
328 omap_set_dma_src_params(up->uart_dma.tx_dma_channel, 0,
329 OMAP_DMA_AMODE_POST_INC, start, 0, 0);
330 omap_set_dma_transfer_params(up->uart_dma.tx_dma_channel,
331 OMAP_DMA_DATA_TYPE_S8,
332 up->uart_dma.tx_buf_size, 1,
333 OMAP_DMA_SYNC_ELEMENT,
334 up->uart_dma.uart_dma_tx, 0);
335 /* FIXME: Cache maintenance needed here? */
336 omap_start_dma(up->uart_dma.tx_dma_channel);
339 static unsigned int check_modem_status(struct uart_omap_port *up)
343 status = serial_in(up, UART_MSR);
344 status |= up->msr_saved_flags;
345 up->msr_saved_flags = 0;
346 if ((status & UART_MSR_ANY_DELTA) == 0)
349 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
350 up->port.state != NULL) {
351 if (status & UART_MSR_TERI)
352 up->port.icount.rng++;
353 if (status & UART_MSR_DDSR)
354 up->port.icount.dsr++;
355 if (status & UART_MSR_DDCD)
356 uart_handle_dcd_change
357 (&up->port, status & UART_MSR_DCD);
358 if (status & UART_MSR_DCTS)
359 uart_handle_cts_change
360 (&up->port, status & UART_MSR_CTS);
361 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
368 * serial_omap_irq() - This handles the interrupt from one port
369 * @irq: uart port irq number
370 * @dev_id: uart port info
372 static inline irqreturn_t serial_omap_irq(int irq, void *dev_id)
374 struct uart_omap_port *up = dev_id;
375 unsigned int iir, lsr;
378 pm_runtime_get_sync(&up->pdev->dev);
379 iir = serial_in(up, UART_IIR);
380 if (iir & UART_IIR_NO_INT) {
381 pm_runtime_mark_last_busy(&up->pdev->dev);
382 pm_runtime_put_autosuspend(&up->pdev->dev);
386 spin_lock_irqsave(&up->port.lock, flags);
387 lsr = serial_in(up, UART_LSR);
388 if (iir & UART_IIR_RLSI) {
390 if (lsr & UART_LSR_DR)
391 receive_chars(up, &lsr);
393 up->ier &= ~(UART_IER_RDI | UART_IER_RLSI);
394 serial_out(up, UART_IER, up->ier);
395 if ((serial_omap_start_rxdma(up) != 0) &&
397 receive_chars(up, &lsr);
401 check_modem_status(up);
402 if ((lsr & UART_LSR_THRE) && (iir & UART_IIR_THRI))
405 spin_unlock_irqrestore(&up->port.lock, flags);
406 pm_runtime_mark_last_busy(&up->pdev->dev);
407 pm_runtime_put_autosuspend(&up->pdev->dev);
409 up->port_activity = jiffies;
413 static unsigned int serial_omap_tx_empty(struct uart_port *port)
415 struct uart_omap_port *up = (struct uart_omap_port *)port;
416 unsigned long flags = 0;
417 unsigned int ret = 0;
419 pm_runtime_get_sync(&up->pdev->dev);
420 dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->pdev->id);
421 spin_lock_irqsave(&up->port.lock, flags);
422 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
423 spin_unlock_irqrestore(&up->port.lock, flags);
424 pm_runtime_put(&up->pdev->dev);
428 static unsigned int serial_omap_get_mctrl(struct uart_port *port)
430 struct uart_omap_port *up = (struct uart_omap_port *)port;
431 unsigned char status;
432 unsigned int ret = 0;
434 pm_runtime_get_sync(&up->pdev->dev);
435 status = check_modem_status(up);
436 pm_runtime_put(&up->pdev->dev);
438 dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->pdev->id);
440 if (status & UART_MSR_DCD)
442 if (status & UART_MSR_RI)
444 if (status & UART_MSR_DSR)
446 if (status & UART_MSR_CTS)
451 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
453 struct uart_omap_port *up = (struct uart_omap_port *)port;
454 unsigned char mcr = 0;
456 dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->pdev->id);
457 if (mctrl & TIOCM_RTS)
459 if (mctrl & TIOCM_DTR)
461 if (mctrl & TIOCM_OUT1)
462 mcr |= UART_MCR_OUT1;
463 if (mctrl & TIOCM_OUT2)
464 mcr |= UART_MCR_OUT2;
465 if (mctrl & TIOCM_LOOP)
466 mcr |= UART_MCR_LOOP;
468 pm_runtime_get_sync(&up->pdev->dev);
469 up->mcr = serial_in(up, UART_MCR);
471 serial_out(up, UART_MCR, up->mcr);
472 pm_runtime_put(&up->pdev->dev);
475 static void serial_omap_break_ctl(struct uart_port *port, int break_state)
477 struct uart_omap_port *up = (struct uart_omap_port *)port;
478 unsigned long flags = 0;
480 dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->pdev->id);
481 pm_runtime_get_sync(&up->pdev->dev);
482 spin_lock_irqsave(&up->port.lock, flags);
483 if (break_state == -1)
484 up->lcr |= UART_LCR_SBC;
486 up->lcr &= ~UART_LCR_SBC;
487 serial_out(up, UART_LCR, up->lcr);
488 spin_unlock_irqrestore(&up->port.lock, flags);
489 pm_runtime_put(&up->pdev->dev);
492 static int serial_omap_startup(struct uart_port *port)
494 struct uart_omap_port *up = (struct uart_omap_port *)port;
495 unsigned long flags = 0;
501 retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
506 dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->pdev->id);
508 pm_runtime_get_sync(&up->pdev->dev);
510 * Clear the FIFO buffers and disable them.
511 * (they will be reenabled in set_termios())
513 serial_omap_clear_fifos(up);
514 /* For Hardware flow control */
515 serial_out(up, UART_MCR, UART_MCR_RTS);
518 * Clear the interrupt registers.
520 (void) serial_in(up, UART_LSR);
521 if (serial_in(up, UART_LSR) & UART_LSR_DR)
522 (void) serial_in(up, UART_RX);
523 (void) serial_in(up, UART_IIR);
524 (void) serial_in(up, UART_MSR);
527 * Now, initialize the UART
529 serial_out(up, UART_LCR, UART_LCR_WLEN8);
530 spin_lock_irqsave(&up->port.lock, flags);
532 * Most PC uarts need OUT2 raised to enable interrupts.
534 up->port.mctrl |= TIOCM_OUT2;
535 serial_omap_set_mctrl(&up->port, up->port.mctrl);
536 spin_unlock_irqrestore(&up->port.lock, flags);
538 up->msr_saved_flags = 0;
540 free_page((unsigned long)up->port.state->xmit.buf);
541 up->port.state->xmit.buf = dma_alloc_coherent(NULL,
543 (dma_addr_t *)&(up->uart_dma.tx_buf_dma_phys),
545 init_timer(&(up->uart_dma.rx_timer));
546 up->uart_dma.rx_timer.function = serial_omap_rx_timeout;
547 up->uart_dma.rx_timer.data = up->pdev->id;
548 /* Currently the buffer size is 4KB. Can increase it */
549 up->uart_dma.rx_buf = dma_alloc_coherent(NULL,
550 up->uart_dma.rx_buf_size,
551 (dma_addr_t *)&(up->uart_dma.rx_buf_dma_phys), 0);
554 * Finally, enable interrupts. Note: Modem status interrupts
555 * are set via set_termios(), which will be occurring imminently
556 * anyway, so we don't enable them here.
558 up->ier = UART_IER_RLSI | UART_IER_RDI;
559 serial_out(up, UART_IER, up->ier);
561 /* Enable module level wake up */
562 serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP);
564 pm_runtime_mark_last_busy(&up->pdev->dev);
565 pm_runtime_put_autosuspend(&up->pdev->dev);
566 up->port_activity = jiffies;
570 static void serial_omap_shutdown(struct uart_port *port)
572 struct uart_omap_port *up = (struct uart_omap_port *)port;
573 unsigned long flags = 0;
575 dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->pdev->id);
577 pm_runtime_get_sync(&up->pdev->dev);
579 * Disable interrupts from this port
582 serial_out(up, UART_IER, 0);
584 spin_lock_irqsave(&up->port.lock, flags);
585 up->port.mctrl &= ~TIOCM_OUT2;
586 serial_omap_set_mctrl(&up->port, up->port.mctrl);
587 spin_unlock_irqrestore(&up->port.lock, flags);
590 * Disable break condition and FIFOs
592 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
593 serial_omap_clear_fifos(up);
596 * Read data port to reset things, and then free the irq
598 if (serial_in(up, UART_LSR) & UART_LSR_DR)
599 (void) serial_in(up, UART_RX);
601 dma_free_coherent(up->port.dev,
602 UART_XMIT_SIZE, up->port.state->xmit.buf,
603 up->uart_dma.tx_buf_dma_phys);
604 up->port.state->xmit.buf = NULL;
605 serial_omap_stop_rx(port);
606 dma_free_coherent(up->port.dev,
607 up->uart_dma.rx_buf_size, up->uart_dma.rx_buf,
608 up->uart_dma.rx_buf_dma_phys);
609 up->uart_dma.rx_buf = NULL;
612 pm_runtime_put(&up->pdev->dev);
613 free_irq(up->port.irq, up);
617 serial_omap_configure_xonxoff
618 (struct uart_omap_port *up, struct ktermios *termios)
620 up->lcr = serial_in(up, UART_LCR);
621 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
622 up->efr = serial_in(up, UART_EFR);
623 serial_out(up, UART_EFR, up->efr & ~UART_EFR_ECB);
625 serial_out(up, UART_XON1, termios->c_cc[VSTART]);
626 serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
628 /* clear SW control mode bits */
629 up->efr &= OMAP_UART_SW_CLR;
633 * Enable XON/XOFF flow control on output.
634 * Transmit XON1, XOFF1
636 if (termios->c_iflag & IXON)
637 up->efr |= OMAP_UART_SW_TX;
641 * Enable XON/XOFF flow control on input.
642 * Receiver compares XON1, XOFF1.
644 if (termios->c_iflag & IXOFF)
645 up->efr |= OMAP_UART_SW_RX;
647 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
648 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
650 up->mcr = serial_in(up, UART_MCR);
654 * Enable any character to restart output.
655 * Operation resumes after receiving any
656 * character after recognition of the XOFF character
658 if (termios->c_iflag & IXANY)
659 up->mcr |= UART_MCR_XONANY;
661 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
662 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
663 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
664 /* Enable special char function UARTi.EFR_REG[5] and
665 * load the new software flow control mode IXON or IXOFF
666 * and restore the UARTi.EFR_REG[4] ENHANCED_EN value.
668 serial_out(up, UART_EFR, up->efr | UART_EFR_SCD);
669 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
671 serial_out(up, UART_MCR, up->mcr & ~UART_MCR_TCRTLR);
672 serial_out(up, UART_LCR, up->lcr);
676 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
677 struct ktermios *old)
679 struct uart_omap_port *up = (struct uart_omap_port *)port;
680 unsigned char cval = 0;
681 unsigned char efr = 0;
682 unsigned long flags = 0;
683 unsigned int baud, quot;
685 switch (termios->c_cflag & CSIZE) {
687 cval = UART_LCR_WLEN5;
690 cval = UART_LCR_WLEN6;
693 cval = UART_LCR_WLEN7;
697 cval = UART_LCR_WLEN8;
701 if (termios->c_cflag & CSTOPB)
702 cval |= UART_LCR_STOP;
703 if (termios->c_cflag & PARENB)
704 cval |= UART_LCR_PARITY;
705 if (!(termios->c_cflag & PARODD))
706 cval |= UART_LCR_EPAR;
709 * Ask the core to calculate the divisor for us.
712 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
713 quot = serial_omap_get_divisor(port, baud);
715 up->dll = quot & 0xff;
717 up->mdr1 = UART_OMAP_MDR1_DISABLE;
719 up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
720 UART_FCR_ENABLE_FIFO;
722 up->fcr |= UART_FCR_DMA_SELECT;
725 * Ok, we're now changing the port state. Do it with
726 * interrupts disabled.
728 pm_runtime_get_sync(&up->pdev->dev);
729 spin_lock_irqsave(&up->port.lock, flags);
732 * Update the per-port timeout.
734 uart_update_timeout(port, termios->c_cflag, baud);
736 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
737 if (termios->c_iflag & INPCK)
738 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
739 if (termios->c_iflag & (BRKINT | PARMRK))
740 up->port.read_status_mask |= UART_LSR_BI;
743 * Characters to ignore
745 up->port.ignore_status_mask = 0;
746 if (termios->c_iflag & IGNPAR)
747 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
748 if (termios->c_iflag & IGNBRK) {
749 up->port.ignore_status_mask |= UART_LSR_BI;
751 * If we're ignoring parity and break indicators,
752 * ignore overruns too (for real raw support).
754 if (termios->c_iflag & IGNPAR)
755 up->port.ignore_status_mask |= UART_LSR_OE;
759 * ignore all characters if CREAD is not set
761 if ((termios->c_cflag & CREAD) == 0)
762 up->port.ignore_status_mask |= UART_LSR_DR;
765 * Modem status interrupts
767 up->ier &= ~UART_IER_MSI;
768 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
769 up->ier |= UART_IER_MSI;
770 serial_out(up, UART_IER, up->ier);
771 serial_out(up, UART_LCR, cval); /* reset DLAB */
773 up->scr = OMAP_UART_SCR_TX_EMPTY;
775 /* FIFOs and DMA Settings */
777 /* FCR can be changed only when the
778 * baud clock is not running
779 * DLL_REG and DLH_REG set to 0.
781 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
782 serial_out(up, UART_DLL, 0);
783 serial_out(up, UART_DLM, 0);
784 serial_out(up, UART_LCR, 0);
786 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
788 up->efr = serial_in(up, UART_EFR);
789 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
791 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
792 up->mcr = serial_in(up, UART_MCR);
793 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
794 /* FIFO ENABLE, DMA MODE */
795 serial_out(up, UART_FCR, up->fcr);
796 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
799 serial_out(up, UART_TI752_TLR, 0);
800 up->scr |= (UART_FCR_TRIGGER_4 | UART_FCR_TRIGGER_8);
803 serial_out(up, UART_OMAP_SCR, up->scr);
805 serial_out(up, UART_EFR, up->efr);
806 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
807 serial_out(up, UART_MCR, up->mcr);
809 /* Protocol, Baud Rate, and Interrupt Settings */
811 serial_out(up, UART_OMAP_MDR1, up->mdr1);
812 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
814 up->efr = serial_in(up, UART_EFR);
815 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
817 serial_out(up, UART_LCR, 0);
818 serial_out(up, UART_IER, 0);
819 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
821 serial_out(up, UART_DLL, up->dll); /* LS of divisor */
822 serial_out(up, UART_DLM, up->dlh); /* MS of divisor */
824 serial_out(up, UART_LCR, 0);
825 serial_out(up, UART_IER, up->ier);
826 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
828 serial_out(up, UART_EFR, up->efr);
829 serial_out(up, UART_LCR, cval);
831 if (baud > 230400 && baud != 3000000)
832 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
834 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
836 serial_out(up, UART_OMAP_MDR1, up->mdr1);
838 /* Hardware Flow Control Configuration */
840 if (termios->c_cflag & CRTSCTS) {
841 efr |= (UART_EFR_CTS | UART_EFR_RTS);
842 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
844 up->mcr = serial_in(up, UART_MCR);
845 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
847 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
848 up->efr = serial_in(up, UART_EFR);
849 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
851 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
852 serial_out(up, UART_EFR, efr); /* Enable AUTORTS and AUTOCTS */
853 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
854 serial_out(up, UART_MCR, up->mcr | UART_MCR_RTS);
855 serial_out(up, UART_LCR, cval);
858 serial_omap_set_mctrl(&up->port, up->port.mctrl);
859 /* Software Flow Control Configuration */
860 serial_omap_configure_xonxoff(up, termios);
862 spin_unlock_irqrestore(&up->port.lock, flags);
863 pm_runtime_put(&up->pdev->dev);
864 dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->pdev->id);
868 serial_omap_pm(struct uart_port *port, unsigned int state,
869 unsigned int oldstate)
871 struct uart_omap_port *up = (struct uart_omap_port *)port;
874 dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->pdev->id);
876 pm_runtime_get_sync(&up->pdev->dev);
877 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
878 efr = serial_in(up, UART_EFR);
879 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
880 serial_out(up, UART_LCR, 0);
882 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
883 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
884 serial_out(up, UART_EFR, efr);
885 serial_out(up, UART_LCR, 0);
887 if (!device_may_wakeup(&up->pdev->dev)) {
889 pm_runtime_forbid(&up->pdev->dev);
891 pm_runtime_allow(&up->pdev->dev);
894 pm_runtime_put(&up->pdev->dev);
897 static void serial_omap_release_port(struct uart_port *port)
899 dev_dbg(port->dev, "serial_omap_release_port+\n");
902 static int serial_omap_request_port(struct uart_port *port)
904 dev_dbg(port->dev, "serial_omap_request_port+\n");
908 static void serial_omap_config_port(struct uart_port *port, int flags)
910 struct uart_omap_port *up = (struct uart_omap_port *)port;
912 dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
914 up->port.type = PORT_OMAP;
918 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
920 /* we don't want the core code to modify any port params */
921 dev_dbg(port->dev, "serial_omap_verify_port+\n");
926 serial_omap_type(struct uart_port *port)
928 struct uart_omap_port *up = (struct uart_omap_port *)port;
930 dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->pdev->id);
934 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
936 static inline void wait_for_xmitr(struct uart_omap_port *up)
938 unsigned int status, tmout = 10000;
940 /* Wait up to 10ms for the character(s) to be sent. */
942 status = serial_in(up, UART_LSR);
944 if (status & UART_LSR_BI)
945 up->lsr_break_flag = UART_LSR_BI;
950 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
952 /* Wait up to 1s for flow control if necessary */
953 if (up->port.flags & UPF_CONS_FLOW) {
955 for (tmout = 1000000; tmout; tmout--) {
956 unsigned int msr = serial_in(up, UART_MSR);
958 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
959 if (msr & UART_MSR_CTS)
967 #ifdef CONFIG_CONSOLE_POLL
969 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
971 struct uart_omap_port *up = (struct uart_omap_port *)port;
973 pm_runtime_get_sync(&up->pdev->dev);
975 serial_out(up, UART_TX, ch);
976 pm_runtime_put(&up->pdev->dev);
979 static int serial_omap_poll_get_char(struct uart_port *port)
981 struct uart_omap_port *up = (struct uart_omap_port *)port;
984 pm_runtime_get_sync(&up->pdev->dev);
985 status = serial_in(up, UART_LSR);
986 if (!(status & UART_LSR_DR))
989 status = serial_in(up, UART_RX);
990 pm_runtime_put(&up->pdev->dev);
994 #endif /* CONFIG_CONSOLE_POLL */
996 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
998 static struct uart_omap_port *serial_omap_console_ports[4];
1000 static struct uart_driver serial_omap_reg;
1002 static void serial_omap_console_putchar(struct uart_port *port, int ch)
1004 struct uart_omap_port *up = (struct uart_omap_port *)port;
1007 serial_out(up, UART_TX, ch);
1011 serial_omap_console_write(struct console *co, const char *s,
1014 struct uart_omap_port *up = serial_omap_console_ports[co->index];
1015 unsigned long flags;
1019 pm_runtime_get_sync(&up->pdev->dev);
1021 local_irq_save(flags);
1024 else if (oops_in_progress)
1025 locked = spin_trylock(&up->port.lock);
1027 spin_lock(&up->port.lock);
1030 * First save the IER then disable the interrupts
1032 ier = serial_in(up, UART_IER);
1033 serial_out(up, UART_IER, 0);
1035 uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1038 * Finally, wait for transmitter to become empty
1039 * and restore the IER
1042 serial_out(up, UART_IER, ier);
1044 * The receive handling will happen properly because the
1045 * receive ready bit will still be set; it is not cleared
1046 * on read. However, modem control will not, we must
1047 * call it if we have saved something in the saved flags
1048 * while processing with interrupts off.
1050 if (up->msr_saved_flags)
1051 check_modem_status(up);
1053 pm_runtime_mark_last_busy(&up->pdev->dev);
1054 pm_runtime_put_autosuspend(&up->pdev->dev);
1056 spin_unlock(&up->port.lock);
1057 local_irq_restore(flags);
1061 serial_omap_console_setup(struct console *co, char *options)
1063 struct uart_omap_port *up;
1069 if (serial_omap_console_ports[co->index] == NULL)
1071 up = serial_omap_console_ports[co->index];
1074 uart_parse_options(options, &baud, &parity, &bits, &flow);
1076 return uart_set_options(&up->port, co, baud, parity, bits, flow);
1079 static struct console serial_omap_console = {
1080 .name = OMAP_SERIAL_NAME,
1081 .write = serial_omap_console_write,
1082 .device = uart_console_device,
1083 .setup = serial_omap_console_setup,
1084 .flags = CON_PRINTBUFFER,
1086 .data = &serial_omap_reg,
1089 static void serial_omap_add_console_port(struct uart_omap_port *up)
1091 serial_omap_console_ports[up->pdev->id] = up;
1094 #define OMAP_CONSOLE (&serial_omap_console)
1098 #define OMAP_CONSOLE NULL
1100 static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1105 static struct uart_ops serial_omap_pops = {
1106 .tx_empty = serial_omap_tx_empty,
1107 .set_mctrl = serial_omap_set_mctrl,
1108 .get_mctrl = serial_omap_get_mctrl,
1109 .stop_tx = serial_omap_stop_tx,
1110 .start_tx = serial_omap_start_tx,
1111 .stop_rx = serial_omap_stop_rx,
1112 .enable_ms = serial_omap_enable_ms,
1113 .break_ctl = serial_omap_break_ctl,
1114 .startup = serial_omap_startup,
1115 .shutdown = serial_omap_shutdown,
1116 .set_termios = serial_omap_set_termios,
1117 .pm = serial_omap_pm,
1118 .type = serial_omap_type,
1119 .release_port = serial_omap_release_port,
1120 .request_port = serial_omap_request_port,
1121 .config_port = serial_omap_config_port,
1122 .verify_port = serial_omap_verify_port,
1123 #ifdef CONFIG_CONSOLE_POLL
1124 .poll_put_char = serial_omap_poll_put_char,
1125 .poll_get_char = serial_omap_poll_get_char,
1129 static struct uart_driver serial_omap_reg = {
1130 .owner = THIS_MODULE,
1131 .driver_name = "OMAP-SERIAL",
1132 .dev_name = OMAP_SERIAL_NAME,
1133 .nr = OMAP_MAX_HSUART_PORTS,
1134 .cons = OMAP_CONSOLE,
1137 #ifdef CONFIG_SUSPEND
1138 static int serial_omap_suspend(struct device *dev)
1140 struct uart_omap_port *up = dev_get_drvdata(dev);
1143 uart_suspend_port(&serial_omap_reg, &up->port);
1147 static int serial_omap_resume(struct device *dev)
1149 struct uart_omap_port *up = dev_get_drvdata(dev);
1152 uart_resume_port(&serial_omap_reg, &up->port);
1157 static void serial_omap_rx_timeout(unsigned long uart_no)
1159 struct uart_omap_port *up = ui[uart_no];
1160 unsigned int curr_dma_pos, curr_transmitted_size;
1163 curr_dma_pos = omap_get_dma_dst_pos(up->uart_dma.rx_dma_channel);
1164 if ((curr_dma_pos == up->uart_dma.prev_rx_dma_pos) ||
1165 (curr_dma_pos == 0)) {
1166 if (jiffies_to_msecs(jiffies - up->port_activity) <
1168 mod_timer(&up->uart_dma.rx_timer, jiffies +
1169 usecs_to_jiffies(up->uart_dma.rx_timeout));
1171 serial_omap_stop_rxdma(up);
1172 up->ier |= (UART_IER_RDI | UART_IER_RLSI);
1173 serial_out(up, UART_IER, up->ier);
1178 curr_transmitted_size = curr_dma_pos -
1179 up->uart_dma.prev_rx_dma_pos;
1180 up->port.icount.rx += curr_transmitted_size;
1181 tty_insert_flip_string(up->port.state->port.tty,
1182 up->uart_dma.rx_buf +
1183 (up->uart_dma.prev_rx_dma_pos -
1184 up->uart_dma.rx_buf_dma_phys),
1185 curr_transmitted_size);
1186 tty_flip_buffer_push(up->port.state->port.tty);
1187 up->uart_dma.prev_rx_dma_pos = curr_dma_pos;
1188 if (up->uart_dma.rx_buf_size +
1189 up->uart_dma.rx_buf_dma_phys == curr_dma_pos) {
1190 ret = serial_omap_start_rxdma(up);
1192 serial_omap_stop_rxdma(up);
1193 up->ier |= (UART_IER_RDI | UART_IER_RLSI);
1194 serial_out(up, UART_IER, up->ier);
1197 mod_timer(&up->uart_dma.rx_timer, jiffies +
1198 usecs_to_jiffies(up->uart_dma.rx_timeout));
1200 up->port_activity = jiffies;
1203 static void uart_rx_dma_callback(int lch, u16 ch_status, void *data)
1208 static int serial_omap_start_rxdma(struct uart_omap_port *up)
1212 if (up->uart_dma.rx_dma_channel == -1) {
1213 pm_runtime_get_sync(&up->pdev->dev);
1214 ret = omap_request_dma(up->uart_dma.uart_dma_rx,
1216 (void *)uart_rx_dma_callback, up,
1217 &(up->uart_dma.rx_dma_channel));
1221 omap_set_dma_src_params(up->uart_dma.rx_dma_channel, 0,
1222 OMAP_DMA_AMODE_CONSTANT,
1223 up->uart_dma.uart_base, 0, 0);
1224 omap_set_dma_dest_params(up->uart_dma.rx_dma_channel, 0,
1225 OMAP_DMA_AMODE_POST_INC,
1226 up->uart_dma.rx_buf_dma_phys, 0, 0);
1227 omap_set_dma_transfer_params(up->uart_dma.rx_dma_channel,
1228 OMAP_DMA_DATA_TYPE_S8,
1229 up->uart_dma.rx_buf_size, 1,
1230 OMAP_DMA_SYNC_ELEMENT,
1231 up->uart_dma.uart_dma_rx, 0);
1233 up->uart_dma.prev_rx_dma_pos = up->uart_dma.rx_buf_dma_phys;
1234 /* FIXME: Cache maintenance needed here? */
1235 omap_start_dma(up->uart_dma.rx_dma_channel);
1236 mod_timer(&up->uart_dma.rx_timer, jiffies +
1237 usecs_to_jiffies(up->uart_dma.rx_timeout));
1238 up->uart_dma.rx_dma_used = true;
1242 static void serial_omap_continue_tx(struct uart_omap_port *up)
1244 struct circ_buf *xmit = &up->port.state->xmit;
1245 unsigned int start = up->uart_dma.tx_buf_dma_phys
1246 + (xmit->tail & (UART_XMIT_SIZE - 1));
1248 if (uart_circ_empty(xmit))
1251 up->uart_dma.tx_buf_size = uart_circ_chars_pending(xmit);
1253 * It is a circular buffer. See if the buffer has wounded back.
1254 * If yes it will have to be transferred in two separate dma
1257 if (start + up->uart_dma.tx_buf_size >=
1258 up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE)
1259 up->uart_dma.tx_buf_size =
1260 (up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE) - start;
1261 omap_set_dma_dest_params(up->uart_dma.tx_dma_channel, 0,
1262 OMAP_DMA_AMODE_CONSTANT,
1263 up->uart_dma.uart_base, 0, 0);
1264 omap_set_dma_src_params(up->uart_dma.tx_dma_channel, 0,
1265 OMAP_DMA_AMODE_POST_INC, start, 0, 0);
1266 omap_set_dma_transfer_params(up->uart_dma.tx_dma_channel,
1267 OMAP_DMA_DATA_TYPE_S8,
1268 up->uart_dma.tx_buf_size, 1,
1269 OMAP_DMA_SYNC_ELEMENT,
1270 up->uart_dma.uart_dma_tx, 0);
1271 /* FIXME: Cache maintenance needed here? */
1272 omap_start_dma(up->uart_dma.tx_dma_channel);
1275 static void uart_tx_dma_callback(int lch, u16 ch_status, void *data)
1277 struct uart_omap_port *up = (struct uart_omap_port *)data;
1278 struct circ_buf *xmit = &up->port.state->xmit;
1280 xmit->tail = (xmit->tail + up->uart_dma.tx_buf_size) & \
1281 (UART_XMIT_SIZE - 1);
1282 up->port.icount.tx += up->uart_dma.tx_buf_size;
1284 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1285 uart_write_wakeup(&up->port);
1287 if (uart_circ_empty(xmit)) {
1288 spin_lock(&(up->uart_dma.tx_lock));
1289 serial_omap_stop_tx(&up->port);
1290 up->uart_dma.tx_dma_used = false;
1291 spin_unlock(&(up->uart_dma.tx_lock));
1293 omap_stop_dma(up->uart_dma.tx_dma_channel);
1294 serial_omap_continue_tx(up);
1296 up->port_activity = jiffies;
1300 static int serial_omap_probe(struct platform_device *pdev)
1302 struct uart_omap_port *up;
1303 struct resource *mem, *irq, *dma_tx, *dma_rx;
1304 struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data;
1307 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1309 dev_err(&pdev->dev, "no mem resource?\n");
1313 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1315 dev_err(&pdev->dev, "no irq resource?\n");
1319 if (!request_mem_region(mem->start, resource_size(mem),
1320 pdev->dev.driver->name)) {
1321 dev_err(&pdev->dev, "memory region already claimed\n");
1325 dma_rx = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1331 dma_tx = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1337 up = kzalloc(sizeof(*up), GFP_KERNEL);
1340 goto do_release_region;
1342 sprintf(up->name, "OMAP UART%d", pdev->id);
1344 up->port.dev = &pdev->dev;
1345 up->port.type = PORT_OMAP;
1346 up->port.iotype = UPIO_MEM;
1347 up->port.irq = irq->start;
1349 up->port.regshift = 2;
1350 up->port.fifosize = 64;
1351 up->port.ops = &serial_omap_pops;
1352 up->port.line = pdev->id;
1354 up->port.mapbase = mem->start;
1355 up->port.membase = ioremap(mem->start, resource_size(mem));
1356 if (!up->port.membase) {
1357 dev_err(&pdev->dev, "can't ioremap UART\n");
1362 up->port.flags = omap_up_info->flags;
1363 up->port.uartclk = omap_up_info->uartclk;
1364 up->uart_dma.uart_base = mem->start;
1366 if (omap_up_info->dma_enabled) {
1367 up->uart_dma.uart_dma_tx = dma_tx->start;
1368 up->uart_dma.uart_dma_rx = dma_rx->start;
1370 up->uart_dma.rx_buf_size = 4096;
1371 up->uart_dma.rx_timeout = 2;
1372 spin_lock_init(&(up->uart_dma.tx_lock));
1373 spin_lock_init(&(up->uart_dma.rx_lock));
1374 up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE;
1375 up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE;
1378 pm_runtime_use_autosuspend(&pdev->dev);
1379 pm_runtime_set_autosuspend_delay(&pdev->dev,
1380 OMAP_UART_AUTOSUSPEND_DELAY);
1382 pm_runtime_irq_safe(&pdev->dev);
1383 pm_runtime_enable(&pdev->dev);
1384 pm_runtime_get_sync(&pdev->dev);
1387 serial_omap_add_console_port(up);
1389 ret = uart_add_one_port(&serial_omap_reg, &up->port);
1391 goto do_release_region;
1393 pm_runtime_put(&pdev->dev);
1394 platform_set_drvdata(pdev, up);
1397 dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n",
1398 pdev->id, __func__, ret);
1400 release_mem_region(mem->start, resource_size(mem));
1404 static int serial_omap_remove(struct platform_device *dev)
1406 struct uart_omap_port *up = platform_get_drvdata(dev);
1409 pm_runtime_disable(&up->pdev->dev);
1410 uart_remove_one_port(&serial_omap_reg, &up->port);
1414 platform_set_drvdata(dev, NULL);
1418 static void serial_omap_restore_context(struct uart_omap_port *up)
1420 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1421 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1422 serial_out(up, UART_EFR, UART_EFR_ECB);
1423 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1424 serial_out(up, UART_IER, 0x0);
1425 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1426 serial_out(up, UART_DLL, up->dll);
1427 serial_out(up, UART_DLM, up->dlh);
1428 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1429 serial_out(up, UART_IER, up->ier);
1430 serial_out(up, UART_FCR, up->fcr);
1431 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1432 serial_out(up, UART_MCR, up->mcr);
1433 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1434 serial_out(up, UART_OMAP_SCR, up->scr);
1435 serial_out(up, UART_EFR, up->efr);
1436 serial_out(up, UART_LCR, up->lcr);
1437 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1440 #ifdef CONFIG_PM_RUNTIME
1441 static int serial_omap_runtime_suspend(struct device *dev)
1443 struct uart_omap_port *up = dev_get_drvdata(dev);
1444 struct omap_uart_port_info *pdata = dev->platform_data;
1449 if (pdata->get_context_loss_count)
1450 up->context_loss_cnt = pdata->get_context_loss_count(dev);
1455 static int serial_omap_runtime_resume(struct device *dev)
1457 struct uart_omap_port *up = dev_get_drvdata(dev);
1458 struct omap_uart_port_info *pdata = dev->platform_data;
1461 if (pdata->get_context_loss_count) {
1462 u32 loss_cnt = pdata->get_context_loss_count(dev);
1464 if (up->context_loss_cnt != loss_cnt)
1465 serial_omap_restore_context(up);
1473 static const struct dev_pm_ops serial_omap_dev_pm_ops = {
1474 SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
1475 SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
1476 serial_omap_runtime_resume, NULL)
1479 static struct platform_driver serial_omap_driver = {
1480 .probe = serial_omap_probe,
1481 .remove = serial_omap_remove,
1483 .name = DRIVER_NAME,
1484 .pm = &serial_omap_dev_pm_ops,
1488 static int __init serial_omap_init(void)
1492 ret = uart_register_driver(&serial_omap_reg);
1495 ret = platform_driver_register(&serial_omap_driver);
1497 uart_unregister_driver(&serial_omap_reg);
1501 static void __exit serial_omap_exit(void)
1503 platform_driver_unregister(&serial_omap_driver);
1504 uart_unregister_driver(&serial_omap_reg);
1507 module_init(serial_omap_init);
1508 module_exit(serial_omap_exit);
1510 MODULE_DESCRIPTION("OMAP High Speed UART driver");
1511 MODULE_LICENSE("GPL");
1512 MODULE_AUTHOR("Texas Instruments Inc");