2 * Driver for OMAP-UART controller.
3 * Based on drivers/serial/8250.c
5 * Copyright (C) 2010 Texas Instruments.
8 * Govindraj R <govindraj.raja@ti.com>
9 * Thara Gopinath <thara@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * Note: This driver is made separate from 8250 driver as we cannot
17 * over load 8250 driver with omap platform specific configuration for
18 * features like DMA, it makes easier to implement features like DMA and
19 * hardware flow control and software flow control configuration with
20 * this driver as required for the omap-platform.
23 #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/console.h>
30 #include <linux/serial_reg.h>
31 #include <linux/delay.h>
32 #include <linux/slab.h>
33 #include <linux/tty.h>
34 #include <linux/tty_flip.h>
35 #include <linux/platform_device.h>
37 #include <linux/clk.h>
38 #include <linux/serial_core.h>
39 #include <linux/irq.h>
40 #include <linux/pm_runtime.h>
42 #include <linux/gpio.h>
43 #include <linux/pinctrl/consumer.h>
44 #include <linux/platform_data/serial-omap.h>
46 #define OMAP_MAX_HSUART_PORTS 6
48 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
50 #define OMAP_UART_REV_42 0x0402
51 #define OMAP_UART_REV_46 0x0406
52 #define OMAP_UART_REV_52 0x0502
53 #define OMAP_UART_REV_63 0x0603
55 #define UART_ERRATA_i202_MDR1_ACCESS BIT(0)
56 #define UART_ERRATA_i291_DMA_FORCEIDLE BIT(1)
58 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
60 /* SCR register bitmasks */
61 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
62 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6)
63 #define OMAP_UART_SCR_TX_EMPTY (1 << 3)
65 /* FCR register bitmasks */
66 #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6)
67 #define OMAP_UART_FCR_TX_FIFO_TRIG_MASK (0x3 << 4)
69 /* MVR register bitmasks */
70 #define OMAP_UART_MVR_SCHEME_SHIFT 30
72 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0
73 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
74 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f
76 #define OMAP_UART_MVR_MAJ_MASK 0x700
77 #define OMAP_UART_MVR_MAJ_SHIFT 8
78 #define OMAP_UART_MVR_MIN_MASK 0x3f
80 #define OMAP_UART_DMA_CH_FREE -1
82 #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
83 #define OMAP_MODE13X_SPEED 230400
86 * Enable module level wakeup in WER reg
88 #define OMAP_UART_WER_MOD_WKUP 0X7F
90 /* Enable XON/XOFF flow control on output */
91 #define OMAP_UART_SW_TX 0x08
93 /* Enable XON/XOFF flow control on input */
94 #define OMAP_UART_SW_RX 0x02
96 #define OMAP_UART_SW_CLR 0xF0
98 #define OMAP_UART_TCR_TRIG 0x0F
100 struct uart_omap_dma {
105 dma_addr_t rx_buf_dma_phys;
106 dma_addr_t tx_buf_dma_phys;
107 unsigned int uart_base;
109 * Buffer for rx dma.It is not required for tx because the buffer
110 * comes from port structure.
112 unsigned char *rx_buf;
113 unsigned int prev_rx_dma_pos;
119 /* timer to poll activity on rx dma */
120 struct timer_list rx_timer;
121 unsigned int rx_buf_size;
122 unsigned int rx_poll_rate;
123 unsigned int rx_timeout;
126 struct uart_omap_port {
127 struct uart_port port;
128 struct uart_omap_dma uart_dma;
143 * Some bits in registers are cleared on a read, so they must
144 * be saved whenever the register is read but the bits will not
145 * be immediately processed.
147 unsigned int lsr_break_flag;
148 unsigned char msr_saved_flags;
150 unsigned long port_activity;
151 int context_loss_cnt;
159 struct pm_qos_request pm_qos_request;
162 struct work_struct qos_work;
163 struct pinctrl *pins;
166 #define to_uart_omap_port(p) ((container_of((p), struct uart_omap_port, port)))
168 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
170 /* Forward declaration of functions */
171 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
173 static struct workqueue_struct *serial_omap_uart_wq;
175 static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
177 offset <<= up->port.regshift;
178 return readw(up->port.membase + offset);
181 static inline void serial_out(struct uart_omap_port *up, int offset, int value)
183 offset <<= up->port.regshift;
184 writew(value, up->port.membase + offset);
187 static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
189 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
190 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
191 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
192 serial_out(up, UART_FCR, 0);
195 static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
197 struct omap_uart_port_info *pdata = up->dev->platform_data;
199 if (!pdata || !pdata->get_context_loss_count)
202 return pdata->get_context_loss_count(up->dev);
205 static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
207 struct omap_uart_port_info *pdata = up->dev->platform_data;
209 if (!pdata || !pdata->enable_wakeup)
212 pdata->enable_wakeup(up->dev, enable);
216 * serial_omap_baud_is_mode16 - check if baud rate is MODE16X
217 * @port: uart port info
218 * @baud: baudrate for which mode needs to be determined
220 * Returns true if baud rate is MODE16X and false if MODE13X
221 * Original table in OMAP TRM named "UART Mode Baud Rates, Divisor Values,
222 * and Error Rates" determines modes not for all common baud rates.
223 * E.g. for 1000000 baud rate mode must be 16x, but according to that
224 * table it's determined as 13x.
227 serial_omap_baud_is_mode16(struct uart_port *port, unsigned int baud)
229 unsigned int n13 = port->uartclk / (13 * baud);
230 unsigned int n16 = port->uartclk / (16 * baud);
231 int baudAbsDiff13 = baud - (port->uartclk / (13 * n13));
232 int baudAbsDiff16 = baud - (port->uartclk / (16 * n16));
233 if(baudAbsDiff13 < 0)
234 baudAbsDiff13 = -baudAbsDiff13;
235 if(baudAbsDiff16 < 0)
236 baudAbsDiff16 = -baudAbsDiff16;
238 return (baudAbsDiff13 > baudAbsDiff16);
242 * serial_omap_get_divisor - calculate divisor value
243 * @port: uart port info
244 * @baud: baudrate for which divisor needs to be calculated.
247 serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
249 unsigned int divisor;
251 if (!serial_omap_baud_is_mode16(port, baud))
255 return port->uartclk/(baud * divisor);
258 static void serial_omap_enable_ms(struct uart_port *port)
260 struct uart_omap_port *up = to_uart_omap_port(port);
262 dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
264 pm_runtime_get_sync(up->dev);
265 up->ier |= UART_IER_MSI;
266 serial_out(up, UART_IER, up->ier);
267 pm_runtime_mark_last_busy(up->dev);
268 pm_runtime_put_autosuspend(up->dev);
271 static void serial_omap_stop_tx(struct uart_port *port)
273 struct uart_omap_port *up = to_uart_omap_port(port);
275 pm_runtime_get_sync(up->dev);
276 if (up->ier & UART_IER_THRI) {
277 up->ier &= ~UART_IER_THRI;
278 serial_out(up, UART_IER, up->ier);
281 pm_runtime_mark_last_busy(up->dev);
282 pm_runtime_put_autosuspend(up->dev);
285 static void serial_omap_stop_rx(struct uart_port *port)
287 struct uart_omap_port *up = to_uart_omap_port(port);
289 pm_runtime_get_sync(up->dev);
290 up->ier &= ~UART_IER_RLSI;
291 up->port.read_status_mask &= ~UART_LSR_DR;
292 serial_out(up, UART_IER, up->ier);
293 pm_runtime_mark_last_busy(up->dev);
294 pm_runtime_put_autosuspend(up->dev);
297 static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
299 struct circ_buf *xmit = &up->port.state->xmit;
302 if (up->port.x_char) {
303 serial_out(up, UART_TX, up->port.x_char);
304 up->port.icount.tx++;
308 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
309 serial_omap_stop_tx(&up->port);
312 count = up->port.fifosize / 4;
314 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
315 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
316 up->port.icount.tx++;
317 if (uart_circ_empty(xmit))
319 } while (--count > 0);
321 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
322 spin_unlock(&up->port.lock);
323 uart_write_wakeup(&up->port);
324 spin_lock(&up->port.lock);
327 if (uart_circ_empty(xmit))
328 serial_omap_stop_tx(&up->port);
331 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
333 if (!(up->ier & UART_IER_THRI)) {
334 up->ier |= UART_IER_THRI;
335 serial_out(up, UART_IER, up->ier);
339 static void serial_omap_start_tx(struct uart_port *port)
341 struct uart_omap_port *up = to_uart_omap_port(port);
343 pm_runtime_get_sync(up->dev);
344 serial_omap_enable_ier_thri(up);
345 pm_runtime_mark_last_busy(up->dev);
346 pm_runtime_put_autosuspend(up->dev);
349 static void serial_omap_throttle(struct uart_port *port)
351 struct uart_omap_port *up = to_uart_omap_port(port);
354 pm_runtime_get_sync(up->dev);
355 spin_lock_irqsave(&up->port.lock, flags);
356 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
357 serial_out(up, UART_IER, up->ier);
358 spin_unlock_irqrestore(&up->port.lock, flags);
359 pm_runtime_mark_last_busy(up->dev);
360 pm_runtime_put_autosuspend(up->dev);
363 static void serial_omap_unthrottle(struct uart_port *port)
365 struct uart_omap_port *up = to_uart_omap_port(port);
368 pm_runtime_get_sync(up->dev);
369 spin_lock_irqsave(&up->port.lock, flags);
370 up->ier |= UART_IER_RLSI | UART_IER_RDI;
371 serial_out(up, UART_IER, up->ier);
372 spin_unlock_irqrestore(&up->port.lock, flags);
373 pm_runtime_mark_last_busy(up->dev);
374 pm_runtime_put_autosuspend(up->dev);
377 static unsigned int check_modem_status(struct uart_omap_port *up)
381 status = serial_in(up, UART_MSR);
382 status |= up->msr_saved_flags;
383 up->msr_saved_flags = 0;
384 if ((status & UART_MSR_ANY_DELTA) == 0)
387 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
388 up->port.state != NULL) {
389 if (status & UART_MSR_TERI)
390 up->port.icount.rng++;
391 if (status & UART_MSR_DDSR)
392 up->port.icount.dsr++;
393 if (status & UART_MSR_DDCD)
394 uart_handle_dcd_change
395 (&up->port, status & UART_MSR_DCD);
396 if (status & UART_MSR_DCTS)
397 uart_handle_cts_change
398 (&up->port, status & UART_MSR_CTS);
399 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
405 static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)
408 unsigned char ch = 0;
410 if (likely(lsr & UART_LSR_DR))
411 ch = serial_in(up, UART_RX);
413 up->port.icount.rx++;
416 if (lsr & UART_LSR_BI) {
418 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
419 up->port.icount.brk++;
421 * We do the SysRQ and SAK checking
422 * here because otherwise the break
423 * may get masked by ignore_status_mask
424 * or read_status_mask.
426 if (uart_handle_break(&up->port))
431 if (lsr & UART_LSR_PE) {
433 up->port.icount.parity++;
436 if (lsr & UART_LSR_FE) {
438 up->port.icount.frame++;
441 if (lsr & UART_LSR_OE)
442 up->port.icount.overrun++;
444 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
445 if (up->port.line == up->port.cons->index) {
446 /* Recover the break flag from console xmit */
447 lsr |= up->lsr_break_flag;
450 uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);
453 static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
455 unsigned char ch = 0;
458 if (!(lsr & UART_LSR_DR))
461 ch = serial_in(up, UART_RX);
463 up->port.icount.rx++;
465 if (uart_handle_sysrq_char(&up->port, ch))
468 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
472 * serial_omap_irq() - This handles the interrupt from one port
473 * @irq: uart port irq number
474 * @dev_id: uart port info
476 static irqreturn_t serial_omap_irq(int irq, void *dev_id)
478 struct uart_omap_port *up = dev_id;
479 unsigned int iir, lsr;
481 irqreturn_t ret = IRQ_NONE;
484 spin_lock(&up->port.lock);
485 pm_runtime_get_sync(up->dev);
488 iir = serial_in(up, UART_IIR);
489 if (iir & UART_IIR_NO_INT)
493 lsr = serial_in(up, UART_LSR);
495 /* extract IRQ type from IIR register */
500 check_modem_status(up);
503 transmit_chars(up, lsr);
505 case UART_IIR_RX_TIMEOUT:
508 serial_omap_rdi(up, lsr);
511 serial_omap_rlsi(up, lsr);
513 case UART_IIR_CTS_RTS_DSR:
514 /* simply try again */
521 } while (!(iir & UART_IIR_NO_INT) && max_count--);
523 spin_unlock(&up->port.lock);
525 tty_flip_buffer_push(&up->port.state->port);
527 pm_runtime_mark_last_busy(up->dev);
528 pm_runtime_put_autosuspend(up->dev);
529 up->port_activity = jiffies;
534 static unsigned int serial_omap_tx_empty(struct uart_port *port)
536 struct uart_omap_port *up = to_uart_omap_port(port);
537 unsigned long flags = 0;
538 unsigned int ret = 0;
540 pm_runtime_get_sync(up->dev);
541 dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
542 spin_lock_irqsave(&up->port.lock, flags);
543 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
544 spin_unlock_irqrestore(&up->port.lock, flags);
545 pm_runtime_mark_last_busy(up->dev);
546 pm_runtime_put_autosuspend(up->dev);
550 static unsigned int serial_omap_get_mctrl(struct uart_port *port)
552 struct uart_omap_port *up = to_uart_omap_port(port);
554 unsigned int ret = 0;
556 pm_runtime_get_sync(up->dev);
557 status = check_modem_status(up);
558 pm_runtime_mark_last_busy(up->dev);
559 pm_runtime_put_autosuspend(up->dev);
561 dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
563 if (status & UART_MSR_DCD)
565 if (status & UART_MSR_RI)
567 if (status & UART_MSR_DSR)
569 if (status & UART_MSR_CTS)
574 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
576 struct uart_omap_port *up = to_uart_omap_port(port);
577 unsigned char mcr = 0, old_mcr;
579 dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
580 if (mctrl & TIOCM_RTS)
582 if (mctrl & TIOCM_DTR)
584 if (mctrl & TIOCM_OUT1)
585 mcr |= UART_MCR_OUT1;
586 if (mctrl & TIOCM_OUT2)
587 mcr |= UART_MCR_OUT2;
588 if (mctrl & TIOCM_LOOP)
589 mcr |= UART_MCR_LOOP;
591 pm_runtime_get_sync(up->dev);
592 old_mcr = serial_in(up, UART_MCR);
593 old_mcr &= ~(UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_OUT1 |
594 UART_MCR_DTR | UART_MCR_RTS);
595 up->mcr = old_mcr | mcr;
596 serial_out(up, UART_MCR, up->mcr);
597 pm_runtime_mark_last_busy(up->dev);
598 pm_runtime_put_autosuspend(up->dev);
600 if (gpio_is_valid(up->DTR_gpio) &&
601 !!(mctrl & TIOCM_DTR) != up->DTR_active) {
602 up->DTR_active = !up->DTR_active;
603 if (gpio_cansleep(up->DTR_gpio))
604 schedule_work(&up->qos_work);
606 gpio_set_value(up->DTR_gpio,
607 up->DTR_active != up->DTR_inverted);
611 static void serial_omap_break_ctl(struct uart_port *port, int break_state)
613 struct uart_omap_port *up = to_uart_omap_port(port);
614 unsigned long flags = 0;
616 dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
617 pm_runtime_get_sync(up->dev);
618 spin_lock_irqsave(&up->port.lock, flags);
619 if (break_state == -1)
620 up->lcr |= UART_LCR_SBC;
622 up->lcr &= ~UART_LCR_SBC;
623 serial_out(up, UART_LCR, up->lcr);
624 spin_unlock_irqrestore(&up->port.lock, flags);
625 pm_runtime_mark_last_busy(up->dev);
626 pm_runtime_put_autosuspend(up->dev);
629 static int serial_omap_startup(struct uart_port *port)
631 struct uart_omap_port *up = to_uart_omap_port(port);
632 unsigned long flags = 0;
638 retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
643 dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
645 pm_runtime_get_sync(up->dev);
647 * Clear the FIFO buffers and disable them.
648 * (they will be reenabled in set_termios())
650 serial_omap_clear_fifos(up);
651 /* For Hardware flow control */
652 serial_out(up, UART_MCR, UART_MCR_RTS);
655 * Clear the interrupt registers.
657 (void) serial_in(up, UART_LSR);
658 if (serial_in(up, UART_LSR) & UART_LSR_DR)
659 (void) serial_in(up, UART_RX);
660 (void) serial_in(up, UART_IIR);
661 (void) serial_in(up, UART_MSR);
664 * Now, initialize the UART
666 serial_out(up, UART_LCR, UART_LCR_WLEN8);
667 spin_lock_irqsave(&up->port.lock, flags);
669 * Most PC uarts need OUT2 raised to enable interrupts.
671 up->port.mctrl |= TIOCM_OUT2;
672 serial_omap_set_mctrl(&up->port, up->port.mctrl);
673 spin_unlock_irqrestore(&up->port.lock, flags);
675 up->msr_saved_flags = 0;
677 * Finally, enable interrupts. Note: Modem status interrupts
678 * are set via set_termios(), which will be occurring imminently
679 * anyway, so we don't enable them here.
681 up->ier = UART_IER_RLSI | UART_IER_RDI;
682 serial_out(up, UART_IER, up->ier);
684 /* Enable module level wake up */
685 serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP);
687 pm_runtime_mark_last_busy(up->dev);
688 pm_runtime_put_autosuspend(up->dev);
689 up->port_activity = jiffies;
693 static void serial_omap_shutdown(struct uart_port *port)
695 struct uart_omap_port *up = to_uart_omap_port(port);
696 unsigned long flags = 0;
698 dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
700 pm_runtime_get_sync(up->dev);
702 * Disable interrupts from this port
705 serial_out(up, UART_IER, 0);
707 spin_lock_irqsave(&up->port.lock, flags);
708 up->port.mctrl &= ~TIOCM_OUT2;
709 serial_omap_set_mctrl(&up->port, up->port.mctrl);
710 spin_unlock_irqrestore(&up->port.lock, flags);
713 * Disable break condition and FIFOs
715 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
716 serial_omap_clear_fifos(up);
719 * Read data port to reset things, and then free the irq
721 if (serial_in(up, UART_LSR) & UART_LSR_DR)
722 (void) serial_in(up, UART_RX);
724 pm_runtime_mark_last_busy(up->dev);
725 pm_runtime_put_autosuspend(up->dev);
726 free_irq(up->port.irq, up);
729 static void serial_omap_uart_qos_work(struct work_struct *work)
731 struct uart_omap_port *up = container_of(work, struct uart_omap_port,
734 pm_qos_update_request(&up->pm_qos_request, up->latency);
735 if (gpio_is_valid(up->DTR_gpio))
736 gpio_set_value_cansleep(up->DTR_gpio,
737 up->DTR_active != up->DTR_inverted);
741 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
742 struct ktermios *old)
744 struct uart_omap_port *up = to_uart_omap_port(port);
745 unsigned char cval = 0;
746 unsigned long flags = 0;
747 unsigned int baud, quot;
749 switch (termios->c_cflag & CSIZE) {
751 cval = UART_LCR_WLEN5;
754 cval = UART_LCR_WLEN6;
757 cval = UART_LCR_WLEN7;
761 cval = UART_LCR_WLEN8;
765 if (termios->c_cflag & CSTOPB)
766 cval |= UART_LCR_STOP;
767 if (termios->c_cflag & PARENB)
768 cval |= UART_LCR_PARITY;
769 if (!(termios->c_cflag & PARODD))
770 cval |= UART_LCR_EPAR;
771 if (termios->c_cflag & CMSPAR)
772 cval |= UART_LCR_SPAR;
775 * Ask the core to calculate the divisor for us.
778 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
779 quot = serial_omap_get_divisor(port, baud);
781 /* calculate wakeup latency constraint */
782 up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8);
783 up->latency = up->calc_latency;
784 schedule_work(&up->qos_work);
786 up->dll = quot & 0xff;
788 up->mdr1 = UART_OMAP_MDR1_DISABLE;
790 up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
791 UART_FCR_ENABLE_FIFO;
794 * Ok, we're now changing the port state. Do it with
795 * interrupts disabled.
797 pm_runtime_get_sync(up->dev);
798 spin_lock_irqsave(&up->port.lock, flags);
801 * Update the per-port timeout.
803 uart_update_timeout(port, termios->c_cflag, baud);
805 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
806 if (termios->c_iflag & INPCK)
807 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
808 if (termios->c_iflag & (BRKINT | PARMRK))
809 up->port.read_status_mask |= UART_LSR_BI;
812 * Characters to ignore
814 up->port.ignore_status_mask = 0;
815 if (termios->c_iflag & IGNPAR)
816 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
817 if (termios->c_iflag & IGNBRK) {
818 up->port.ignore_status_mask |= UART_LSR_BI;
820 * If we're ignoring parity and break indicators,
821 * ignore overruns too (for real raw support).
823 if (termios->c_iflag & IGNPAR)
824 up->port.ignore_status_mask |= UART_LSR_OE;
828 * ignore all characters if CREAD is not set
830 if ((termios->c_cflag & CREAD) == 0)
831 up->port.ignore_status_mask |= UART_LSR_DR;
834 * Modem status interrupts
836 up->ier &= ~UART_IER_MSI;
837 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
838 up->ier |= UART_IER_MSI;
839 serial_out(up, UART_IER, up->ier);
840 serial_out(up, UART_LCR, cval); /* reset DLAB */
844 /* FIFOs and DMA Settings */
846 /* FCR can be changed only when the
847 * baud clock is not running
848 * DLL_REG and DLH_REG set to 0.
850 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
851 serial_out(up, UART_DLL, 0);
852 serial_out(up, UART_DLM, 0);
853 serial_out(up, UART_LCR, 0);
855 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
857 up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB;
858 up->efr &= ~UART_EFR_SCD;
859 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
861 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
862 up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR;
863 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
864 /* FIFO ENABLE, DMA MODE */
866 up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
868 * NOTE: Setting OMAP_UART_SCR_RX_TRIG_GRANU1_MASK
869 * sets Enables the granularity of 1 for TRIGGER RX
870 * level. Along with setting RX FIFO trigger level
871 * to 1 (as noted below, 16 characters) and TLR[3:0]
872 * to zero this will result RX FIFO threshold level
873 * to 1 character, instead of 16 as noted in comment
877 /* Set receive FIFO threshold to 16 characters and
878 * transmit FIFO threshold to 16 spaces
880 up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
881 up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK;
882 up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 |
883 UART_FCR_ENABLE_FIFO;
885 serial_out(up, UART_FCR, up->fcr);
886 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
888 serial_out(up, UART_OMAP_SCR, up->scr);
890 /* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */
891 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
892 serial_out(up, UART_MCR, up->mcr);
893 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
894 serial_out(up, UART_EFR, up->efr);
895 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
897 /* Protocol, Baud Rate, and Interrupt Settings */
899 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
900 serial_omap_mdr1_errataset(up, up->mdr1);
902 serial_out(up, UART_OMAP_MDR1, up->mdr1);
904 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
905 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
907 serial_out(up, UART_LCR, 0);
908 serial_out(up, UART_IER, 0);
909 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
911 serial_out(up, UART_DLL, up->dll); /* LS of divisor */
912 serial_out(up, UART_DLM, up->dlh); /* MS of divisor */
914 serial_out(up, UART_LCR, 0);
915 serial_out(up, UART_IER, up->ier);
916 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
918 serial_out(up, UART_EFR, up->efr);
919 serial_out(up, UART_LCR, cval);
921 if (!serial_omap_baud_is_mode16(port, baud))
922 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
924 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
926 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
927 serial_omap_mdr1_errataset(up, up->mdr1);
929 serial_out(up, UART_OMAP_MDR1, up->mdr1);
931 /* Configure flow control */
932 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
934 /* XON1/XOFF1 accessible mode B, TCRTLR=0, ECB=0 */
935 serial_out(up, UART_XON1, termios->c_cc[VSTART]);
936 serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
938 /* Enable access to TCR/TLR */
939 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
940 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
941 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
943 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
945 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
946 /* Enable AUTORTS and AUTOCTS */
947 up->efr |= UART_EFR_CTS | UART_EFR_RTS;
949 /* Ensure MCR RTS is asserted */
950 up->mcr |= UART_MCR_RTS;
952 /* Disable AUTORTS and AUTOCTS */
953 up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS);
956 if (up->port.flags & UPF_SOFT_FLOW) {
957 /* clear SW control mode bits */
958 up->efr &= OMAP_UART_SW_CLR;
962 * Enable XON/XOFF flow control on input.
963 * Receiver compares XON1, XOFF1.
965 if (termios->c_iflag & IXON)
966 up->efr |= OMAP_UART_SW_RX;
970 * Enable XON/XOFF flow control on output.
971 * Transmit XON1, XOFF1
973 if (termios->c_iflag & IXOFF)
974 up->efr |= OMAP_UART_SW_TX;
978 * Enable any character to restart output.
979 * Operation resumes after receiving any
980 * character after recognition of the XOFF character
982 if (termios->c_iflag & IXANY)
983 up->mcr |= UART_MCR_XONANY;
985 up->mcr &= ~UART_MCR_XONANY;
987 serial_out(up, UART_MCR, up->mcr);
988 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
989 serial_out(up, UART_EFR, up->efr);
990 serial_out(up, UART_LCR, up->lcr);
992 serial_omap_set_mctrl(&up->port, up->port.mctrl);
994 spin_unlock_irqrestore(&up->port.lock, flags);
995 pm_runtime_mark_last_busy(up->dev);
996 pm_runtime_put_autosuspend(up->dev);
997 dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
1000 static int serial_omap_set_wake(struct uart_port *port, unsigned int state)
1002 struct uart_omap_port *up = to_uart_omap_port(port);
1004 serial_omap_enable_wakeup(up, state);
1010 serial_omap_pm(struct uart_port *port, unsigned int state,
1011 unsigned int oldstate)
1013 struct uart_omap_port *up = to_uart_omap_port(port);
1016 dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
1018 pm_runtime_get_sync(up->dev);
1019 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1020 efr = serial_in(up, UART_EFR);
1021 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
1022 serial_out(up, UART_LCR, 0);
1024 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
1025 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1026 serial_out(up, UART_EFR, efr);
1027 serial_out(up, UART_LCR, 0);
1029 if (!device_may_wakeup(up->dev)) {
1031 pm_runtime_forbid(up->dev);
1033 pm_runtime_allow(up->dev);
1036 pm_runtime_mark_last_busy(up->dev);
1037 pm_runtime_put_autosuspend(up->dev);
1040 static void serial_omap_release_port(struct uart_port *port)
1042 dev_dbg(port->dev, "serial_omap_release_port+\n");
1045 static int serial_omap_request_port(struct uart_port *port)
1047 dev_dbg(port->dev, "serial_omap_request_port+\n");
1051 static void serial_omap_config_port(struct uart_port *port, int flags)
1053 struct uart_omap_port *up = to_uart_omap_port(port);
1055 dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
1057 up->port.type = PORT_OMAP;
1058 up->port.flags |= UPF_SOFT_FLOW | UPF_HARD_FLOW;
1062 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
1064 /* we don't want the core code to modify any port params */
1065 dev_dbg(port->dev, "serial_omap_verify_port+\n");
1070 serial_omap_type(struct uart_port *port)
1072 struct uart_omap_port *up = to_uart_omap_port(port);
1074 dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
1078 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1080 static inline void wait_for_xmitr(struct uart_omap_port *up)
1082 unsigned int status, tmout = 10000;
1084 /* Wait up to 10ms for the character(s) to be sent. */
1086 status = serial_in(up, UART_LSR);
1088 if (status & UART_LSR_BI)
1089 up->lsr_break_flag = UART_LSR_BI;
1094 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
1096 /* Wait up to 1s for flow control if necessary */
1097 if (up->port.flags & UPF_CONS_FLOW) {
1099 for (tmout = 1000000; tmout; tmout--) {
1100 unsigned int msr = serial_in(up, UART_MSR);
1102 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1103 if (msr & UART_MSR_CTS)
1111 #ifdef CONFIG_CONSOLE_POLL
1113 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
1115 struct uart_omap_port *up = to_uart_omap_port(port);
1117 pm_runtime_get_sync(up->dev);
1119 serial_out(up, UART_TX, ch);
1120 pm_runtime_mark_last_busy(up->dev);
1121 pm_runtime_put_autosuspend(up->dev);
1124 static int serial_omap_poll_get_char(struct uart_port *port)
1126 struct uart_omap_port *up = to_uart_omap_port(port);
1127 unsigned int status;
1129 pm_runtime_get_sync(up->dev);
1130 status = serial_in(up, UART_LSR);
1131 if (!(status & UART_LSR_DR)) {
1132 status = NO_POLL_CHAR;
1136 status = serial_in(up, UART_RX);
1139 pm_runtime_mark_last_busy(up->dev);
1140 pm_runtime_put_autosuspend(up->dev);
1145 #endif /* CONFIG_CONSOLE_POLL */
1147 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
1149 static struct uart_omap_port *serial_omap_console_ports[OMAP_MAX_HSUART_PORTS];
1151 static struct uart_driver serial_omap_reg;
1153 static void serial_omap_console_putchar(struct uart_port *port, int ch)
1155 struct uart_omap_port *up = to_uart_omap_port(port);
1158 serial_out(up, UART_TX, ch);
1162 serial_omap_console_write(struct console *co, const char *s,
1165 struct uart_omap_port *up = serial_omap_console_ports[co->index];
1166 unsigned long flags;
1170 pm_runtime_get_sync(up->dev);
1172 local_irq_save(flags);
1175 else if (oops_in_progress)
1176 locked = spin_trylock(&up->port.lock);
1178 spin_lock(&up->port.lock);
1181 * First save the IER then disable the interrupts
1183 ier = serial_in(up, UART_IER);
1184 serial_out(up, UART_IER, 0);
1186 uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1189 * Finally, wait for transmitter to become empty
1190 * and restore the IER
1193 serial_out(up, UART_IER, ier);
1195 * The receive handling will happen properly because the
1196 * receive ready bit will still be set; it is not cleared
1197 * on read. However, modem control will not, we must
1198 * call it if we have saved something in the saved flags
1199 * while processing with interrupts off.
1201 if (up->msr_saved_flags)
1202 check_modem_status(up);
1204 pm_runtime_mark_last_busy(up->dev);
1205 pm_runtime_put_autosuspend(up->dev);
1207 spin_unlock(&up->port.lock);
1208 local_irq_restore(flags);
1212 serial_omap_console_setup(struct console *co, char *options)
1214 struct uart_omap_port *up;
1220 if (serial_omap_console_ports[co->index] == NULL)
1222 up = serial_omap_console_ports[co->index];
1225 uart_parse_options(options, &baud, &parity, &bits, &flow);
1227 return uart_set_options(&up->port, co, baud, parity, bits, flow);
1230 static struct console serial_omap_console = {
1231 .name = OMAP_SERIAL_NAME,
1232 .write = serial_omap_console_write,
1233 .device = uart_console_device,
1234 .setup = serial_omap_console_setup,
1235 .flags = CON_PRINTBUFFER,
1237 .data = &serial_omap_reg,
1240 static void serial_omap_add_console_port(struct uart_omap_port *up)
1242 serial_omap_console_ports[up->port.line] = up;
1245 #define OMAP_CONSOLE (&serial_omap_console)
1249 #define OMAP_CONSOLE NULL
1251 static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1256 static struct uart_ops serial_omap_pops = {
1257 .tx_empty = serial_omap_tx_empty,
1258 .set_mctrl = serial_omap_set_mctrl,
1259 .get_mctrl = serial_omap_get_mctrl,
1260 .stop_tx = serial_omap_stop_tx,
1261 .start_tx = serial_omap_start_tx,
1262 .throttle = serial_omap_throttle,
1263 .unthrottle = serial_omap_unthrottle,
1264 .stop_rx = serial_omap_stop_rx,
1265 .enable_ms = serial_omap_enable_ms,
1266 .break_ctl = serial_omap_break_ctl,
1267 .startup = serial_omap_startup,
1268 .shutdown = serial_omap_shutdown,
1269 .set_termios = serial_omap_set_termios,
1270 .pm = serial_omap_pm,
1271 .set_wake = serial_omap_set_wake,
1272 .type = serial_omap_type,
1273 .release_port = serial_omap_release_port,
1274 .request_port = serial_omap_request_port,
1275 .config_port = serial_omap_config_port,
1276 .verify_port = serial_omap_verify_port,
1277 #ifdef CONFIG_CONSOLE_POLL
1278 .poll_put_char = serial_omap_poll_put_char,
1279 .poll_get_char = serial_omap_poll_get_char,
1283 static struct uart_driver serial_omap_reg = {
1284 .owner = THIS_MODULE,
1285 .driver_name = "OMAP-SERIAL",
1286 .dev_name = OMAP_SERIAL_NAME,
1287 .nr = OMAP_MAX_HSUART_PORTS,
1288 .cons = OMAP_CONSOLE,
1291 #ifdef CONFIG_PM_SLEEP
1292 static int serial_omap_suspend(struct device *dev)
1294 struct uart_omap_port *up = dev_get_drvdata(dev);
1296 uart_suspend_port(&serial_omap_reg, &up->port);
1297 flush_work(&up->qos_work);
1302 static int serial_omap_resume(struct device *dev)
1304 struct uart_omap_port *up = dev_get_drvdata(dev);
1306 uart_resume_port(&serial_omap_reg, &up->port);
1312 static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
1315 u16 revision, major, minor;
1317 mvr = serial_in(up, UART_OMAP_MVER);
1319 /* Check revision register scheme */
1320 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
1323 case 0: /* Legacy Scheme: OMAP2/3 */
1324 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
1325 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
1326 OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
1327 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
1330 /* New Scheme: OMAP4+ */
1331 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
1332 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
1333 OMAP_UART_MVR_MAJ_SHIFT;
1334 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
1338 "Unknown %s revision, defaulting to highest\n",
1340 /* highest possible revision */
1345 /* normalize revision for the driver */
1346 revision = UART_BUILD_REVISION(major, minor);
1349 case OMAP_UART_REV_46:
1350 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1351 UART_ERRATA_i291_DMA_FORCEIDLE);
1353 case OMAP_UART_REV_52:
1354 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1355 UART_ERRATA_i291_DMA_FORCEIDLE);
1357 case OMAP_UART_REV_63:
1358 up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
1365 static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
1367 struct omap_uart_port_info *omap_up_info;
1369 omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
1371 return NULL; /* out of memory */
1373 of_property_read_u32(dev->of_node, "clock-frequency",
1374 &omap_up_info->uartclk);
1375 return omap_up_info;
1378 static int serial_omap_probe(struct platform_device *pdev)
1380 struct uart_omap_port *up;
1381 struct resource *mem, *irq;
1382 struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data;
1385 if (pdev->dev.of_node)
1386 omap_up_info = of_get_uart_port_info(&pdev->dev);
1388 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1390 dev_err(&pdev->dev, "no mem resource?\n");
1394 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1396 dev_err(&pdev->dev, "no irq resource?\n");
1400 if (!devm_request_mem_region(&pdev->dev, mem->start, resource_size(mem),
1401 pdev->dev.driver->name)) {
1402 dev_err(&pdev->dev, "memory region already claimed\n");
1406 if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1407 omap_up_info->DTR_present) {
1408 ret = gpio_request(omap_up_info->DTR_gpio, "omap-serial");
1411 ret = gpio_direction_output(omap_up_info->DTR_gpio,
1412 omap_up_info->DTR_inverted);
1417 up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
1421 if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1422 omap_up_info->DTR_present) {
1423 up->DTR_gpio = omap_up_info->DTR_gpio;
1424 up->DTR_inverted = omap_up_info->DTR_inverted;
1426 up->DTR_gpio = -EINVAL;
1429 up->dev = &pdev->dev;
1430 up->port.dev = &pdev->dev;
1431 up->port.type = PORT_OMAP;
1432 up->port.iotype = UPIO_MEM;
1433 up->port.irq = irq->start;
1435 up->port.regshift = 2;
1436 up->port.fifosize = 64;
1437 up->port.ops = &serial_omap_pops;
1439 if (pdev->dev.of_node)
1440 up->port.line = of_alias_get_id(pdev->dev.of_node, "serial");
1442 up->port.line = pdev->id;
1444 if (up->port.line < 0) {
1445 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
1451 up->pins = devm_pinctrl_get_select_default(&pdev->dev);
1452 if (IS_ERR(up->pins)) {
1453 dev_warn(&pdev->dev, "did not get pins for uart%i error: %li\n",
1454 up->port.line, PTR_ERR(up->pins));
1458 sprintf(up->name, "OMAP UART%d", up->port.line);
1459 up->port.mapbase = mem->start;
1460 up->port.membase = devm_ioremap(&pdev->dev, mem->start,
1461 resource_size(mem));
1462 if (!up->port.membase) {
1463 dev_err(&pdev->dev, "can't ioremap UART\n");
1468 up->port.flags = omap_up_info->flags;
1469 up->port.uartclk = omap_up_info->uartclk;
1470 if (!up->port.uartclk) {
1471 up->port.uartclk = DEFAULT_CLK_SPEED;
1472 dev_warn(&pdev->dev, "No clock speed specified: using default:"
1473 "%d\n", DEFAULT_CLK_SPEED);
1476 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1477 up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1478 pm_qos_add_request(&up->pm_qos_request,
1479 PM_QOS_CPU_DMA_LATENCY, up->latency);
1480 serial_omap_uart_wq = create_singlethread_workqueue(up->name);
1481 INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1483 platform_set_drvdata(pdev, up);
1484 pm_runtime_enable(&pdev->dev);
1485 pm_runtime_use_autosuspend(&pdev->dev);
1486 pm_runtime_set_autosuspend_delay(&pdev->dev,
1487 omap_up_info->autosuspend_timeout);
1489 pm_runtime_irq_safe(&pdev->dev);
1490 pm_runtime_get_sync(&pdev->dev);
1492 omap_serial_fill_features_erratas(up);
1494 ui[up->port.line] = up;
1495 serial_omap_add_console_port(up);
1497 ret = uart_add_one_port(&serial_omap_reg, &up->port);
1501 pm_runtime_mark_last_busy(up->dev);
1502 pm_runtime_put_autosuspend(up->dev);
1506 pm_runtime_put(&pdev->dev);
1507 pm_runtime_disable(&pdev->dev);
1510 dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n",
1511 pdev->id, __func__, ret);
1515 static int serial_omap_remove(struct platform_device *dev)
1517 struct uart_omap_port *up = platform_get_drvdata(dev);
1519 pm_runtime_put_sync(up->dev);
1520 pm_runtime_disable(up->dev);
1521 uart_remove_one_port(&serial_omap_reg, &up->port);
1522 pm_qos_remove_request(&up->pm_qos_request);
1528 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1529 * The access to uart register after MDR1 Access
1530 * causes UART to corrupt data.
1533 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1534 * give 10 times as much
1536 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1540 serial_out(up, UART_OMAP_MDR1, mdr1);
1542 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1543 UART_FCR_CLEAR_RCVR);
1545 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1546 * TX_FIFO_E bit is 1.
1548 while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1549 (UART_LSR_THRE | UART_LSR_DR))) {
1552 /* Should *never* happen. we warn and carry on */
1553 dev_crit(up->dev, "Errata i202: timedout %x\n",
1554 serial_in(up, UART_LSR));
1561 #ifdef CONFIG_PM_RUNTIME
1562 static void serial_omap_restore_context(struct uart_omap_port *up)
1564 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1565 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1567 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1569 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1570 serial_out(up, UART_EFR, UART_EFR_ECB);
1571 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1572 serial_out(up, UART_IER, 0x0);
1573 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1574 serial_out(up, UART_DLL, up->dll);
1575 serial_out(up, UART_DLM, up->dlh);
1576 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1577 serial_out(up, UART_IER, up->ier);
1578 serial_out(up, UART_FCR, up->fcr);
1579 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1580 serial_out(up, UART_MCR, up->mcr);
1581 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1582 serial_out(up, UART_OMAP_SCR, up->scr);
1583 serial_out(up, UART_EFR, up->efr);
1584 serial_out(up, UART_LCR, up->lcr);
1585 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1586 serial_omap_mdr1_errataset(up, up->mdr1);
1588 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1591 static int serial_omap_runtime_suspend(struct device *dev)
1593 struct uart_omap_port *up = dev_get_drvdata(dev);
1594 struct omap_uart_port_info *pdata = dev->platform_data;
1602 up->context_loss_cnt = serial_omap_get_context_loss_count(up);
1604 if (device_may_wakeup(dev)) {
1605 if (!up->wakeups_enabled) {
1606 serial_omap_enable_wakeup(up, true);
1607 up->wakeups_enabled = true;
1610 if (up->wakeups_enabled) {
1611 serial_omap_enable_wakeup(up, false);
1612 up->wakeups_enabled = false;
1616 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1617 schedule_work(&up->qos_work);
1622 static int serial_omap_runtime_resume(struct device *dev)
1624 struct uart_omap_port *up = dev_get_drvdata(dev);
1626 int loss_cnt = serial_omap_get_context_loss_count(up);
1629 dev_err(dev, "serial_omap_get_context_loss_count failed : %d\n",
1631 serial_omap_restore_context(up);
1632 } else if (up->context_loss_cnt != loss_cnt) {
1633 serial_omap_restore_context(up);
1635 up->latency = up->calc_latency;
1636 schedule_work(&up->qos_work);
1642 static const struct dev_pm_ops serial_omap_dev_pm_ops = {
1643 SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
1644 SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
1645 serial_omap_runtime_resume, NULL)
1648 #if defined(CONFIG_OF)
1649 static const struct of_device_id omap_serial_of_match[] = {
1650 { .compatible = "ti,omap2-uart" },
1651 { .compatible = "ti,omap3-uart" },
1652 { .compatible = "ti,omap4-uart" },
1655 MODULE_DEVICE_TABLE(of, omap_serial_of_match);
1658 static struct platform_driver serial_omap_driver = {
1659 .probe = serial_omap_probe,
1660 .remove = serial_omap_remove,
1662 .name = DRIVER_NAME,
1663 .pm = &serial_omap_dev_pm_ops,
1664 .of_match_table = of_match_ptr(omap_serial_of_match),
1668 static int __init serial_omap_init(void)
1672 ret = uart_register_driver(&serial_omap_reg);
1675 ret = platform_driver_register(&serial_omap_driver);
1677 uart_unregister_driver(&serial_omap_reg);
1681 static void __exit serial_omap_exit(void)
1683 platform_driver_unregister(&serial_omap_driver);
1684 uart_unregister_driver(&serial_omap_reg);
1687 module_init(serial_omap_init);
1688 module_exit(serial_omap_exit);
1690 MODULE_DESCRIPTION("OMAP High Speed UART driver");
1691 MODULE_LICENSE("GPL");
1692 MODULE_AUTHOR("Texas Instruments Inc");