drivers/tty/serial/omap-serial.c

   1 /*
   2  * Driver for OMAP-UART controller.
   3  * Based on drivers/serial/8250.c
   4  *
   5  * Copyright (C) 2010 Texas Instruments.
   6  *
   7  * Authors:
   8  *      Govindraj R     <govindraj.raja@ti.com>
   9  *      Thara Gopinath  <thara@ti.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * Note: This driver is made separate from 8250 driver as we cannot
  17  * over load 8250 driver with omap platform specific configuration for
  18  * features like DMA, it makes easier to implement features like DMA and
  19  * hardware flow control and software flow control configuration with
  20  * this driver as required for the omap-platform.
  21  */
  22
  23 #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  24 #define SUPPORT_SYSRQ
  25 #endif
  26
  27 #include <linux/module.h>
  28 #include <linux/init.h>
  29 #include <linux/console.h>
  30 #include <linux/serial_reg.h>
  31 #include <linux/delay.h>
  32 #include <linux/slab.h>
  33 #include <linux/tty.h>
  34 #include <linux/tty_flip.h>
  35 #include <linux/platform_device.h>
  36 #include <linux/io.h>
  37 #include <linux/clk.h>
  38 #include <linux/serial_core.h>
  39 #include <linux/irq.h>
  40 #include <linux/pm_runtime.h>
  41 #include <linux/of.h>
  42 #include <linux/of_irq.h>
  43 #include <linux/gpio.h>
  44 #include <linux/of_gpio.h>
  45 #include <linux/platform_data/serial-omap.h>
  46
  47 #include <dt-bindings/gpio/gpio.h>
  48
  49 #define OMAP_MAX_HSUART_PORTS   10
  50
  51 #define UART_BUILD_REVISION(x, y)       (((x) << 8) | (y))
  52
  53 #define OMAP_UART_REV_42 0x0402
  54 #define OMAP_UART_REV_46 0x0406
  55 #define OMAP_UART_REV_52 0x0502
  56 #define OMAP_UART_REV_63 0x0603
  57
  58 #define OMAP_UART_TX_WAKEUP_EN          BIT(7)
  59
  60 /* Feature flags */
  61 #define OMAP_UART_WER_HAS_TX_WAKEUP     BIT(0)
  62
  63 #define UART_ERRATA_i202_MDR1_ACCESS    BIT(0)
  64 #define UART_ERRATA_i291_DMA_FORCEIDLE  BIT(1)
  65
  66 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
  67
  68 /* SCR register bitmasks */
  69 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK               (1 << 7)
  70 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK               (1 << 6)
  71 #define OMAP_UART_SCR_TX_EMPTY                  (1 << 3)
  72
  73 /* FCR register bitmasks */
  74 #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK                 (0x3 << 6)
  75 #define OMAP_UART_FCR_TX_FIFO_TRIG_MASK                 (0x3 << 4)
  76
  77 /* MVR register bitmasks */
  78 #define OMAP_UART_MVR_SCHEME_SHIFT      30
  79
  80 #define OMAP_UART_LEGACY_MVR_MAJ_MASK   0xf0
  81 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT  4
  82 #define OMAP_UART_LEGACY_MVR_MIN_MASK   0x0f
  83
  84 #define OMAP_UART_MVR_MAJ_MASK          0x700
  85 #define OMAP_UART_MVR_MAJ_SHIFT         8
  86 #define OMAP_UART_MVR_MIN_MASK          0x3f
  87
  88 #define OMAP_UART_DMA_CH_FREE   -1
  89
  90 #define MSR_SAVE_FLAGS          UART_MSR_ANY_DELTA
  91 #define OMAP_MODE13X_SPEED      230400
  92
  93 /* WER = 0x7F
  94  * Enable module level wakeup in WER reg
  95  */
  96 #define OMAP_UART_WER_MOD_WKUP  0X7F
  97
  98 /* Enable XON/XOFF flow control on output */
  99 #define OMAP_UART_SW_TX         0x08
 100
 101 /* Enable XON/XOFF flow control on input */
 102 #define OMAP_UART_SW_RX         0x02
 103
 104 #define OMAP_UART_SW_CLR        0xF0
 105
 106 #define OMAP_UART_TCR_TRIG      0x0F
 107
 108 struct uart_omap_dma {
 109         u8                      uart_dma_tx;
 110         u8                      uart_dma_rx;
 111         int                     rx_dma_channel;
 112         int                     tx_dma_channel;
 113         dma_addr_t              rx_buf_dma_phys;
 114         dma_addr_t              tx_buf_dma_phys;
 115         unsigned int            uart_base;
 116         /*
 117          * Buffer for rx dma.It is not required for tx because the buffer
 118          * comes from port structure.
 119          */
 120         unsigned char           *rx_buf;
 121         unsigned int            prev_rx_dma_pos;
 122         int                     tx_buf_size;
 123         int                     tx_dma_used;
 124         int                     rx_dma_used;
 125         spinlock_t              tx_lock;
 126         spinlock_t              rx_lock;
 127         /* timer to poll activity on rx dma */
 128         struct timer_list       rx_timer;
 129         unsigned int            rx_buf_size;
 130         unsigned int            rx_poll_rate;
 131         unsigned int            rx_timeout;
 132 };
 133
 134 struct uart_omap_port {
 135         struct uart_port        port;
 136         struct uart_omap_dma    uart_dma;
 137         struct device           *dev;
 138         int                     wakeirq;
 139
 140         unsigned char           ier;
 141         unsigned char           lcr;
 142         unsigned char           mcr;
 143         unsigned char           fcr;
 144         unsigned char           efr;
 145         unsigned char           dll;
 146         unsigned char           dlh;
 147         unsigned char           mdr1;
 148         unsigned char           scr;
 149         unsigned char           wer;
 150
 151         int                     use_dma;
 152         /*
 153          * Some bits in registers are cleared on a read, so they must
 154          * be saved whenever the register is read but the bits will not
 155          * be immediately processed.
 156          */
 157         unsigned int            lsr_break_flag;
 158         unsigned char           msr_saved_flags;
 159         char                    name[20];
 160         unsigned long           port_activity;
 161         int                     context_loss_cnt;
 162         u32                     errata;
 163         u8                      wakeups_enabled;
 164         u32                     features;
 165
 166         int                     rts_gpio;
 167
 168         struct pm_qos_request   pm_qos_request;
 169         u32                     latency;
 170         u32                     calc_latency;
 171         struct work_struct      qos_work;
 172         bool                    is_suspending;
 173 };
 174
 175 #define to_uart_omap_port(p) ((container_of((p), struct uart_omap_port, port)))
 176
 177 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
 178
 179 /* Forward declaration of functions */
 180 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
 181
 182 static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
 183 {
 184         offset <<= up->port.regshift;
 185         return readw(up->port.membase + offset);
 186 }
 187
 188 static inline void serial_out(struct uart_omap_port *up, int offset, int value)
 189 {
 190         offset <<= up->port.regshift;
 191         writew(value, up->port.membase + offset);
 192 }
 193
 194 static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
 195 {
 196         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
 197         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
 198                        UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
 199         serial_out(up, UART_FCR, 0);
 200 }
 201
 202 static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
 203 {
 204         struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
 205
 206         if (!pdata || !pdata->get_context_loss_count)
 207                 return -EINVAL;
 208
 209         return pdata->get_context_loss_count(up->dev);
 210 }
 211
 212 static inline void serial_omap_enable_wakeirq(struct uart_omap_port *up,
 213                                        bool enable)
 214 {
 215         if (!up->wakeirq)
 216                 return;
 217
 218         if (enable)
 219                 enable_irq(up->wakeirq);
 220         else
 221                 disable_irq_nosync(up->wakeirq);
 222 }
 223
 224 static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
 225 {
 226         struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
 227
 228         if (enable == up->wakeups_enabled)
 229                 return;
 230
 231         serial_omap_enable_wakeirq(up, enable);
 232         up->wakeups_enabled = enable;
 233
 234         if (!pdata || !pdata->enable_wakeup)
 235                 return;
 236
 237         pdata->enable_wakeup(up->dev, enable);
 238 }
 239
 240 /*
 241  * Calculate the absolute difference between the desired and actual baud
 242  * rate for the given mode.
 243  */
 244 static inline int calculate_baud_abs_diff(struct uart_port *port,
 245                                 unsigned int baud, unsigned int mode)
 246 {
 247         unsigned int n = port->uartclk / (mode * baud);
 248         int abs_diff;
 249
 250         if (n == 0)
 251                 n = 1;
 252
 253         abs_diff = baud - (port->uartclk / (mode * n));
 254         if (abs_diff < 0)
 255                 abs_diff = -abs_diff;
 256
 257         return abs_diff;
 258 }
 259
 260 /*
 261  * serial_omap_baud_is_mode16 - check if baud rate is MODE16X
 262  * @port: uart port info
 263  * @baud: baudrate for which mode needs to be determined
 264  *
 265  * Returns true if baud rate is MODE16X and false if MODE13X
 266  * Original table in OMAP TRM named "UART Mode Baud Rates, Divisor Values,
 267  * and Error Rates" determines modes not for all common baud rates.
 268  * E.g. for 1000000 baud rate mode must be 16x, but according to that
 269  * table it's determined as 13x.
 270  */
 271 static bool
 272 serial_omap_baud_is_mode16(struct uart_port *port, unsigned int baud)
 273 {
 274         int abs_diff_13 = calculate_baud_abs_diff(port, baud, 13);
 275         int abs_diff_16 = calculate_baud_abs_diff(port, baud, 16);
 276
 277         return (abs_diff_13 >= abs_diff_16);
 278 }
 279
 280 /*
 281  * serial_omap_get_divisor - calculate divisor value
 282  * @port: uart port info
 283  * @baud: baudrate for which divisor needs to be calculated.
 284  */
 285 static unsigned int
 286 serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
 287 {
 288         unsigned int mode;
 289
 290         if (!serial_omap_baud_is_mode16(port, baud))
 291                 mode = 13;
 292         else
 293                 mode = 16;
 294         return port->uartclk/(mode * baud);
 295 }
 296
 297 static void serial_omap_enable_ms(struct uart_port *port)
 298 {
 299         struct uart_omap_port *up = to_uart_omap_port(port);
 300
 301         dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
 302
 303         pm_runtime_get_sync(up->dev);
 304         up->ier |= UART_IER_MSI;
 305         serial_out(up, UART_IER, up->ier);
 306         pm_runtime_mark_last_busy(up->dev);
 307         pm_runtime_put_autosuspend(up->dev);
 308 }
 309
 310 static void serial_omap_stop_tx(struct uart_port *port)
 311 {
 312         struct uart_omap_port *up = to_uart_omap_port(port);
 313         int res;
 314
 315         pm_runtime_get_sync(up->dev);
 316
 317         /* Handle RS-485 */
 318         if (port->rs485.flags & SER_RS485_ENABLED) {
 319                 if (up->scr & OMAP_UART_SCR_TX_EMPTY) {
 320                         /* THR interrupt is fired when both TX FIFO and TX
 321                          * shift register are empty. This means there's nothing
 322                          * left to transmit now, so make sure the THR interrupt
 323                          * is fired when TX FIFO is below the trigger level,
 324                          * disable THR interrupts and toggle the RS-485 GPIO
 325                          * data direction pin if needed.
 326                          */
 327                         up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
 328                         serial_out(up, UART_OMAP_SCR, up->scr);
 329                         res = (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) ?
 330                                 1 : 0;
 331                         if (gpio_get_value(up->rts_gpio) != res) {
 332                                 if (port->rs485.delay_rts_after_send > 0)
 333                                         mdelay(
 334                                         port->rs485.delay_rts_after_send);
 335                                 gpio_set_value(up->rts_gpio, res);
 336                         }
 337                 } else {
 338                         /* We're asked to stop, but there's still stuff in the
 339                          * UART FIFO, so make sure the THR interrupt is fired
 340                          * when both TX FIFO and TX shift register are empty.
 341                          * The next THR interrupt (if no transmission is started
 342                          * in the meantime) will indicate the end of a
 343                          * transmission. Therefore we _don't_ disable THR
 344                          * interrupts in this situation.
 345                          */
 346                         up->scr |= OMAP_UART_SCR_TX_EMPTY;
 347                         serial_out(up, UART_OMAP_SCR, up->scr);
 348                         return;
 349                 }
 350         }
 351
 352         if (up->ier & UART_IER_THRI) {
 353                 up->ier &= ~UART_IER_THRI;
 354                 serial_out(up, UART_IER, up->ier);
 355         }
 356
 357         if ((port->rs485.flags & SER_RS485_ENABLED) &&
 358             !(port->rs485.flags & SER_RS485_RX_DURING_TX)) {
 359                 /*
 360                  * Empty the RX FIFO, we are not interested in anything
 361                  * received during the half-duplex transmission.
 362                  */
 363                 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_RCVR);
 364                 /* Re-enable RX interrupts */
 365                 up->ier |= UART_IER_RLSI | UART_IER_RDI;
 366                 up->port.read_status_mask |= UART_LSR_DR;
 367                 serial_out(up, UART_IER, up->ier);
 368         }
 369
 370         pm_runtime_mark_last_busy(up->dev);
 371         pm_runtime_put_autosuspend(up->dev);
 372 }
 373
 374 static void serial_omap_stop_rx(struct uart_port *port)
 375 {
 376         struct uart_omap_port *up = to_uart_omap_port(port);
 377
 378         pm_runtime_get_sync(up->dev);
 379         up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
 380         up->port.read_status_mask &= ~UART_LSR_DR;
 381         serial_out(up, UART_IER, up->ier);
 382         pm_runtime_mark_last_busy(up->dev);
 383         pm_runtime_put_autosuspend(up->dev);
 384 }
 385
 386 static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
 387 {
 388         struct circ_buf *xmit = &up->port.state->xmit;
 389         int count;
 390
 391         if (up->port.x_char) {
 392                 serial_out(up, UART_TX, up->port.x_char);
 393                 up->port.icount.tx++;
 394                 up->port.x_char = 0;
 395                 return;
 396         }
 397         if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
 398                 serial_omap_stop_tx(&up->port);
 399                 return;
 400         }
 401         count = up->port.fifosize / 4;
 402         do {
 403                 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
 404                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 405                 up->port.icount.tx++;
 406                 if (uart_circ_empty(xmit))
 407                         break;
 408         } while (--count > 0);
 409
 410         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 411                 uart_write_wakeup(&up->port);
 412
 413         if (uart_circ_empty(xmit))
 414                 serial_omap_stop_tx(&up->port);
 415 }
 416
 417 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
 418 {
 419         if (!(up->ier & UART_IER_THRI)) {
 420                 up->ier |= UART_IER_THRI;
 421                 serial_out(up, UART_IER, up->ier);
 422         }
 423 }
 424
 425 static void serial_omap_start_tx(struct uart_port *port)
 426 {
 427         struct uart_omap_port *up = to_uart_omap_port(port);
 428         int res;
 429
 430         pm_runtime_get_sync(up->dev);
 431
 432         /* Handle RS-485 */
 433         if (port->rs485.flags & SER_RS485_ENABLED) {
 434                 /* Fire THR interrupts when FIFO is below trigger level */
 435                 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
 436                 serial_out(up, UART_OMAP_SCR, up->scr);
 437
 438                 /* if rts not already enabled */
 439                 res = (port->rs485.flags & SER_RS485_RTS_ON_SEND) ? 1 : 0;
 440                 if (gpio_get_value(up->rts_gpio) != res) {
 441                         gpio_set_value(up->rts_gpio, res);
 442                         if (port->rs485.delay_rts_before_send > 0)
 443                                 mdelay(port->rs485.delay_rts_before_send);
 444                 }
 445         }
 446
 447         if ((port->rs485.flags & SER_RS485_ENABLED) &&
 448             !(port->rs485.flags & SER_RS485_RX_DURING_TX))
 449                 serial_omap_stop_rx(port);
 450
 451         serial_omap_enable_ier_thri(up);
 452         pm_runtime_mark_last_busy(up->dev);
 453         pm_runtime_put_autosuspend(up->dev);
 454 }
 455
 456 static void serial_omap_throttle(struct uart_port *port)
 457 {
 458         struct uart_omap_port *up = to_uart_omap_port(port);
 459         unsigned long flags;
 460
 461         pm_runtime_get_sync(up->dev);
 462         spin_lock_irqsave(&up->port.lock, flags);
 463         up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
 464         serial_out(up, UART_IER, up->ier);
 465         spin_unlock_irqrestore(&up->port.lock, flags);
 466         pm_runtime_mark_last_busy(up->dev);
 467         pm_runtime_put_autosuspend(up->dev);
 468 }
 469
 470 static void serial_omap_unthrottle(struct uart_port *port)
 471 {
 472         struct uart_omap_port *up = to_uart_omap_port(port);
 473         unsigned long flags;
 474
 475         pm_runtime_get_sync(up->dev);
 476         spin_lock_irqsave(&up->port.lock, flags);
 477         up->ier |= UART_IER_RLSI | UART_IER_RDI;
 478         serial_out(up, UART_IER, up->ier);
 479         spin_unlock_irqrestore(&up->port.lock, flags);
 480         pm_runtime_mark_last_busy(up->dev);
 481         pm_runtime_put_autosuspend(up->dev);
 482 }
 483
 484 static unsigned int check_modem_status(struct uart_omap_port *up)
 485 {
 486         unsigned int status;
 487
 488         status = serial_in(up, UART_MSR);
 489         status |= up->msr_saved_flags;
 490         up->msr_saved_flags = 0;
 491         if ((status & UART_MSR_ANY_DELTA) == 0)
 492                 return status;
 493
 494         if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
 495             up->port.state != NULL) {
 496                 if (status & UART_MSR_TERI)
 497                         up->port.icount.rng++;
 498                 if (status & UART_MSR_DDSR)
 499                         up->port.icount.dsr++;
 500                 if (status & UART_MSR_DDCD)
 501                         uart_handle_dcd_change
 502                                 (&up->port, status & UART_MSR_DCD);
 503                 if (status & UART_MSR_DCTS)
 504                         uart_handle_cts_change
 505                                 (&up->port, status & UART_MSR_CTS);
 506                 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
 507         }
 508
 509         return status;
 510 }
 511
 512 static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)
 513 {
 514         unsigned int flag;
 515         unsigned char ch = 0;
 516
 517         if (likely(lsr & UART_LSR_DR))
 518                 ch = serial_in(up, UART_RX);
 519
 520         up->port.icount.rx++;
 521         flag = TTY_NORMAL;
 522
 523         if (lsr & UART_LSR_BI) {
 524                 flag = TTY_BREAK;
 525                 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
 526                 up->port.icount.brk++;
 527                 /*
 528                  * We do the SysRQ and SAK checking
 529                  * here because otherwise the break
 530                  * may get masked by ignore_status_mask
 531                  * or read_status_mask.
 532                  */
 533                 if (uart_handle_break(&up->port))
 534                         return;
 535
 536         }
 537
 538         if (lsr & UART_LSR_PE) {
 539                 flag = TTY_PARITY;
 540                 up->port.icount.parity++;
 541         }
 542
 543         if (lsr & UART_LSR_FE) {
 544                 flag = TTY_FRAME;
 545                 up->port.icount.frame++;
 546         }
 547
 548         if (lsr & UART_LSR_OE)
 549                 up->port.icount.overrun++;
 550
 551 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
 552         if (up->port.line == up->port.cons->index) {
 553                 /* Recover the break flag from console xmit */
 554                 lsr |= up->lsr_break_flag;
 555         }
 556 #endif
 557         uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);
 558 }
 559
 560 static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
 561 {
 562         unsigned char ch = 0;
 563         unsigned int flag;
 564
 565         if (!(lsr & UART_LSR_DR))
 566                 return;
 567
 568         ch = serial_in(up, UART_RX);
 569         flag = TTY_NORMAL;
 570         up->port.icount.rx++;
 571
 572         if (uart_handle_sysrq_char(&up->port, ch))
 573                 return;
 574
 575         uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
 576 }
 577
 578 /**
 579  * serial_omap_irq() - This handles the interrupt from one port
 580  * @irq: uart port irq number
 581  * @dev_id: uart port info
 582  */
 583 static irqreturn_t serial_omap_irq(int irq, void *dev_id)
 584 {
 585         struct uart_omap_port *up = dev_id;
 586         unsigned int iir, lsr;
 587         unsigned int type;
 588         irqreturn_t ret = IRQ_NONE;
 589         int max_count = 256;
 590
 591         spin_lock(&up->port.lock);
 592         pm_runtime_get_sync(up->dev);
 593
 594         do {
 595                 iir = serial_in(up, UART_IIR);
 596                 if (iir & UART_IIR_NO_INT)
 597                         break;
 598
 599                 ret = IRQ_HANDLED;
 600                 lsr = serial_in(up, UART_LSR);
 601
 602                 /* extract IRQ type from IIR register */
 603                 type = iir & 0x3e;
 604
 605                 switch (type) {
 606                 case UART_IIR_MSI:
 607                         check_modem_status(up);
 608                         break;
 609                 case UART_IIR_THRI:
 610                         transmit_chars(up, lsr);
 611                         break;
 612                 case UART_IIR_RX_TIMEOUT:
 613                         /* FALLTHROUGH */
 614                 case UART_IIR_RDI:
 615                         serial_omap_rdi(up, lsr);
 616                         break;
 617                 case UART_IIR_RLSI:
 618                         serial_omap_rlsi(up, lsr);
 619                         break;
 620                 case UART_IIR_CTS_RTS_DSR:
 621                         /* simply try again */
 622                         break;
 623                 case UART_IIR_XOFF:
 624                         /* FALLTHROUGH */
 625                 default:
 626                         break;
 627                 }
 628         } while (!(iir & UART_IIR_NO_INT) && max_count--);
 629
 630         spin_unlock(&up->port.lock);
 631
 632         tty_flip_buffer_push(&up->port.state->port);
 633
 634         pm_runtime_mark_last_busy(up->dev);
 635         pm_runtime_put_autosuspend(up->dev);
 636         up->port_activity = jiffies;
 637
 638         return ret;
 639 }
 640
 641 static unsigned int serial_omap_tx_empty(struct uart_port *port)
 642 {
 643         struct uart_omap_port *up = to_uart_omap_port(port);
 644         unsigned long flags = 0;
 645         unsigned int ret = 0;
 646
 647         pm_runtime_get_sync(up->dev);
 648         dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
 649         spin_lock_irqsave(&up->port.lock, flags);
 650         ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
 651         spin_unlock_irqrestore(&up->port.lock, flags);
 652         pm_runtime_mark_last_busy(up->dev);
 653         pm_runtime_put_autosuspend(up->dev);
 654         return ret;
 655 }
 656
 657 static unsigned int serial_omap_get_mctrl(struct uart_port *port)
 658 {
 659         struct uart_omap_port *up = to_uart_omap_port(port);
 660         unsigned int status;
 661         unsigned int ret = 0;
 662
 663         pm_runtime_get_sync(up->dev);
 664         status = check_modem_status(up);
 665         pm_runtime_mark_last_busy(up->dev);
 666         pm_runtime_put_autosuspend(up->dev);
 667
 668         dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
 669
 670         if (status & UART_MSR_DCD)
 671                 ret |= TIOCM_CAR;
 672         if (status & UART_MSR_RI)
 673                 ret |= TIOCM_RNG;
 674         if (status & UART_MSR_DSR)
 675                 ret |= TIOCM_DSR;
 676         if (status & UART_MSR_CTS)
 677                 ret |= TIOCM_CTS;
 678         return ret;
 679 }
 680
 681 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
 682 {
 683         struct uart_omap_port *up = to_uart_omap_port(port);
 684         unsigned char mcr = 0, old_mcr;
 685
 686         dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
 687         if (mctrl & TIOCM_RTS)
 688                 mcr |= UART_MCR_RTS;
 689         if (mctrl & TIOCM_DTR)
 690                 mcr |= UART_MCR_DTR;
 691         if (mctrl & TIOCM_OUT1)
 692                 mcr |= UART_MCR_OUT1;
 693         if (mctrl & TIOCM_OUT2)
 694                 mcr |= UART_MCR_OUT2;
 695         if (mctrl & TIOCM_LOOP)
 696                 mcr |= UART_MCR_LOOP;
 697
 698         pm_runtime_get_sync(up->dev);
 699         old_mcr = serial_in(up, UART_MCR);
 700         old_mcr &= ~(UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_OUT1 |
 701                      UART_MCR_DTR | UART_MCR_RTS);
 702         up->mcr = old_mcr | mcr;
 703         serial_out(up, UART_MCR, up->mcr);
 704         pm_runtime_mark_last_busy(up->dev);
 705         pm_runtime_put_autosuspend(up->dev);
 706 }
 707
 708 static void serial_omap_break_ctl(struct uart_port *port, int break_state)
 709 {
 710         struct uart_omap_port *up = to_uart_omap_port(port);
 711         unsigned long flags = 0;
 712
 713         dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
 714         pm_runtime_get_sync(up->dev);
 715         spin_lock_irqsave(&up->port.lock, flags);
 716         if (break_state == -1)
 717                 up->lcr |= UART_LCR_SBC;
 718         else
 719                 up->lcr &= ~UART_LCR_SBC;
 720         serial_out(up, UART_LCR, up->lcr);
 721         spin_unlock_irqrestore(&up->port.lock, flags);
 722         pm_runtime_mark_last_busy(up->dev);
 723         pm_runtime_put_autosuspend(up->dev);
 724 }
 725
 726 static int serial_omap_startup(struct uart_port *port)
 727 {
 728         struct uart_omap_port *up = to_uart_omap_port(port);
 729         unsigned long flags = 0;
 730         int retval;
 731
 732         /*
 733          * Allocate the IRQ
 734          */
 735         retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
 736                                 up->name, up);
 737         if (retval)
 738                 return retval;
 739
 740         /* Optional wake-up IRQ */
 741         if (up->wakeirq) {
 742                 retval = request_irq(up->wakeirq, serial_omap_irq,
 743                                      up->port.irqflags, up->name, up);
 744                 if (retval) {
 745                         free_irq(up->port.irq, up);
 746                         return retval;
 747                 }
 748                 disable_irq(up->wakeirq);
 749         }
 750
 751         dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
 752
 753         pm_runtime_get_sync(up->dev);
 754         /*
 755          * Clear the FIFO buffers and disable them.
 756          * (they will be reenabled in set_termios())
 757          */
 758         serial_omap_clear_fifos(up);
 759         /* For Hardware flow control */
 760         serial_out(up, UART_MCR, UART_MCR_RTS);
 761
 762         /*
 763          * Clear the interrupt registers.
 764          */
 765         (void) serial_in(up, UART_LSR);
 766         if (serial_in(up, UART_LSR) & UART_LSR_DR)
 767                 (void) serial_in(up, UART_RX);
 768         (void) serial_in(up, UART_IIR);
 769         (void) serial_in(up, UART_MSR);
 770
 771         /*
 772          * Now, initialize the UART
 773          */
 774         serial_out(up, UART_LCR, UART_LCR_WLEN8);
 775         spin_lock_irqsave(&up->port.lock, flags);
 776         /*
 777          * Most PC uarts need OUT2 raised to enable interrupts.
 778          */
 779         up->port.mctrl |= TIOCM_OUT2;
 780         serial_omap_set_mctrl(&up->port, up->port.mctrl);
 781         spin_unlock_irqrestore(&up->port.lock, flags);
 782
 783         up->msr_saved_flags = 0;
 784         /*
 785          * Finally, enable interrupts. Note: Modem status interrupts
 786          * are set via set_termios(), which will be occurring imminently
 787          * anyway, so we don't enable them here.
 788          */
 789         up->ier = UART_IER_RLSI | UART_IER_RDI;
 790         serial_out(up, UART_IER, up->ier);
 791
 792         /* Enable module level wake up */
 793         up->wer = OMAP_UART_WER_MOD_WKUP;
 794         if (up->features & OMAP_UART_WER_HAS_TX_WAKEUP)
 795                 up->wer |= OMAP_UART_TX_WAKEUP_EN;
 796
 797         serial_out(up, UART_OMAP_WER, up->wer);
 798
 799         pm_runtime_mark_last_busy(up->dev);
 800         pm_runtime_put_autosuspend(up->dev);
 801         up->port_activity = jiffies;
 802         return 0;
 803 }
 804
 805 static void serial_omap_shutdown(struct uart_port *port)
 806 {
 807         struct uart_omap_port *up = to_uart_omap_port(port);
 808         unsigned long flags = 0;
 809
 810         dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
 811
 812         pm_runtime_get_sync(up->dev);
 813         /*
 814          * Disable interrupts from this port
 815          */
 816         up->ier = 0;
 817         serial_out(up, UART_IER, 0);
 818
 819         spin_lock_irqsave(&up->port.lock, flags);
 820         up->port.mctrl &= ~TIOCM_OUT2;
 821         serial_omap_set_mctrl(&up->port, up->port.mctrl);
 822         spin_unlock_irqrestore(&up->port.lock, flags);
 823
 824         /*
 825          * Disable break condition and FIFOs
 826          */
 827         serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
 828         serial_omap_clear_fifos(up);
 829
 830         /*
 831          * Read data port to reset things, and then free the irq
 832          */
 833         if (serial_in(up, UART_LSR) & UART_LSR_DR)
 834                 (void) serial_in(up, UART_RX);
 835
 836         pm_runtime_mark_last_busy(up->dev);
 837         pm_runtime_put_autosuspend(up->dev);
 838         free_irq(up->port.irq, up);
 839         if (up->wakeirq)
 840                 free_irq(up->wakeirq, up);
 841 }
 842
 843 static void serial_omap_uart_qos_work(struct work_struct *work)
 844 {
 845         struct uart_omap_port *up = container_of(work, struct uart_omap_port,
 846                                                 qos_work);
 847
 848         pm_qos_update_request(&up->pm_qos_request, up->latency);
 849 }
 850
 851 static void
 852 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
 853                         struct ktermios *old)
 854 {
 855         struct uart_omap_port *up = to_uart_omap_port(port);
 856         unsigned char cval = 0;
 857         unsigned long flags = 0;
 858         unsigned int baud, quot;
 859
 860         switch (termios->c_cflag & CSIZE) {
 861         case CS5:
 862                 cval = UART_LCR_WLEN5;
 863                 break;
 864         case CS6:
 865                 cval = UART_LCR_WLEN6;
 866                 break;
 867         case CS7:
 868                 cval = UART_LCR_WLEN7;
 869                 break;
 870         default:
 871         case CS8:
 872                 cval = UART_LCR_WLEN8;
 873                 break;
 874         }
 875
 876         if (termios->c_cflag & CSTOPB)
 877                 cval |= UART_LCR_STOP;
 878         if (termios->c_cflag & PARENB)
 879                 cval |= UART_LCR_PARITY;
 880         if (!(termios->c_cflag & PARODD))
 881                 cval |= UART_LCR_EPAR;
 882         if (termios->c_cflag & CMSPAR)
 883                 cval |= UART_LCR_SPAR;
 884
 885         /*
 886          * Ask the core to calculate the divisor for us.
 887          */
 888
 889         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
 890         quot = serial_omap_get_divisor(port, baud);
 891
 892         /* calculate wakeup latency constraint */
 893         up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8);
 894         up->latency = up->calc_latency;
 895         schedule_work(&up->qos_work);
 896
 897         up->dll = quot & 0xff;
 898         up->dlh = quot >> 8;
 899         up->mdr1 = UART_OMAP_MDR1_DISABLE;
 900
 901         up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
 902                         UART_FCR_ENABLE_FIFO;
 903
 904         /*
 905          * Ok, we're now changing the port state. Do it with
 906          * interrupts disabled.
 907          */
 908         pm_runtime_get_sync(up->dev);
 909         spin_lock_irqsave(&up->port.lock, flags);
 910
 911         /*
 912          * Update the per-port timeout.
 913          */
 914         uart_update_timeout(port, termios->c_cflag, baud);
 915
 916         up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
 917         if (termios->c_iflag & INPCK)
 918                 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
 919         if (termios->c_iflag & (BRKINT | PARMRK))
 920                 up->port.read_status_mask |= UART_LSR_BI;
 921
 922         /*
 923          * Characters to ignore
 924          */
 925         up->port.ignore_status_mask = 0;
 926         if (termios->c_iflag & IGNPAR)
 927                 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
 928         if (termios->c_iflag & IGNBRK) {
 929                 up->port.ignore_status_mask |= UART_LSR_BI;
 930                 /*
 931                  * If we're ignoring parity and break indicators,
 932                  * ignore overruns too (for real raw support).
 933                  */
 934                 if (termios->c_iflag & IGNPAR)
 935                         up->port.ignore_status_mask |= UART_LSR_OE;
 936         }
 937
 938         /*
 939          * ignore all characters if CREAD is not set
 940          */
 941         if ((termios->c_cflag & CREAD) == 0)
 942                 up->port.ignore_status_mask |= UART_LSR_DR;
 943
 944         /*
 945          * Modem status interrupts
 946          */
 947         up->ier &= ~UART_IER_MSI;
 948         if (UART_ENABLE_MS(&up->port, termios->c_cflag))
 949                 up->ier |= UART_IER_MSI;
 950         serial_out(up, UART_IER, up->ier);
 951         serial_out(up, UART_LCR, cval);         /* reset DLAB */
 952         up->lcr = cval;
 953         up->scr = 0;
 954
 955         /* FIFOs and DMA Settings */
 956
 957         /* FCR can be changed only when the
 958          * baud clock is not running
 959          * DLL_REG and DLH_REG set to 0.
 960          */
 961         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 962         serial_out(up, UART_DLL, 0);
 963         serial_out(up, UART_DLM, 0);
 964         serial_out(up, UART_LCR, 0);
 965
 966         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 967
 968         up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB;
 969         up->efr &= ~UART_EFR_SCD;
 970         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 971
 972         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 973         up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR;
 974         serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
 975         /* FIFO ENABLE, DMA MODE */
 976
 977         up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
 978         /*
 979          * NOTE: Setting OMAP_UART_SCR_RX_TRIG_GRANU1_MASK
 980          * sets Enables the granularity of 1 for TRIGGER RX
 981          * level. Along with setting RX FIFO trigger level
 982          * to 1 (as noted below, 16 characters) and TLR[3:0]
 983          * to zero this will result RX FIFO threshold level
 984          * to 1 character, instead of 16 as noted in comment
 985          * below.
 986          */
 987
 988         /* Set receive FIFO threshold to 16 characters and
 989          * transmit FIFO threshold to 32 spaces
 990          */
 991         up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
 992         up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK;
 993         up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 |
 994                 UART_FCR_ENABLE_FIFO;
 995
 996         serial_out(up, UART_FCR, up->fcr);
 997         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 998
 999         serial_out(up, UART_OMAP_SCR, up->scr);
1000
1001         /* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */
1002         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1003         serial_out(up, UART_MCR, up->mcr);
1004         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1005         serial_out(up, UART_EFR, up->efr);
1006         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1007
1008         /* Protocol, Baud Rate, and Interrupt Settings */
1009
1010         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1011                 serial_omap_mdr1_errataset(up, up->mdr1);
1012         else
1013                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1014
1015         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1016         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
1017
1018         serial_out(up, UART_LCR, 0);
1019         serial_out(up, UART_IER, 0);
1020         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1021
1022         serial_out(up, UART_DLL, up->dll);      /* LS of divisor */
1023         serial_out(up, UART_DLM, up->dlh);      /* MS of divisor */
1024
1025         serial_out(up, UART_LCR, 0);
1026         serial_out(up, UART_IER, up->ier);
1027         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1028
1029         serial_out(up, UART_EFR, up->efr);
1030         serial_out(up, UART_LCR, cval);
1031
1032         if (!serial_omap_baud_is_mode16(port, baud))
1033                 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
1034         else
1035                 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
1036
1037         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1038                 serial_omap_mdr1_errataset(up, up->mdr1);
1039         else
1040                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1041
1042         /* Configure flow control */
1043         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1044
1045         /* XON1/XOFF1 accessible mode B, TCRTLR=0, ECB=0 */
1046         serial_out(up, UART_XON1, termios->c_cc[VSTART]);
1047         serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
1048
1049         /* Enable access to TCR/TLR */
1050         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
1051         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1052         serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
1053
1054         serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
1055
1056         if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
1057                 /* Enable AUTORTS and AUTOCTS */
1058                 up->efr |= UART_EFR_CTS | UART_EFR_RTS;
1059
1060                 /* Ensure MCR RTS is asserted */
1061                 up->mcr |= UART_MCR_RTS;
1062         } else {
1063                 /* Disable AUTORTS and AUTOCTS */
1064                 up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS);
1065         }
1066
1067         if (up->port.flags & UPF_SOFT_FLOW) {
1068                 /* clear SW control mode bits */
1069                 up->efr &= OMAP_UART_SW_CLR;
1070
1071                 /*
1072                  * IXON Flag:
1073                  * Enable XON/XOFF flow control on input.
1074                  * Receiver compares XON1, XOFF1.
1075                  */
1076                 if (termios->c_iflag & IXON)
1077                         up->efr |= OMAP_UART_SW_RX;
1078
1079                 /*
1080                  * IXOFF Flag:
1081                  * Enable XON/XOFF flow control on output.
1082                  * Transmit XON1, XOFF1
1083                  */
1084                 if (termios->c_iflag & IXOFF)
1085                         up->efr |= OMAP_UART_SW_TX;
1086
1087                 /*
1088                  * IXANY Flag:
1089                  * Enable any character to restart output.
1090                  * Operation resumes after receiving any
1091                  * character after recognition of the XOFF character
1092                  */
1093                 if (termios->c_iflag & IXANY)
1094                         up->mcr |= UART_MCR_XONANY;
1095                 else
1096                         up->mcr &= ~UART_MCR_XONANY;
1097         }
1098         serial_out(up, UART_MCR, up->mcr);
1099         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1100         serial_out(up, UART_EFR, up->efr);
1101         serial_out(up, UART_LCR, up->lcr);
1102
1103         serial_omap_set_mctrl(&up->port, up->port.mctrl);
1104
1105         spin_unlock_irqrestore(&up->port.lock, flags);
1106         pm_runtime_mark_last_busy(up->dev);
1107         pm_runtime_put_autosuspend(up->dev);
1108         dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
1109 }
1110
1111 static void
1112 serial_omap_pm(struct uart_port *port, unsigned int state,
1113                unsigned int oldstate)
1114 {
1115         struct uart_omap_port *up = to_uart_omap_port(port);
1116         unsigned char efr;
1117
1118         dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
1119
1120         pm_runtime_get_sync(up->dev);
1121         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1122         efr = serial_in(up, UART_EFR);
1123         serial_out(up, UART_EFR, efr | UART_EFR_ECB);
1124         serial_out(up, UART_LCR, 0);
1125
1126         serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
1127         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1128         serial_out(up, UART_EFR, efr);
1129         serial_out(up, UART_LCR, 0);
1130
1131         if (!device_may_wakeup(up->dev)) {
1132                 if (!state)
1133                         pm_runtime_forbid(up->dev);
1134                 else
1135                         pm_runtime_allow(up->dev);
1136         }
1137
1138         pm_runtime_mark_last_busy(up->dev);
1139         pm_runtime_put_autosuspend(up->dev);
1140 }
1141
1142 static void serial_omap_release_port(struct uart_port *port)
1143 {
1144         dev_dbg(port->dev, "serial_omap_release_port+\n");
1145 }
1146
1147 static int serial_omap_request_port(struct uart_port *port)
1148 {
1149         dev_dbg(port->dev, "serial_omap_request_port+\n");
1150         return 0;
1151 }
1152
1153 static void serial_omap_config_port(struct uart_port *port, int flags)
1154 {
1155         struct uart_omap_port *up = to_uart_omap_port(port);
1156
1157         dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
1158                                                         up->port.line);
1159         up->port.type = PORT_OMAP;
1160         up->port.flags |= UPF_SOFT_FLOW | UPF_HARD_FLOW;
1161 }
1162
1163 static int
1164 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
1165 {
1166         /* we don't want the core code to modify any port params */
1167         dev_dbg(port->dev, "serial_omap_verify_port+\n");
1168         return -EINVAL;
1169 }
1170
1171 static const char *
1172 serial_omap_type(struct uart_port *port)
1173 {
1174         struct uart_omap_port *up = to_uart_omap_port(port);
1175
1176         dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
1177         return up->name;
1178 }
1179
1180 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1181
1182 static inline void wait_for_xmitr(struct uart_omap_port *up)
1183 {
1184         unsigned int status, tmout = 10000;
1185
1186         /* Wait up to 10ms for the character(s) to be sent. */
1187         do {
1188                 status = serial_in(up, UART_LSR);
1189
1190                 if (status & UART_LSR_BI)
1191                         up->lsr_break_flag = UART_LSR_BI;
1192
1193                 if (--tmout == 0)
1194                         break;
1195                 udelay(1);
1196         } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
1197
1198         /* Wait up to 1s for flow control if necessary */
1199         if (up->port.flags & UPF_CONS_FLOW) {
1200                 tmout = 1000000;
1201                 for (tmout = 1000000; tmout; tmout--) {
1202                         unsigned int msr = serial_in(up, UART_MSR);
1203
1204                         up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1205                         if (msr & UART_MSR_CTS)
1206                                 break;
1207
1208                         udelay(1);
1209                 }
1210         }
1211 }
1212
1213 #ifdef CONFIG_CONSOLE_POLL
1214
1215 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
1216 {
1217         struct uart_omap_port *up = to_uart_omap_port(port);
1218
1219         pm_runtime_get_sync(up->dev);
1220         wait_for_xmitr(up);
1221         serial_out(up, UART_TX, ch);
1222         pm_runtime_mark_last_busy(up->dev);
1223         pm_runtime_put_autosuspend(up->dev);
1224 }
1225
1226 static int serial_omap_poll_get_char(struct uart_port *port)
1227 {
1228         struct uart_omap_port *up = to_uart_omap_port(port);
1229         unsigned int status;
1230
1231         pm_runtime_get_sync(up->dev);
1232         status = serial_in(up, UART_LSR);
1233         if (!(status & UART_LSR_DR)) {
1234                 status = NO_POLL_CHAR;
1235                 goto out;
1236         }
1237
1238         status = serial_in(up, UART_RX);
1239
1240 out:
1241         pm_runtime_mark_last_busy(up->dev);
1242         pm_runtime_put_autosuspend(up->dev);
1243
1244         return status;
1245 }
1246
1247 #endif /* CONFIG_CONSOLE_POLL */
1248
1249 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
1250
1251 static struct uart_omap_port *serial_omap_console_ports[OMAP_MAX_HSUART_PORTS];
1252
1253 static struct uart_driver serial_omap_reg;
1254
1255 static void serial_omap_console_putchar(struct uart_port *port, int ch)
1256 {
1257         struct uart_omap_port *up = to_uart_omap_port(port);
1258
1259         wait_for_xmitr(up);
1260         serial_out(up, UART_TX, ch);
1261 }
1262
1263 static void
1264 serial_omap_console_write(struct console *co, const char *s,
1265                 unsigned int count)
1266 {
1267         struct uart_omap_port *up = serial_omap_console_ports[co->index];
1268         unsigned long flags;
1269         unsigned int ier;
1270         int locked = 1;
1271
1272         pm_runtime_get_sync(up->dev);
1273
1274         local_irq_save(flags);
1275         if (up->port.sysrq)
1276                 locked = 0;
1277         else if (oops_in_progress)
1278                 locked = spin_trylock(&up->port.lock);
1279         else
1280                 spin_lock(&up->port.lock);
1281
1282         /*
1283          * First save the IER then disable the interrupts
1284          */
1285         ier = serial_in(up, UART_IER);
1286         serial_out(up, UART_IER, 0);
1287
1288         uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1289
1290         /*
1291          * Finally, wait for transmitter to become empty
1292          * and restore the IER
1293          */
1294         wait_for_xmitr(up);
1295         serial_out(up, UART_IER, ier);
1296         /*
1297          * The receive handling will happen properly because the
1298          * receive ready bit will still be set; it is not cleared
1299          * on read.  However, modem control will not, we must
1300          * call it if we have saved something in the saved flags
1301          * while processing with interrupts off.
1302          */
1303         if (up->msr_saved_flags)
1304                 check_modem_status(up);
1305
1306         pm_runtime_mark_last_busy(up->dev);
1307         pm_runtime_put_autosuspend(up->dev);
1308         if (locked)
1309                 spin_unlock(&up->port.lock);
1310         local_irq_restore(flags);
1311 }
1312
1313 static int __init
1314 serial_omap_console_setup(struct console *co, char *options)
1315 {
1316         struct uart_omap_port *up;
1317         int baud = 115200;
1318         int bits = 8;
1319         int parity = 'n';
1320         int flow = 'n';
1321
1322         if (serial_omap_console_ports[co->index] == NULL)
1323                 return -ENODEV;
1324         up = serial_omap_console_ports[co->index];
1325
1326         if (options)
1327                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1328
1329         return uart_set_options(&up->port, co, baud, parity, bits, flow);
1330 }
1331
1332 static struct console serial_omap_console = {
1333         .name           = OMAP_SERIAL_NAME,
1334         .write          = serial_omap_console_write,
1335         .device         = uart_console_device,
1336         .setup          = serial_omap_console_setup,
1337         .flags          = CON_PRINTBUFFER,
1338         .index          = -1,
1339         .data           = &serial_omap_reg,
1340 };
1341
1342 static void serial_omap_add_console_port(struct uart_omap_port *up)
1343 {
1344         serial_omap_console_ports[up->port.line] = up;
1345 }
1346
1347 #define OMAP_CONSOLE    (&serial_omap_console)
1348
1349 #else
1350
1351 #define OMAP_CONSOLE    NULL
1352
1353 static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1354 {}
1355
1356 #endif
1357
1358 /* Enable or disable the rs485 support */
1359 static int
1360 serial_omap_config_rs485(struct uart_port *port, struct serial_rs485 *rs485conf)
1361 {
1362         struct uart_omap_port *up = to_uart_omap_port(port);
1363         unsigned int mode;
1364         int val;
1365
1366         pm_runtime_get_sync(up->dev);
1367
1368         /* Disable interrupts from this port */
1369         mode = up->ier;
1370         up->ier = 0;
1371         serial_out(up, UART_IER, 0);
1372
1373         /* store new config */
1374         port->rs485 = *rs485conf;
1375
1376         /*
1377          * Just as a precaution, only allow rs485
1378          * to be enabled if the gpio pin is valid
1379          */
1380         if (gpio_is_valid(up->rts_gpio)) {
1381                 /* enable / disable rts */
1382                 val = (port->rs485.flags & SER_RS485_ENABLED) ?
1383                         SER_RS485_RTS_AFTER_SEND : SER_RS485_RTS_ON_SEND;
1384                 val = (port->rs485.flags & val) ? 1 : 0;
1385                 gpio_set_value(up->rts_gpio, val);
1386         } else
1387                 port->rs485.flags &= ~SER_RS485_ENABLED;
1388
1389         /* Enable interrupts */
1390         up->ier = mode;
1391         serial_out(up, UART_IER, up->ier);
1392
1393         /* If RS-485 is disabled, make sure the THR interrupt is fired when
1394          * TX FIFO is below the trigger level.
1395          */
1396         if (!(port->rs485.flags & SER_RS485_ENABLED) &&
1397             (up->scr & OMAP_UART_SCR_TX_EMPTY)) {
1398                 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
1399                 serial_out(up, UART_OMAP_SCR, up->scr);
1400         }
1401
1402         pm_runtime_mark_last_busy(up->dev);
1403         pm_runtime_put_autosuspend(up->dev);
1404
1405         return 0;
1406 }
1407
1408 static struct uart_ops serial_omap_pops = {
1409         .tx_empty       = serial_omap_tx_empty,
1410         .set_mctrl      = serial_omap_set_mctrl,
1411         .get_mctrl      = serial_omap_get_mctrl,
1412         .stop_tx        = serial_omap_stop_tx,
1413         .start_tx       = serial_omap_start_tx,
1414         .throttle       = serial_omap_throttle,
1415         .unthrottle     = serial_omap_unthrottle,
1416         .stop_rx        = serial_omap_stop_rx,
1417         .enable_ms      = serial_omap_enable_ms,
1418         .break_ctl      = serial_omap_break_ctl,
1419         .startup        = serial_omap_startup,
1420         .shutdown       = serial_omap_shutdown,
1421         .set_termios    = serial_omap_set_termios,
1422         .pm             = serial_omap_pm,
1423         .type           = serial_omap_type,
1424         .release_port   = serial_omap_release_port,
1425         .request_port   = serial_omap_request_port,
1426         .config_port    = serial_omap_config_port,
1427         .verify_port    = serial_omap_verify_port,
1428 #ifdef CONFIG_CONSOLE_POLL
1429         .poll_put_char  = serial_omap_poll_put_char,
1430         .poll_get_char  = serial_omap_poll_get_char,
1431 #endif
1432 };
1433
1434 static struct uart_driver serial_omap_reg = {
1435         .owner          = THIS_MODULE,
1436         .driver_name    = "OMAP-SERIAL",
1437         .dev_name       = OMAP_SERIAL_NAME,
1438         .nr             = OMAP_MAX_HSUART_PORTS,
1439         .cons           = OMAP_CONSOLE,
1440 };
1441
1442 #ifdef CONFIG_PM_SLEEP
1443 static int serial_omap_prepare(struct device *dev)
1444 {
1445         struct uart_omap_port *up = dev_get_drvdata(dev);
1446
1447         up->is_suspending = true;
1448
1449         return 0;
1450 }
1451
1452 static void serial_omap_complete(struct device *dev)
1453 {
1454         struct uart_omap_port *up = dev_get_drvdata(dev);
1455
1456         up->is_suspending = false;
1457 }
1458
1459 static int serial_omap_suspend(struct device *dev)
1460 {
1461         struct uart_omap_port *up = dev_get_drvdata(dev);
1462
1463         uart_suspend_port(&serial_omap_reg, &up->port);
1464         flush_work(&up->qos_work);
1465
1466         if (device_may_wakeup(dev))
1467                 serial_omap_enable_wakeup(up, true);
1468         else
1469                 serial_omap_enable_wakeup(up, false);
1470
1471         return 0;
1472 }
1473
1474 static int serial_omap_resume(struct device *dev)
1475 {
1476         struct uart_omap_port *up = dev_get_drvdata(dev);
1477
1478         if (device_may_wakeup(dev))
1479                 serial_omap_enable_wakeup(up, false);
1480
1481         uart_resume_port(&serial_omap_reg, &up->port);
1482
1483         return 0;
1484 }
1485 #else
1486 #define serial_omap_prepare NULL
1487 #define serial_omap_complete NULL
1488 #endif /* CONFIG_PM_SLEEP */
1489
1490 static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
1491 {
1492         u32 mvr, scheme;
1493         u16 revision, major, minor;
1494
1495         mvr = readl(up->port.membase + (UART_OMAP_MVER << up->port.regshift));
1496
1497         /* Check revision register scheme */
1498         scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
1499
1500         switch (scheme) {
1501         case 0: /* Legacy Scheme: OMAP2/3 */
1502                 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
1503                 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
1504                                         OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
1505                 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
1506                 break;
1507         case 1:
1508                 /* New Scheme: OMAP4+ */
1509                 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
1510                 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
1511                                         OMAP_UART_MVR_MAJ_SHIFT;
1512                 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
1513                 break;
1514         default:
1515                 dev_warn(up->dev,
1516                         "Unknown %s revision, defaulting to highest\n",
1517                         up->name);
1518                 /* highest possible revision */
1519                 major = 0xff;
1520                 minor = 0xff;
1521         }
1522
1523         /* normalize revision for the driver */
1524         revision = UART_BUILD_REVISION(major, minor);
1525
1526         switch (revision) {
1527         case OMAP_UART_REV_46:
1528                 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1529                                 UART_ERRATA_i291_DMA_FORCEIDLE);
1530                 break;
1531         case OMAP_UART_REV_52:
1532                 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1533                                 UART_ERRATA_i291_DMA_FORCEIDLE);
1534                 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1535                 break;
1536         case OMAP_UART_REV_63:
1537                 up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
1538                 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1539                 break;
1540         default:
1541                 break;
1542         }
1543 }
1544
1545 static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
1546 {
1547         struct omap_uart_port_info *omap_up_info;
1548
1549         omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
1550         if (!omap_up_info)
1551                 return NULL; /* out of memory */
1552
1553         of_property_read_u32(dev->of_node, "clock-frequency",
1554                                          &omap_up_info->uartclk);
1555         return omap_up_info;
1556 }
1557
1558 static int serial_omap_probe_rs485(struct uart_omap_port *up,
1559                                    struct device_node *np)
1560 {
1561         struct serial_rs485 *rs485conf = &up->port.rs485;
1562         u32 rs485_delay[2];
1563         enum of_gpio_flags flags;
1564         int ret;
1565
1566         rs485conf->flags = 0;
1567         up->rts_gpio = -EINVAL;
1568
1569         if (!np)
1570                 return 0;
1571
1572         if (of_property_read_bool(np, "rs485-rts-active-high"))
1573                 rs485conf->flags |= SER_RS485_RTS_ON_SEND;
1574         else
1575                 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
1576
1577         /* check for tx enable gpio */
1578         up->rts_gpio = of_get_named_gpio_flags(np, "rts-gpio", 0, &flags);
1579         if (gpio_is_valid(up->rts_gpio)) {
1580                 ret = devm_gpio_request(up->dev, up->rts_gpio, "omap-serial");
1581                 if (ret < 0)
1582                         return ret;
1583                 ret = gpio_direction_output(up->rts_gpio,
1584                                             flags & SER_RS485_RTS_AFTER_SEND);
1585                 if (ret < 0)
1586                         return ret;
1587         } else if (up->rts_gpio == -EPROBE_DEFER) {
1588                 return -EPROBE_DEFER;
1589         } else {
1590                 up->rts_gpio = -EINVAL;
1591         }
1592
1593         if (of_property_read_u32_array(np, "rs485-rts-delay",
1594                                     rs485_delay, 2) == 0) {
1595                 rs485conf->delay_rts_before_send = rs485_delay[0];
1596                 rs485conf->delay_rts_after_send = rs485_delay[1];
1597         }
1598
1599         if (of_property_read_bool(np, "rs485-rx-during-tx"))
1600                 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1601
1602         if (of_property_read_bool(np, "linux,rs485-enabled-at-boot-time"))
1603                 rs485conf->flags |= SER_RS485_ENABLED;
1604
1605         return 0;
1606 }
1607
1608 static int serial_omap_probe(struct platform_device *pdev)
1609 {
1610         struct omap_uart_port_info *omap_up_info = dev_get_platdata(&pdev->dev);
1611         struct uart_omap_port *up;
1612         struct resource *mem;
1613         void __iomem *base;
1614         int uartirq = 0;
1615         int wakeirq = 0;
1616         int ret;
1617
1618         /* The optional wakeirq may be specified in the board dts file */
1619         if (pdev->dev.of_node) {
1620                 uartirq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1621                 if (!uartirq)
1622                         return -EPROBE_DEFER;
1623                 wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1);
1624                 omap_up_info = of_get_uart_port_info(&pdev->dev);
1625                 pdev->dev.platform_data = omap_up_info;
1626         } else {
1627                 uartirq = platform_get_irq(pdev, 0);
1628                 if (uartirq < 0)
1629                         return -EPROBE_DEFER;
1630         }
1631
1632         up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
1633         if (!up)
1634                 return -ENOMEM;
1635
1636         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1637         base = devm_ioremap_resource(&pdev->dev, mem);
1638         if (IS_ERR(base))
1639                 return PTR_ERR(base);
1640
1641         up->dev = &pdev->dev;
1642         up->port.dev = &pdev->dev;
1643         up->port.type = PORT_OMAP;
1644         up->port.iotype = UPIO_MEM;
1645         up->port.irq = uartirq;
1646         up->wakeirq = wakeirq;
1647         if (!up->wakeirq)
1648                 dev_info(up->port.dev, "no wakeirq for uart%d\n",
1649                          up->port.line);
1650
1651         up->port.regshift = 2;
1652         up->port.fifosize = 64;
1653         up->port.ops = &serial_omap_pops;
1654
1655         if (pdev->dev.of_node)
1656                 ret = of_alias_get_id(pdev->dev.of_node, "serial");
1657         else
1658                 ret = pdev->id;
1659
1660         if (ret < 0) {
1661                 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
1662                         ret);
1663                 goto err_port_line;
1664         }
1665         up->port.line = ret;
1666
1667         if (up->port.line >= OMAP_MAX_HSUART_PORTS) {
1668                 dev_err(&pdev->dev, "uart ID %d >  MAX %d.\n", up->port.line,
1669                         OMAP_MAX_HSUART_PORTS);
1670                 ret = -ENXIO;
1671                 goto err_port_line;
1672         }
1673
1674         ret = serial_omap_probe_rs485(up, pdev->dev.of_node);
1675         if (ret < 0)
1676                 goto err_rs485;
1677
1678         sprintf(up->name, "OMAP UART%d", up->port.line);
1679         up->port.mapbase = mem->start;
1680         up->port.membase = base;
1681         up->port.flags = omap_up_info->flags;
1682         up->port.uartclk = omap_up_info->uartclk;
1683         up->port.rs485_config = serial_omap_config_rs485;
1684         if (!up->port.uartclk) {
1685                 up->port.uartclk = DEFAULT_CLK_SPEED;
1686                 dev_warn(&pdev->dev,
1687                          "No clock speed specified: using default: %d\n",
1688                          DEFAULT_CLK_SPEED);
1689         }
1690
1691         up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1692         up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1693         pm_qos_add_request(&up->pm_qos_request,
1694                 PM_QOS_CPU_DMA_LATENCY, up->latency);
1695         INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1696
1697         platform_set_drvdata(pdev, up);
1698         if (omap_up_info->autosuspend_timeout == 0)
1699                 omap_up_info->autosuspend_timeout = -1;
1700
1701         device_init_wakeup(up->dev, true);
1702         pm_runtime_use_autosuspend(&pdev->dev);
1703         pm_runtime_set_autosuspend_delay(&pdev->dev,
1704                         omap_up_info->autosuspend_timeout);
1705
1706         pm_runtime_irq_safe(&pdev->dev);
1707         pm_runtime_enable(&pdev->dev);
1708
1709         pm_runtime_get_sync(&pdev->dev);
1710
1711         omap_serial_fill_features_erratas(up);
1712
1713         ui[up->port.line] = up;
1714         serial_omap_add_console_port(up);
1715
1716         ret = uart_add_one_port(&serial_omap_reg, &up->port);
1717         if (ret != 0)
1718                 goto err_add_port;
1719
1720         pm_runtime_mark_last_busy(up->dev);
1721         pm_runtime_put_autosuspend(up->dev);
1722         return 0;
1723
1724 err_add_port:
1725         pm_runtime_put(&pdev->dev);
1726         pm_runtime_disable(&pdev->dev);
1727 err_rs485:
1728 err_port_line:
1729         return ret;
1730 }
1731
1732 static int serial_omap_remove(struct platform_device *dev)
1733 {
1734         struct uart_omap_port *up = platform_get_drvdata(dev);
1735
1736         pm_runtime_put_sync(up->dev);
1737         pm_runtime_disable(up->dev);
1738         uart_remove_one_port(&serial_omap_reg, &up->port);
1739         pm_qos_remove_request(&up->pm_qos_request);
1740         device_init_wakeup(&dev->dev, false);
1741
1742         return 0;
1743 }
1744
1745 /*
1746  * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1747  * The access to uart register after MDR1 Access
1748  * causes UART to corrupt data.
1749  *
1750  * Need a delay =
1751  * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1752  * give 10 times as much
1753  */
1754 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1755 {
1756         u8 timeout = 255;
1757
1758         serial_out(up, UART_OMAP_MDR1, mdr1);
1759         udelay(2);
1760         serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1761                         UART_FCR_CLEAR_RCVR);
1762         /*
1763          * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1764          * TX_FIFO_E bit is 1.
1765          */
1766         while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1767                                 (UART_LSR_THRE | UART_LSR_DR))) {
1768                 timeout--;
1769                 if (!timeout) {
1770                         /* Should *never* happen. we warn and carry on */
1771                         dev_crit(up->dev, "Errata i202: timedout %x\n",
1772                                                 serial_in(up, UART_LSR));
1773                         break;
1774                 }
1775                 udelay(1);
1776         }
1777 }
1778
1779 #ifdef CONFIG_PM
1780 static void serial_omap_restore_context(struct uart_omap_port *up)
1781 {
1782         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1783                 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1784         else
1785                 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1786
1787         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1788         serial_out(up, UART_EFR, UART_EFR_ECB);
1789         serial_out(up, UART_LCR, 0x0); /* Operational mode */
1790         serial_out(up, UART_IER, 0x0);
1791         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1792         serial_out(up, UART_DLL, up->dll);
1793         serial_out(up, UART_DLM, up->dlh);
1794         serial_out(up, UART_LCR, 0x0); /* Operational mode */
1795         serial_out(up, UART_IER, up->ier);
1796         serial_out(up, UART_FCR, up->fcr);
1797         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1798         serial_out(up, UART_MCR, up->mcr);
1799         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1800         serial_out(up, UART_OMAP_SCR, up->scr);
1801         serial_out(up, UART_EFR, up->efr);
1802         serial_out(up, UART_LCR, up->lcr);
1803         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1804                 serial_omap_mdr1_errataset(up, up->mdr1);
1805         else
1806                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1807         serial_out(up, UART_OMAP_WER, up->wer);
1808 }
1809
1810 static int serial_omap_runtime_suspend(struct device *dev)
1811 {
1812         struct uart_omap_port *up = dev_get_drvdata(dev);
1813
1814         if (!up)
1815                 return -EINVAL;
1816
1817         /*
1818         * When using 'no_console_suspend', the console UART must not be
1819         * suspended. Since driver suspend is managed by runtime suspend,
1820         * preventing runtime suspend (by returning error) will keep device
1821         * active during suspend.
1822         */
1823         if (up->is_suspending && !console_suspend_enabled &&
1824             uart_console(&up->port))
1825                 return -EBUSY;
1826
1827         up->context_loss_cnt = serial_omap_get_context_loss_count(up);
1828
1829         serial_omap_enable_wakeup(up, true);
1830
1831         up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1832         schedule_work(&up->qos_work);
1833
1834         return 0;
1835 }
1836
1837 static int serial_omap_runtime_resume(struct device *dev)
1838 {
1839         struct uart_omap_port *up = dev_get_drvdata(dev);
1840
1841         int loss_cnt = serial_omap_get_context_loss_count(up);
1842
1843         serial_omap_enable_wakeup(up, false);
1844
1845         if (loss_cnt < 0) {
1846                 dev_dbg(dev, "serial_omap_get_context_loss_count failed : %d\n",
1847                         loss_cnt);
1848                 serial_omap_restore_context(up);
1849         } else if (up->context_loss_cnt != loss_cnt) {
1850                 serial_omap_restore_context(up);
1851         }
1852         up->latency = up->calc_latency;
1853         schedule_work(&up->qos_work);
1854
1855         return 0;
1856 }
1857 #endif
1858
1859 static const struct dev_pm_ops serial_omap_dev_pm_ops = {
1860         SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
1861         SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
1862                                 serial_omap_runtime_resume, NULL)
1863         .prepare        = serial_omap_prepare,
1864         .complete       = serial_omap_complete,
1865 };
1866
1867 #if defined(CONFIG_OF)
1868 static const struct of_device_id omap_serial_of_match[] = {
1869         { .compatible = "ti,omap2-uart" },
1870         { .compatible = "ti,omap3-uart" },
1871         { .compatible = "ti,omap4-uart" },
1872         {},
1873 };
1874 MODULE_DEVICE_TABLE(of, omap_serial_of_match);
1875 #endif
1876
1877 static struct platform_driver serial_omap_driver = {
1878         .probe          = serial_omap_probe,
1879         .remove         = serial_omap_remove,
1880         .driver         = {
1881                 .name   = DRIVER_NAME,
1882                 .pm     = &serial_omap_dev_pm_ops,
1883                 .of_match_table = of_match_ptr(omap_serial_of_match),
1884         },
1885 };
1886
1887 static int __init serial_omap_init(void)
1888 {
1889         int ret;
1890
1891         ret = uart_register_driver(&serial_omap_reg);
1892         if (ret != 0)
1893                 return ret;
1894         ret = platform_driver_register(&serial_omap_driver);
1895         if (ret != 0)
1896                 uart_unregister_driver(&serial_omap_reg);
1897         return ret;
1898 }
1899
1900 static void __exit serial_omap_exit(void)
1901 {
1902         platform_driver_unregister(&serial_omap_driver);
1903         uart_unregister_driver(&serial_omap_reg);
1904 }
1905
1906 module_init(serial_omap_init);
1907 module_exit(serial_omap_exit);
1908
1909 MODULE_DESCRIPTION("OMAP High Speed UART driver");
1910 MODULE_LICENSE("GPL");
1911 MODULE_AUTHOR("Texas Instruments Inc");