2 *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
4 *This program is free software; you can redistribute it and/or modify
5 *it under the terms of the GNU General Public License as published by
6 *the Free Software Foundation; version 2 of the License.
8 *This program is distributed in the hope that it will be useful,
9 *but WITHOUT ANY WARRANTY; without even the implied warranty of
10 *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 *GNU General Public License for more details.
13 *You should have received a copy of the GNU General Public License
14 *along with this program; if not, write to the Free Software
15 *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
17 #if defined(CONFIG_SERIAL_PCH_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
20 #include <linux/kernel.h>
21 #include <linux/serial_reg.h>
22 #include <linux/slab.h>
23 #include <linux/module.h>
24 #include <linux/pci.h>
25 #include <linux/console.h>
26 #include <linux/serial_core.h>
27 #include <linux/tty.h>
28 #include <linux/tty_flip.h>
29 #include <linux/interrupt.h>
31 #include <linux/dmi.h>
32 #include <linux/nmi.h>
33 #include <linux/delay.h>
35 #include <linux/debugfs.h>
36 #include <linux/dmaengine.h>
37 #include <linux/pch_dma.h>
40 PCH_UART_HANDLED_RX_INT_SHIFT,
41 PCH_UART_HANDLED_TX_INT_SHIFT,
42 PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
43 PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
44 PCH_UART_HANDLED_MS_INT_SHIFT,
45 PCH_UART_HANDLED_LS_INT_SHIFT,
53 #define PCH_UART_DRIVER_DEVICE "ttyPCH"
55 /* Set the max number of UART port
56 * Intel EG20T PCH: 4 port
57 * LAPIS Semiconductor ML7213 IOH: 3 port
58 * LAPIS Semiconductor ML7223 IOH: 2 port
62 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
63 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
64 #define PCH_UART_HANDLED_RX_ERR_INT (1<<((\
65 PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
66 #define PCH_UART_HANDLED_RX_TRG_INT (1<<((\
67 PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
68 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
70 #define PCH_UART_HANDLED_LS_INT (1<<((PCH_UART_HANDLED_LS_INT_SHIFT)<<1))
72 #define PCH_UART_RBR 0x00
73 #define PCH_UART_THR 0x00
75 #define PCH_UART_IER_MASK (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
76 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
77 #define PCH_UART_IER_ERBFI 0x00000001
78 #define PCH_UART_IER_ETBEI 0x00000002
79 #define PCH_UART_IER_ELSI 0x00000004
80 #define PCH_UART_IER_EDSSI 0x00000008
82 #define PCH_UART_IIR_IP 0x00000001
83 #define PCH_UART_IIR_IID 0x00000006
84 #define PCH_UART_IIR_MSI 0x00000000
85 #define PCH_UART_IIR_TRI 0x00000002
86 #define PCH_UART_IIR_RRI 0x00000004
87 #define PCH_UART_IIR_REI 0x00000006
88 #define PCH_UART_IIR_TOI 0x00000008
89 #define PCH_UART_IIR_FIFO256 0x00000020
90 #define PCH_UART_IIR_FIFO64 PCH_UART_IIR_FIFO256
91 #define PCH_UART_IIR_FE 0x000000C0
93 #define PCH_UART_FCR_FIFOE 0x00000001
94 #define PCH_UART_FCR_RFR 0x00000002
95 #define PCH_UART_FCR_TFR 0x00000004
96 #define PCH_UART_FCR_DMS 0x00000008
97 #define PCH_UART_FCR_FIFO256 0x00000020
98 #define PCH_UART_FCR_RFTL 0x000000C0
100 #define PCH_UART_FCR_RFTL1 0x00000000
101 #define PCH_UART_FCR_RFTL64 0x00000040
102 #define PCH_UART_FCR_RFTL128 0x00000080
103 #define PCH_UART_FCR_RFTL224 0x000000C0
104 #define PCH_UART_FCR_RFTL16 PCH_UART_FCR_RFTL64
105 #define PCH_UART_FCR_RFTL32 PCH_UART_FCR_RFTL128
106 #define PCH_UART_FCR_RFTL56 PCH_UART_FCR_RFTL224
107 #define PCH_UART_FCR_RFTL4 PCH_UART_FCR_RFTL64
108 #define PCH_UART_FCR_RFTL8 PCH_UART_FCR_RFTL128
109 #define PCH_UART_FCR_RFTL14 PCH_UART_FCR_RFTL224
110 #define PCH_UART_FCR_RFTL_SHIFT 6
112 #define PCH_UART_LCR_WLS 0x00000003
113 #define PCH_UART_LCR_STB 0x00000004
114 #define PCH_UART_LCR_PEN 0x00000008
115 #define PCH_UART_LCR_EPS 0x00000010
116 #define PCH_UART_LCR_SP 0x00000020
117 #define PCH_UART_LCR_SB 0x00000040
118 #define PCH_UART_LCR_DLAB 0x00000080
119 #define PCH_UART_LCR_NP 0x00000000
120 #define PCH_UART_LCR_OP PCH_UART_LCR_PEN
121 #define PCH_UART_LCR_EP (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
122 #define PCH_UART_LCR_1P (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
123 #define PCH_UART_LCR_0P (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
126 #define PCH_UART_LCR_5BIT 0x00000000
127 #define PCH_UART_LCR_6BIT 0x00000001
128 #define PCH_UART_LCR_7BIT 0x00000002
129 #define PCH_UART_LCR_8BIT 0x00000003
131 #define PCH_UART_MCR_DTR 0x00000001
132 #define PCH_UART_MCR_RTS 0x00000002
133 #define PCH_UART_MCR_OUT 0x0000000C
134 #define PCH_UART_MCR_LOOP 0x00000010
135 #define PCH_UART_MCR_AFE 0x00000020
137 #define PCH_UART_LSR_DR 0x00000001
138 #define PCH_UART_LSR_ERR (1<<7)
140 #define PCH_UART_MSR_DCTS 0x00000001
141 #define PCH_UART_MSR_DDSR 0x00000002
142 #define PCH_UART_MSR_TERI 0x00000004
143 #define PCH_UART_MSR_DDCD 0x00000008
144 #define PCH_UART_MSR_CTS 0x00000010
145 #define PCH_UART_MSR_DSR 0x00000020
146 #define PCH_UART_MSR_RI 0x00000040
147 #define PCH_UART_MSR_DCD 0x00000080
148 #define PCH_UART_MSR_DELTA (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
149 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
151 #define PCH_UART_DLL 0x00
152 #define PCH_UART_DLM 0x01
154 #define PCH_UART_BRCSR 0x0E
156 #define PCH_UART_IID_RLS (PCH_UART_IIR_REI)
157 #define PCH_UART_IID_RDR (PCH_UART_IIR_RRI)
158 #define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
159 #define PCH_UART_IID_THRE (PCH_UART_IIR_TRI)
160 #define PCH_UART_IID_MS (PCH_UART_IIR_MSI)
162 #define PCH_UART_HAL_PARITY_NONE (PCH_UART_LCR_NP)
163 #define PCH_UART_HAL_PARITY_ODD (PCH_UART_LCR_OP)
164 #define PCH_UART_HAL_PARITY_EVEN (PCH_UART_LCR_EP)
165 #define PCH_UART_HAL_PARITY_FIX1 (PCH_UART_LCR_1P)
166 #define PCH_UART_HAL_PARITY_FIX0 (PCH_UART_LCR_0P)
167 #define PCH_UART_HAL_5BIT (PCH_UART_LCR_5BIT)
168 #define PCH_UART_HAL_6BIT (PCH_UART_LCR_6BIT)
169 #define PCH_UART_HAL_7BIT (PCH_UART_LCR_7BIT)
170 #define PCH_UART_HAL_8BIT (PCH_UART_LCR_8BIT)
171 #define PCH_UART_HAL_STB1 0
172 #define PCH_UART_HAL_STB2 (PCH_UART_LCR_STB)
174 #define PCH_UART_HAL_CLR_TX_FIFO (PCH_UART_FCR_TFR)
175 #define PCH_UART_HAL_CLR_RX_FIFO (PCH_UART_FCR_RFR)
176 #define PCH_UART_HAL_CLR_ALL_FIFO (PCH_UART_HAL_CLR_TX_FIFO | \
177 PCH_UART_HAL_CLR_RX_FIFO)
179 #define PCH_UART_HAL_DMA_MODE0 0
180 #define PCH_UART_HAL_FIFO_DIS 0
181 #define PCH_UART_HAL_FIFO16 (PCH_UART_FCR_FIFOE)
182 #define PCH_UART_HAL_FIFO256 (PCH_UART_FCR_FIFOE | \
183 PCH_UART_FCR_FIFO256)
184 #define PCH_UART_HAL_FIFO64 (PCH_UART_HAL_FIFO256)
185 #define PCH_UART_HAL_TRIGGER1 (PCH_UART_FCR_RFTL1)
186 #define PCH_UART_HAL_TRIGGER64 (PCH_UART_FCR_RFTL64)
187 #define PCH_UART_HAL_TRIGGER128 (PCH_UART_FCR_RFTL128)
188 #define PCH_UART_HAL_TRIGGER224 (PCH_UART_FCR_RFTL224)
189 #define PCH_UART_HAL_TRIGGER16 (PCH_UART_FCR_RFTL16)
190 #define PCH_UART_HAL_TRIGGER32 (PCH_UART_FCR_RFTL32)
191 #define PCH_UART_HAL_TRIGGER56 (PCH_UART_FCR_RFTL56)
192 #define PCH_UART_HAL_TRIGGER4 (PCH_UART_FCR_RFTL4)
193 #define PCH_UART_HAL_TRIGGER8 (PCH_UART_FCR_RFTL8)
194 #define PCH_UART_HAL_TRIGGER14 (PCH_UART_FCR_RFTL14)
195 #define PCH_UART_HAL_TRIGGER_L (PCH_UART_FCR_RFTL64)
196 #define PCH_UART_HAL_TRIGGER_M (PCH_UART_FCR_RFTL128)
197 #define PCH_UART_HAL_TRIGGER_H (PCH_UART_FCR_RFTL224)
199 #define PCH_UART_HAL_RX_INT (PCH_UART_IER_ERBFI)
200 #define PCH_UART_HAL_TX_INT (PCH_UART_IER_ETBEI)
201 #define PCH_UART_HAL_RX_ERR_INT (PCH_UART_IER_ELSI)
202 #define PCH_UART_HAL_MS_INT (PCH_UART_IER_EDSSI)
203 #define PCH_UART_HAL_ALL_INT (PCH_UART_IER_MASK)
205 #define PCH_UART_HAL_DTR (PCH_UART_MCR_DTR)
206 #define PCH_UART_HAL_RTS (PCH_UART_MCR_RTS)
207 #define PCH_UART_HAL_OUT (PCH_UART_MCR_OUT)
208 #define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP)
209 #define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE)
211 #define PCI_VENDOR_ID_ROHM 0x10DB
213 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
215 #define DEFAULT_UARTCLK 1843200 /* 1.8432 MHz */
216 #define CMITC_UARTCLK 192000000 /* 192.0000 MHz */
217 #define FRI2_64_UARTCLK 64000000 /* 64.0000 MHz */
218 #define FRI2_48_UARTCLK 48000000 /* 48.0000 MHz */
219 #define NTC1_UARTCLK 64000000 /* 64.0000 MHz */
220 #define MINNOW_UARTCLK 50000000 /* 50.0000 MHz */
222 struct pch_uart_buffer {
228 struct uart_port port;
230 void __iomem *membase;
231 resource_size_t mapbase;
233 struct pci_dev *pdev;
235 unsigned int uartclk;
241 struct pch_uart_buffer rxbuf;
245 unsigned int use_dma;
246 struct dma_async_tx_descriptor *desc_tx;
247 struct dma_async_tx_descriptor *desc_rx;
248 struct pch_dma_slave param_tx;
249 struct pch_dma_slave param_rx;
250 struct dma_chan *chan_tx;
251 struct dma_chan *chan_rx;
252 struct scatterlist *sg_tx_p;
254 struct scatterlist sg_rx;
257 dma_addr_t rx_buf_dma;
259 struct dentry *debugfs;
261 /* protect the eg20t_port private structure and io access to membase */
266 * struct pch_uart_driver_data - private data structure for UART-DMA
267 * @port_type: The number of DMA channel
268 * @line_no: UART port line number (0, 1, 2...)
270 struct pch_uart_driver_data {
275 enum pch_uart_num_t {
289 static struct pch_uart_driver_data drv_dat[] = {
290 [pch_et20t_uart0] = {PCH_UART_8LINE, 0},
291 [pch_et20t_uart1] = {PCH_UART_2LINE, 1},
292 [pch_et20t_uart2] = {PCH_UART_2LINE, 2},
293 [pch_et20t_uart3] = {PCH_UART_2LINE, 3},
294 [pch_ml7213_uart0] = {PCH_UART_8LINE, 0},
295 [pch_ml7213_uart1] = {PCH_UART_2LINE, 1},
296 [pch_ml7213_uart2] = {PCH_UART_2LINE, 2},
297 [pch_ml7223_uart0] = {PCH_UART_8LINE, 0},
298 [pch_ml7223_uart1] = {PCH_UART_2LINE, 1},
299 [pch_ml7831_uart0] = {PCH_UART_8LINE, 0},
300 [pch_ml7831_uart1] = {PCH_UART_2LINE, 1},
303 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
304 static struct eg20t_port *pch_uart_ports[PCH_UART_NR];
306 static unsigned int default_baud = 9600;
307 static unsigned int user_uartclk = 0;
308 static const int trigger_level_256[4] = { 1, 64, 128, 224 };
309 static const int trigger_level_64[4] = { 1, 16, 32, 56 };
310 static const int trigger_level_16[4] = { 1, 4, 8, 14 };
311 static const int trigger_level_1[4] = { 1, 1, 1, 1 };
313 #ifdef CONFIG_DEBUG_FS
315 #define PCH_REGS_BUFSIZE 1024
318 static ssize_t port_show_regs(struct file *file, char __user *user_buf,
319 size_t count, loff_t *ppos)
321 struct eg20t_port *priv = file->private_data;
327 buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL);
331 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
332 "PCH EG20T port[%d] regs:\n", priv->port.line);
334 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
335 "=================================\n");
336 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
337 "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER));
338 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
339 "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR));
340 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
341 "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR));
342 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
343 "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR));
344 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
345 "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR));
346 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
347 "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR));
348 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
350 ioread8(priv->membase + PCH_UART_BRCSR));
352 lcr = ioread8(priv->membase + UART_LCR);
353 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
354 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
355 "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL));
356 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
357 "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM));
358 iowrite8(lcr, priv->membase + UART_LCR);
360 if (len > PCH_REGS_BUFSIZE)
361 len = PCH_REGS_BUFSIZE;
363 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
368 static const struct file_operations port_regs_ops = {
369 .owner = THIS_MODULE,
371 .read = port_show_regs,
372 .llseek = default_llseek,
374 #endif /* CONFIG_DEBUG_FS */
376 static struct dmi_system_id pch_uart_dmi_table[] = {
380 DMI_MATCH(DMI_BOARD_NAME, "CM-iTC"),
382 (void *)CMITC_UARTCLK,
387 DMI_MATCH(DMI_BIOS_VERSION, "FRI2"),
389 (void *)FRI2_64_UARTCLK,
392 .ident = "Fish River Island II",
394 DMI_MATCH(DMI_PRODUCT_NAME, "Fish River Island II"),
396 (void *)FRI2_48_UARTCLK,
401 DMI_MATCH(DMI_BOARD_NAME, "COMe-mTT"),
403 (void *)NTC1_UARTCLK,
406 .ident = "nanoETXexpress-TT",
408 DMI_MATCH(DMI_BOARD_NAME, "nanoETXexpress-TT"),
410 (void *)NTC1_UARTCLK,
413 .ident = "MinnowBoard",
415 DMI_MATCH(DMI_BOARD_NAME, "MinnowBoard"),
417 (void *)MINNOW_UARTCLK,
421 /* Return UART clock, checking for board specific clocks. */
422 static unsigned int pch_uart_get_uartclk(void)
424 const struct dmi_system_id *d;
429 d = dmi_first_match(pch_uart_dmi_table);
431 return (unsigned long)d->driver_data;
433 return DEFAULT_UARTCLK;
436 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
439 u8 ier = ioread8(priv->membase + UART_IER);
440 ier |= flag & PCH_UART_IER_MASK;
441 iowrite8(ier, priv->membase + UART_IER);
444 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
447 u8 ier = ioread8(priv->membase + UART_IER);
448 ier &= ~(flag & PCH_UART_IER_MASK);
449 iowrite8(ier, priv->membase + UART_IER);
452 static int pch_uart_hal_set_line(struct eg20t_port *priv, unsigned int baud,
453 unsigned int parity, unsigned int bits,
456 unsigned int dll, dlm, lcr;
459 div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud);
460 if (div < 0 || USHRT_MAX <= div) {
461 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div);
465 dll = (unsigned int)div & 0x00FFU;
466 dlm = ((unsigned int)div >> 8) & 0x00FFU;
468 if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
469 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity);
473 if (bits & ~PCH_UART_LCR_WLS) {
474 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits);
478 if (stb & ~PCH_UART_LCR_STB) {
479 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb);
487 dev_dbg(priv->port.dev, "%s:baud = %u, div = %04x, lcr = %02x (%lu)\n",
488 __func__, baud, div, lcr, jiffies);
489 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
490 iowrite8(dll, priv->membase + PCH_UART_DLL);
491 iowrite8(dlm, priv->membase + PCH_UART_DLM);
492 iowrite8(lcr, priv->membase + UART_LCR);
497 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
500 if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
501 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n",
506 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
507 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
508 priv->membase + UART_FCR);
509 iowrite8(priv->fcr, priv->membase + UART_FCR);
514 static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
515 unsigned int dmamode,
516 unsigned int fifo_size, unsigned int trigger)
520 if (dmamode & ~PCH_UART_FCR_DMS) {
521 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n",
526 if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
527 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n",
528 __func__, fifo_size);
532 if (trigger & ~PCH_UART_FCR_RFTL) {
533 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n",
538 switch (priv->fifo_size) {
540 priv->trigger_level =
541 trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
544 priv->trigger_level =
545 trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
548 priv->trigger_level =
549 trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
552 priv->trigger_level =
553 trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
557 dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
558 iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
559 iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
560 priv->membase + UART_FCR);
561 iowrite8(fcr, priv->membase + UART_FCR);
567 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
569 unsigned int msr = ioread8(priv->membase + UART_MSR);
570 priv->dmsr = msr & PCH_UART_MSR_DELTA;
574 static void pch_uart_hal_write(struct eg20t_port *priv,
575 const unsigned char *buf, int tx_size)
580 for (i = 0; i < tx_size;) {
582 iowrite8(thr, priv->membase + PCH_UART_THR);
586 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
591 struct uart_port *port = &priv->port;
593 lsr = ioread8(priv->membase + UART_LSR);
594 for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
595 i < rx_size && lsr & (UART_LSR_DR | UART_LSR_BI);
596 lsr = ioread8(priv->membase + UART_LSR)) {
597 rbr = ioread8(priv->membase + PCH_UART_RBR);
599 if (lsr & UART_LSR_BI) {
601 if (uart_handle_break(port))
606 if (uart_handle_sysrq_char(port, rbr))
616 static unsigned char pch_uart_hal_get_iid(struct eg20t_port *priv)
618 return ioread8(priv->membase + UART_IIR) &\
619 (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP);
622 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
624 return ioread8(priv->membase + UART_LSR);
627 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
631 lcr = ioread8(priv->membase + UART_LCR);
633 lcr |= PCH_UART_LCR_SB;
635 lcr &= ~PCH_UART_LCR_SB;
637 iowrite8(lcr, priv->membase + UART_LCR);
640 static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
643 struct uart_port *port = &priv->port;
644 struct tty_port *tport = &port->state->port;
646 tty_insert_flip_string(tport, buf, size);
647 tty_flip_buffer_push(tport);
652 static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf)
655 struct uart_port *port = &priv->port;
658 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n",
659 __func__, port->x_char, jiffies);
660 buf[0] = port->x_char;
668 static int dma_push_rx(struct eg20t_port *priv, int size)
670 struct tty_struct *tty;
672 struct uart_port *port = &priv->port;
673 struct tty_port *tport = &port->state->port;
676 tty = tty_port_tty_get(tport);
678 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
682 room = tty_buffer_request_room(tport, size);
685 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
690 tty_insert_flip_string(tport, sg_virt(&priv->sg_rx), size);
692 port->icount.rx += room;
699 static void pch_free_dma(struct uart_port *port)
701 struct eg20t_port *priv;
702 priv = container_of(port, struct eg20t_port, port);
705 dma_release_channel(priv->chan_tx);
706 priv->chan_tx = NULL;
709 dma_release_channel(priv->chan_rx);
710 priv->chan_rx = NULL;
713 if (priv->rx_buf_dma) {
714 dma_free_coherent(port->dev, port->fifosize, priv->rx_buf_virt,
716 priv->rx_buf_virt = NULL;
717 priv->rx_buf_dma = 0;
723 static bool filter(struct dma_chan *chan, void *slave)
725 struct pch_dma_slave *param = slave;
727 if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
728 chan->device->dev)) {
729 chan->private = param;
736 static void pch_request_dma(struct uart_port *port)
739 struct dma_chan *chan;
740 struct pci_dev *dma_dev;
741 struct pch_dma_slave *param;
742 struct eg20t_port *priv =
743 container_of(port, struct eg20t_port, port);
745 dma_cap_set(DMA_SLAVE, mask);
747 dma_dev = pci_get_bus_and_slot(priv->pdev->bus->number,
748 PCI_DEVFN(0xa, 0)); /* Get DMA's dev
751 param = &priv->param_tx;
752 param->dma_dev = &dma_dev->dev;
753 param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */
755 param->tx_reg = port->mapbase + UART_TX;
756 chan = dma_request_channel(mask, filter, param);
758 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n",
762 priv->chan_tx = chan;
765 param = &priv->param_rx;
766 param->dma_dev = &dma_dev->dev;
767 param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */
769 param->rx_reg = port->mapbase + UART_RX;
770 chan = dma_request_channel(mask, filter, param);
772 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n",
774 dma_release_channel(priv->chan_tx);
775 priv->chan_tx = NULL;
779 /* Get Consistent memory for DMA */
780 priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
781 &priv->rx_buf_dma, GFP_KERNEL);
782 priv->chan_rx = chan;
785 static void pch_dma_rx_complete(void *arg)
787 struct eg20t_port *priv = arg;
788 struct uart_port *port = &priv->port;
791 dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);
792 count = dma_push_rx(priv, priv->trigger_level);
794 tty_flip_buffer_push(&port->state->port);
795 async_tx_ack(priv->desc_rx);
796 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
797 PCH_UART_HAL_RX_ERR_INT);
800 static void pch_dma_tx_complete(void *arg)
802 struct eg20t_port *priv = arg;
803 struct uart_port *port = &priv->port;
804 struct circ_buf *xmit = &port->state->xmit;
805 struct scatterlist *sg = priv->sg_tx_p;
808 for (i = 0; i < priv->nent; i++, sg++) {
809 xmit->tail += sg_dma_len(sg);
810 port->icount.tx += sg_dma_len(sg);
812 xmit->tail &= UART_XMIT_SIZE - 1;
813 async_tx_ack(priv->desc_tx);
814 dma_unmap_sg(port->dev, sg, priv->nent, DMA_TO_DEVICE);
815 priv->tx_dma_use = 0;
817 kfree(priv->sg_tx_p);
818 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
821 static int pop_tx(struct eg20t_port *priv, int size)
824 struct uart_port *port = &priv->port;
825 struct circ_buf *xmit = &port->state->xmit;
827 if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size)
832 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
833 int sz = min(size - count, cnt_to_end);
834 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz);
835 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1);
837 } while (!uart_circ_empty(xmit) && count < size);
840 dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n",
841 count, size - count, jiffies);
846 static int handle_rx_to(struct eg20t_port *priv)
848 struct pch_uart_buffer *buf;
851 if (!priv->start_rx) {
852 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
853 PCH_UART_HAL_RX_ERR_INT);
858 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
859 ret = push_rx(priv, buf->buf, rx_size);
862 } while (rx_size == buf->size);
864 return PCH_UART_HANDLED_RX_INT;
867 static int handle_rx(struct eg20t_port *priv)
869 return handle_rx_to(priv);
872 static int dma_handle_rx(struct eg20t_port *priv)
874 struct uart_port *port = &priv->port;
875 struct dma_async_tx_descriptor *desc;
876 struct scatterlist *sg;
878 priv = container_of(port, struct eg20t_port, port);
881 sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
883 sg_dma_len(sg) = priv->trigger_level;
885 sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
886 sg_dma_len(sg), (unsigned long)priv->rx_buf_virt &
889 sg_dma_address(sg) = priv->rx_buf_dma;
891 desc = dmaengine_prep_slave_sg(priv->chan_rx,
892 sg, 1, DMA_DEV_TO_MEM,
893 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
898 priv->desc_rx = desc;
899 desc->callback = pch_dma_rx_complete;
900 desc->callback_param = priv;
901 desc->tx_submit(desc);
902 dma_async_issue_pending(priv->chan_rx);
904 return PCH_UART_HANDLED_RX_INT;
907 static unsigned int handle_tx(struct eg20t_port *priv)
909 struct uart_port *port = &priv->port;
910 struct circ_buf *xmit = &port->state->xmit;
916 if (!priv->start_tx) {
917 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
919 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
924 fifo_size = max(priv->fifo_size, 1);
926 if (pop_tx_x(priv, xmit->buf)) {
927 pch_uart_hal_write(priv, xmit->buf, 1);
932 size = min(xmit->head - xmit->tail, fifo_size);
936 tx_size = pop_tx(priv, size);
938 port->icount.tx += tx_size;
942 priv->tx_empty = tx_empty;
945 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
946 uart_write_wakeup(port);
949 return PCH_UART_HANDLED_TX_INT;
952 static unsigned int dma_handle_tx(struct eg20t_port *priv)
954 struct uart_port *port = &priv->port;
955 struct circ_buf *xmit = &port->state->xmit;
956 struct scatterlist *sg;
960 struct dma_async_tx_descriptor *desc;
967 if (!priv->start_tx) {
968 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
970 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
975 if (priv->tx_dma_use) {
976 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n",
978 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
983 fifo_size = max(priv->fifo_size, 1);
985 if (pop_tx_x(priv, xmit->buf)) {
986 pch_uart_hal_write(priv, xmit->buf, 1);
992 bytes = min((int)CIRC_CNT(xmit->head, xmit->tail,
993 UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
994 xmit->tail, UART_XMIT_SIZE));
996 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__);
997 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
998 uart_write_wakeup(port);
1002 if (bytes > fifo_size) {
1003 num = bytes / fifo_size + 1;
1005 rem = bytes % fifo_size;
1012 dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n",
1013 __func__, num, size, rem);
1015 priv->tx_dma_use = 1;
1017 priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
1018 if (!priv->sg_tx_p) {
1019 dev_err(priv->port.dev, "%s:kzalloc Failed\n", __func__);
1023 sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
1026 for (i = 0; i < num; i++, sg++) {
1028 sg_set_page(sg, virt_to_page(xmit->buf),
1029 rem, fifo_size * i);
1031 sg_set_page(sg, virt_to_page(xmit->buf),
1032 size, fifo_size * i);
1036 nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);
1038 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__);
1043 for (i = 0; i < nent; i++, sg++) {
1044 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) +
1046 sg_dma_address(sg) = (sg_dma_address(sg) &
1047 ~(UART_XMIT_SIZE - 1)) + sg->offset;
1048 if (i == (nent - 1))
1049 sg_dma_len(sg) = rem;
1051 sg_dma_len(sg) = size;
1054 desc = dmaengine_prep_slave_sg(priv->chan_tx,
1055 priv->sg_tx_p, nent, DMA_MEM_TO_DEV,
1056 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1058 dev_err(priv->port.dev, "%s:device_prep_slave_sg Failed\n",
1062 dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);
1063 priv->desc_tx = desc;
1064 desc->callback = pch_dma_tx_complete;
1065 desc->callback_param = priv;
1067 desc->tx_submit(desc);
1069 dma_async_issue_pending(priv->chan_tx);
1071 return PCH_UART_HANDLED_TX_INT;
1074 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
1076 struct uart_port *port = &priv->port;
1077 struct tty_struct *tty = tty_port_tty_get(&port->state->port);
1078 char *error_msg[5] = {};
1081 if (lsr & PCH_UART_LSR_ERR)
1082 error_msg[i++] = "Error data in FIFO\n";
1084 if (lsr & UART_LSR_FE) {
1085 port->icount.frame++;
1086 error_msg[i++] = " Framing Error\n";
1089 if (lsr & UART_LSR_PE) {
1090 port->icount.parity++;
1091 error_msg[i++] = " Parity Error\n";
1094 if (lsr & UART_LSR_OE) {
1095 port->icount.overrun++;
1096 error_msg[i++] = " Overrun Error\n";
1100 for (i = 0; error_msg[i] != NULL; i++)
1101 dev_err(&priv->pdev->dev, error_msg[i]);
1107 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
1109 struct eg20t_port *priv = dev_id;
1110 unsigned int handled;
1114 unsigned long flags;
1118 spin_lock_irqsave(&priv->lock, flags);
1121 iid = pch_uart_hal_get_iid(priv);
1122 if (iid & PCH_UART_IIR_IP) /* No Interrupt */
1125 case PCH_UART_IID_RLS: /* Receiver Line Status */
1126 lsr = pch_uart_hal_get_line_status(priv);
1127 if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
1128 UART_LSR_PE | UART_LSR_OE)) {
1129 pch_uart_err_ir(priv, lsr);
1130 ret = PCH_UART_HANDLED_RX_ERR_INT;
1132 ret = PCH_UART_HANDLED_LS_INT;
1135 case PCH_UART_IID_RDR: /* Received Data Ready */
1136 if (priv->use_dma) {
1137 pch_uart_hal_disable_interrupt(priv,
1138 PCH_UART_HAL_RX_INT |
1139 PCH_UART_HAL_RX_ERR_INT);
1140 ret = dma_handle_rx(priv);
1142 pch_uart_hal_enable_interrupt(priv,
1143 PCH_UART_HAL_RX_INT |
1144 PCH_UART_HAL_RX_ERR_INT);
1146 ret = handle_rx(priv);
1149 case PCH_UART_IID_RDR_TO: /* Received Data Ready
1151 ret = handle_rx_to(priv);
1153 case PCH_UART_IID_THRE: /* Transmitter Holding Register
1156 ret = dma_handle_tx(priv);
1158 ret = handle_tx(priv);
1160 case PCH_UART_IID_MS: /* Modem Status */
1161 msr = pch_uart_hal_get_modem(priv);
1162 next = 0; /* MS ir prioirty is the lowest. So, MS ir
1163 means final interrupt */
1164 if ((msr & UART_MSR_ANY_DELTA) == 0)
1166 ret |= PCH_UART_HANDLED_MS_INT;
1168 default: /* Never junp to this label */
1169 dev_err(priv->port.dev, "%s:iid=%02x (%lu)\n", __func__,
1175 handled |= (unsigned int)ret;
1178 spin_unlock_irqrestore(&priv->lock, flags);
1179 return IRQ_RETVAL(handled);
1182 /* This function tests whether the transmitter fifo and shifter for the port
1183 described by 'port' is empty. */
1184 static unsigned int pch_uart_tx_empty(struct uart_port *port)
1186 struct eg20t_port *priv;
1188 priv = container_of(port, struct eg20t_port, port);
1190 return TIOCSER_TEMT;
1195 /* Returns the current state of modem control inputs. */
1196 static unsigned int pch_uart_get_mctrl(struct uart_port *port)
1198 struct eg20t_port *priv;
1200 unsigned int ret = 0;
1202 priv = container_of(port, struct eg20t_port, port);
1203 modem = pch_uart_hal_get_modem(priv);
1205 if (modem & UART_MSR_DCD)
1208 if (modem & UART_MSR_RI)
1211 if (modem & UART_MSR_DSR)
1214 if (modem & UART_MSR_CTS)
1220 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1223 struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
1225 if (mctrl & TIOCM_DTR)
1226 mcr |= UART_MCR_DTR;
1227 if (mctrl & TIOCM_RTS)
1228 mcr |= UART_MCR_RTS;
1229 if (mctrl & TIOCM_LOOP)
1230 mcr |= UART_MCR_LOOP;
1232 if (priv->mcr & UART_MCR_AFE)
1233 mcr |= UART_MCR_AFE;
1236 iowrite8(mcr, priv->membase + UART_MCR);
1239 static void pch_uart_stop_tx(struct uart_port *port)
1241 struct eg20t_port *priv;
1242 priv = container_of(port, struct eg20t_port, port);
1244 priv->tx_dma_use = 0;
1247 static void pch_uart_start_tx(struct uart_port *port)
1249 struct eg20t_port *priv;
1251 priv = container_of(port, struct eg20t_port, port);
1253 if (priv->use_dma) {
1254 if (priv->tx_dma_use) {
1255 dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n",
1262 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
1265 static void pch_uart_stop_rx(struct uart_port *port)
1267 struct eg20t_port *priv;
1268 priv = container_of(port, struct eg20t_port, port);
1270 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
1271 PCH_UART_HAL_RX_ERR_INT);
1274 /* Enable the modem status interrupts. */
1275 static void pch_uart_enable_ms(struct uart_port *port)
1277 struct eg20t_port *priv;
1278 priv = container_of(port, struct eg20t_port, port);
1279 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
1282 /* Control the transmission of a break signal. */
1283 static void pch_uart_break_ctl(struct uart_port *port, int ctl)
1285 struct eg20t_port *priv;
1286 unsigned long flags;
1288 priv = container_of(port, struct eg20t_port, port);
1289 spin_lock_irqsave(&priv->lock, flags);
1290 pch_uart_hal_set_break(priv, ctl);
1291 spin_unlock_irqrestore(&priv->lock, flags);
1294 /* Grab any interrupt resources and initialise any low level driver state. */
1295 static int pch_uart_startup(struct uart_port *port)
1297 struct eg20t_port *priv;
1302 priv = container_of(port, struct eg20t_port, port);
1306 priv->uartclk = port->uartclk;
1308 port->uartclk = priv->uartclk;
1310 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1311 ret = pch_uart_hal_set_line(priv, default_baud,
1312 PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
1317 switch (priv->fifo_size) {
1319 fifo_size = PCH_UART_HAL_FIFO256;
1322 fifo_size = PCH_UART_HAL_FIFO64;
1325 fifo_size = PCH_UART_HAL_FIFO16;
1329 fifo_size = PCH_UART_HAL_FIFO_DIS;
1333 switch (priv->trigger) {
1334 case PCH_UART_HAL_TRIGGER1:
1337 case PCH_UART_HAL_TRIGGER_L:
1338 trigger_level = priv->fifo_size / 4;
1340 case PCH_UART_HAL_TRIGGER_M:
1341 trigger_level = priv->fifo_size / 2;
1343 case PCH_UART_HAL_TRIGGER_H:
1345 trigger_level = priv->fifo_size - (priv->fifo_size / 8);
1349 priv->trigger_level = trigger_level;
1350 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1351 fifo_size, priv->trigger);
1355 ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
1356 KBUILD_MODNAME, priv);
1361 pch_request_dma(port);
1364 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
1365 PCH_UART_HAL_RX_ERR_INT);
1366 uart_update_timeout(port, CS8, default_baud);
1371 static void pch_uart_shutdown(struct uart_port *port)
1373 struct eg20t_port *priv;
1376 priv = container_of(port, struct eg20t_port, port);
1377 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1378 pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
1379 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1380 PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
1382 dev_err(priv->port.dev,
1383 "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
1387 free_irq(priv->port.irq, priv);
1390 /* Change the port parameters, including word length, parity, stop
1391 *bits. Update read_status_mask and ignore_status_mask to indicate
1392 *the types of events we are interested in receiving. */
1393 static void pch_uart_set_termios(struct uart_port *port,
1394 struct ktermios *termios, struct ktermios *old)
1397 unsigned int baud, parity, bits, stb;
1398 struct eg20t_port *priv;
1399 unsigned long flags;
1401 priv = container_of(port, struct eg20t_port, port);
1402 switch (termios->c_cflag & CSIZE) {
1404 bits = PCH_UART_HAL_5BIT;
1407 bits = PCH_UART_HAL_6BIT;
1410 bits = PCH_UART_HAL_7BIT;
1413 bits = PCH_UART_HAL_8BIT;
1416 if (termios->c_cflag & CSTOPB)
1417 stb = PCH_UART_HAL_STB2;
1419 stb = PCH_UART_HAL_STB1;
1421 if (termios->c_cflag & PARENB) {
1422 if (termios->c_cflag & PARODD)
1423 parity = PCH_UART_HAL_PARITY_ODD;
1425 parity = PCH_UART_HAL_PARITY_EVEN;
1428 parity = PCH_UART_HAL_PARITY_NONE;
1430 /* Only UART0 has auto hardware flow function */
1431 if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256))
1432 priv->mcr |= UART_MCR_AFE;
1434 priv->mcr &= ~UART_MCR_AFE;
1436 termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
1438 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1440 spin_lock_irqsave(&priv->lock, flags);
1441 spin_lock(&port->lock);
1443 uart_update_timeout(port, termios->c_cflag, baud);
1444 rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
1448 pch_uart_set_mctrl(&priv->port, priv->port.mctrl);
1449 /* Don't rewrite B0 */
1450 if (tty_termios_baud_rate(termios))
1451 tty_termios_encode_baud_rate(termios, baud, baud);
1454 spin_unlock(&port->lock);
1455 spin_unlock_irqrestore(&priv->lock, flags);
1458 static const char *pch_uart_type(struct uart_port *port)
1460 return KBUILD_MODNAME;
1463 static void pch_uart_release_port(struct uart_port *port)
1465 struct eg20t_port *priv;
1467 priv = container_of(port, struct eg20t_port, port);
1468 pci_iounmap(priv->pdev, priv->membase);
1469 pci_release_regions(priv->pdev);
1472 static int pch_uart_request_port(struct uart_port *port)
1474 struct eg20t_port *priv;
1476 void __iomem *membase;
1478 priv = container_of(port, struct eg20t_port, port);
1479 ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
1483 membase = pci_iomap(priv->pdev, 1, 0);
1485 pci_release_regions(priv->pdev);
1488 priv->membase = port->membase = membase;
1493 static void pch_uart_config_port(struct uart_port *port, int type)
1495 struct eg20t_port *priv;
1497 priv = container_of(port, struct eg20t_port, port);
1498 if (type & UART_CONFIG_TYPE) {
1499 port->type = priv->port_type;
1500 pch_uart_request_port(port);
1504 static int pch_uart_verify_port(struct uart_port *port,
1505 struct serial_struct *serinfo)
1507 struct eg20t_port *priv;
1509 priv = container_of(port, struct eg20t_port, port);
1510 if (serinfo->flags & UPF_LOW_LATENCY) {
1511 dev_info(priv->port.dev,
1512 "PCH UART : Use PIO Mode (without DMA)\n");
1514 serinfo->flags &= ~UPF_LOW_LATENCY;
1516 #ifndef CONFIG_PCH_DMA
1517 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n",
1521 dev_info(priv->port.dev, "PCH UART : Use DMA Mode\n");
1523 pch_request_dma(port);
1530 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_PCH_UART_CONSOLE)
1532 * Wait for transmitter & holding register to empty
1534 static void wait_for_xmitr(struct eg20t_port *up, int bits)
1536 unsigned int status, tmout = 10000;
1538 /* Wait up to 10ms for the character(s) to be sent. */
1540 status = ioread8(up->membase + UART_LSR);
1542 if ((status & bits) == bits)
1549 /* Wait up to 1s for flow control if necessary */
1550 if (up->port.flags & UPF_CONS_FLOW) {
1552 for (tmout = 1000000; tmout; tmout--) {
1553 unsigned int msr = ioread8(up->membase + UART_MSR);
1554 if (msr & UART_MSR_CTS)
1557 touch_nmi_watchdog();
1561 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_PCH_UART_CONSOLE */
1563 #ifdef CONFIG_CONSOLE_POLL
1565 * Console polling routines for communicate via uart while
1566 * in an interrupt or debug context.
1568 static int pch_uart_get_poll_char(struct uart_port *port)
1570 struct eg20t_port *priv =
1571 container_of(port, struct eg20t_port, port);
1572 u8 lsr = ioread8(priv->membase + UART_LSR);
1574 if (!(lsr & UART_LSR_DR))
1575 return NO_POLL_CHAR;
1577 return ioread8(priv->membase + PCH_UART_RBR);
1581 static void pch_uart_put_poll_char(struct uart_port *port,
1585 struct eg20t_port *priv =
1586 container_of(port, struct eg20t_port, port);
1589 * First save the IER then disable the interrupts
1591 ier = ioread8(priv->membase + UART_IER);
1592 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1594 wait_for_xmitr(priv, UART_LSR_THRE);
1596 * Send the character out.
1597 * If a LF, also do CR...
1599 iowrite8(c, priv->membase + PCH_UART_THR);
1601 wait_for_xmitr(priv, UART_LSR_THRE);
1602 iowrite8(13, priv->membase + PCH_UART_THR);
1606 * Finally, wait for transmitter to become empty
1607 * and restore the IER
1609 wait_for_xmitr(priv, BOTH_EMPTY);
1610 iowrite8(ier, priv->membase + UART_IER);
1612 #endif /* CONFIG_CONSOLE_POLL */
1614 static struct uart_ops pch_uart_ops = {
1615 .tx_empty = pch_uart_tx_empty,
1616 .set_mctrl = pch_uart_set_mctrl,
1617 .get_mctrl = pch_uart_get_mctrl,
1618 .stop_tx = pch_uart_stop_tx,
1619 .start_tx = pch_uart_start_tx,
1620 .stop_rx = pch_uart_stop_rx,
1621 .enable_ms = pch_uart_enable_ms,
1622 .break_ctl = pch_uart_break_ctl,
1623 .startup = pch_uart_startup,
1624 .shutdown = pch_uart_shutdown,
1625 .set_termios = pch_uart_set_termios,
1626 /* .pm = pch_uart_pm, Not supported yet */
1627 /* .set_wake = pch_uart_set_wake, Not supported yet */
1628 .type = pch_uart_type,
1629 .release_port = pch_uart_release_port,
1630 .request_port = pch_uart_request_port,
1631 .config_port = pch_uart_config_port,
1632 .verify_port = pch_uart_verify_port,
1633 #ifdef CONFIG_CONSOLE_POLL
1634 .poll_get_char = pch_uart_get_poll_char,
1635 .poll_put_char = pch_uart_put_poll_char,
1639 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1641 static void pch_console_putchar(struct uart_port *port, int ch)
1643 struct eg20t_port *priv =
1644 container_of(port, struct eg20t_port, port);
1646 wait_for_xmitr(priv, UART_LSR_THRE);
1647 iowrite8(ch, priv->membase + PCH_UART_THR);
1651 * Print a string to the serial port trying not to disturb
1652 * any possible real use of the port...
1654 * The console_lock must be held when we get here.
1657 pch_console_write(struct console *co, const char *s, unsigned int count)
1659 struct eg20t_port *priv;
1660 unsigned long flags;
1661 int priv_locked = 1;
1662 int port_locked = 1;
1665 priv = pch_uart_ports[co->index];
1667 touch_nmi_watchdog();
1669 local_irq_save(flags);
1670 if (priv->port.sysrq) {
1671 /* call to uart_handle_sysrq_char already took the priv lock */
1673 /* serial8250_handle_port() already took the port lock */
1675 } else if (oops_in_progress) {
1676 priv_locked = spin_trylock(&priv->lock);
1677 port_locked = spin_trylock(&priv->port.lock);
1679 spin_lock(&priv->lock);
1680 spin_lock(&priv->port.lock);
1684 * First save the IER then disable the interrupts
1686 ier = ioread8(priv->membase + UART_IER);
1688 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1690 uart_console_write(&priv->port, s, count, pch_console_putchar);
1693 * Finally, wait for transmitter to become empty
1694 * and restore the IER
1696 wait_for_xmitr(priv, BOTH_EMPTY);
1697 iowrite8(ier, priv->membase + UART_IER);
1700 spin_unlock(&priv->port.lock);
1702 spin_unlock(&priv->lock);
1703 local_irq_restore(flags);
1706 static int __init pch_console_setup(struct console *co, char *options)
1708 struct uart_port *port;
1709 int baud = default_baud;
1715 * Check whether an invalid uart number has been specified, and
1716 * if so, search for the first available port that does have
1719 if (co->index >= PCH_UART_NR)
1721 port = &pch_uart_ports[co->index]->port;
1723 if (!port || (!port->iobase && !port->membase))
1726 port->uartclk = pch_uart_get_uartclk();
1729 uart_parse_options(options, &baud, &parity, &bits, &flow);
1731 return uart_set_options(port, co, baud, parity, bits, flow);
1734 static struct uart_driver pch_uart_driver;
1736 static struct console pch_console = {
1737 .name = PCH_UART_DRIVER_DEVICE,
1738 .write = pch_console_write,
1739 .device = uart_console_device,
1740 .setup = pch_console_setup,
1741 .flags = CON_PRINTBUFFER | CON_ANYTIME,
1743 .data = &pch_uart_driver,
1746 #define PCH_CONSOLE (&pch_console)
1748 #define PCH_CONSOLE NULL
1749 #endif /* CONFIG_SERIAL_PCH_UART_CONSOLE */
1751 static struct uart_driver pch_uart_driver = {
1752 .owner = THIS_MODULE,
1753 .driver_name = KBUILD_MODNAME,
1754 .dev_name = PCH_UART_DRIVER_DEVICE,
1758 .cons = PCH_CONSOLE,
1761 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1762 const struct pci_device_id *id)
1764 struct eg20t_port *priv;
1766 unsigned int iobase;
1767 unsigned int mapbase;
1768 unsigned char *rxbuf;
1771 struct pch_uart_driver_data *board;
1772 char name[32]; /* for debugfs file name */
1774 board = &drv_dat[id->driver_data];
1775 port_type = board->port_type;
1777 priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
1779 goto init_port_alloc_err;
1781 rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
1783 goto init_port_free_txbuf;
1785 switch (port_type) {
1787 fifosize = 256; /* EG20T/ML7213: UART0 */
1790 fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/
1793 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
1794 goto init_port_hal_free;
1797 pci_enable_msi(pdev);
1798 pci_set_master(pdev);
1800 spin_lock_init(&priv->lock);
1802 iobase = pci_resource_start(pdev, 0);
1803 mapbase = pci_resource_start(pdev, 1);
1804 priv->mapbase = mapbase;
1805 priv->iobase = iobase;
1808 priv->rxbuf.buf = rxbuf;
1809 priv->rxbuf.size = PAGE_SIZE;
1811 priv->fifo_size = fifosize;
1812 priv->uartclk = pch_uart_get_uartclk();
1813 priv->port_type = PORT_MAX_8250 + port_type + 1;
1814 priv->port.dev = &pdev->dev;
1815 priv->port.iobase = iobase;
1816 priv->port.membase = NULL;
1817 priv->port.mapbase = mapbase;
1818 priv->port.irq = pdev->irq;
1819 priv->port.iotype = UPIO_PORT;
1820 priv->port.ops = &pch_uart_ops;
1821 priv->port.flags = UPF_BOOT_AUTOCONF;
1822 priv->port.fifosize = fifosize;
1823 priv->port.line = board->line_no;
1824 priv->trigger = PCH_UART_HAL_TRIGGER_M;
1826 spin_lock_init(&priv->port.lock);
1828 pci_set_drvdata(pdev, priv);
1829 priv->trigger_level = 1;
1832 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1833 pch_uart_ports[board->line_no] = priv;
1835 ret = uart_add_one_port(&pch_uart_driver, &priv->port);
1837 goto init_port_hal_free;
1839 #ifdef CONFIG_DEBUG_FS
1840 snprintf(name, sizeof(name), "uart%d_regs", board->line_no);
1841 priv->debugfs = debugfs_create_file(name, S_IFREG | S_IRUGO,
1842 NULL, priv, &port_regs_ops);
1848 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1849 pch_uart_ports[board->line_no] = NULL;
1851 free_page((unsigned long)rxbuf);
1852 init_port_free_txbuf:
1854 init_port_alloc_err:
1859 static void pch_uart_exit_port(struct eg20t_port *priv)
1862 #ifdef CONFIG_DEBUG_FS
1864 debugfs_remove(priv->debugfs);
1866 uart_remove_one_port(&pch_uart_driver, &priv->port);
1867 pci_set_drvdata(priv->pdev, NULL);
1868 free_page((unsigned long)priv->rxbuf.buf);
1871 static void pch_uart_pci_remove(struct pci_dev *pdev)
1873 struct eg20t_port *priv = pci_get_drvdata(pdev);
1875 pci_disable_msi(pdev);
1877 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1878 pch_uart_ports[priv->port.line] = NULL;
1880 pch_uart_exit_port(priv);
1881 pci_disable_device(pdev);
1886 static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1888 struct eg20t_port *priv = pci_get_drvdata(pdev);
1890 uart_suspend_port(&pch_uart_driver, &priv->port);
1892 pci_save_state(pdev);
1893 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1897 static int pch_uart_pci_resume(struct pci_dev *pdev)
1899 struct eg20t_port *priv = pci_get_drvdata(pdev);
1902 pci_set_power_state(pdev, PCI_D0);
1903 pci_restore_state(pdev);
1905 ret = pci_enable_device(pdev);
1908 "%s-pci_enable_device failed(ret=%d) ", __func__, ret);
1912 uart_resume_port(&pch_uart_driver, &priv->port);
1917 #define pch_uart_pci_suspend NULL
1918 #define pch_uart_pci_resume NULL
1921 static DEFINE_PCI_DEVICE_TABLE(pch_uart_pci_id) = {
1922 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
1923 .driver_data = pch_et20t_uart0},
1924 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
1925 .driver_data = pch_et20t_uart1},
1926 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
1927 .driver_data = pch_et20t_uart2},
1928 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
1929 .driver_data = pch_et20t_uart3},
1930 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),
1931 .driver_data = pch_ml7213_uart0},
1932 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),
1933 .driver_data = pch_ml7213_uart1},
1934 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
1935 .driver_data = pch_ml7213_uart2},
1936 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C),
1937 .driver_data = pch_ml7223_uart0},
1938 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D),
1939 .driver_data = pch_ml7223_uart1},
1940 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811),
1941 .driver_data = pch_ml7831_uart0},
1942 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812),
1943 .driver_data = pch_ml7831_uart1},
1947 static int pch_uart_pci_probe(struct pci_dev *pdev,
1948 const struct pci_device_id *id)
1951 struct eg20t_port *priv;
1953 ret = pci_enable_device(pdev);
1957 priv = pch_uart_init_port(pdev, id);
1960 goto probe_disable_device;
1962 pci_set_drvdata(pdev, priv);
1966 probe_disable_device:
1967 pci_disable_msi(pdev);
1968 pci_disable_device(pdev);
1973 static struct pci_driver pch_uart_pci_driver = {
1975 .id_table = pch_uart_pci_id,
1976 .probe = pch_uart_pci_probe,
1977 .remove = pch_uart_pci_remove,
1978 .suspend = pch_uart_pci_suspend,
1979 .resume = pch_uart_pci_resume,
1982 static int __init pch_uart_module_init(void)
1986 /* register as UART driver */
1987 ret = uart_register_driver(&pch_uart_driver);
1991 /* register as PCI driver */
1992 ret = pci_register_driver(&pch_uart_pci_driver);
1994 uart_unregister_driver(&pch_uart_driver);
1998 module_init(pch_uart_module_init);
2000 static void __exit pch_uart_module_exit(void)
2002 pci_unregister_driver(&pch_uart_pci_driver);
2003 uart_unregister_driver(&pch_uart_driver);
2005 module_exit(pch_uart_module_exit);
2007 MODULE_LICENSE("GPL v2");
2008 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
2009 module_param(default_baud, uint, S_IRUGO);
2010 MODULE_PARM_DESC(default_baud,
2011 "Default BAUD for initial driver state and console (default 9600)");
2012 module_param(user_uartclk, uint, S_IRUGO);
2013 MODULE_PARM_DESC(user_uartclk,
2014 "Override UART default or board specific UART clock");