drivers/tty/serial/samsung.c

   1 /*
   2  * Driver core for Samsung SoC onboard UARTs.
   3  *
   4  * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
   5  *      http://armlinux.simtec.co.uk/
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 /* Hote on 2410 error handling
  13  *
  14  * The s3c2410 manual has a love/hate affair with the contents of the
  15  * UERSTAT register in the UART blocks, and keeps marking some of the
  16  * error bits as reserved. Having checked with the s3c2410x01,
  17  * it copes with BREAKs properly, so I am happy to ignore the RESERVED
  18  * feature from the latter versions of the manual.
  19  *
  20  * If it becomes aparrent that latter versions of the 2410 remove these
  21  * bits, then action will have to be taken to differentiate the versions
  22  * and change the policy on BREAK
  23  *
  24  * BJD, 04-Nov-2004
  25 */
  26
  27 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  28 #define SUPPORT_SYSRQ
  29 #endif
  30
  31 #include <linux/dmaengine.h>
  32 #include <linux/dma-mapping.h>
  33 #include <linux/slab.h>
  34 #include <linux/module.h>
  35 #include <linux/ioport.h>
  36 #include <linux/io.h>
  37 #include <linux/platform_device.h>
  38 #include <linux/init.h>
  39 #include <linux/sysrq.h>
  40 #include <linux/console.h>
  41 #include <linux/tty.h>
  42 #include <linux/tty_flip.h>
  43 #include <linux/serial_core.h>
  44 #include <linux/serial.h>
  45 #include <linux/serial_s3c.h>
  46 #include <linux/delay.h>
  47 #include <linux/clk.h>
  48 #include <linux/cpufreq.h>
  49 #include <linux/of.h>
  50
  51 #include <asm/irq.h>
  52
  53 #include "samsung.h"
  54
  55 #if     defined(CONFIG_SERIAL_SAMSUNG_DEBUG) && \
  56         !defined(MODULE)
  57
  58 extern void printascii(const char *);
  59
  60 __printf(1, 2)
  61 static void dbg(const char *fmt, ...)
  62 {
  63         va_list va;
  64         char buff[256];
  65
  66         va_start(va, fmt);
  67         vscnprintf(buff, sizeof(buff), fmt, va);
  68         va_end(va);
  69
  70         printascii(buff);
  71 }
  72
  73 #else
  74 #define dbg(fmt, ...) do { if (0) no_printk(fmt, ##__VA_ARGS__); } while (0)
  75 #endif
  76
  77 /* UART name and device definitions */
  78
  79 #define S3C24XX_SERIAL_NAME     "ttySAC"
  80 #define S3C24XX_SERIAL_MAJOR    204
  81 #define S3C24XX_SERIAL_MINOR    64
  82
  83 #define S3C24XX_TX_PIO                  1
  84 #define S3C24XX_TX_DMA                  2
  85 #define S3C24XX_RX_PIO                  1
  86 #define S3C24XX_RX_DMA                  2
  87 /* macros to change one thing to another */
  88
  89 #define tx_enabled(port) ((port)->unused[0])
  90 #define rx_enabled(port) ((port)->unused[1])
  91
  92 /* flag to ignore all characters coming in */
  93 #define RXSTAT_DUMMY_READ (0x10000000)
  94
  95 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
  96 {
  97         return container_of(port, struct s3c24xx_uart_port, port);
  98 }
  99
 100 /* translate a port to the device name */
 101
 102 static inline const char *s3c24xx_serial_portname(struct uart_port *port)
 103 {
 104         return to_platform_device(port->dev)->name;
 105 }
 106
 107 static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
 108 {
 109         return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
 110 }
 111
 112 /*
 113  * s3c64xx and later SoC's include the interrupt mask and status registers in
 114  * the controller itself, unlike the s3c24xx SoC's which have these registers
 115  * in the interrupt controller. Check if the port type is s3c64xx or higher.
 116  */
 117 static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
 118 {
 119         return to_ourport(port)->info->type == PORT_S3C6400;
 120 }
 121
 122 static void s3c24xx_serial_rx_enable(struct uart_port *port)
 123 {
 124         unsigned long flags;
 125         unsigned int ucon, ufcon;
 126         int count = 10000;
 127
 128         spin_lock_irqsave(&port->lock, flags);
 129
 130         while (--count && !s3c24xx_serial_txempty_nofifo(port))
 131                 udelay(100);
 132
 133         ufcon = rd_regl(port, S3C2410_UFCON);
 134         ufcon |= S3C2410_UFCON_RESETRX;
 135         wr_regl(port, S3C2410_UFCON, ufcon);
 136
 137         ucon = rd_regl(port, S3C2410_UCON);
 138         ucon |= S3C2410_UCON_RXIRQMODE;
 139         wr_regl(port, S3C2410_UCON, ucon);
 140
 141         rx_enabled(port) = 1;
 142         spin_unlock_irqrestore(&port->lock, flags);
 143 }
 144
 145 static void s3c24xx_serial_rx_disable(struct uart_port *port)
 146 {
 147         unsigned long flags;
 148         unsigned int ucon;
 149
 150         spin_lock_irqsave(&port->lock, flags);
 151
 152         ucon = rd_regl(port, S3C2410_UCON);
 153         ucon &= ~S3C2410_UCON_RXIRQMODE;
 154         wr_regl(port, S3C2410_UCON, ucon);
 155
 156         rx_enabled(port) = 0;
 157         spin_unlock_irqrestore(&port->lock, flags);
 158 }
 159
 160 static void s3c24xx_serial_stop_tx(struct uart_port *port)
 161 {
 162         struct s3c24xx_uart_port *ourport = to_ourport(port);
 163         struct s3c24xx_uart_dma *dma = ourport->dma;
 164         struct circ_buf *xmit = &port->state->xmit;
 165         struct dma_tx_state state;
 166         int count;
 167
 168         if (!tx_enabled(port))
 169                 return;
 170
 171         if (s3c24xx_serial_has_interrupt_mask(port))
 172                 __set_bit(S3C64XX_UINTM_TXD,
 173                         portaddrl(port, S3C64XX_UINTM));
 174         else
 175                 disable_irq_nosync(ourport->tx_irq);
 176
 177         if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) {
 178                 dmaengine_pause(dma->tx_chan);
 179                 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
 180                 dmaengine_terminate_all(dma->tx_chan);
 181                 dma_sync_single_for_cpu(ourport->port.dev,
 182                         dma->tx_transfer_addr, dma->tx_size, DMA_TO_DEVICE);
 183                 async_tx_ack(dma->tx_desc);
 184                 count = dma->tx_bytes_requested - state.residue;
 185                 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
 186                 port->icount.tx += count;
 187         }
 188
 189         tx_enabled(port) = 0;
 190         ourport->tx_in_progress = 0;
 191
 192         if (port->flags & UPF_CONS_FLOW)
 193                 s3c24xx_serial_rx_enable(port);
 194
 195         ourport->tx_mode = 0;
 196 }
 197
 198 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport);
 199
 200 static void s3c24xx_serial_tx_dma_complete(void *args)
 201 {
 202         struct s3c24xx_uart_port *ourport = args;
 203         struct uart_port *port = &ourport->port;
 204         struct circ_buf *xmit = &port->state->xmit;
 205         struct s3c24xx_uart_dma *dma = ourport->dma;
 206         struct dma_tx_state state;
 207         unsigned long flags;
 208         int count;
 209
 210
 211         dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
 212         count = dma->tx_bytes_requested - state.residue;
 213         async_tx_ack(dma->tx_desc);
 214
 215         dma_sync_single_for_cpu(ourport->port.dev, dma->tx_transfer_addr,
 216                                 dma->tx_size, DMA_TO_DEVICE);
 217
 218         spin_lock_irqsave(&port->lock, flags);
 219
 220         xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
 221         port->icount.tx += count;
 222         ourport->tx_in_progress = 0;
 223
 224         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 225                 uart_write_wakeup(port);
 226
 227         s3c24xx_serial_start_next_tx(ourport);
 228         spin_unlock_irqrestore(&port->lock, flags);
 229 }
 230
 231 static void enable_tx_dma(struct s3c24xx_uart_port *ourport)
 232 {
 233         struct uart_port *port = &ourport->port;
 234         u32 ucon;
 235
 236         /* Mask Tx interrupt */
 237         if (s3c24xx_serial_has_interrupt_mask(port))
 238                 __set_bit(S3C64XX_UINTM_TXD,
 239                           portaddrl(port, S3C64XX_UINTM));
 240         else
 241                 disable_irq_nosync(ourport->tx_irq);
 242
 243         /* Enable tx dma mode */
 244         ucon = rd_regl(port, S3C2410_UCON);
 245         ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK);
 246         ucon |= (dma_get_cache_alignment() >= 16) ?
 247                 S3C64XX_UCON_TXBURST_16 : S3C64XX_UCON_TXBURST_1;
 248         ucon |= S3C64XX_UCON_TXMODE_DMA;
 249         wr_regl(port,  S3C2410_UCON, ucon);
 250
 251         ourport->tx_mode = S3C24XX_TX_DMA;
 252 }
 253
 254 static void enable_tx_pio(struct s3c24xx_uart_port *ourport)
 255 {
 256         struct uart_port *port = &ourport->port;
 257         u32 ucon, ufcon;
 258
 259         /* Set ufcon txtrig */
 260         ourport->tx_in_progress = S3C24XX_TX_PIO;
 261         ufcon = rd_regl(port, S3C2410_UFCON);
 262         wr_regl(port,  S3C2410_UFCON, ufcon);
 263
 264         /* Enable tx pio mode */
 265         ucon = rd_regl(port, S3C2410_UCON);
 266         ucon &= ~(S3C64XX_UCON_TXMODE_MASK);
 267         ucon |= S3C64XX_UCON_TXMODE_CPU;
 268         wr_regl(port,  S3C2410_UCON, ucon);
 269
 270         /* Unmask Tx interrupt */
 271         if (s3c24xx_serial_has_interrupt_mask(port))
 272                 __clear_bit(S3C64XX_UINTM_TXD,
 273                             portaddrl(port, S3C64XX_UINTM));
 274         else
 275                 enable_irq(ourport->tx_irq);
 276
 277         ourport->tx_mode = S3C24XX_TX_PIO;
 278 }
 279
 280 static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport)
 281 {
 282         if (ourport->tx_mode != S3C24XX_TX_PIO)
 283                 enable_tx_pio(ourport);
 284 }
 285
 286 static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport,
 287                                       unsigned int count)
 288 {
 289         struct uart_port *port = &ourport->port;
 290         struct circ_buf *xmit = &port->state->xmit;
 291         struct s3c24xx_uart_dma *dma = ourport->dma;
 292
 293
 294         if (ourport->tx_mode != S3C24XX_TX_DMA)
 295                 enable_tx_dma(ourport);
 296
 297         dma->tx_size = count & ~(dma_get_cache_alignment() - 1);
 298         dma->tx_transfer_addr = dma->tx_addr + xmit->tail;
 299
 300         dma_sync_single_for_device(ourport->port.dev, dma->tx_transfer_addr,
 301                                 dma->tx_size, DMA_TO_DEVICE);
 302
 303         dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan,
 304                                 dma->tx_transfer_addr, dma->tx_size,
 305                                 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
 306         if (!dma->tx_desc) {
 307                 dev_err(ourport->port.dev, "Unable to get desc for Tx\n");
 308                 return -EIO;
 309         }
 310
 311         dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete;
 312         dma->tx_desc->callback_param = ourport;
 313         dma->tx_bytes_requested = dma->tx_size;
 314
 315         ourport->tx_in_progress = S3C24XX_TX_DMA;
 316         dma->tx_cookie = dmaengine_submit(dma->tx_desc);
 317         dma_async_issue_pending(dma->tx_chan);
 318         return 0;
 319 }
 320
 321 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport)
 322 {
 323         struct uart_port *port = &ourport->port;
 324         struct circ_buf *xmit = &port->state->xmit;
 325         unsigned long count;
 326
 327         /* Get data size up to the end of buffer */
 328         count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 329
 330         if (!count) {
 331                 s3c24xx_serial_stop_tx(port);
 332                 return;
 333         }
 334
 335         if (!ourport->dma || !ourport->dma->tx_chan ||
 336             count < ourport->min_dma_size ||
 337             xmit->tail & (dma_get_cache_alignment() - 1))
 338                 s3c24xx_serial_start_tx_pio(ourport);
 339         else
 340                 s3c24xx_serial_start_tx_dma(ourport, count);
 341 }
 342
 343 static void s3c24xx_serial_start_tx(struct uart_port *port)
 344 {
 345         struct s3c24xx_uart_port *ourport = to_ourport(port);
 346         struct circ_buf *xmit = &port->state->xmit;
 347
 348         if (!tx_enabled(port)) {
 349                 if (port->flags & UPF_CONS_FLOW)
 350                         s3c24xx_serial_rx_disable(port);
 351
 352                 tx_enabled(port) = 1;
 353                 if (!ourport->dma || !ourport->dma->tx_chan)
 354                         s3c24xx_serial_start_tx_pio(ourport);
 355         }
 356
 357         if (ourport->dma && ourport->dma->tx_chan) {
 358                 if (!uart_circ_empty(xmit) && !ourport->tx_in_progress)
 359                         s3c24xx_serial_start_next_tx(ourport);
 360         }
 361 }
 362
 363 static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport,
 364                 struct tty_port *tty, int count)
 365 {
 366         struct s3c24xx_uart_dma *dma = ourport->dma;
 367         int copied;
 368
 369         if (!count)
 370                 return;
 371
 372         dma_sync_single_for_cpu(ourport->port.dev, dma->rx_addr,
 373                                 dma->rx_size, DMA_FROM_DEVICE);
 374
 375         ourport->port.icount.rx += count;
 376         if (!tty) {
 377                 dev_err(ourport->port.dev, "No tty port\n");
 378                 return;
 379         }
 380         copied = tty_insert_flip_string(tty,
 381                         ((unsigned char *)(ourport->dma->rx_buf)), count);
 382         if (copied != count) {
 383                 WARN_ON(1);
 384                 dev_err(ourport->port.dev, "RxData copy to tty layer failed\n");
 385         }
 386 }
 387
 388 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
 389                                      unsigned long ufstat);
 390
 391 static void uart_rx_drain_fifo(struct s3c24xx_uart_port *ourport)
 392 {
 393         struct uart_port *port = &ourport->port;
 394         struct tty_port *tty = &port->state->port;
 395         unsigned int ch, ufstat;
 396         unsigned int count;
 397
 398         ufstat = rd_regl(port, S3C2410_UFSTAT);
 399         count = s3c24xx_serial_rx_fifocnt(ourport, ufstat);
 400
 401         if (!count)
 402                 return;
 403
 404         while (count-- > 0) {
 405                 ch = rd_regb(port, S3C2410_URXH);
 406
 407                 ourport->port.icount.rx++;
 408                 tty_insert_flip_char(tty, ch, TTY_NORMAL);
 409         }
 410
 411         tty_flip_buffer_push(tty);
 412 }
 413
 414 static void s3c24xx_serial_stop_rx(struct uart_port *port)
 415 {
 416         struct s3c24xx_uart_port *ourport = to_ourport(port);
 417         struct s3c24xx_uart_dma *dma = ourport->dma;
 418         struct tty_port *t = &port->state->port;
 419         struct dma_tx_state state;
 420         enum dma_status dma_status;
 421         unsigned int received;
 422
 423         if (rx_enabled(port)) {
 424                 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
 425                 if (s3c24xx_serial_has_interrupt_mask(port))
 426                         __set_bit(S3C64XX_UINTM_RXD,
 427                                 portaddrl(port, S3C64XX_UINTM));
 428                 else
 429                         disable_irq_nosync(ourport->rx_irq);
 430                 rx_enabled(port) = 0;
 431         }
 432         if (dma && dma->rx_chan) {
 433                 dmaengine_pause(dma->tx_chan);
 434                 dma_status = dmaengine_tx_status(dma->rx_chan,
 435                                 dma->rx_cookie, &state);
 436                 if (dma_status == DMA_IN_PROGRESS ||
 437                         dma_status == DMA_PAUSED) {
 438                         received = dma->rx_bytes_requested - state.residue;
 439                         dmaengine_terminate_all(dma->rx_chan);
 440                         s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 441                 }
 442         }
 443 }
 444
 445 static inline struct s3c24xx_uart_info
 446         *s3c24xx_port_to_info(struct uart_port *port)
 447 {
 448         return to_ourport(port)->info;
 449 }
 450
 451 static inline struct s3c2410_uartcfg
 452         *s3c24xx_port_to_cfg(struct uart_port *port)
 453 {
 454         struct s3c24xx_uart_port *ourport;
 455
 456         if (port->dev == NULL)
 457                 return NULL;
 458
 459         ourport = container_of(port, struct s3c24xx_uart_port, port);
 460         return ourport->cfg;
 461 }
 462
 463 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
 464                                      unsigned long ufstat)
 465 {
 466         struct s3c24xx_uart_info *info = ourport->info;
 467
 468         if (ufstat & info->rx_fifofull)
 469                 return ourport->port.fifosize;
 470
 471         return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
 472 }
 473
 474 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport);
 475 static void s3c24xx_serial_rx_dma_complete(void *args)
 476 {
 477         struct s3c24xx_uart_port *ourport = args;
 478         struct uart_port *port = &ourport->port;
 479
 480         struct s3c24xx_uart_dma *dma = ourport->dma;
 481         struct tty_port *t = &port->state->port;
 482         struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
 483
 484         struct dma_tx_state state;
 485         unsigned long flags;
 486         int received;
 487
 488         dmaengine_tx_status(dma->rx_chan,  dma->rx_cookie, &state);
 489         received  = dma->rx_bytes_requested - state.residue;
 490         async_tx_ack(dma->rx_desc);
 491
 492         spin_lock_irqsave(&port->lock, flags);
 493
 494         if (received)
 495                 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 496
 497         if (tty) {
 498                 tty_flip_buffer_push(t);
 499                 tty_kref_put(tty);
 500         }
 501
 502         s3c64xx_start_rx_dma(ourport);
 503
 504         spin_unlock_irqrestore(&port->lock, flags);
 505 }
 506
 507 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport)
 508 {
 509         struct s3c24xx_uart_dma *dma = ourport->dma;
 510
 511         dma_sync_single_for_device(ourport->port.dev, dma->rx_addr,
 512                                 dma->rx_size, DMA_FROM_DEVICE);
 513
 514         dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan,
 515                                 dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM,
 516                                 DMA_PREP_INTERRUPT);
 517         if (!dma->rx_desc) {
 518                 dev_err(ourport->port.dev, "Unable to get desc for Rx\n");
 519                 return;
 520         }
 521
 522         dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete;
 523         dma->rx_desc->callback_param = ourport;
 524         dma->rx_bytes_requested = dma->rx_size;
 525
 526         dma->rx_cookie = dmaengine_submit(dma->rx_desc);
 527         dma_async_issue_pending(dma->rx_chan);
 528 }
 529
 530 /* ? - where has parity gone?? */
 531 #define S3C2410_UERSTAT_PARITY (0x1000)
 532
 533 static void enable_rx_dma(struct s3c24xx_uart_port *ourport)
 534 {
 535         struct uart_port *port = &ourport->port;
 536         unsigned int ucon;
 537
 538         /* set Rx mode to DMA mode */
 539         ucon = rd_regl(port, S3C2410_UCON);
 540         ucon &= ~(S3C64XX_UCON_RXBURST_MASK |
 541                         S3C64XX_UCON_TIMEOUT_MASK |
 542                         S3C64XX_UCON_EMPTYINT_EN |
 543                         S3C64XX_UCON_DMASUS_EN |
 544                         S3C64XX_UCON_TIMEOUT_EN |
 545                         S3C64XX_UCON_RXMODE_MASK);
 546         ucon |= S3C64XX_UCON_RXBURST_16 |
 547                         0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
 548                         S3C64XX_UCON_EMPTYINT_EN |
 549                         S3C64XX_UCON_TIMEOUT_EN |
 550                         S3C64XX_UCON_RXMODE_DMA;
 551         wr_regl(port, S3C2410_UCON, ucon);
 552
 553         ourport->rx_mode = S3C24XX_RX_DMA;
 554 }
 555
 556 static void enable_rx_pio(struct s3c24xx_uart_port *ourport)
 557 {
 558         struct uart_port *port = &ourport->port;
 559         unsigned int ucon;
 560
 561         /* set Rx mode to DMA mode */
 562         ucon = rd_regl(port, S3C2410_UCON);
 563         ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK |
 564                         S3C64XX_UCON_EMPTYINT_EN |
 565                         S3C64XX_UCON_DMASUS_EN |
 566                         S3C64XX_UCON_TIMEOUT_EN |
 567                         S3C64XX_UCON_RXMODE_MASK);
 568         ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
 569                         S3C64XX_UCON_TIMEOUT_EN |
 570                         S3C64XX_UCON_RXMODE_CPU;
 571         wr_regl(port, S3C2410_UCON, ucon);
 572
 573         ourport->rx_mode = S3C24XX_RX_PIO;
 574 }
 575
 576 static irqreturn_t s3c24xx_serial_rx_chars_dma(void *dev_id)
 577 {
 578         unsigned int utrstat, ufstat, received;
 579         struct s3c24xx_uart_port *ourport = dev_id;
 580         struct uart_port *port = &ourport->port;
 581         struct s3c24xx_uart_dma *dma = ourport->dma;
 582         struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
 583         struct tty_port *t = &port->state->port;
 584         unsigned long flags;
 585         struct dma_tx_state state;
 586
 587         utrstat = rd_regl(port, S3C2410_UTRSTAT);
 588         ufstat = rd_regl(port, S3C2410_UFSTAT);
 589
 590         spin_lock_irqsave(&port->lock, flags);
 591
 592         if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) {
 593                 s3c64xx_start_rx_dma(ourport);
 594                 if (ourport->rx_mode == S3C24XX_RX_PIO)
 595                         enable_rx_dma(ourport);
 596                 goto finish;
 597         }
 598
 599         if (ourport->rx_mode == S3C24XX_RX_DMA) {
 600                 dmaengine_pause(dma->rx_chan);
 601                 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
 602                 dmaengine_terminate_all(dma->rx_chan);
 603                 received = dma->rx_bytes_requested - state.residue;
 604                 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 605
 606                 enable_rx_pio(ourport);
 607         }
 608
 609         uart_rx_drain_fifo(ourport);
 610
 611         if (tty) {
 612                 tty_flip_buffer_push(t);
 613                 tty_kref_put(tty);
 614         }
 615
 616         wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT);
 617
 618 finish:
 619         spin_unlock_irqrestore(&port->lock, flags);
 620
 621         return IRQ_HANDLED;
 622 }
 623
 624 static irqreturn_t s3c24xx_serial_rx_chars_pio(void *dev_id)
 625 {
 626         struct s3c24xx_uart_port *ourport = dev_id;
 627         struct uart_port *port = &ourport->port;
 628         unsigned int ufcon, ch, flag, ufstat, uerstat;
 629         unsigned long flags;
 630         int max_count = port->fifosize;
 631
 632         spin_lock_irqsave(&port->lock, flags);
 633
 634         while (max_count-- > 0) {
 635                 ufcon = rd_regl(port, S3C2410_UFCON);
 636                 ufstat = rd_regl(port, S3C2410_UFSTAT);
 637
 638                 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
 639                         break;
 640
 641                 uerstat = rd_regl(port, S3C2410_UERSTAT);
 642                 ch = rd_regb(port, S3C2410_URXH);
 643
 644                 if (port->flags & UPF_CONS_FLOW) {
 645                         int txe = s3c24xx_serial_txempty_nofifo(port);
 646
 647                         if (rx_enabled(port)) {
 648                                 if (!txe) {
 649                                         rx_enabled(port) = 0;
 650                                         continue;
 651                                 }
 652                         } else {
 653                                 if (txe) {
 654                                         ufcon |= S3C2410_UFCON_RESETRX;
 655                                         wr_regl(port, S3C2410_UFCON, ufcon);
 656                                         rx_enabled(port) = 1;
 657                                         spin_unlock_irqrestore(&port->lock,
 658                                                         flags);
 659                                         goto out;
 660                                 }
 661                                 continue;
 662                         }
 663                 }
 664
 665                 /* insert the character into the buffer */
 666
 667                 flag = TTY_NORMAL;
 668                 port->icount.rx++;
 669
 670                 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
 671                         dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
 672                             ch, uerstat);
 673
 674                         /* check for break */
 675                         if (uerstat & S3C2410_UERSTAT_BREAK) {
 676                                 dbg("break!\n");
 677                                 port->icount.brk++;
 678                                 if (uart_handle_break(port))
 679                                         continue; /* Ignore character */
 680                         }
 681
 682                         if (uerstat & S3C2410_UERSTAT_FRAME)
 683                                 port->icount.frame++;
 684                         if (uerstat & S3C2410_UERSTAT_OVERRUN)
 685                                 port->icount.overrun++;
 686
 687                         uerstat &= port->read_status_mask;
 688
 689                         if (uerstat & S3C2410_UERSTAT_BREAK)
 690                                 flag = TTY_BREAK;
 691                         else if (uerstat & S3C2410_UERSTAT_PARITY)
 692                                 flag = TTY_PARITY;
 693                         else if (uerstat & (S3C2410_UERSTAT_FRAME |
 694                                             S3C2410_UERSTAT_OVERRUN))
 695                                 flag = TTY_FRAME;
 696                 }
 697
 698                 if (uart_handle_sysrq_char(port, ch))
 699                         continue; /* Ignore character */
 700
 701                 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
 702                                  ch, flag);
 703         }
 704
 705         spin_unlock_irqrestore(&port->lock, flags);
 706         tty_flip_buffer_push(&port->state->port);
 707
 708 out:
 709         return IRQ_HANDLED;
 710 }
 711
 712
 713 static irqreturn_t s3c24xx_serial_rx_chars(int irq, void *dev_id)
 714 {
 715         struct s3c24xx_uart_port *ourport = dev_id;
 716
 717         if (ourport->dma && ourport->dma->rx_chan)
 718                 return s3c24xx_serial_rx_chars_dma(dev_id);
 719         return s3c24xx_serial_rx_chars_pio(dev_id);
 720 }
 721
 722 static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
 723 {
 724         struct s3c24xx_uart_port *ourport = id;
 725         struct uart_port *port = &ourport->port;
 726         struct circ_buf *xmit = &port->state->xmit;
 727         unsigned long flags;
 728         int count, dma_count = 0;
 729
 730         spin_lock_irqsave(&port->lock, flags);
 731
 732         count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 733
 734         if (ourport->dma && ourport->dma->tx_chan &&
 735             count >= ourport->min_dma_size) {
 736                 int align = dma_get_cache_alignment() -
 737                         (xmit->tail & (dma_get_cache_alignment() - 1));
 738                 if (count-align >= ourport->min_dma_size) {
 739                         dma_count = count-align;
 740                         count = align;
 741                 }
 742         }
 743
 744         if (port->x_char) {
 745                 wr_regb(port, S3C2410_UTXH, port->x_char);
 746                 port->icount.tx++;
 747                 port->x_char = 0;
 748                 goto out;
 749         }
 750
 751         /* if there isn't anything more to transmit, or the uart is now
 752          * stopped, disable the uart and exit
 753         */
 754
 755         if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
 756                 s3c24xx_serial_stop_tx(port);
 757                 goto out;
 758         }
 759
 760         /* try and drain the buffer... */
 761
 762         if (count > port->fifosize) {
 763                 count = port->fifosize;
 764                 dma_count = 0;
 765         }
 766
 767         while (!uart_circ_empty(xmit) && count > 0) {
 768                 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
 769                         break;
 770
 771                 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
 772                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 773                 port->icount.tx++;
 774                 count--;
 775         }
 776
 777         if (!count && dma_count) {
 778                 s3c24xx_serial_start_tx_dma(ourport, dma_count);
 779                 goto out;
 780         }
 781
 782         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
 783                 spin_unlock(&port->lock);
 784                 uart_write_wakeup(port);
 785                 spin_lock(&port->lock);
 786         }
 787
 788         if (uart_circ_empty(xmit))
 789                 s3c24xx_serial_stop_tx(port);
 790
 791 out:
 792         spin_unlock_irqrestore(&port->lock, flags);
 793         return IRQ_HANDLED;
 794 }
 795
 796 /* interrupt handler for s3c64xx and later SoC's.*/
 797 static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
 798 {
 799         struct s3c24xx_uart_port *ourport = id;
 800         struct uart_port *port = &ourport->port;
 801         unsigned int pend = rd_regl(port, S3C64XX_UINTP);
 802         irqreturn_t ret = IRQ_HANDLED;
 803
 804         if (pend & S3C64XX_UINTM_RXD_MSK) {
 805                 ret = s3c24xx_serial_rx_chars(irq, id);
 806                 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
 807         }
 808         if (pend & S3C64XX_UINTM_TXD_MSK) {
 809                 ret = s3c24xx_serial_tx_chars(irq, id);
 810                 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
 811         }
 812         return ret;
 813 }
 814
 815 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
 816 {
 817         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
 818         unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
 819         unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
 820
 821         if (ufcon & S3C2410_UFCON_FIFOMODE) {
 822                 if ((ufstat & info->tx_fifomask) != 0 ||
 823                     (ufstat & info->tx_fifofull))
 824                         return 0;
 825
 826                 return 1;
 827         }
 828
 829         return s3c24xx_serial_txempty_nofifo(port);
 830 }
 831
 832 /* no modem control lines */
 833 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
 834 {
 835         unsigned int umstat = rd_regb(port, S3C2410_UMSTAT);
 836
 837         if (umstat & S3C2410_UMSTAT_CTS)
 838                 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
 839         else
 840                 return TIOCM_CAR | TIOCM_DSR;
 841 }
 842
 843 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
 844 {
 845         unsigned int umcon = rd_regl(port, S3C2410_UMCON);
 846
 847         if (mctrl & TIOCM_RTS)
 848                 umcon |= S3C2410_UMCOM_RTS_LOW;
 849         else
 850                 umcon &= ~S3C2410_UMCOM_RTS_LOW;
 851
 852         wr_regl(port, S3C2410_UMCON, umcon);
 853 }
 854
 855 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
 856 {
 857         unsigned long flags;
 858         unsigned int ucon;
 859
 860         spin_lock_irqsave(&port->lock, flags);
 861
 862         ucon = rd_regl(port, S3C2410_UCON);
 863
 864         if (break_state)
 865                 ucon |= S3C2410_UCON_SBREAK;
 866         else
 867                 ucon &= ~S3C2410_UCON_SBREAK;
 868
 869         wr_regl(port, S3C2410_UCON, ucon);
 870
 871         spin_unlock_irqrestore(&port->lock, flags);
 872 }
 873
 874 static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p)
 875 {
 876         struct s3c24xx_uart_dma *dma = p->dma;
 877         dma_cap_mask_t mask;
 878         unsigned long flags;
 879
 880         /* Default slave configuration parameters */
 881         dma->rx_conf.direction          = DMA_DEV_TO_MEM;
 882         dma->rx_conf.src_addr_width     = DMA_SLAVE_BUSWIDTH_1_BYTE;
 883         dma->rx_conf.src_addr           = p->port.mapbase + S3C2410_URXH;
 884         dma->rx_conf.src_maxburst       = 16;
 885
 886         dma->tx_conf.direction          = DMA_MEM_TO_DEV;
 887         dma->tx_conf.dst_addr_width     = DMA_SLAVE_BUSWIDTH_1_BYTE;
 888         dma->tx_conf.dst_addr           = p->port.mapbase + S3C2410_UTXH;
 889         if (dma_get_cache_alignment() >= 16)
 890                 dma->tx_conf.dst_maxburst = 16;
 891         else
 892                 dma->tx_conf.dst_maxburst = 1;
 893
 894         dma_cap_zero(mask);
 895         dma_cap_set(DMA_SLAVE, mask);
 896
 897         dma->rx_chan = dma_request_slave_channel_compat(mask, dma->fn,
 898                                         dma->rx_param, p->port.dev, "rx");
 899         if (!dma->rx_chan)
 900                 return -ENODEV;
 901
 902         dmaengine_slave_config(dma->rx_chan, &dma->rx_conf);
 903
 904         dma->tx_chan = dma_request_slave_channel_compat(mask, dma->fn,
 905                                         dma->tx_param, p->port.dev, "tx");
 906         if (!dma->tx_chan) {
 907                 dma_release_channel(dma->rx_chan);
 908                 return -ENODEV;
 909         }
 910
 911         dmaengine_slave_config(dma->tx_chan, &dma->tx_conf);
 912
 913         /* RX buffer */
 914         dma->rx_size = PAGE_SIZE;
 915
 916         dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL);
 917
 918         if (!dma->rx_buf) {
 919                 dma_release_channel(dma->rx_chan);
 920                 dma_release_channel(dma->tx_chan);
 921                 return -ENOMEM;
 922         }
 923
 924         dma->rx_addr = dma_map_single(dma->rx_chan->device->dev, dma->rx_buf,
 925                                 dma->rx_size, DMA_FROM_DEVICE);
 926
 927         spin_lock_irqsave(&p->port.lock, flags);
 928
 929         /* TX buffer */
 930         dma->tx_addr = dma_map_single(dma->tx_chan->device->dev,
 931                                 p->port.state->xmit.buf,
 932                                 UART_XMIT_SIZE, DMA_TO_DEVICE);
 933
 934         spin_unlock_irqrestore(&p->port.lock, flags);
 935
 936         return 0;
 937 }
 938
 939 static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p)
 940 {
 941         struct s3c24xx_uart_dma *dma = p->dma;
 942
 943         if (dma->rx_chan) {
 944                 dmaengine_terminate_all(dma->rx_chan);
 945                 dma_unmap_single(dma->rx_chan->device->dev, dma->rx_addr,
 946                                 dma->rx_size, DMA_FROM_DEVICE);
 947                 kfree(dma->rx_buf);
 948                 dma_release_channel(dma->rx_chan);
 949                 dma->rx_chan = NULL;
 950         }
 951
 952         if (dma->tx_chan) {
 953                 dmaengine_terminate_all(dma->tx_chan);
 954                 dma_unmap_single(dma->tx_chan->device->dev, dma->tx_addr,
 955                                 UART_XMIT_SIZE, DMA_TO_DEVICE);
 956                 dma_release_channel(dma->tx_chan);
 957                 dma->tx_chan = NULL;
 958         }
 959 }
 960
 961 static void s3c24xx_serial_shutdown(struct uart_port *port)
 962 {
 963         struct s3c24xx_uart_port *ourport = to_ourport(port);
 964
 965         if (ourport->tx_claimed) {
 966                 if (!s3c24xx_serial_has_interrupt_mask(port))
 967                         free_irq(ourport->tx_irq, ourport);
 968                 tx_enabled(port) = 0;
 969                 ourport->tx_claimed = 0;
 970                 ourport->tx_mode = 0;
 971         }
 972
 973         if (ourport->rx_claimed) {
 974                 if (!s3c24xx_serial_has_interrupt_mask(port))
 975                         free_irq(ourport->rx_irq, ourport);
 976                 ourport->rx_claimed = 0;
 977                 rx_enabled(port) = 0;
 978         }
 979
 980         /* Clear pending interrupts and mask all interrupts */
 981         if (s3c24xx_serial_has_interrupt_mask(port)) {
 982                 free_irq(port->irq, ourport);
 983
 984                 wr_regl(port, S3C64XX_UINTP, 0xf);
 985                 wr_regl(port, S3C64XX_UINTM, 0xf);
 986         }
 987
 988         if (ourport->dma)
 989                 s3c24xx_serial_release_dma(ourport);
 990
 991         ourport->tx_in_progress = 0;
 992 }
 993
 994 static int s3c24xx_serial_startup(struct uart_port *port)
 995 {
 996         struct s3c24xx_uart_port *ourport = to_ourport(port);
 997         int ret;
 998
 999         dbg("s3c24xx_serial_startup: port=%p (%08llx,%p)\n",
1000             port, (unsigned long long)port->mapbase, port->membase);
1001
1002         rx_enabled(port) = 1;
1003
1004         ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
1005                           s3c24xx_serial_portname(port), ourport);
1006
1007         if (ret != 0) {
1008                 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
1009                 return ret;
1010         }
1011
1012         ourport->rx_claimed = 1;
1013
1014         dbg("requesting tx irq...\n");
1015
1016         tx_enabled(port) = 1;
1017
1018         ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
1019                           s3c24xx_serial_portname(port), ourport);
1020
1021         if (ret) {
1022                 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
1023                 goto err;
1024         }
1025
1026         ourport->tx_claimed = 1;
1027
1028         dbg("s3c24xx_serial_startup ok\n");
1029
1030         /* the port reset code should have done the correct
1031          * register setup for the port controls */
1032
1033         return ret;
1034
1035 err:
1036         s3c24xx_serial_shutdown(port);
1037         return ret;
1038 }
1039
1040 static int s3c64xx_serial_startup(struct uart_port *port)
1041 {
1042         struct s3c24xx_uart_port *ourport = to_ourport(port);
1043         unsigned long flags;
1044         unsigned int ufcon;
1045         int ret;
1046
1047         dbg("s3c64xx_serial_startup: port=%p (%08llx,%p)\n",
1048             port, (unsigned long long)port->mapbase, port->membase);
1049
1050         wr_regl(port, S3C64XX_UINTM, 0xf);
1051         if (ourport->dma) {
1052                 ret = s3c24xx_serial_request_dma(ourport);
1053                 if (ret < 0) {
1054                         dev_warn(port->dev, "DMA request failed\n");
1055                         return ret;
1056                 }
1057         }
1058
1059         ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
1060                           s3c24xx_serial_portname(port), ourport);
1061         if (ret) {
1062                 dev_err(port->dev, "cannot get irq %d\n", port->irq);
1063                 return ret;
1064         }
1065
1066         /* For compatibility with s3c24xx Soc's */
1067         rx_enabled(port) = 1;
1068         ourport->rx_claimed = 1;
1069         tx_enabled(port) = 0;
1070         ourport->tx_claimed = 1;
1071
1072         spin_lock_irqsave(&port->lock, flags);
1073
1074         ufcon = rd_regl(port, S3C2410_UFCON);
1075         ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1076         if (!uart_console(port))
1077                 ufcon |= S3C2410_UFCON_RESETTX;
1078         wr_regl(port, S3C2410_UFCON, ufcon);
1079
1080         enable_rx_pio(ourport);
1081
1082         spin_unlock_irqrestore(&port->lock, flags);
1083
1084         /* Enable Rx Interrupt */
1085         __clear_bit(S3C64XX_UINTM_RXD, portaddrl(port, S3C64XX_UINTM));
1086
1087         dbg("s3c64xx_serial_startup ok\n");
1088         return ret;
1089 }
1090
1091 /* power power management control */
1092
1093 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
1094                               unsigned int old)
1095 {
1096         struct s3c24xx_uart_port *ourport = to_ourport(port);
1097         int timeout = 10000;
1098
1099         ourport->pm_level = level;
1100
1101         switch (level) {
1102         case 3:
1103                 while (--timeout && !s3c24xx_serial_txempty_nofifo(port))
1104                         udelay(100);
1105
1106                 if (!IS_ERR(ourport->baudclk))
1107                         clk_disable_unprepare(ourport->baudclk);
1108
1109                 clk_disable_unprepare(ourport->clk);
1110                 break;
1111
1112         case 0:
1113                 clk_prepare_enable(ourport->clk);
1114
1115                 if (!IS_ERR(ourport->baudclk))
1116                         clk_prepare_enable(ourport->baudclk);
1117
1118                 break;
1119         default:
1120                 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
1121         }
1122 }
1123
1124 /* baud rate calculation
1125  *
1126  * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
1127  * of different sources, including the peripheral clock ("pclk") and an
1128  * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
1129  * with a programmable extra divisor.
1130  *
1131  * The following code goes through the clock sources, and calculates the
1132  * baud clocks (and the resultant actual baud rates) and then tries to
1133  * pick the closest one and select that.
1134  *
1135 */
1136
1137 #define MAX_CLK_NAME_LENGTH 15
1138
1139 static inline int s3c24xx_serial_getsource(struct uart_port *port)
1140 {
1141         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1142         unsigned int ucon;
1143
1144         if (info->num_clks == 1)
1145                 return 0;
1146
1147         ucon = rd_regl(port, S3C2410_UCON);
1148         ucon &= info->clksel_mask;
1149         return ucon >> info->clksel_shift;
1150 }
1151
1152 static void s3c24xx_serial_setsource(struct uart_port *port,
1153                         unsigned int clk_sel)
1154 {
1155         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1156         unsigned int ucon;
1157
1158         if (info->num_clks == 1)
1159                 return;
1160
1161         ucon = rd_regl(port, S3C2410_UCON);
1162         if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
1163                 return;
1164
1165         ucon &= ~info->clksel_mask;
1166         ucon |= clk_sel << info->clksel_shift;
1167         wr_regl(port, S3C2410_UCON, ucon);
1168 }
1169
1170 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
1171                         unsigned int req_baud, struct clk **best_clk,
1172                         unsigned int *clk_num)
1173 {
1174         struct s3c24xx_uart_info *info = ourport->info;
1175         struct clk *clk;
1176         unsigned long rate;
1177         unsigned int cnt, baud, quot, clk_sel, best_quot = 0;
1178         char clkname[MAX_CLK_NAME_LENGTH];
1179         int calc_deviation, deviation = (1 << 30) - 1;
1180
1181         clk_sel = (ourport->cfg->clk_sel) ? ourport->cfg->clk_sel :
1182                         ourport->info->def_clk_sel;
1183         for (cnt = 0; cnt < info->num_clks; cnt++) {
1184                 if (!(clk_sel & (1 << cnt)))
1185                         continue;
1186
1187                 sprintf(clkname, "clk_uart_baud%d", cnt);
1188                 clk = clk_get(ourport->port.dev, clkname);
1189                 if (IS_ERR(clk))
1190                         continue;
1191
1192                 rate = clk_get_rate(clk);
1193                 if (!rate)
1194                         continue;
1195
1196                 if (ourport->info->has_divslot) {
1197                         unsigned long div = rate / req_baud;
1198
1199                         /* The UDIVSLOT register on the newer UARTs allows us to
1200                          * get a divisor adjustment of 1/16th on the baud clock.
1201                          *
1202                          * We don't keep the UDIVSLOT value (the 16ths we
1203                          * calculated by not multiplying the baud by 16) as it
1204                          * is easy enough to recalculate.
1205                          */
1206
1207                         quot = div / 16;
1208                         baud = rate / div;
1209                 } else {
1210                         quot = (rate + (8 * req_baud)) / (16 * req_baud);
1211                         baud = rate / (quot * 16);
1212                 }
1213                 quot--;
1214
1215                 calc_deviation = req_baud - baud;
1216                 if (calc_deviation < 0)
1217                         calc_deviation = -calc_deviation;
1218
1219                 if (calc_deviation < deviation) {
1220                         *best_clk = clk;
1221                         best_quot = quot;
1222                         *clk_num = cnt;
1223                         deviation = calc_deviation;
1224                 }
1225         }
1226
1227         return best_quot;
1228 }
1229
1230 /* udivslot_table[]
1231  *
1232  * This table takes the fractional value of the baud divisor and gives
1233  * the recommended setting for the UDIVSLOT register.
1234  */
1235 static u16 udivslot_table[16] = {
1236         [0] = 0x0000,
1237         [1] = 0x0080,
1238         [2] = 0x0808,
1239         [3] = 0x0888,
1240         [4] = 0x2222,
1241         [5] = 0x4924,
1242         [6] = 0x4A52,
1243         [7] = 0x54AA,
1244         [8] = 0x5555,
1245         [9] = 0xD555,
1246         [10] = 0xD5D5,
1247         [11] = 0xDDD5,
1248         [12] = 0xDDDD,
1249         [13] = 0xDFDD,
1250         [14] = 0xDFDF,
1251         [15] = 0xFFDF,
1252 };
1253
1254 static void s3c24xx_serial_set_termios(struct uart_port *port,
1255                                        struct ktermios *termios,
1256                                        struct ktermios *old)
1257 {
1258         struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
1259         struct s3c24xx_uart_port *ourport = to_ourport(port);
1260         struct clk *clk = ERR_PTR(-EINVAL);
1261         unsigned long flags;
1262         unsigned int baud, quot, clk_sel = 0;
1263         unsigned int ulcon;
1264         unsigned int umcon;
1265         unsigned int udivslot = 0;
1266
1267         /*
1268          * We don't support modem control lines.
1269          */
1270         termios->c_cflag &= ~(HUPCL | CMSPAR);
1271         termios->c_cflag |= CLOCAL;
1272
1273         /*
1274          * Ask the core to calculate the divisor for us.
1275          */
1276
1277         baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
1278         quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
1279         if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
1280                 quot = port->custom_divisor;
1281         if (IS_ERR(clk))
1282                 return;
1283
1284         /* check to see if we need  to change clock source */
1285
1286         if (ourport->baudclk != clk) {
1287                 s3c24xx_serial_setsource(port, clk_sel);
1288
1289                 if (!IS_ERR(ourport->baudclk)) {
1290                         clk_disable_unprepare(ourport->baudclk);
1291                         ourport->baudclk = ERR_PTR(-EINVAL);
1292                 }
1293
1294                 clk_prepare_enable(clk);
1295
1296                 ourport->baudclk = clk;
1297                 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
1298         }
1299
1300         if (ourport->info->has_divslot) {
1301                 unsigned int div = ourport->baudclk_rate / baud;
1302
1303                 if (cfg->has_fracval) {
1304                         udivslot = (div & 15);
1305                         dbg("fracval = %04x\n", udivslot);
1306                 } else {
1307                         udivslot = udivslot_table[div & 15];
1308                         dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
1309                 }
1310         }
1311
1312         switch (termios->c_cflag & CSIZE) {
1313         case CS5:
1314                 dbg("config: 5bits/char\n");
1315                 ulcon = S3C2410_LCON_CS5;
1316                 break;
1317         case CS6:
1318                 dbg("config: 6bits/char\n");
1319                 ulcon = S3C2410_LCON_CS6;
1320                 break;
1321         case CS7:
1322                 dbg("config: 7bits/char\n");
1323                 ulcon = S3C2410_LCON_CS7;
1324                 break;
1325         case CS8:
1326         default:
1327                 dbg("config: 8bits/char\n");
1328                 ulcon = S3C2410_LCON_CS8;
1329                 break;
1330         }
1331
1332         /* preserve original lcon IR settings */
1333         ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
1334
1335         if (termios->c_cflag & CSTOPB)
1336                 ulcon |= S3C2410_LCON_STOPB;
1337
1338         if (termios->c_cflag & PARENB) {
1339                 if (termios->c_cflag & PARODD)
1340                         ulcon |= S3C2410_LCON_PODD;
1341                 else
1342                         ulcon |= S3C2410_LCON_PEVEN;
1343         } else {
1344                 ulcon |= S3C2410_LCON_PNONE;
1345         }
1346
1347         spin_lock_irqsave(&port->lock, flags);
1348
1349         dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
1350             ulcon, quot, udivslot);
1351
1352         wr_regl(port, S3C2410_ULCON, ulcon);
1353         wr_regl(port, S3C2410_UBRDIV, quot);
1354
1355         umcon = rd_regl(port, S3C2410_UMCON);
1356         if (termios->c_cflag & CRTSCTS) {
1357                 umcon |= S3C2410_UMCOM_AFC;
1358                 /* Disable RTS when RX FIFO contains 63 bytes */
1359                 umcon &= ~S3C2412_UMCON_AFC_8;
1360         } else {
1361                 umcon &= ~S3C2410_UMCOM_AFC;
1362         }
1363         wr_regl(port, S3C2410_UMCON, umcon);
1364
1365         if (ourport->info->has_divslot)
1366                 wr_regl(port, S3C2443_DIVSLOT, udivslot);
1367
1368         dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
1369             rd_regl(port, S3C2410_ULCON),
1370             rd_regl(port, S3C2410_UCON),
1371             rd_regl(port, S3C2410_UFCON));
1372
1373         /*
1374          * Update the per-port timeout.
1375          */
1376         uart_update_timeout(port, termios->c_cflag, baud);
1377
1378         /*
1379          * Which character status flags are we interested in?
1380          */
1381         port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
1382         if (termios->c_iflag & INPCK)
1383                 port->read_status_mask |= S3C2410_UERSTAT_FRAME |
1384                         S3C2410_UERSTAT_PARITY;
1385         /*
1386          * Which character status flags should we ignore?
1387          */
1388         port->ignore_status_mask = 0;
1389         if (termios->c_iflag & IGNPAR)
1390                 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
1391         if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
1392                 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
1393
1394         /*
1395          * Ignore all characters if CREAD is not set.
1396          */
1397         if ((termios->c_cflag & CREAD) == 0)
1398                 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
1399
1400         spin_unlock_irqrestore(&port->lock, flags);
1401 }
1402
1403 static const char *s3c24xx_serial_type(struct uart_port *port)
1404 {
1405         switch (port->type) {
1406         case PORT_S3C2410:
1407                 return "S3C2410";
1408         case PORT_S3C2440:
1409                 return "S3C2440";
1410         case PORT_S3C2412:
1411                 return "S3C2412";
1412         case PORT_S3C6400:
1413                 return "S3C6400/10";
1414         default:
1415                 return NULL;
1416         }
1417 }
1418
1419 #define MAP_SIZE (0x100)
1420
1421 static void s3c24xx_serial_release_port(struct uart_port *port)
1422 {
1423         release_mem_region(port->mapbase, MAP_SIZE);
1424 }
1425
1426 static int s3c24xx_serial_request_port(struct uart_port *port)
1427 {
1428         const char *name = s3c24xx_serial_portname(port);
1429         return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
1430 }
1431
1432 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
1433 {
1434         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1435
1436         if (flags & UART_CONFIG_TYPE &&
1437             s3c24xx_serial_request_port(port) == 0)
1438                 port->type = info->type;
1439 }
1440
1441 /*
1442  * verify the new serial_struct (for TIOCSSERIAL).
1443  */
1444 static int
1445 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
1446 {
1447         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1448
1449         if (ser->type != PORT_UNKNOWN && ser->type != info->type)
1450                 return -EINVAL;
1451
1452         return 0;
1453 }
1454
1455
1456 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1457
1458 static struct console s3c24xx_serial_console;
1459
1460 static int __init s3c24xx_serial_console_init(void)
1461 {
1462         register_console(&s3c24xx_serial_console);
1463         return 0;
1464 }
1465 console_initcall(s3c24xx_serial_console_init);
1466
1467 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
1468 #else
1469 #define S3C24XX_SERIAL_CONSOLE NULL
1470 #endif
1471
1472 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1473 static int s3c24xx_serial_get_poll_char(struct uart_port *port);
1474 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1475                          unsigned char c);
1476 #endif
1477
1478 static struct uart_ops s3c24xx_serial_ops = {
1479         .pm             = s3c24xx_serial_pm,
1480         .tx_empty       = s3c24xx_serial_tx_empty,
1481         .get_mctrl      = s3c24xx_serial_get_mctrl,
1482         .set_mctrl      = s3c24xx_serial_set_mctrl,
1483         .stop_tx        = s3c24xx_serial_stop_tx,
1484         .start_tx       = s3c24xx_serial_start_tx,
1485         .stop_rx        = s3c24xx_serial_stop_rx,
1486         .break_ctl      = s3c24xx_serial_break_ctl,
1487         .startup        = s3c24xx_serial_startup,
1488         .shutdown       = s3c24xx_serial_shutdown,
1489         .set_termios    = s3c24xx_serial_set_termios,
1490         .type           = s3c24xx_serial_type,
1491         .release_port   = s3c24xx_serial_release_port,
1492         .request_port   = s3c24xx_serial_request_port,
1493         .config_port    = s3c24xx_serial_config_port,
1494         .verify_port    = s3c24xx_serial_verify_port,
1495 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1496         .poll_get_char = s3c24xx_serial_get_poll_char,
1497         .poll_put_char = s3c24xx_serial_put_poll_char,
1498 #endif
1499 };
1500
1501 static struct uart_driver s3c24xx_uart_drv = {
1502         .owner          = THIS_MODULE,
1503         .driver_name    = "s3c2410_serial",
1504         .nr             = CONFIG_SERIAL_SAMSUNG_UARTS,
1505         .cons           = S3C24XX_SERIAL_CONSOLE,
1506         .dev_name       = S3C24XX_SERIAL_NAME,
1507         .major          = S3C24XX_SERIAL_MAJOR,
1508         .minor          = S3C24XX_SERIAL_MINOR,
1509 };
1510
1511 #define __PORT_LOCK_UNLOCKED(i) \
1512         __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[i].port.lock)
1513 static struct s3c24xx_uart_port
1514 s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
1515         [0] = {
1516                 .port = {
1517                         .lock           = __PORT_LOCK_UNLOCKED(0),
1518                         .iotype         = UPIO_MEM,
1519                         .uartclk        = 0,
1520                         .fifosize       = 16,
1521                         .ops            = &s3c24xx_serial_ops,
1522                         .flags          = UPF_BOOT_AUTOCONF,
1523                         .line           = 0,
1524                 }
1525         },
1526         [1] = {
1527                 .port = {
1528                         .lock           = __PORT_LOCK_UNLOCKED(1),
1529                         .iotype         = UPIO_MEM,
1530                         .uartclk        = 0,
1531                         .fifosize       = 16,
1532                         .ops            = &s3c24xx_serial_ops,
1533                         .flags          = UPF_BOOT_AUTOCONF,
1534                         .line           = 1,
1535                 }
1536         },
1537 #if CONFIG_SERIAL_SAMSUNG_UARTS > 2
1538
1539         [2] = {
1540                 .port = {
1541                         .lock           = __PORT_LOCK_UNLOCKED(2),
1542                         .iotype         = UPIO_MEM,
1543                         .uartclk        = 0,
1544                         .fifosize       = 16,
1545                         .ops            = &s3c24xx_serial_ops,
1546                         .flags          = UPF_BOOT_AUTOCONF,
1547                         .line           = 2,
1548                 }
1549         },
1550 #endif
1551 #if CONFIG_SERIAL_SAMSUNG_UARTS > 3
1552         [3] = {
1553                 .port = {
1554                         .lock           = __PORT_LOCK_UNLOCKED(3),
1555                         .iotype         = UPIO_MEM,
1556                         .uartclk        = 0,
1557                         .fifosize       = 16,
1558                         .ops            = &s3c24xx_serial_ops,
1559                         .flags          = UPF_BOOT_AUTOCONF,
1560                         .line           = 3,
1561                 }
1562         }
1563 #endif
1564 };
1565 #undef __PORT_LOCK_UNLOCKED
1566
1567 /* s3c24xx_serial_resetport
1568  *
1569  * reset the fifos and other the settings.
1570 */
1571
1572 static void s3c24xx_serial_resetport(struct uart_port *port,
1573                                    struct s3c2410_uartcfg *cfg)
1574 {
1575         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1576         unsigned long ucon = rd_regl(port, S3C2410_UCON);
1577         unsigned int ucon_mask;
1578
1579         ucon_mask = info->clksel_mask;
1580         if (info->type == PORT_S3C2440)
1581                 ucon_mask |= S3C2440_UCON0_DIVMASK;
1582
1583         ucon &= ucon_mask;
1584         wr_regl(port, S3C2410_UCON,  ucon | cfg->ucon);
1585
1586         /* reset both fifos */
1587         wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1588         wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1589
1590         /* some delay is required after fifo reset */
1591         udelay(1);
1592 }
1593
1594
1595 #ifdef CONFIG_CPU_FREQ
1596
1597 static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1598                                              unsigned long val, void *data)
1599 {
1600         struct s3c24xx_uart_port *port;
1601         struct uart_port *uport;
1602
1603         port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1604         uport = &port->port;
1605
1606         /* check to see if port is enabled */
1607
1608         if (port->pm_level != 0)
1609                 return 0;
1610
1611         /* try and work out if the baudrate is changing, we can detect
1612          * a change in rate, but we do not have support for detecting
1613          * a disturbance in the clock-rate over the change.
1614          */
1615
1616         if (IS_ERR(port->baudclk))
1617                 goto exit;
1618
1619         if (port->baudclk_rate == clk_get_rate(port->baudclk))
1620                 goto exit;
1621
1622         if (val == CPUFREQ_PRECHANGE) {
1623                 /* we should really shut the port down whilst the
1624                  * frequency change is in progress. */
1625
1626         } else if (val == CPUFREQ_POSTCHANGE) {
1627                 struct ktermios *termios;
1628                 struct tty_struct *tty;
1629
1630                 if (uport->state == NULL)
1631                         goto exit;
1632
1633                 tty = uport->state->port.tty;
1634
1635                 if (tty == NULL)
1636                         goto exit;
1637
1638                 termios = &tty->termios;
1639
1640                 if (termios == NULL) {
1641                         dev_warn(uport->dev, "%s: no termios?\n", __func__);
1642                         goto exit;
1643                 }
1644
1645                 s3c24xx_serial_set_termios(uport, termios, NULL);
1646         }
1647
1648 exit:
1649         return 0;
1650 }
1651
1652 static inline int
1653 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1654 {
1655         port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1656
1657         return cpufreq_register_notifier(&port->freq_transition,
1658                                          CPUFREQ_TRANSITION_NOTIFIER);
1659 }
1660
1661 static inline void
1662 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1663 {
1664         cpufreq_unregister_notifier(&port->freq_transition,
1665                                     CPUFREQ_TRANSITION_NOTIFIER);
1666 }
1667
1668 #else
1669 static inline int
1670 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1671 {
1672         return 0;
1673 }
1674
1675 static inline void
1676 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1677 {
1678 }
1679 #endif
1680
1681 /* s3c24xx_serial_init_port
1682  *
1683  * initialise a single serial port from the platform device given
1684  */
1685
1686 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1687                                     struct platform_device *platdev)
1688 {
1689         struct uart_port *port = &ourport->port;
1690         struct s3c2410_uartcfg *cfg = ourport->cfg;
1691         struct resource *res;
1692         int ret;
1693
1694         dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1695
1696         if (platdev == NULL)
1697                 return -ENODEV;
1698
1699         if (port->mapbase != 0)
1700                 return 0;
1701
1702         /* setup info for port */
1703         port->dev       = &platdev->dev;
1704
1705         /* Startup sequence is different for s3c64xx and higher SoC's */
1706         if (s3c24xx_serial_has_interrupt_mask(port))
1707                 s3c24xx_serial_ops.startup = s3c64xx_serial_startup;
1708
1709         port->uartclk = 1;
1710
1711         if (cfg->uart_flags & UPF_CONS_FLOW) {
1712                 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1713                 port->flags |= UPF_CONS_FLOW;
1714         }
1715
1716         /* sort our the physical and virtual addresses for each UART */
1717
1718         res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1719         if (res == NULL) {
1720                 dev_err(port->dev, "failed to find memory resource for uart\n");
1721                 return -EINVAL;
1722         }
1723
1724         dbg("resource %pR)\n", res);
1725
1726         port->membase = devm_ioremap(port->dev, res->start, resource_size(res));
1727         if (!port->membase) {
1728                 dev_err(port->dev, "failed to remap controller address\n");
1729                 return -EBUSY;
1730         }
1731
1732         port->mapbase = res->start;
1733         ret = platform_get_irq(platdev, 0);
1734         if (ret < 0)
1735                 port->irq = 0;
1736         else {
1737                 port->irq = ret;
1738                 ourport->rx_irq = ret;
1739                 ourport->tx_irq = ret + 1;
1740         }
1741
1742         ret = platform_get_irq(platdev, 1);
1743         if (ret > 0)
1744                 ourport->tx_irq = ret;
1745         /*
1746          * DMA is currently supported only on DT platforms, if DMA properties
1747          * are specified.
1748          */
1749         if (platdev->dev.of_node && of_find_property(platdev->dev.of_node,
1750                                                      "dmas", NULL)) {
1751                 ourport->dma = devm_kzalloc(port->dev,
1752                                             sizeof(*ourport->dma),
1753                                             GFP_KERNEL);
1754                 if (!ourport->dma)
1755                         return -ENOMEM;
1756         }
1757
1758         ourport->clk    = clk_get(&platdev->dev, "uart");
1759         if (IS_ERR(ourport->clk)) {
1760                 pr_err("%s: Controller clock not found\n",
1761                                 dev_name(&platdev->dev));
1762                 return PTR_ERR(ourport->clk);
1763         }
1764
1765         ret = clk_prepare_enable(ourport->clk);
1766         if (ret) {
1767                 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
1768                 clk_put(ourport->clk);
1769                 return ret;
1770         }
1771
1772         /* Keep all interrupts masked and cleared */
1773         if (s3c24xx_serial_has_interrupt_mask(port)) {
1774                 wr_regl(port, S3C64XX_UINTM, 0xf);
1775                 wr_regl(port, S3C64XX_UINTP, 0xf);
1776                 wr_regl(port, S3C64XX_UINTSP, 0xf);
1777         }
1778
1779         dbg("port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n",
1780             &port->mapbase, port->membase, port->irq,
1781             ourport->rx_irq, ourport->tx_irq, port->uartclk);
1782
1783         /* reset the fifos (and setup the uart) */
1784         s3c24xx_serial_resetport(port, cfg);
1785         return 0;
1786 }
1787
1788 /* Device driver serial port probe */
1789
1790 static const struct of_device_id s3c24xx_uart_dt_match[];
1791 static int probe_index;
1792
1793 static inline struct s3c24xx_serial_drv_data *s3c24xx_get_driver_data(
1794                         struct platform_device *pdev)
1795 {
1796 #ifdef CONFIG_OF
1797         if (pdev->dev.of_node) {
1798                 const struct of_device_id *match;
1799                 match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node);
1800                 return (struct s3c24xx_serial_drv_data *)match->data;
1801         }
1802 #endif
1803         return (struct s3c24xx_serial_drv_data *)
1804                         platform_get_device_id(pdev)->driver_data;
1805 }
1806
1807 static int s3c24xx_serial_probe(struct platform_device *pdev)
1808 {
1809         struct device_node *np = pdev->dev.of_node;
1810         struct s3c24xx_uart_port *ourport;
1811         int index = probe_index;
1812         int ret;
1813
1814         if (np) {
1815                 ret = of_alias_get_id(np, "serial");
1816                 if (ret >= 0)
1817                         index = ret;
1818         }
1819
1820         dbg("s3c24xx_serial_probe(%p) %d\n", pdev, index);
1821
1822         ourport = &s3c24xx_serial_ports[index];
1823
1824         ourport->drv_data = s3c24xx_get_driver_data(pdev);
1825         if (!ourport->drv_data) {
1826                 dev_err(&pdev->dev, "could not find driver data\n");
1827                 return -ENODEV;
1828         }
1829
1830         ourport->baudclk = ERR_PTR(-EINVAL);
1831         ourport->info = ourport->drv_data->info;
1832         ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
1833                         dev_get_platdata(&pdev->dev) :
1834                         ourport->drv_data->def_cfg;
1835
1836         if (np)
1837                 of_property_read_u32(np,
1838                         "samsung,uart-fifosize", &ourport->port.fifosize);
1839
1840         if (ourport->drv_data->fifosize[index])
1841                 ourport->port.fifosize = ourport->drv_data->fifosize[index];
1842         else if (ourport->info->fifosize)
1843                 ourport->port.fifosize = ourport->info->fifosize;
1844
1845         /*
1846          * DMA transfers must be aligned at least to cache line size,
1847          * so find minimal transfer size suitable for DMA mode
1848          */
1849         ourport->min_dma_size = max_t(int, ourport->port.fifosize,
1850                                     dma_get_cache_alignment());
1851
1852         probe_index++;
1853
1854         dbg("%s: initialising port %p...\n", __func__, ourport);
1855
1856         ret = s3c24xx_serial_init_port(ourport, pdev);
1857         if (ret < 0)
1858                 return ret;
1859
1860         if (!s3c24xx_uart_drv.state) {
1861                 ret = uart_register_driver(&s3c24xx_uart_drv);
1862                 if (ret < 0) {
1863                         pr_err("Failed to register Samsung UART driver\n");
1864                         return ret;
1865                 }
1866         }
1867
1868         dbg("%s: adding port\n", __func__);
1869         uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
1870         platform_set_drvdata(pdev, &ourport->port);
1871
1872         /*
1873          * Deactivate the clock enabled in s3c24xx_serial_init_port here,
1874          * so that a potential re-enablement through the pm-callback overlaps
1875          * and keeps the clock enabled in this case.
1876          */
1877         clk_disable_unprepare(ourport->clk);
1878
1879         ret = s3c24xx_serial_cpufreq_register(ourport);
1880         if (ret < 0)
1881                 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
1882
1883         return 0;
1884 }
1885
1886 static int s3c24xx_serial_remove(struct platform_device *dev)
1887 {
1888         struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1889
1890         if (port) {
1891                 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
1892                 uart_remove_one_port(&s3c24xx_uart_drv, port);
1893         }
1894
1895         uart_unregister_driver(&s3c24xx_uart_drv);
1896
1897         return 0;
1898 }
1899
1900 /* UART power management code */
1901 #ifdef CONFIG_PM_SLEEP
1902 static int s3c24xx_serial_suspend(struct device *dev)
1903 {
1904         struct uart_port *port = s3c24xx_dev_to_port(dev);
1905
1906         if (port)
1907                 uart_suspend_port(&s3c24xx_uart_drv, port);
1908
1909         return 0;
1910 }
1911
1912 static int s3c24xx_serial_resume(struct device *dev)
1913 {
1914         struct uart_port *port = s3c24xx_dev_to_port(dev);
1915         struct s3c24xx_uart_port *ourport = to_ourport(port);
1916
1917         if (port) {
1918                 clk_prepare_enable(ourport->clk);
1919                 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
1920                 clk_disable_unprepare(ourport->clk);
1921
1922                 uart_resume_port(&s3c24xx_uart_drv, port);
1923         }
1924
1925         return 0;
1926 }
1927
1928 static int s3c24xx_serial_resume_noirq(struct device *dev)
1929 {
1930         struct uart_port *port = s3c24xx_dev_to_port(dev);
1931
1932         if (port) {
1933                 /* restore IRQ mask */
1934                 if (s3c24xx_serial_has_interrupt_mask(port)) {
1935                         unsigned int uintm = 0xf;
1936                         if (tx_enabled(port))
1937                                 uintm &= ~S3C64XX_UINTM_TXD_MSK;
1938                         if (rx_enabled(port))
1939                                 uintm &= ~S3C64XX_UINTM_RXD_MSK;
1940                         wr_regl(port, S3C64XX_UINTM, uintm);
1941                 }
1942         }
1943
1944         return 0;
1945 }
1946
1947 static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
1948         .suspend = s3c24xx_serial_suspend,
1949         .resume = s3c24xx_serial_resume,
1950         .resume_noirq = s3c24xx_serial_resume_noirq,
1951 };
1952 #define SERIAL_SAMSUNG_PM_OPS   (&s3c24xx_serial_pm_ops)
1953
1954 #else /* !CONFIG_PM_SLEEP */
1955
1956 #define SERIAL_SAMSUNG_PM_OPS   NULL
1957 #endif /* CONFIG_PM_SLEEP */
1958
1959 /* Console code */
1960
1961 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1962
1963 static struct uart_port *cons_uart;
1964
1965 static int
1966 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1967 {
1968         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1969         unsigned long ufstat, utrstat;
1970
1971         if (ufcon & S3C2410_UFCON_FIFOMODE) {
1972                 /* fifo mode - check amount of data in fifo registers... */
1973
1974                 ufstat = rd_regl(port, S3C2410_UFSTAT);
1975                 return (ufstat & info->tx_fifofull) ? 0 : 1;
1976         }
1977
1978         /* in non-fifo mode, we go and use the tx buffer empty */
1979
1980         utrstat = rd_regl(port, S3C2410_UTRSTAT);
1981         return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1982 }
1983
1984 static bool
1985 s3c24xx_port_configured(unsigned int ucon)
1986 {
1987         /* consider the serial port configured if the tx/rx mode set */
1988         return (ucon & 0xf) != 0;
1989 }
1990
1991 #ifdef CONFIG_CONSOLE_POLL
1992 /*
1993  * Console polling routines for writing and reading from the uart while
1994  * in an interrupt or debug context.
1995  */
1996
1997 static int s3c24xx_serial_get_poll_char(struct uart_port *port)
1998 {
1999         struct s3c24xx_uart_port *ourport = to_ourport(port);
2000         unsigned int ufstat;
2001
2002         ufstat = rd_regl(port, S3C2410_UFSTAT);
2003         if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
2004                 return NO_POLL_CHAR;
2005
2006         return rd_regb(port, S3C2410_URXH);
2007 }
2008
2009 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
2010                 unsigned char c)
2011 {
2012         unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2013         unsigned int ucon = rd_regl(port, S3C2410_UCON);
2014
2015         /* not possible to xmit on unconfigured port */
2016         if (!s3c24xx_port_configured(ucon))
2017                 return;
2018
2019         while (!s3c24xx_serial_console_txrdy(port, ufcon))
2020                 cpu_relax();
2021         wr_regb(port, S3C2410_UTXH, c);
2022 }
2023
2024 #endif /* CONFIG_CONSOLE_POLL */
2025
2026 static void
2027 s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
2028 {
2029         unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2030
2031         while (!s3c24xx_serial_console_txrdy(port, ufcon))
2032                 cpu_relax();
2033         wr_regb(port, S3C2410_UTXH, ch);
2034 }
2035
2036 static void
2037 s3c24xx_serial_console_write(struct console *co, const char *s,
2038                              unsigned int count)
2039 {
2040         unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
2041
2042         /* not possible to xmit on unconfigured port */
2043         if (!s3c24xx_port_configured(ucon))
2044                 return;
2045
2046         uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
2047 }
2048
2049 static void __init
2050 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
2051                            int *parity, int *bits)
2052 {
2053         struct clk *clk;
2054         unsigned int ulcon;
2055         unsigned int ucon;
2056         unsigned int ubrdiv;
2057         unsigned long rate;
2058         unsigned int clk_sel;
2059         char clk_name[MAX_CLK_NAME_LENGTH];
2060
2061         ulcon  = rd_regl(port, S3C2410_ULCON);
2062         ucon   = rd_regl(port, S3C2410_UCON);
2063         ubrdiv = rd_regl(port, S3C2410_UBRDIV);
2064
2065         dbg("s3c24xx_serial_get_options: port=%p\n"
2066             "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
2067             port, ulcon, ucon, ubrdiv);
2068
2069         if (s3c24xx_port_configured(ucon)) {
2070                 switch (ulcon & S3C2410_LCON_CSMASK) {
2071                 case S3C2410_LCON_CS5:
2072                         *bits = 5;
2073                         break;
2074                 case S3C2410_LCON_CS6:
2075                         *bits = 6;
2076                         break;
2077                 case S3C2410_LCON_CS7:
2078                         *bits = 7;
2079                         break;
2080                 case S3C2410_LCON_CS8:
2081                 default:
2082                         *bits = 8;
2083                         break;
2084                 }
2085
2086                 switch (ulcon & S3C2410_LCON_PMASK) {
2087                 case S3C2410_LCON_PEVEN:
2088                         *parity = 'e';
2089                         break;
2090
2091                 case S3C2410_LCON_PODD:
2092                         *parity = 'o';
2093                         break;
2094
2095                 case S3C2410_LCON_PNONE:
2096                 default:
2097                         *parity = 'n';
2098                 }
2099
2100                 /* now calculate the baud rate */
2101
2102                 clk_sel = s3c24xx_serial_getsource(port);
2103                 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
2104
2105                 clk = clk_get(port->dev, clk_name);
2106                 if (!IS_ERR(clk))
2107                         rate = clk_get_rate(clk);
2108                 else
2109                         rate = 1;
2110
2111                 *baud = rate / (16 * (ubrdiv + 1));
2112                 dbg("calculated baud %d\n", *baud);
2113         }
2114
2115 }
2116
2117 static int __init
2118 s3c24xx_serial_console_setup(struct console *co, char *options)
2119 {
2120         struct uart_port *port;
2121         int baud = 9600;
2122         int bits = 8;
2123         int parity = 'n';
2124         int flow = 'n';
2125
2126         dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
2127             co, co->index, options);
2128
2129         /* is this a valid port */
2130
2131         if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
2132                 co->index = 0;
2133
2134         port = &s3c24xx_serial_ports[co->index].port;
2135
2136         /* is the port configured? */
2137
2138         if (port->mapbase == 0x0)
2139                 return -ENODEV;
2140
2141         cons_uart = port;
2142
2143         dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
2144
2145         /*
2146          * Check whether an invalid uart number has been specified, and
2147          * if so, search for the first available port that does have
2148          * console support.
2149          */
2150         if (options)
2151                 uart_parse_options(options, &baud, &parity, &bits, &flow);
2152         else
2153                 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
2154
2155         dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
2156
2157         return uart_set_options(port, co, baud, parity, bits, flow);
2158 }
2159
2160 static struct console s3c24xx_serial_console = {
2161         .name           = S3C24XX_SERIAL_NAME,
2162         .device         = uart_console_device,
2163         .flags          = CON_PRINTBUFFER,
2164         .index          = -1,
2165         .write          = s3c24xx_serial_console_write,
2166         .setup          = s3c24xx_serial_console_setup,
2167         .data           = &s3c24xx_uart_drv,
2168 };
2169 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
2170
2171 #ifdef CONFIG_CPU_S3C2410
2172 static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
2173         .info = &(struct s3c24xx_uart_info) {
2174                 .name           = "Samsung S3C2410 UART",
2175                 .type           = PORT_S3C2410,
2176                 .fifosize       = 16,
2177                 .rx_fifomask    = S3C2410_UFSTAT_RXMASK,
2178                 .rx_fifoshift   = S3C2410_UFSTAT_RXSHIFT,
2179                 .rx_fifofull    = S3C2410_UFSTAT_RXFULL,
2180                 .tx_fifofull    = S3C2410_UFSTAT_TXFULL,
2181                 .tx_fifomask    = S3C2410_UFSTAT_TXMASK,
2182                 .tx_fifoshift   = S3C2410_UFSTAT_TXSHIFT,
2183                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,
2184                 .num_clks       = 2,
2185                 .clksel_mask    = S3C2410_UCON_CLKMASK,
2186                 .clksel_shift   = S3C2410_UCON_CLKSHIFT,
2187         },
2188         .def_cfg = &(struct s3c2410_uartcfg) {
2189                 .ucon           = S3C2410_UCON_DEFAULT,
2190                 .ufcon          = S3C2410_UFCON_DEFAULT,
2191         },
2192 };
2193 #define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
2194 #else
2195 #define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2196 #endif
2197
2198 #ifdef CONFIG_CPU_S3C2412
2199 static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
2200         .info = &(struct s3c24xx_uart_info) {
2201                 .name           = "Samsung S3C2412 UART",
2202                 .type           = PORT_S3C2412,
2203                 .fifosize       = 64,
2204                 .has_divslot    = 1,
2205                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2206                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2207                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2208                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2209                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2210                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2211                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2212                 .num_clks       = 4,
2213                 .clksel_mask    = S3C2412_UCON_CLKMASK,
2214                 .clksel_shift   = S3C2412_UCON_CLKSHIFT,
2215         },
2216         .def_cfg = &(struct s3c2410_uartcfg) {
2217                 .ucon           = S3C2410_UCON_DEFAULT,
2218                 .ufcon          = S3C2410_UFCON_DEFAULT,
2219         },
2220 };
2221 #define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
2222 #else
2223 #define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2224 #endif
2225
2226 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
2227         defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
2228 static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
2229         .info = &(struct s3c24xx_uart_info) {
2230                 .name           = "Samsung S3C2440 UART",
2231                 .type           = PORT_S3C2440,
2232                 .fifosize       = 64,
2233                 .has_divslot    = 1,
2234                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2235                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2236                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2237                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2238                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2239                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2240                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2241                 .num_clks       = 4,
2242                 .clksel_mask    = S3C2412_UCON_CLKMASK,
2243                 .clksel_shift   = S3C2412_UCON_CLKSHIFT,
2244         },
2245         .def_cfg = &(struct s3c2410_uartcfg) {
2246                 .ucon           = S3C2410_UCON_DEFAULT,
2247                 .ufcon          = S3C2410_UFCON_DEFAULT,
2248         },
2249 };
2250 #define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
2251 #else
2252 #define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2253 #endif
2254
2255 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
2256 static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
2257         .info = &(struct s3c24xx_uart_info) {
2258                 .name           = "Samsung S3C6400 UART",
2259                 .type           = PORT_S3C6400,
2260                 .fifosize       = 64,
2261                 .has_divslot    = 1,
2262                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2263                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2264                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2265                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2266                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2267                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2268                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2269                 .num_clks       = 4,
2270                 .clksel_mask    = S3C6400_UCON_CLKMASK,
2271                 .clksel_shift   = S3C6400_UCON_CLKSHIFT,
2272         },
2273         .def_cfg = &(struct s3c2410_uartcfg) {
2274                 .ucon           = S3C2410_UCON_DEFAULT,
2275                 .ufcon          = S3C2410_UFCON_DEFAULT,
2276         },
2277 };
2278 #define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
2279 #else
2280 #define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2281 #endif
2282
2283 #ifdef CONFIG_CPU_S5PV210
2284 static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
2285         .info = &(struct s3c24xx_uart_info) {
2286                 .name           = "Samsung S5PV210 UART",
2287                 .type           = PORT_S3C6400,
2288                 .has_divslot    = 1,
2289                 .rx_fifomask    = S5PV210_UFSTAT_RXMASK,
2290                 .rx_fifoshift   = S5PV210_UFSTAT_RXSHIFT,
2291                 .rx_fifofull    = S5PV210_UFSTAT_RXFULL,
2292                 .tx_fifofull    = S5PV210_UFSTAT_TXFULL,
2293                 .tx_fifomask    = S5PV210_UFSTAT_TXMASK,
2294                 .tx_fifoshift   = S5PV210_UFSTAT_TXSHIFT,
2295                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,
2296                 .num_clks       = 2,
2297                 .clksel_mask    = S5PV210_UCON_CLKMASK,
2298                 .clksel_shift   = S5PV210_UCON_CLKSHIFT,
2299         },
2300         .def_cfg = &(struct s3c2410_uartcfg) {
2301                 .ucon           = S5PV210_UCON_DEFAULT,
2302                 .ufcon          = S5PV210_UFCON_DEFAULT,
2303         },
2304         .fifosize = { 256, 64, 16, 16 },
2305 };
2306 #define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
2307 #else
2308 #define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2309 #endif
2310
2311 #if defined(CONFIG_ARCH_EXYNOS)
2312 #define EXYNOS_COMMON_SERIAL_DRV_DATA                           \
2313         .info = &(struct s3c24xx_uart_info) {                   \
2314                 .name           = "Samsung Exynos UART",        \
2315                 .type           = PORT_S3C6400,                 \
2316                 .has_divslot    = 1,                            \
2317                 .rx_fifomask    = S5PV210_UFSTAT_RXMASK,        \
2318                 .rx_fifoshift   = S5PV210_UFSTAT_RXSHIFT,       \
2319                 .rx_fifofull    = S5PV210_UFSTAT_RXFULL,        \
2320                 .tx_fifofull    = S5PV210_UFSTAT_TXFULL,        \
2321                 .tx_fifomask    = S5PV210_UFSTAT_TXMASK,        \
2322                 .tx_fifoshift   = S5PV210_UFSTAT_TXSHIFT,       \
2323                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,         \
2324                 .num_clks       = 1,                            \
2325                 .clksel_mask    = 0,                            \
2326                 .clksel_shift   = 0,                            \
2327         },                                                      \
2328         .def_cfg = &(struct s3c2410_uartcfg) {                  \
2329                 .ucon           = S5PV210_UCON_DEFAULT,         \
2330                 .ufcon          = S5PV210_UFCON_DEFAULT,        \
2331                 .has_fracval    = 1,                            \
2332         }                                                       \
2333
2334 static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
2335         EXYNOS_COMMON_SERIAL_DRV_DATA,
2336         .fifosize = { 256, 64, 16, 16 },
2337 };
2338
2339 static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = {
2340         EXYNOS_COMMON_SERIAL_DRV_DATA,
2341         .fifosize = { 64, 256, 16, 256 },
2342 };
2343
2344 #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
2345 #define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos5433_serial_drv_data)
2346 #else
2347 #define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2348 #define EXYNOS5433_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2349 #endif
2350
2351 static const struct platform_device_id s3c24xx_serial_driver_ids[] = {
2352         {
2353                 .name           = "s3c2410-uart",
2354                 .driver_data    = S3C2410_SERIAL_DRV_DATA,
2355         }, {
2356                 .name           = "s3c2412-uart",
2357                 .driver_data    = S3C2412_SERIAL_DRV_DATA,
2358         }, {
2359                 .name           = "s3c2440-uart",
2360                 .driver_data    = S3C2440_SERIAL_DRV_DATA,
2361         }, {
2362                 .name           = "s3c6400-uart",
2363                 .driver_data    = S3C6400_SERIAL_DRV_DATA,
2364         }, {
2365                 .name           = "s5pv210-uart",
2366                 .driver_data    = S5PV210_SERIAL_DRV_DATA,
2367         }, {
2368                 .name           = "exynos4210-uart",
2369                 .driver_data    = EXYNOS4210_SERIAL_DRV_DATA,
2370         }, {
2371                 .name           = "exynos5433-uart",
2372                 .driver_data    = EXYNOS5433_SERIAL_DRV_DATA,
2373         },
2374         { },
2375 };
2376 MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
2377
2378 #ifdef CONFIG_OF
2379 static const struct of_device_id s3c24xx_uart_dt_match[] = {
2380         { .compatible = "samsung,s3c2410-uart",
2381                 .data = (void *)S3C2410_SERIAL_DRV_DATA },
2382         { .compatible = "samsung,s3c2412-uart",
2383                 .data = (void *)S3C2412_SERIAL_DRV_DATA },
2384         { .compatible = "samsung,s3c2440-uart",
2385                 .data = (void *)S3C2440_SERIAL_DRV_DATA },
2386         { .compatible = "samsung,s3c6400-uart",
2387                 .data = (void *)S3C6400_SERIAL_DRV_DATA },
2388         { .compatible = "samsung,s5pv210-uart",
2389                 .data = (void *)S5PV210_SERIAL_DRV_DATA },
2390         { .compatible = "samsung,exynos4210-uart",
2391                 .data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
2392         { .compatible = "samsung,exynos5433-uart",
2393                 .data = (void *)EXYNOS5433_SERIAL_DRV_DATA },
2394         {},
2395 };
2396 MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
2397 #endif
2398
2399 static struct platform_driver samsung_serial_driver = {
2400         .probe          = s3c24xx_serial_probe,
2401         .remove         = s3c24xx_serial_remove,
2402         .id_table       = s3c24xx_serial_driver_ids,
2403         .driver         = {
2404                 .name   = "samsung-uart",
2405                 .pm     = SERIAL_SAMSUNG_PM_OPS,
2406                 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
2407         },
2408 };
2409
2410 module_platform_driver(samsung_serial_driver);
2411
2412 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2413 /*
2414  * Early console.
2415  */
2416
2417 struct samsung_early_console_data {
2418         u32 txfull_mask;
2419 };
2420
2421 static void samsung_early_busyuart(struct uart_port *port)
2422 {
2423         while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE))
2424                 ;
2425 }
2426
2427 static void samsung_early_busyuart_fifo(struct uart_port *port)
2428 {
2429         struct samsung_early_console_data *data = port->private_data;
2430
2431         while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask)
2432                 ;
2433 }
2434
2435 static void samsung_early_putc(struct uart_port *port, int c)
2436 {
2437         if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE)
2438                 samsung_early_busyuart_fifo(port);
2439         else
2440                 samsung_early_busyuart(port);
2441
2442         writeb(c, port->membase + S3C2410_UTXH);
2443 }
2444
2445 static void samsung_early_write(struct console *con, const char *s, unsigned n)
2446 {
2447         struct earlycon_device *dev = con->data;
2448
2449         uart_console_write(&dev->port, s, n, samsung_early_putc);
2450 }
2451
2452 static int __init samsung_early_console_setup(struct earlycon_device *device,
2453                                               const char *opt)
2454 {
2455         if (!device->port.membase)
2456                 return -ENODEV;
2457
2458         device->con->write = samsung_early_write;
2459         return 0;
2460 }
2461
2462 /* S3C2410 */
2463 static struct samsung_early_console_data s3c2410_early_console_data = {
2464         .txfull_mask = S3C2410_UFSTAT_TXFULL,
2465 };
2466
2467 static int __init s3c2410_early_console_setup(struct earlycon_device *device,
2468                                               const char *opt)
2469 {
2470         device->port.private_data = &s3c2410_early_console_data;
2471         return samsung_early_console_setup(device, opt);
2472 }
2473 OF_EARLYCON_DECLARE(s3c2410, "samsung,s3c2410-uart",
2474                         s3c2410_early_console_setup);
2475 EARLYCON_DECLARE(s3c2410, s3c2410_early_console_setup);
2476
2477 /* S3C2412, S3C2440, S3C64xx */
2478 static struct samsung_early_console_data s3c2440_early_console_data = {
2479         .txfull_mask = S3C2440_UFSTAT_TXFULL,
2480 };
2481
2482 static int __init s3c2440_early_console_setup(struct earlycon_device *device,
2483                                               const char *opt)
2484 {
2485         device->port.private_data = &s3c2440_early_console_data;
2486         return samsung_early_console_setup(device, opt);
2487 }
2488 OF_EARLYCON_DECLARE(s3c2412, "samsung,s3c2412-uart",
2489                         s3c2440_early_console_setup);
2490 OF_EARLYCON_DECLARE(s3c2440, "samsung,s3c2440-uart",
2491                         s3c2440_early_console_setup);
2492 OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart",
2493                         s3c2440_early_console_setup);
2494 EARLYCON_DECLARE(s3c2412, s3c2440_early_console_setup);
2495 EARLYCON_DECLARE(s3c2440, s3c2440_early_console_setup);
2496 EARLYCON_DECLARE(s3c6400, s3c2440_early_console_setup);
2497
2498 /* S5PV210, EXYNOS */
2499 static struct samsung_early_console_data s5pv210_early_console_data = {
2500         .txfull_mask = S5PV210_UFSTAT_TXFULL,
2501 };
2502
2503 static int __init s5pv210_early_console_setup(struct earlycon_device *device,
2504                                               const char *opt)
2505 {
2506         device->port.private_data = &s5pv210_early_console_data;
2507         return samsung_early_console_setup(device, opt);
2508 }
2509 OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart",
2510                         s5pv210_early_console_setup);
2511 OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart",
2512                         s5pv210_early_console_setup);
2513 EARLYCON_DECLARE(s5pv210, s5pv210_early_console_setup);
2514 EARLYCON_DECLARE(exynos4210, s5pv210_early_console_setup);
2515 #endif
2516
2517 MODULE_ALIAS("platform:samsung-uart");
2518 MODULE_DESCRIPTION("Samsung SoC Serial port driver");
2519 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
2520 MODULE_LICENSE("GPL v2");