2 * Driver core for Samsung SoC onboard UARTs.
4 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 /* Hote on 2410 error handling
14 * The s3c2410 manual has a love/hate affair with the contents of the
15 * UERSTAT register in the UART blocks, and keeps marking some of the
16 * error bits as reserved. Having checked with the s3c2410x01,
17 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
18 * feature from the latter versions of the manual.
20 * If it becomes aparrent that latter versions of the 2410 remove these
21 * bits, then action will have to be taken to differentiate the versions
22 * and change the policy on BREAK
27 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
31 #include <linux/module.h>
32 #include <linux/ioport.h>
34 #include <linux/platform_device.h>
35 #include <linux/init.h>
36 #include <linux/sysrq.h>
37 #include <linux/console.h>
38 #include <linux/tty.h>
39 #include <linux/tty_flip.h>
40 #include <linux/serial_core.h>
41 #include <linux/serial.h>
42 #include <linux/delay.h>
43 #include <linux/clk.h>
44 #include <linux/cpufreq.h>
49 #include <mach/hardware.h>
52 #include <plat/regs-serial.h>
53 #include <plat/clock.h>
57 /* UART name and device definitions */
59 #define S3C24XX_SERIAL_NAME "ttySAC"
60 #define S3C24XX_SERIAL_MAJOR 204
61 #define S3C24XX_SERIAL_MINOR 64
63 /* macros to change one thing to another */
65 #define tx_enabled(port) ((port)->unused[0])
66 #define rx_enabled(port) ((port)->unused[1])
68 /* flag to ignore all characters coming in */
69 #define RXSTAT_DUMMY_READ (0x10000000)
71 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
73 return container_of(port, struct s3c24xx_uart_port, port);
76 /* translate a port to the device name */
78 static inline const char *s3c24xx_serial_portname(struct uart_port *port)
80 return to_platform_device(port->dev)->name;
83 static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
85 return (rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE);
89 * s3c64xx and later SoC's include the interrupt mask and status registers in
90 * the controller itself, unlike the s3c24xx SoC's which have these registers
91 * in the interrupt controller. Check if the port type is s3c64xx or higher.
93 static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
95 return to_ourport(port)->info->type == PORT_S3C6400;
98 static void s3c24xx_serial_rx_enable(struct uart_port *port)
101 unsigned int ucon, ufcon;
104 spin_lock_irqsave(&port->lock, flags);
106 while (--count && !s3c24xx_serial_txempty_nofifo(port))
109 ufcon = rd_regl(port, S3C2410_UFCON);
110 ufcon |= S3C2410_UFCON_RESETRX;
111 wr_regl(port, S3C2410_UFCON, ufcon);
113 ucon = rd_regl(port, S3C2410_UCON);
114 ucon |= S3C2410_UCON_RXIRQMODE;
115 wr_regl(port, S3C2410_UCON, ucon);
117 rx_enabled(port) = 1;
118 spin_unlock_irqrestore(&port->lock, flags);
121 static void s3c24xx_serial_rx_disable(struct uart_port *port)
126 spin_lock_irqsave(&port->lock, flags);
128 ucon = rd_regl(port, S3C2410_UCON);
129 ucon &= ~S3C2410_UCON_RXIRQMODE;
130 wr_regl(port, S3C2410_UCON, ucon);
132 rx_enabled(port) = 0;
133 spin_unlock_irqrestore(&port->lock, flags);
136 static void s3c24xx_serial_stop_tx(struct uart_port *port)
138 struct s3c24xx_uart_port *ourport = to_ourport(port);
140 if (tx_enabled(port)) {
141 if (s3c24xx_serial_has_interrupt_mask(port))
142 __set_bit(S3C64XX_UINTM_TXD,
143 portaddrl(port, S3C64XX_UINTM));
145 disable_irq_nosync(ourport->tx_irq);
146 tx_enabled(port) = 0;
147 if (port->flags & UPF_CONS_FLOW)
148 s3c24xx_serial_rx_enable(port);
152 static void s3c24xx_serial_start_tx(struct uart_port *port)
154 struct s3c24xx_uart_port *ourport = to_ourport(port);
156 if (!tx_enabled(port)) {
157 if (port->flags & UPF_CONS_FLOW)
158 s3c24xx_serial_rx_disable(port);
160 if (s3c24xx_serial_has_interrupt_mask(port))
161 __clear_bit(S3C64XX_UINTM_TXD,
162 portaddrl(port, S3C64XX_UINTM));
164 enable_irq(ourport->tx_irq);
165 tx_enabled(port) = 1;
169 static void s3c24xx_serial_stop_rx(struct uart_port *port)
171 struct s3c24xx_uart_port *ourport = to_ourport(port);
173 if (rx_enabled(port)) {
174 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
175 if (s3c24xx_serial_has_interrupt_mask(port))
176 __set_bit(S3C64XX_UINTM_RXD,
177 portaddrl(port, S3C64XX_UINTM));
179 disable_irq_nosync(ourport->rx_irq);
180 rx_enabled(port) = 0;
184 static void s3c24xx_serial_enable_ms(struct uart_port *port)
188 static inline struct s3c24xx_uart_info *s3c24xx_port_to_info(struct uart_port *port)
190 return to_ourport(port)->info;
193 static inline struct s3c2410_uartcfg *s3c24xx_port_to_cfg(struct uart_port *port)
195 struct s3c24xx_uart_port *ourport;
197 if (port->dev == NULL)
200 ourport = container_of(port, struct s3c24xx_uart_port, port);
204 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
205 unsigned long ufstat)
207 struct s3c24xx_uart_info *info = ourport->info;
209 if (ufstat & info->rx_fifofull)
210 return ourport->port.fifosize;
212 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
216 /* ? - where has parity gone?? */
217 #define S3C2410_UERSTAT_PARITY (0x1000)
220 s3c24xx_serial_rx_chars(int irq, void *dev_id)
222 struct s3c24xx_uart_port *ourport = dev_id;
223 struct uart_port *port = &ourport->port;
224 struct tty_struct *tty = port->state->port.tty;
225 unsigned int ufcon, ch, flag, ufstat, uerstat;
228 while (max_count-- > 0) {
229 ufcon = rd_regl(port, S3C2410_UFCON);
230 ufstat = rd_regl(port, S3C2410_UFSTAT);
232 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
235 uerstat = rd_regl(port, S3C2410_UERSTAT);
236 ch = rd_regb(port, S3C2410_URXH);
238 if (port->flags & UPF_CONS_FLOW) {
239 int txe = s3c24xx_serial_txempty_nofifo(port);
241 if (rx_enabled(port)) {
243 rx_enabled(port) = 0;
248 ufcon |= S3C2410_UFCON_RESETRX;
249 wr_regl(port, S3C2410_UFCON, ufcon);
250 rx_enabled(port) = 1;
257 /* insert the character into the buffer */
262 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
263 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
266 /* check for break */
267 if (uerstat & S3C2410_UERSTAT_BREAK) {
270 if (uart_handle_break(port))
274 if (uerstat & S3C2410_UERSTAT_FRAME)
275 port->icount.frame++;
276 if (uerstat & S3C2410_UERSTAT_OVERRUN)
277 port->icount.overrun++;
279 uerstat &= port->read_status_mask;
281 if (uerstat & S3C2410_UERSTAT_BREAK)
283 else if (uerstat & S3C2410_UERSTAT_PARITY)
285 else if (uerstat & (S3C2410_UERSTAT_FRAME |
286 S3C2410_UERSTAT_OVERRUN))
290 if (uart_handle_sysrq_char(port, ch))
293 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
299 tty_flip_buffer_push(tty);
305 static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
307 struct s3c24xx_uart_port *ourport = id;
308 struct uart_port *port = &ourport->port;
309 struct circ_buf *xmit = &port->state->xmit;
313 wr_regb(port, S3C2410_UTXH, port->x_char);
319 /* if there isn't anything more to transmit, or the uart is now
320 * stopped, disable the uart and exit
323 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
324 s3c24xx_serial_stop_tx(port);
328 /* try and drain the buffer... */
330 while (!uart_circ_empty(xmit) && count-- > 0) {
331 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
334 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
335 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
339 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
340 uart_write_wakeup(port);
342 if (uart_circ_empty(xmit))
343 s3c24xx_serial_stop_tx(port);
349 /* interrupt handler for s3c64xx and later SoC's.*/
350 static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
352 struct s3c24xx_uart_port *ourport = id;
353 struct uart_port *port = &ourport->port;
354 unsigned int pend = rd_regl(port, S3C64XX_UINTP);
356 irqreturn_t ret = IRQ_HANDLED;
358 spin_lock_irqsave(&port->lock, flags);
359 if (pend & S3C64XX_UINTM_RXD_MSK) {
360 ret = s3c24xx_serial_rx_chars(irq, id);
361 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
363 if (pend & S3C64XX_UINTM_TXD_MSK) {
364 ret = s3c24xx_serial_tx_chars(irq, id);
365 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
367 spin_unlock_irqrestore(&port->lock, flags);
371 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
373 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
374 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
375 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
377 if (ufcon & S3C2410_UFCON_FIFOMODE) {
378 if ((ufstat & info->tx_fifomask) != 0 ||
379 (ufstat & info->tx_fifofull))
385 return s3c24xx_serial_txempty_nofifo(port);
388 /* no modem control lines */
389 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
391 unsigned int umstat = rd_regb(port, S3C2410_UMSTAT);
393 if (umstat & S3C2410_UMSTAT_CTS)
394 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
396 return TIOCM_CAR | TIOCM_DSR;
399 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
401 /* todo - possibly remove AFC and do manual CTS */
404 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
409 spin_lock_irqsave(&port->lock, flags);
411 ucon = rd_regl(port, S3C2410_UCON);
414 ucon |= S3C2410_UCON_SBREAK;
416 ucon &= ~S3C2410_UCON_SBREAK;
418 wr_regl(port, S3C2410_UCON, ucon);
420 spin_unlock_irqrestore(&port->lock, flags);
423 static void s3c24xx_serial_shutdown(struct uart_port *port)
425 struct s3c24xx_uart_port *ourport = to_ourport(port);
427 if (ourport->tx_claimed) {
428 if (!s3c24xx_serial_has_interrupt_mask(port))
429 free_irq(ourport->tx_irq, ourport);
430 tx_enabled(port) = 0;
431 ourport->tx_claimed = 0;
434 if (ourport->rx_claimed) {
435 if (!s3c24xx_serial_has_interrupt_mask(port))
436 free_irq(ourport->rx_irq, ourport);
437 ourport->rx_claimed = 0;
438 rx_enabled(port) = 0;
441 /* Clear pending interrupts and mask all interrupts */
442 if (s3c24xx_serial_has_interrupt_mask(port)) {
443 wr_regl(port, S3C64XX_UINTP, 0xf);
444 wr_regl(port, S3C64XX_UINTM, 0xf);
448 static int s3c24xx_serial_startup(struct uart_port *port)
450 struct s3c24xx_uart_port *ourport = to_ourport(port);
453 dbg("s3c24xx_serial_startup: port=%p (%08lx,%p)\n",
454 port->mapbase, port->membase);
456 rx_enabled(port) = 1;
458 ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
459 s3c24xx_serial_portname(port), ourport);
462 printk(KERN_ERR "cannot get irq %d\n", ourport->rx_irq);
466 ourport->rx_claimed = 1;
468 dbg("requesting tx irq...\n");
470 tx_enabled(port) = 1;
472 ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
473 s3c24xx_serial_portname(port), ourport);
476 printk(KERN_ERR "cannot get irq %d\n", ourport->tx_irq);
480 ourport->tx_claimed = 1;
482 dbg("s3c24xx_serial_startup ok\n");
484 /* the port reset code should have done the correct
485 * register setup for the port controls */
490 s3c24xx_serial_shutdown(port);
494 static int s3c64xx_serial_startup(struct uart_port *port)
496 struct s3c24xx_uart_port *ourport = to_ourport(port);
499 dbg("s3c64xx_serial_startup: port=%p (%08lx,%p)\n",
500 port->mapbase, port->membase);
502 ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
503 s3c24xx_serial_portname(port), ourport);
505 printk(KERN_ERR "cannot get irq %d\n", port->irq);
509 /* For compatibility with s3c24xx Soc's */
510 rx_enabled(port) = 1;
511 ourport->rx_claimed = 1;
512 tx_enabled(port) = 0;
513 ourport->tx_claimed = 1;
515 /* Enable Rx Interrupt */
516 __clear_bit(S3C64XX_UINTM_RXD, portaddrl(port, S3C64XX_UINTM));
517 dbg("s3c64xx_serial_startup ok\n");
521 /* power power management control */
523 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
526 struct s3c24xx_uart_port *ourport = to_ourport(port);
528 ourport->pm_level = level;
532 if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
533 clk_disable(ourport->baudclk);
535 clk_disable(ourport->clk);
539 clk_enable(ourport->clk);
541 if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
542 clk_enable(ourport->baudclk);
546 printk(KERN_ERR "s3c24xx_serial: unknown pm %d\n", level);
550 /* baud rate calculation
552 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
553 * of different sources, including the peripheral clock ("pclk") and an
554 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
555 * with a programmable extra divisor.
557 * The following code goes through the clock sources, and calculates the
558 * baud clocks (and the resultant actual baud rates) and then tries to
559 * pick the closest one and select that.
563 #define MAX_CLK_NAME_LENGTH 15
565 static inline int s3c24xx_serial_getsource(struct uart_port *port)
567 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
570 if (info->num_clks == 1)
573 ucon = rd_regl(port, S3C2410_UCON);
574 ucon &= info->clksel_mask;
575 return ucon >> info->clksel_shift;
578 static void s3c24xx_serial_setsource(struct uart_port *port,
579 unsigned int clk_sel)
581 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
584 if (info->num_clks == 1)
587 ucon = rd_regl(port, S3C2410_UCON);
588 if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
591 ucon &= ~info->clksel_mask;
592 ucon |= clk_sel << info->clksel_shift;
593 wr_regl(port, S3C2410_UCON, ucon);
596 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
597 unsigned int req_baud, struct clk **best_clk,
598 unsigned int *clk_num)
600 struct s3c24xx_uart_info *info = ourport->info;
603 unsigned int cnt, baud, quot, clk_sel, best_quot = 0;
604 char clkname[MAX_CLK_NAME_LENGTH];
605 int calc_deviation, deviation = (1 << 30) - 1;
608 clk_sel = (ourport->cfg->clk_sel) ? ourport->cfg->clk_sel :
609 ourport->info->def_clk_sel;
610 for (cnt = 0; cnt < info->num_clks; cnt++) {
611 if (!(clk_sel & (1 << cnt)))
614 sprintf(clkname, "clk_uart_baud%d", cnt);
615 clk = clk_get(ourport->port.dev, clkname);
616 if (IS_ERR_OR_NULL(clk))
619 rate = clk_get_rate(clk);
623 if (ourport->info->has_divslot) {
624 unsigned long div = rate / req_baud;
626 /* The UDIVSLOT register on the newer UARTs allows us to
627 * get a divisor adjustment of 1/16th on the baud clock.
629 * We don't keep the UDIVSLOT value (the 16ths we
630 * calculated by not multiplying the baud by 16) as it
631 * is easy enough to recalculate.
637 quot = (rate + (8 * req_baud)) / (16 * req_baud);
638 baud = rate / (quot * 16);
642 calc_deviation = req_baud - baud;
643 if (calc_deviation < 0)
644 calc_deviation = -calc_deviation;
646 if (calc_deviation < deviation) {
650 deviation = calc_deviation;
659 * This table takes the fractional value of the baud divisor and gives
660 * the recommended setting for the UDIVSLOT register.
662 static u16 udivslot_table[16] = {
681 static void s3c24xx_serial_set_termios(struct uart_port *port,
682 struct ktermios *termios,
683 struct ktermios *old)
685 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
686 struct s3c24xx_uart_port *ourport = to_ourport(port);
687 struct clk *clk = NULL;
689 unsigned int baud, quot, clk_sel = 0;
692 unsigned int udivslot = 0;
695 * We don't support modem control lines.
697 termios->c_cflag &= ~(HUPCL | CMSPAR);
698 termios->c_cflag |= CLOCAL;
701 * Ask the core to calculate the divisor for us.
704 baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
705 quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
706 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
707 quot = port->custom_divisor;
711 /* check to see if we need to change clock source */
713 if (ourport->baudclk != clk) {
714 s3c24xx_serial_setsource(port, clk_sel);
716 if (ourport->baudclk != NULL && !IS_ERR(ourport->baudclk)) {
717 clk_disable(ourport->baudclk);
718 ourport->baudclk = NULL;
723 ourport->baudclk = clk;
724 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
727 if (ourport->info->has_divslot) {
728 unsigned int div = ourport->baudclk_rate / baud;
730 if (cfg->has_fracval) {
731 udivslot = (div & 15);
732 dbg("fracval = %04x\n", udivslot);
734 udivslot = udivslot_table[div & 15];
735 dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
739 switch (termios->c_cflag & CSIZE) {
741 dbg("config: 5bits/char\n");
742 ulcon = S3C2410_LCON_CS5;
745 dbg("config: 6bits/char\n");
746 ulcon = S3C2410_LCON_CS6;
749 dbg("config: 7bits/char\n");
750 ulcon = S3C2410_LCON_CS7;
754 dbg("config: 8bits/char\n");
755 ulcon = S3C2410_LCON_CS8;
759 /* preserve original lcon IR settings */
760 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
762 if (termios->c_cflag & CSTOPB)
763 ulcon |= S3C2410_LCON_STOPB;
765 umcon = (termios->c_cflag & CRTSCTS) ? S3C2410_UMCOM_AFC : 0;
767 if (termios->c_cflag & PARENB) {
768 if (termios->c_cflag & PARODD)
769 ulcon |= S3C2410_LCON_PODD;
771 ulcon |= S3C2410_LCON_PEVEN;
773 ulcon |= S3C2410_LCON_PNONE;
776 spin_lock_irqsave(&port->lock, flags);
778 dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
779 ulcon, quot, udivslot);
781 wr_regl(port, S3C2410_ULCON, ulcon);
782 wr_regl(port, S3C2410_UBRDIV, quot);
783 wr_regl(port, S3C2410_UMCON, umcon);
785 if (ourport->info->has_divslot)
786 wr_regl(port, S3C2443_DIVSLOT, udivslot);
788 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
789 rd_regl(port, S3C2410_ULCON),
790 rd_regl(port, S3C2410_UCON),
791 rd_regl(port, S3C2410_UFCON));
794 * Update the per-port timeout.
796 uart_update_timeout(port, termios->c_cflag, baud);
799 * Which character status flags are we interested in?
801 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
802 if (termios->c_iflag & INPCK)
803 port->read_status_mask |= S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_PARITY;
806 * Which character status flags should we ignore?
808 port->ignore_status_mask = 0;
809 if (termios->c_iflag & IGNPAR)
810 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
811 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
812 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
815 * Ignore all characters if CREAD is not set.
817 if ((termios->c_cflag & CREAD) == 0)
818 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
820 spin_unlock_irqrestore(&port->lock, flags);
823 static const char *s3c24xx_serial_type(struct uart_port *port)
825 switch (port->type) {
839 #define MAP_SIZE (0x100)
841 static void s3c24xx_serial_release_port(struct uart_port *port)
843 release_mem_region(port->mapbase, MAP_SIZE);
846 static int s3c24xx_serial_request_port(struct uart_port *port)
848 const char *name = s3c24xx_serial_portname(port);
849 return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
852 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
854 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
856 if (flags & UART_CONFIG_TYPE &&
857 s3c24xx_serial_request_port(port) == 0)
858 port->type = info->type;
862 * verify the new serial_struct (for TIOCSSERIAL).
865 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
867 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
869 if (ser->type != PORT_UNKNOWN && ser->type != info->type)
876 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
878 static struct console s3c24xx_serial_console;
880 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
882 #define S3C24XX_SERIAL_CONSOLE NULL
885 static struct uart_ops s3c24xx_serial_ops = {
886 .pm = s3c24xx_serial_pm,
887 .tx_empty = s3c24xx_serial_tx_empty,
888 .get_mctrl = s3c24xx_serial_get_mctrl,
889 .set_mctrl = s3c24xx_serial_set_mctrl,
890 .stop_tx = s3c24xx_serial_stop_tx,
891 .start_tx = s3c24xx_serial_start_tx,
892 .stop_rx = s3c24xx_serial_stop_rx,
893 .enable_ms = s3c24xx_serial_enable_ms,
894 .break_ctl = s3c24xx_serial_break_ctl,
895 .startup = s3c24xx_serial_startup,
896 .shutdown = s3c24xx_serial_shutdown,
897 .set_termios = s3c24xx_serial_set_termios,
898 .type = s3c24xx_serial_type,
899 .release_port = s3c24xx_serial_release_port,
900 .request_port = s3c24xx_serial_request_port,
901 .config_port = s3c24xx_serial_config_port,
902 .verify_port = s3c24xx_serial_verify_port,
905 static struct uart_driver s3c24xx_uart_drv = {
906 .owner = THIS_MODULE,
907 .driver_name = "s3c2410_serial",
908 .nr = CONFIG_SERIAL_SAMSUNG_UARTS,
909 .cons = S3C24XX_SERIAL_CONSOLE,
910 .dev_name = S3C24XX_SERIAL_NAME,
911 .major = S3C24XX_SERIAL_MAJOR,
912 .minor = S3C24XX_SERIAL_MINOR,
915 static struct s3c24xx_uart_port s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
918 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[0].port.lock),
922 .ops = &s3c24xx_serial_ops,
923 .flags = UPF_BOOT_AUTOCONF,
929 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[1].port.lock),
933 .ops = &s3c24xx_serial_ops,
934 .flags = UPF_BOOT_AUTOCONF,
938 #if CONFIG_SERIAL_SAMSUNG_UARTS > 2
942 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[2].port.lock),
946 .ops = &s3c24xx_serial_ops,
947 .flags = UPF_BOOT_AUTOCONF,
952 #if CONFIG_SERIAL_SAMSUNG_UARTS > 3
955 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[3].port.lock),
959 .ops = &s3c24xx_serial_ops,
960 .flags = UPF_BOOT_AUTOCONF,
967 /* s3c24xx_serial_resetport
969 * reset the fifos and other the settings.
972 static void s3c24xx_serial_resetport(struct uart_port *port,
973 struct s3c2410_uartcfg *cfg)
975 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
976 unsigned long ucon = rd_regl(port, S3C2410_UCON);
977 unsigned int ucon_mask;
979 ucon_mask = info->clksel_mask;
980 if (info->type == PORT_S3C2440)
981 ucon_mask |= S3C2440_UCON0_DIVMASK;
984 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
986 /* reset both fifos */
987 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
988 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
990 /* some delay is required after fifo reset */
995 #ifdef CONFIG_CPU_FREQ
997 static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
998 unsigned long val, void *data)
1000 struct s3c24xx_uart_port *port;
1001 struct uart_port *uport;
1003 port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1004 uport = &port->port;
1006 /* check to see if port is enabled */
1008 if (port->pm_level != 0)
1011 /* try and work out if the baudrate is changing, we can detect
1012 * a change in rate, but we do not have support for detecting
1013 * a disturbance in the clock-rate over the change.
1016 if (IS_ERR(port->clk))
1019 if (port->baudclk_rate == clk_get_rate(port->clk))
1022 if (val == CPUFREQ_PRECHANGE) {
1023 /* we should really shut the port down whilst the
1024 * frequency change is in progress. */
1026 } else if (val == CPUFREQ_POSTCHANGE) {
1027 struct ktermios *termios;
1028 struct tty_struct *tty;
1030 if (uport->state == NULL)
1033 tty = uport->state->port.tty;
1038 termios = tty->termios;
1040 if (termios == NULL) {
1041 printk(KERN_WARNING "%s: no termios?\n", __func__);
1045 s3c24xx_serial_set_termios(uport, termios, NULL);
1052 static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1054 port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1056 return cpufreq_register_notifier(&port->freq_transition,
1057 CPUFREQ_TRANSITION_NOTIFIER);
1060 static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1062 cpufreq_unregister_notifier(&port->freq_transition,
1063 CPUFREQ_TRANSITION_NOTIFIER);
1067 static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1072 static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1077 /* s3c24xx_serial_init_port
1079 * initialise a single serial port from the platform device given
1082 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1083 struct platform_device *platdev)
1085 struct uart_port *port = &ourport->port;
1086 struct s3c2410_uartcfg *cfg = ourport->cfg;
1087 struct resource *res;
1090 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1092 if (platdev == NULL)
1095 if (port->mapbase != 0)
1098 /* setup info for port */
1099 port->dev = &platdev->dev;
1101 /* Startup sequence is different for s3c64xx and higher SoC's */
1102 if (s3c24xx_serial_has_interrupt_mask(port))
1103 s3c24xx_serial_ops.startup = s3c64xx_serial_startup;
1107 if (cfg->uart_flags & UPF_CONS_FLOW) {
1108 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1109 port->flags |= UPF_CONS_FLOW;
1112 /* sort our the physical and virtual addresses for each UART */
1114 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1116 printk(KERN_ERR "failed to find memory resource for uart\n");
1120 dbg("resource %p (%lx..%lx)\n", res, res->start, res->end);
1122 port->mapbase = res->start;
1123 port->membase = S3C_VA_UART + (res->start & 0xfffff);
1124 ret = platform_get_irq(platdev, 0);
1129 ourport->rx_irq = ret;
1130 ourport->tx_irq = ret + 1;
1133 ret = platform_get_irq(platdev, 1);
1135 ourport->tx_irq = ret;
1137 ourport->clk = clk_get(&platdev->dev, "uart");
1139 /* Keep all interrupts masked and cleared */
1140 if (s3c24xx_serial_has_interrupt_mask(port)) {
1141 wr_regl(port, S3C64XX_UINTM, 0xf);
1142 wr_regl(port, S3C64XX_UINTP, 0xf);
1143 wr_regl(port, S3C64XX_UINTSP, 0xf);
1146 dbg("port: map=%08x, mem=%08x, irq=%d (%d,%d), clock=%ld\n",
1147 port->mapbase, port->membase, port->irq,
1148 ourport->rx_irq, ourport->tx_irq, port->uartclk);
1150 /* reset the fifos (and setup the uart) */
1151 s3c24xx_serial_resetport(port, cfg);
1155 static ssize_t s3c24xx_serial_show_clksrc(struct device *dev,
1156 struct device_attribute *attr,
1159 struct uart_port *port = s3c24xx_dev_to_port(dev);
1160 struct s3c24xx_uart_port *ourport = to_ourport(port);
1162 return snprintf(buf, PAGE_SIZE, "* %s\n", ourport->baudclk->name);
1165 static DEVICE_ATTR(clock_source, S_IRUGO, s3c24xx_serial_show_clksrc, NULL);
1168 /* Device driver serial port probe */
1170 static const struct of_device_id s3c24xx_uart_dt_match[];
1171 static int probe_index;
1173 static inline struct s3c24xx_serial_drv_data *s3c24xx_get_driver_data(
1174 struct platform_device *pdev)
1177 if (pdev->dev.of_node) {
1178 const struct of_device_id *match;
1179 match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node);
1180 return (struct s3c24xx_serial_drv_data *)match->data;
1183 return (struct s3c24xx_serial_drv_data *)
1184 platform_get_device_id(pdev)->driver_data;
1187 static int s3c24xx_serial_probe(struct platform_device *pdev)
1189 struct s3c24xx_uart_port *ourport;
1192 dbg("s3c24xx_serial_probe(%p) %d\n", pdev, probe_index);
1194 ourport = &s3c24xx_serial_ports[probe_index];
1196 ourport->drv_data = s3c24xx_get_driver_data(pdev);
1197 if (!ourport->drv_data) {
1198 dev_err(&pdev->dev, "could not find driver data\n");
1202 ourport->info = ourport->drv_data->info;
1203 ourport->cfg = (pdev->dev.platform_data) ?
1204 (struct s3c2410_uartcfg *)pdev->dev.platform_data :
1205 ourport->drv_data->def_cfg;
1207 ourport->port.fifosize = (ourport->info->fifosize) ?
1208 ourport->info->fifosize :
1209 ourport->drv_data->fifosize[probe_index];
1213 dbg("%s: initialising port %p...\n", __func__, ourport);
1215 ret = s3c24xx_serial_init_port(ourport, pdev);
1219 dbg("%s: adding port\n", __func__);
1220 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
1221 platform_set_drvdata(pdev, &ourport->port);
1223 ret = device_create_file(&pdev->dev, &dev_attr_clock_source);
1225 dev_err(&pdev->dev, "failed to add clock source attr.\n");
1227 ret = s3c24xx_serial_cpufreq_register(ourport);
1229 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
1237 static int __devexit s3c24xx_serial_remove(struct platform_device *dev)
1239 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1242 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
1243 device_remove_file(&dev->dev, &dev_attr_clock_source);
1244 uart_remove_one_port(&s3c24xx_uart_drv, port);
1250 /* UART power management code */
1251 #ifdef CONFIG_PM_SLEEP
1252 static int s3c24xx_serial_suspend(struct device *dev)
1254 struct uart_port *port = s3c24xx_dev_to_port(dev);
1257 uart_suspend_port(&s3c24xx_uart_drv, port);
1262 static int s3c24xx_serial_resume(struct device *dev)
1264 struct uart_port *port = s3c24xx_dev_to_port(dev);
1265 struct s3c24xx_uart_port *ourport = to_ourport(port);
1268 clk_enable(ourport->clk);
1269 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
1270 clk_disable(ourport->clk);
1272 uart_resume_port(&s3c24xx_uart_drv, port);
1278 static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
1279 .suspend = s3c24xx_serial_suspend,
1280 .resume = s3c24xx_serial_resume,
1282 #define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops)
1284 #else /* !CONFIG_PM_SLEEP */
1286 #define SERIAL_SAMSUNG_PM_OPS NULL
1287 #endif /* CONFIG_PM_SLEEP */
1291 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1293 static struct uart_port *cons_uart;
1296 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1298 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1299 unsigned long ufstat, utrstat;
1301 if (ufcon & S3C2410_UFCON_FIFOMODE) {
1302 /* fifo mode - check amount of data in fifo registers... */
1304 ufstat = rd_regl(port, S3C2410_UFSTAT);
1305 return (ufstat & info->tx_fifofull) ? 0 : 1;
1308 /* in non-fifo mode, we go and use the tx buffer empty */
1310 utrstat = rd_regl(port, S3C2410_UTRSTAT);
1311 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1315 s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
1317 unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON);
1318 while (!s3c24xx_serial_console_txrdy(port, ufcon))
1320 wr_regb(cons_uart, S3C2410_UTXH, ch);
1324 s3c24xx_serial_console_write(struct console *co, const char *s,
1327 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
1331 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
1332 int *parity, int *bits)
1337 unsigned int ubrdiv;
1339 unsigned int clk_sel;
1340 char clk_name[MAX_CLK_NAME_LENGTH];
1342 ulcon = rd_regl(port, S3C2410_ULCON);
1343 ucon = rd_regl(port, S3C2410_UCON);
1344 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
1346 dbg("s3c24xx_serial_get_options: port=%p\n"
1347 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
1348 port, ulcon, ucon, ubrdiv);
1350 if ((ucon & 0xf) != 0) {
1351 /* consider the serial port configured if the tx/rx mode set */
1353 switch (ulcon & S3C2410_LCON_CSMASK) {
1354 case S3C2410_LCON_CS5:
1357 case S3C2410_LCON_CS6:
1360 case S3C2410_LCON_CS7:
1364 case S3C2410_LCON_CS8:
1369 switch (ulcon & S3C2410_LCON_PMASK) {
1370 case S3C2410_LCON_PEVEN:
1374 case S3C2410_LCON_PODD:
1378 case S3C2410_LCON_PNONE:
1383 /* now calculate the baud rate */
1385 clk_sel = s3c24xx_serial_getsource(port);
1386 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
1388 clk = clk_get(port->dev, clk_name);
1389 if (!IS_ERR(clk) && clk != NULL)
1390 rate = clk_get_rate(clk);
1394 *baud = rate / (16 * (ubrdiv + 1));
1395 dbg("calculated baud %d\n", *baud);
1401 s3c24xx_serial_console_setup(struct console *co, char *options)
1403 struct uart_port *port;
1409 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
1410 co, co->index, options);
1412 /* is this a valid port */
1414 if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
1417 port = &s3c24xx_serial_ports[co->index].port;
1419 /* is the port configured? */
1421 if (port->mapbase == 0x0)
1426 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
1429 * Check whether an invalid uart number has been specified, and
1430 * if so, search for the first available port that does have
1434 uart_parse_options(options, &baud, &parity, &bits, &flow);
1436 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
1438 dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
1440 return uart_set_options(port, co, baud, parity, bits, flow);
1443 static struct console s3c24xx_serial_console = {
1444 .name = S3C24XX_SERIAL_NAME,
1445 .device = uart_console_device,
1446 .flags = CON_PRINTBUFFER,
1448 .write = s3c24xx_serial_console_write,
1449 .setup = s3c24xx_serial_console_setup,
1450 .data = &s3c24xx_uart_drv,
1452 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
1454 #ifdef CONFIG_CPU_S3C2410
1455 static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
1456 .info = &(struct s3c24xx_uart_info) {
1457 .name = "Samsung S3C2410 UART",
1458 .type = PORT_S3C2410,
1460 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
1461 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
1462 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
1463 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
1464 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
1465 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
1466 .def_clk_sel = S3C2410_UCON_CLKSEL0,
1468 .clksel_mask = S3C2410_UCON_CLKMASK,
1469 .clksel_shift = S3C2410_UCON_CLKSHIFT,
1471 .def_cfg = &(struct s3c2410_uartcfg) {
1472 .ucon = S3C2410_UCON_DEFAULT,
1473 .ufcon = S3C2410_UFCON_DEFAULT,
1476 #define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
1478 #define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1481 #ifdef CONFIG_CPU_S3C2412
1482 static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
1483 .info = &(struct s3c24xx_uart_info) {
1484 .name = "Samsung S3C2412 UART",
1485 .type = PORT_S3C2412,
1488 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1489 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1490 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1491 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1492 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1493 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1494 .def_clk_sel = S3C2410_UCON_CLKSEL2,
1496 .clksel_mask = S3C2412_UCON_CLKMASK,
1497 .clksel_shift = S3C2412_UCON_CLKSHIFT,
1499 .def_cfg = &(struct s3c2410_uartcfg) {
1500 .ucon = S3C2410_UCON_DEFAULT,
1501 .ufcon = S3C2410_UFCON_DEFAULT,
1504 #define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
1506 #define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1509 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
1510 defined(CONFIG_CPU_S3C2443)
1511 static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
1512 .info = &(struct s3c24xx_uart_info) {
1513 .name = "Samsung S3C2440 UART",
1514 .type = PORT_S3C2440,
1517 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1518 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1519 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1520 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1521 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1522 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1523 .def_clk_sel = S3C2410_UCON_CLKSEL2,
1525 .clksel_mask = S3C2412_UCON_CLKMASK,
1526 .clksel_shift = S3C2412_UCON_CLKSHIFT,
1528 .def_cfg = &(struct s3c2410_uartcfg) {
1529 .ucon = S3C2410_UCON_DEFAULT,
1530 .ufcon = S3C2410_UFCON_DEFAULT,
1533 #define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
1535 #define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1538 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410) || \
1539 defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450) || \
1540 defined(CONFIG_CPU_S5PC100)
1541 static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
1542 .info = &(struct s3c24xx_uart_info) {
1543 .name = "Samsung S3C6400 UART",
1544 .type = PORT_S3C6400,
1547 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1548 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1549 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1550 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1551 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1552 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1553 .def_clk_sel = S3C2410_UCON_CLKSEL2,
1555 .clksel_mask = S3C6400_UCON_CLKMASK,
1556 .clksel_shift = S3C6400_UCON_CLKSHIFT,
1558 .def_cfg = &(struct s3c2410_uartcfg) {
1559 .ucon = S3C2410_UCON_DEFAULT,
1560 .ufcon = S3C2410_UFCON_DEFAULT,
1563 #define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
1565 #define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1568 #ifdef CONFIG_CPU_S5PV210
1569 static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
1570 .info = &(struct s3c24xx_uart_info) {
1571 .name = "Samsung S5PV210 UART",
1572 .type = PORT_S3C6400,
1574 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
1575 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
1576 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
1577 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
1578 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
1579 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
1580 .def_clk_sel = S3C2410_UCON_CLKSEL0,
1582 .clksel_mask = S5PV210_UCON_CLKMASK,
1583 .clksel_shift = S5PV210_UCON_CLKSHIFT,
1585 .def_cfg = &(struct s3c2410_uartcfg) {
1586 .ucon = S5PV210_UCON_DEFAULT,
1587 .ufcon = S5PV210_UFCON_DEFAULT,
1589 .fifosize = { 256, 64, 16, 16 },
1591 #define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
1593 #define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1596 #ifdef CONFIG_CPU_EXYNOS4210
1597 static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
1598 .info = &(struct s3c24xx_uart_info) {
1599 .name = "Samsung Exynos4 UART",
1600 .type = PORT_S3C6400,
1602 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
1603 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
1604 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
1605 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
1606 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
1607 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
1608 .def_clk_sel = S3C2410_UCON_CLKSEL0,
1613 .def_cfg = &(struct s3c2410_uartcfg) {
1614 .ucon = S5PV210_UCON_DEFAULT,
1615 .ufcon = S5PV210_UFCON_DEFAULT,
1618 .fifosize = { 256, 64, 16, 16 },
1620 #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
1622 #define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1625 static struct platform_device_id s3c24xx_serial_driver_ids[] = {
1627 .name = "s3c2410-uart",
1628 .driver_data = S3C2410_SERIAL_DRV_DATA,
1630 .name = "s3c2412-uart",
1631 .driver_data = S3C2412_SERIAL_DRV_DATA,
1633 .name = "s3c2440-uart",
1634 .driver_data = S3C2440_SERIAL_DRV_DATA,
1636 .name = "s3c6400-uart",
1637 .driver_data = S3C6400_SERIAL_DRV_DATA,
1639 .name = "s5pv210-uart",
1640 .driver_data = S5PV210_SERIAL_DRV_DATA,
1642 .name = "exynos4210-uart",
1643 .driver_data = EXYNOS4210_SERIAL_DRV_DATA,
1647 MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
1650 static const struct of_device_id s3c24xx_uart_dt_match[] = {
1651 { .compatible = "samsung,exynos4210-uart",
1652 .data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
1655 MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
1657 #define s3c24xx_uart_dt_match NULL
1660 static struct platform_driver samsung_serial_driver = {
1661 .probe = s3c24xx_serial_probe,
1662 .remove = __devexit_p(s3c24xx_serial_remove),
1663 .id_table = s3c24xx_serial_driver_ids,
1665 .name = "samsung-uart",
1666 .owner = THIS_MODULE,
1667 .pm = SERIAL_SAMSUNG_PM_OPS,
1668 .of_match_table = s3c24xx_uart_dt_match,
1672 /* module initialisation code */
1674 static int __init s3c24xx_serial_modinit(void)
1678 ret = uart_register_driver(&s3c24xx_uart_drv);
1680 printk(KERN_ERR "failed to register UART driver\n");
1684 return platform_driver_register(&samsung_serial_driver);
1687 static void __exit s3c24xx_serial_modexit(void)
1689 uart_unregister_driver(&s3c24xx_uart_drv);
1692 module_init(s3c24xx_serial_modinit);
1693 module_exit(s3c24xx_serial_modexit);
1695 MODULE_ALIAS("platform:samsung-uart");
1696 MODULE_DESCRIPTION("Samsung SoC Serial port driver");
1697 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1698 MODULE_LICENSE("GPL v2");