5 * Driver for Samsung SoC onboard UARTs.
7 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
8 * http://armlinux.simtec.co.uk/
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/dmaengine.h>
17 struct s3c24xx_uart_info {
20 unsigned int fifosize;
21 unsigned long rx_fifomask;
22 unsigned long rx_fifoshift;
23 unsigned long rx_fifofull;
24 unsigned long tx_fifomask;
25 unsigned long tx_fifoshift;
26 unsigned long tx_fifofull;
27 unsigned int def_clk_sel;
28 unsigned long num_clks;
29 unsigned long clksel_mask;
30 unsigned long clksel_shift;
32 /* uart port features */
34 unsigned int has_divslot:1;
37 int (*reset_port)(struct uart_port *, struct s3c2410_uartcfg *);
40 struct s3c24xx_serial_drv_data {
41 struct s3c24xx_uart_info *info;
42 struct s3c2410_uartcfg *def_cfg;
43 unsigned int fifosize[CONFIG_SERIAL_SAMSUNG_UARTS];
46 struct s3c24xx_uart_dma {
51 unsigned int rx_chan_id;
52 unsigned int tx_chan_id;
54 struct dma_slave_config rx_conf;
55 struct dma_slave_config tx_conf;
57 struct dma_chan *rx_chan;
58 struct dma_chan *tx_chan;
63 dma_cookie_t rx_cookie;
64 dma_cookie_t tx_cookie;
68 dma_addr_t tx_transfer_addr;
73 struct dma_async_tx_descriptor *tx_desc;
74 struct dma_async_tx_descriptor *rx_desc;
76 int tx_bytes_requested;
77 int rx_bytes_requested;
80 struct s3c24xx_uart_port {
81 unsigned char rx_claimed;
82 unsigned char tx_claimed;
83 unsigned int pm_level;
84 unsigned long baudclk_rate;
89 unsigned int tx_in_progress;
93 struct s3c24xx_uart_info *info;
96 struct uart_port port;
97 struct s3c24xx_serial_drv_data *drv_data;
99 /* reference to platform data */
100 struct s3c2410_uartcfg *cfg;
102 struct s3c24xx_uart_dma *dma;
104 #ifdef CONFIG_CPU_FREQ
105 struct notifier_block freq_transition;
109 /* conversion functions */
111 #define s3c24xx_dev_to_port(__dev) dev_get_drvdata(__dev)
113 /* register access controls */
115 #define portaddr(port, reg) ((port)->membase + (reg))
116 #define portaddrl(port, reg) \
117 ((unsigned long *)(unsigned long)((port)->membase + (reg)))
119 #define rd_regb(port, reg) (__raw_readb(portaddr(port, reg)))
120 #define rd_regl(port, reg) (__raw_readl(portaddr(port, reg)))
122 #define wr_regb(port, reg, val) __raw_writeb(val, portaddr(port, reg))
123 #define wr_regl(port, reg, val) __raw_writel(val, portaddr(port, reg))