2 * SC16IS7xx tty serial driver - Copyright (C) 2014 GridPoint
3 * Author: Jon Ringle <jringle@gridpoint.com>
5 * Based on max310x.c, by Alexander Shiyan <shc_work@mail.ru>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
14 #include <linux/bitops.h>
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/device.h>
18 #include <linux/gpio.h>
19 #include <linux/i2c.h>
20 #include <linux/module.h>
22 #include <linux/of_device.h>
23 #include <linux/regmap.h>
24 #include <linux/serial_core.h>
25 #include <linux/serial.h>
26 #include <linux/tty.h>
27 #include <linux/tty_flip.h>
28 #include <linux/spi/spi.h>
29 #include <linux/uaccess.h>
31 #define SC16IS7XX_NAME "sc16is7xx"
33 /* SC16IS7XX register definitions */
34 #define SC16IS7XX_RHR_REG (0x00) /* RX FIFO */
35 #define SC16IS7XX_THR_REG (0x00) /* TX FIFO */
36 #define SC16IS7XX_IER_REG (0x01) /* Interrupt enable */
37 #define SC16IS7XX_IIR_REG (0x02) /* Interrupt Identification */
38 #define SC16IS7XX_FCR_REG (0x02) /* FIFO control */
39 #define SC16IS7XX_LCR_REG (0x03) /* Line Control */
40 #define SC16IS7XX_MCR_REG (0x04) /* Modem Control */
41 #define SC16IS7XX_LSR_REG (0x05) /* Line Status */
42 #define SC16IS7XX_MSR_REG (0x06) /* Modem Status */
43 #define SC16IS7XX_SPR_REG (0x07) /* Scratch Pad */
44 #define SC16IS7XX_TXLVL_REG (0x08) /* TX FIFO level */
45 #define SC16IS7XX_RXLVL_REG (0x09) /* RX FIFO level */
46 #define SC16IS7XX_IODIR_REG (0x0a) /* I/O Direction
49 #define SC16IS7XX_IOSTATE_REG (0x0b) /* I/O State
52 #define SC16IS7XX_IOINTENA_REG (0x0c) /* I/O Interrupt Enable
55 #define SC16IS7XX_IOCONTROL_REG (0x0e) /* I/O Control
58 #define SC16IS7XX_EFCR_REG (0x0f) /* Extra Features Control */
60 /* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */
61 #define SC16IS7XX_TCR_REG (0x06) /* Transmit control */
62 #define SC16IS7XX_TLR_REG (0x07) /* Trigger level */
64 /* Special Register set: Only if ((LCR[7] == 1) && (LCR != 0xBF)) */
65 #define SC16IS7XX_DLL_REG (0x00) /* Divisor Latch Low */
66 #define SC16IS7XX_DLH_REG (0x01) /* Divisor Latch High */
68 /* Enhanced Register set: Only if (LCR == 0xBF) */
69 #define SC16IS7XX_EFR_REG (0x02) /* Enhanced Features */
70 #define SC16IS7XX_XON1_REG (0x04) /* Xon1 word */
71 #define SC16IS7XX_XON2_REG (0x05) /* Xon2 word */
72 #define SC16IS7XX_XOFF1_REG (0x06) /* Xoff1 word */
73 #define SC16IS7XX_XOFF2_REG (0x07) /* Xoff2 word */
75 /* IER register bits */
76 #define SC16IS7XX_IER_RDI_BIT (1 << 0) /* Enable RX data interrupt */
77 #define SC16IS7XX_IER_THRI_BIT (1 << 1) /* Enable TX holding register
79 #define SC16IS7XX_IER_RLSI_BIT (1 << 2) /* Enable RX line status
81 #define SC16IS7XX_IER_MSI_BIT (1 << 3) /* Enable Modem status
84 /* IER register bits - write only if (EFR[4] == 1) */
85 #define SC16IS7XX_IER_SLEEP_BIT (1 << 4) /* Enable Sleep mode */
86 #define SC16IS7XX_IER_XOFFI_BIT (1 << 5) /* Enable Xoff interrupt */
87 #define SC16IS7XX_IER_RTSI_BIT (1 << 6) /* Enable nRTS interrupt */
88 #define SC16IS7XX_IER_CTSI_BIT (1 << 7) /* Enable nCTS interrupt */
90 /* FCR register bits */
91 #define SC16IS7XX_FCR_FIFO_BIT (1 << 0) /* Enable FIFO */
92 #define SC16IS7XX_FCR_RXRESET_BIT (1 << 1) /* Reset RX FIFO */
93 #define SC16IS7XX_FCR_TXRESET_BIT (1 << 2) /* Reset TX FIFO */
94 #define SC16IS7XX_FCR_RXLVLL_BIT (1 << 6) /* RX Trigger level LSB */
95 #define SC16IS7XX_FCR_RXLVLH_BIT (1 << 7) /* RX Trigger level MSB */
97 /* FCR register bits - write only if (EFR[4] == 1) */
98 #define SC16IS7XX_FCR_TXLVLL_BIT (1 << 4) /* TX Trigger level LSB */
99 #define SC16IS7XX_FCR_TXLVLH_BIT (1 << 5) /* TX Trigger level MSB */
101 /* IIR register bits */
102 #define SC16IS7XX_IIR_NO_INT_BIT (1 << 0) /* No interrupts pending */
103 #define SC16IS7XX_IIR_ID_MASK 0x3e /* Mask for the interrupt ID */
104 #define SC16IS7XX_IIR_THRI_SRC 0x02 /* TX holding register empty */
105 #define SC16IS7XX_IIR_RDI_SRC 0x04 /* RX data interrupt */
106 #define SC16IS7XX_IIR_RLSE_SRC 0x06 /* RX line status error */
107 #define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */
108 #define SC16IS7XX_IIR_MSI_SRC 0x00 /* Modem status interrupt
111 #define SC16IS7XX_IIR_INPIN_SRC 0x30 /* Input pin change of state
114 #define SC16IS7XX_IIR_XOFFI_SRC 0x10 /* Received Xoff */
115 #define SC16IS7XX_IIR_CTSRTS_SRC 0x20 /* nCTS,nRTS change of state
119 /* LCR register bits */
120 #define SC16IS7XX_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */
121 #define SC16IS7XX_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1
123 * Word length bits table:
129 #define SC16IS7XX_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit
131 * STOP length bit table:
133 * 1 -> 1-1.5 stop bits if
135 * 2 stop bits otherwise
137 #define SC16IS7XX_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */
138 #define SC16IS7XX_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */
139 #define SC16IS7XX_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */
140 #define SC16IS7XX_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */
141 #define SC16IS7XX_LCR_DLAB_BIT (1 << 7) /* Divisor Latch enable */
142 #define SC16IS7XX_LCR_WORD_LEN_5 (0x00)
143 #define SC16IS7XX_LCR_WORD_LEN_6 (0x01)
144 #define SC16IS7XX_LCR_WORD_LEN_7 (0x02)
145 #define SC16IS7XX_LCR_WORD_LEN_8 (0x03)
146 #define SC16IS7XX_LCR_CONF_MODE_A SC16IS7XX_LCR_DLAB_BIT /* Special
148 #define SC16IS7XX_LCR_CONF_MODE_B 0xBF /* Enhanced
151 /* MCR register bits */
152 #define SC16IS7XX_MCR_DTR_BIT (1 << 0) /* DTR complement
155 #define SC16IS7XX_MCR_RTS_BIT (1 << 1) /* RTS complement */
156 #define SC16IS7XX_MCR_TCRTLR_BIT (1 << 2) /* TCR/TLR register enable */
157 #define SC16IS7XX_MCR_LOOP_BIT (1 << 4) /* Enable loopback test mode */
158 #define SC16IS7XX_MCR_XONANY_BIT (1 << 5) /* Enable Xon Any
162 #define SC16IS7XX_MCR_IRDA_BIT (1 << 6) /* Enable IrDA mode
166 #define SC16IS7XX_MCR_CLKSEL_BIT (1 << 7) /* Divide clock by 4
171 /* LSR register bits */
172 #define SC16IS7XX_LSR_DR_BIT (1 << 0) /* Receiver data ready */
173 #define SC16IS7XX_LSR_OE_BIT (1 << 1) /* Overrun Error */
174 #define SC16IS7XX_LSR_PE_BIT (1 << 2) /* Parity Error */
175 #define SC16IS7XX_LSR_FE_BIT (1 << 3) /* Frame Error */
176 #define SC16IS7XX_LSR_BI_BIT (1 << 4) /* Break Interrupt */
177 #define SC16IS7XX_LSR_BRK_ERROR_MASK 0x1E /* BI, FE, PE, OE bits */
178 #define SC16IS7XX_LSR_THRE_BIT (1 << 5) /* TX holding register empty */
179 #define SC16IS7XX_LSR_TEMT_BIT (1 << 6) /* Transmitter empty */
180 #define SC16IS7XX_LSR_FIFOE_BIT (1 << 7) /* Fifo Error */
182 /* MSR register bits */
183 #define SC16IS7XX_MSR_DCTS_BIT (1 << 0) /* Delta CTS Clear To Send */
184 #define SC16IS7XX_MSR_DDSR_BIT (1 << 1) /* Delta DSR Data Set Ready
188 #define SC16IS7XX_MSR_DRI_BIT (1 << 2) /* Delta RI Ring Indicator
192 #define SC16IS7XX_MSR_DCD_BIT (1 << 3) /* Delta CD Carrier Detect
196 #define SC16IS7XX_MSR_CTS_BIT (1 << 0) /* CTS */
197 #define SC16IS7XX_MSR_DSR_BIT (1 << 1) /* DSR (IO4)
200 #define SC16IS7XX_MSR_RI_BIT (1 << 2) /* RI (IO7)
203 #define SC16IS7XX_MSR_CD_BIT (1 << 3) /* CD (IO6)
206 #define SC16IS7XX_MSR_DELTA_MASK 0x0F /* Any of the delta bits! */
210 * TCR trigger levels are available from 0 to 60 characters with a granularity
212 * The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is
213 * no built-in hardware check to make sure this condition is met. Also, the TCR
214 * must be programmed with this condition before auto RTS or software flow
215 * control is enabled to avoid spurious operation of the device.
217 #define SC16IS7XX_TCR_RX_HALT(words) ((((words) / 4) & 0x0f) << 0)
218 #define SC16IS7XX_TCR_RX_RESUME(words) ((((words) / 4) & 0x0f) << 4)
222 * If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the
223 * FIFO Control Register (FCR) are used for the transmit and receive FIFO
224 * trigger levels. Trigger levels from 4 characters to 60 characters are
225 * available with a granularity of four.
227 * When the trigger level setting in TLR is zero, the SC16IS740/750/760 uses the
228 * trigger level setting defined in FCR. If TLR has non-zero trigger level value
229 * the trigger level defined in FCR is discarded. This applies to both transmit
230 * FIFO and receive FIFO trigger level setting.
232 * When TLR is used for RX trigger level control, FCR[7:6] should be left at the
233 * default state, that is, '00'.
235 #define SC16IS7XX_TLR_TX_TRIGGER(words) ((((words) / 4) & 0x0f) << 0)
236 #define SC16IS7XX_TLR_RX_TRIGGER(words) ((((words) / 4) & 0x0f) << 4)
238 /* IOControl register bits (Only 750/760) */
239 #define SC16IS7XX_IOCONTROL_LATCH_BIT (1 << 0) /* Enable input latching */
240 #define SC16IS7XX_IOCONTROL_GPIO_BIT (1 << 1) /* Enable GPIO[7:4] */
241 #define SC16IS7XX_IOCONTROL_SRESET_BIT (1 << 3) /* Software Reset */
243 /* EFCR register bits */
244 #define SC16IS7XX_EFCR_9BIT_MODE_BIT (1 << 0) /* Enable 9-bit or Multidrop
246 #define SC16IS7XX_EFCR_RXDISABLE_BIT (1 << 1) /* Disable receiver */
247 #define SC16IS7XX_EFCR_TXDISABLE_BIT (1 << 2) /* Disable transmitter */
248 #define SC16IS7XX_EFCR_AUTO_RS485_BIT (1 << 4) /* Auto RS485 RTS direction */
249 #define SC16IS7XX_EFCR_RTS_INVERT_BIT (1 << 5) /* RTS output inversion */
250 #define SC16IS7XX_EFCR_IRDA_MODE_BIT (1 << 7) /* IrDA mode
251 * 0 = rate upto 115.2 kbit/s
253 * 1 = rate upto 1.152 Mbit/s
257 /* EFR register bits */
258 #define SC16IS7XX_EFR_AUTORTS_BIT (1 << 6) /* Auto RTS flow ctrl enable */
259 #define SC16IS7XX_EFR_AUTOCTS_BIT (1 << 7) /* Auto CTS flow ctrl enable */
260 #define SC16IS7XX_EFR_XOFF2_DETECT_BIT (1 << 5) /* Enable Xoff2 detection */
261 #define SC16IS7XX_EFR_ENABLE_BIT (1 << 4) /* Enable enhanced functions
262 * and writing to IER[7:4],
265 #define SC16IS7XX_EFR_SWFLOW3_BIT (1 << 3) /* SWFLOW bit 3 */
266 #define SC16IS7XX_EFR_SWFLOW2_BIT (1 << 2) /* SWFLOW bit 2
268 * SWFLOW bits 3 & 2 table:
269 * 00 -> no transmitter flow
271 * 01 -> transmitter generates
273 * 10 -> transmitter generates
275 * 11 -> transmitter generates
276 * XON1, XON2, XOFF1 and
279 #define SC16IS7XX_EFR_SWFLOW1_BIT (1 << 1) /* SWFLOW bit 2 */
280 #define SC16IS7XX_EFR_SWFLOW0_BIT (1 << 0) /* SWFLOW bit 3
282 * SWFLOW bits 3 & 2 table:
283 * 00 -> no received flow
285 * 01 -> receiver compares
287 * 10 -> receiver compares
289 * 11 -> receiver compares
290 * XON1, XON2, XOFF1 and
294 /* Misc definitions */
295 #define SC16IS7XX_FIFO_SIZE (64)
296 #define SC16IS7XX_REG_SHIFT 2
298 struct sc16is7xx_devtype {
304 #define SC16IS7XX_RECONF_MD (1 << 0)
305 #define SC16IS7XX_RECONF_IER (1 << 1)
307 struct sc16is7xx_one_config {
312 struct sc16is7xx_one {
313 struct uart_port port;
314 struct kthread_work tx_work;
315 struct kthread_work reg_work;
316 struct sc16is7xx_one_config config;
319 struct sc16is7xx_port {
320 struct uart_driver uart;
321 struct sc16is7xx_devtype *devtype;
322 struct regmap *regmap;
324 #ifdef CONFIG_GPIOLIB
325 struct gpio_chip gpio;
327 unsigned char buf[SC16IS7XX_FIFO_SIZE];
328 struct kthread_worker kworker;
329 struct task_struct *kworker_task;
330 struct kthread_work irq_work;
331 struct sc16is7xx_one p[0];
334 #define to_sc16is7xx_port(p,e) ((container_of((p), struct sc16is7xx_port, e)))
335 #define to_sc16is7xx_one(p,e) ((container_of((p), struct sc16is7xx_one, e)))
337 static u8 sc16is7xx_port_read(struct uart_port *port, u8 reg)
339 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
340 unsigned int val = 0;
342 regmap_read(s->regmap,
343 (reg << SC16IS7XX_REG_SHIFT) | port->line, &val);
348 static void sc16is7xx_port_write(struct uart_port *port, u8 reg, u8 val)
350 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
352 regmap_write(s->regmap,
353 (reg << SC16IS7XX_REG_SHIFT) | port->line, val);
356 static void sc16is7xx_port_update(struct uart_port *port, u8 reg,
359 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
361 regmap_update_bits(s->regmap,
362 (reg << SC16IS7XX_REG_SHIFT) | port->line,
367 static void sc16is7xx_power(struct uart_port *port, int on)
369 sc16is7xx_port_update(port, SC16IS7XX_IER_REG,
370 SC16IS7XX_IER_SLEEP_BIT,
371 on ? 0 : SC16IS7XX_IER_SLEEP_BIT);
374 static const struct sc16is7xx_devtype sc16is74x_devtype = {
380 static const struct sc16is7xx_devtype sc16is750_devtype = {
386 static const struct sc16is7xx_devtype sc16is752_devtype = {
392 static const struct sc16is7xx_devtype sc16is760_devtype = {
398 static const struct sc16is7xx_devtype sc16is762_devtype = {
404 static bool sc16is7xx_regmap_volatile(struct device *dev, unsigned int reg)
406 switch (reg >> SC16IS7XX_REG_SHIFT) {
407 case SC16IS7XX_RHR_REG:
408 case SC16IS7XX_IIR_REG:
409 case SC16IS7XX_LSR_REG:
410 case SC16IS7XX_MSR_REG:
411 case SC16IS7XX_TXLVL_REG:
412 case SC16IS7XX_RXLVL_REG:
413 case SC16IS7XX_IOSTATE_REG:
422 static bool sc16is7xx_regmap_precious(struct device *dev, unsigned int reg)
424 switch (reg >> SC16IS7XX_REG_SHIFT) {
425 case SC16IS7XX_RHR_REG:
434 static int sc16is7xx_set_baud(struct uart_port *port, int baud)
436 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
439 unsigned long clk = port->uartclk, div = clk / 16 / baud;
442 prescaler = SC16IS7XX_MCR_CLKSEL_BIT;
446 lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG);
448 /* Open the LCR divisors for configuration */
449 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
450 SC16IS7XX_LCR_CONF_MODE_B);
452 /* Enable enhanced features */
453 regcache_cache_bypass(s->regmap, true);
454 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG,
455 SC16IS7XX_EFR_ENABLE_BIT);
456 regcache_cache_bypass(s->regmap, false);
458 /* Put LCR back to the normal mode */
459 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
461 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
462 SC16IS7XX_MCR_CLKSEL_BIT,
465 /* Open the LCR divisors for configuration */
466 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
467 SC16IS7XX_LCR_CONF_MODE_A);
469 /* Write the new divisor */
470 regcache_cache_bypass(s->regmap, true);
471 sc16is7xx_port_write(port, SC16IS7XX_DLH_REG, div / 256);
472 sc16is7xx_port_write(port, SC16IS7XX_DLL_REG, div % 256);
473 regcache_cache_bypass(s->regmap, false);
475 /* Put LCR back to the normal mode */
476 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
478 return DIV_ROUND_CLOSEST(clk / 16, div);
481 static void sc16is7xx_handle_rx(struct uart_port *port, unsigned int rxlen,
484 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
485 unsigned int lsr = 0, ch, flag, bytes_read, i;
486 bool read_lsr = (iir == SC16IS7XX_IIR_RLSE_SRC) ? true : false;
488 if (unlikely(rxlen >= sizeof(s->buf))) {
489 dev_warn_ratelimited(port->dev,
490 "Port %i: Possible RX FIFO overrun: %d\n",
492 port->icount.buf_overrun++;
493 /* Ensure sanity of RX level */
494 rxlen = sizeof(s->buf);
498 /* Only read lsr if there are possible errors in FIFO */
500 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
501 if (!(lsr & SC16IS7XX_LSR_FIFOE_BIT))
502 read_lsr = false; /* No errors left in FIFO */
507 s->buf[0] = sc16is7xx_port_read(port, SC16IS7XX_RHR_REG);
510 regcache_cache_bypass(s->regmap, true);
511 regmap_raw_read(s->regmap, SC16IS7XX_RHR_REG,
513 regcache_cache_bypass(s->regmap, false);
517 lsr &= SC16IS7XX_LSR_BRK_ERROR_MASK;
523 if (lsr & SC16IS7XX_LSR_BI_BIT) {
525 if (uart_handle_break(port))
527 } else if (lsr & SC16IS7XX_LSR_PE_BIT)
528 port->icount.parity++;
529 else if (lsr & SC16IS7XX_LSR_FE_BIT)
530 port->icount.frame++;
531 else if (lsr & SC16IS7XX_LSR_OE_BIT)
532 port->icount.overrun++;
534 lsr &= port->read_status_mask;
535 if (lsr & SC16IS7XX_LSR_BI_BIT)
537 else if (lsr & SC16IS7XX_LSR_PE_BIT)
539 else if (lsr & SC16IS7XX_LSR_FE_BIT)
541 else if (lsr & SC16IS7XX_LSR_OE_BIT)
545 for (i = 0; i < bytes_read; ++i) {
547 if (uart_handle_sysrq_char(port, ch))
550 if (lsr & port->ignore_status_mask)
553 uart_insert_char(port, lsr, SC16IS7XX_LSR_OE_BIT, ch,
559 tty_flip_buffer_push(&port->state->port);
562 static void sc16is7xx_handle_tx(struct uart_port *port)
564 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
565 struct circ_buf *xmit = &port->state->xmit;
566 unsigned int txlen, to_send, i;
568 if (unlikely(port->x_char)) {
569 sc16is7xx_port_write(port, SC16IS7XX_THR_REG, port->x_char);
575 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
578 /* Get length of data pending in circular buffer */
579 to_send = uart_circ_chars_pending(xmit);
580 if (likely(to_send)) {
581 /* Limit to size of TX FIFO */
582 txlen = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG);
583 to_send = (to_send > txlen) ? txlen : to_send;
585 /* Add data to send */
586 port->icount.tx += to_send;
588 /* Convert to linear buffer */
589 for (i = 0; i < to_send; ++i) {
590 s->buf[i] = xmit->buf[xmit->tail];
591 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
593 regcache_cache_bypass(s->regmap, true);
594 regmap_raw_write(s->regmap, SC16IS7XX_THR_REG, s->buf, to_send);
595 regcache_cache_bypass(s->regmap, false);
598 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
599 uart_write_wakeup(port);
602 static void sc16is7xx_port_irq(struct sc16is7xx_port *s, int portno)
604 struct uart_port *port = &s->p[portno].port;
607 unsigned int iir, msr, rxlen;
609 iir = sc16is7xx_port_read(port, SC16IS7XX_IIR_REG);
610 if (iir & SC16IS7XX_IIR_NO_INT_BIT)
613 iir &= SC16IS7XX_IIR_ID_MASK;
616 case SC16IS7XX_IIR_RDI_SRC:
617 case SC16IS7XX_IIR_RLSE_SRC:
618 case SC16IS7XX_IIR_RTOI_SRC:
619 case SC16IS7XX_IIR_XOFFI_SRC:
620 rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG);
622 sc16is7xx_handle_rx(port, rxlen, iir);
625 case SC16IS7XX_IIR_CTSRTS_SRC:
626 msr = sc16is7xx_port_read(port, SC16IS7XX_MSR_REG);
627 uart_handle_cts_change(port,
628 !!(msr & SC16IS7XX_MSR_CTS_BIT));
630 case SC16IS7XX_IIR_THRI_SRC:
631 sc16is7xx_handle_tx(port);
634 dev_err_ratelimited(port->dev,
635 "Port %i: Unexpected interrupt: %x",
642 static void sc16is7xx_ist(struct kthread_work *ws)
644 struct sc16is7xx_port *s = to_sc16is7xx_port(ws, irq_work);
647 for (i = 0; i < s->uart.nr; ++i)
648 sc16is7xx_port_irq(s, i);
651 static irqreturn_t sc16is7xx_irq(int irq, void *dev_id)
653 struct sc16is7xx_port *s = (struct sc16is7xx_port *)dev_id;
655 queue_kthread_work(&s->kworker, &s->irq_work);
660 static void sc16is7xx_tx_proc(struct kthread_work *ws)
662 struct uart_port *port = &(to_sc16is7xx_one(ws, tx_work)->port);
664 if ((port->rs485.flags & SER_RS485_ENABLED) &&
665 (port->rs485.delay_rts_before_send > 0))
666 msleep(port->rs485.delay_rts_before_send);
668 sc16is7xx_handle_tx(port);
671 static void sc16is7xx_reg_proc(struct kthread_work *ws)
673 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, reg_work);
674 struct sc16is7xx_one_config config;
675 unsigned long irqflags;
677 spin_lock_irqsave(&one->port.lock, irqflags);
678 config = one->config;
679 memset(&one->config, 0, sizeof(one->config));
680 spin_unlock_irqrestore(&one->port.lock, irqflags);
682 if (config.flags & SC16IS7XX_RECONF_MD)
683 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG,
684 SC16IS7XX_MCR_LOOP_BIT,
685 (one->port.mctrl & TIOCM_LOOP) ?
686 SC16IS7XX_MCR_LOOP_BIT : 0);
688 if (config.flags & SC16IS7XX_RECONF_IER)
689 sc16is7xx_port_update(&one->port, SC16IS7XX_IER_REG,
690 config.ier_clear, 0);
693 static void sc16is7xx_ier_clear(struct uart_port *port, u8 bit)
695 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
696 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
698 one->config.flags |= SC16IS7XX_RECONF_IER;
699 one->config.ier_clear |= bit;
700 queue_kthread_work(&s->kworker, &one->reg_work);
703 static void sc16is7xx_stop_tx(struct uart_port *port)
705 sc16is7xx_ier_clear(port, SC16IS7XX_IER_THRI_BIT);
708 static void sc16is7xx_stop_rx(struct uart_port *port)
710 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT);
713 static void sc16is7xx_start_tx(struct uart_port *port)
715 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
716 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
718 queue_kthread_work(&s->kworker, &one->tx_work);
721 static unsigned int sc16is7xx_tx_empty(struct uart_port *port)
725 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
727 return (lsr & SC16IS7XX_LSR_TEMT_BIT) ? TIOCSER_TEMT : 0;
730 static unsigned int sc16is7xx_get_mctrl(struct uart_port *port)
732 /* DCD and DSR are not wired and CTS/RTS is handled automatically
733 * so just indicate DSR and CAR asserted
735 return TIOCM_DSR | TIOCM_CAR;
738 static void sc16is7xx_set_mctrl(struct uart_port *port, unsigned int mctrl)
740 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
741 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
743 one->config.flags |= SC16IS7XX_RECONF_MD;
744 queue_kthread_work(&s->kworker, &one->reg_work);
747 static void sc16is7xx_break_ctl(struct uart_port *port, int break_state)
749 sc16is7xx_port_update(port, SC16IS7XX_LCR_REG,
750 SC16IS7XX_LCR_TXBREAK_BIT,
751 break_state ? SC16IS7XX_LCR_TXBREAK_BIT : 0);
754 static void sc16is7xx_set_termios(struct uart_port *port,
755 struct ktermios *termios,
756 struct ktermios *old)
758 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
759 unsigned int lcr, flow = 0;
762 /* Mask termios capabilities we don't support */
763 termios->c_cflag &= ~CMSPAR;
766 switch (termios->c_cflag & CSIZE) {
768 lcr = SC16IS7XX_LCR_WORD_LEN_5;
771 lcr = SC16IS7XX_LCR_WORD_LEN_6;
774 lcr = SC16IS7XX_LCR_WORD_LEN_7;
777 lcr = SC16IS7XX_LCR_WORD_LEN_8;
780 lcr = SC16IS7XX_LCR_WORD_LEN_8;
781 termios->c_cflag &= ~CSIZE;
782 termios->c_cflag |= CS8;
787 if (termios->c_cflag & PARENB) {
788 lcr |= SC16IS7XX_LCR_PARITY_BIT;
789 if (!(termios->c_cflag & PARODD))
790 lcr |= SC16IS7XX_LCR_EVENPARITY_BIT;
794 if (termios->c_cflag & CSTOPB)
795 lcr |= SC16IS7XX_LCR_STOPLEN_BIT; /* 2 stops */
797 /* Set read status mask */
798 port->read_status_mask = SC16IS7XX_LSR_OE_BIT;
799 if (termios->c_iflag & INPCK)
800 port->read_status_mask |= SC16IS7XX_LSR_PE_BIT |
801 SC16IS7XX_LSR_FE_BIT;
802 if (termios->c_iflag & (BRKINT | PARMRK))
803 port->read_status_mask |= SC16IS7XX_LSR_BI_BIT;
805 /* Set status ignore mask */
806 port->ignore_status_mask = 0;
807 if (termios->c_iflag & IGNBRK)
808 port->ignore_status_mask |= SC16IS7XX_LSR_BI_BIT;
809 if (!(termios->c_cflag & CREAD))
810 port->ignore_status_mask |= SC16IS7XX_LSR_BRK_ERROR_MASK;
812 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
813 SC16IS7XX_LCR_CONF_MODE_B);
815 /* Configure flow control */
816 regcache_cache_bypass(s->regmap, true);
817 sc16is7xx_port_write(port, SC16IS7XX_XON1_REG, termios->c_cc[VSTART]);
818 sc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, termios->c_cc[VSTOP]);
819 if (termios->c_cflag & CRTSCTS)
820 flow |= SC16IS7XX_EFR_AUTOCTS_BIT |
821 SC16IS7XX_EFR_AUTORTS_BIT;
822 if (termios->c_iflag & IXON)
823 flow |= SC16IS7XX_EFR_SWFLOW3_BIT;
824 if (termios->c_iflag & IXOFF)
825 flow |= SC16IS7XX_EFR_SWFLOW1_BIT;
827 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG, flow);
828 regcache_cache_bypass(s->regmap, false);
830 /* Update LCR register */
831 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
833 /* Get baud rate generator configuration */
834 baud = uart_get_baud_rate(port, termios, old,
835 port->uartclk / 16 / 4 / 0xffff,
838 /* Setup baudrate generator */
839 baud = sc16is7xx_set_baud(port, baud);
841 /* Update timeout according to new baud rate */
842 uart_update_timeout(port, termios->c_cflag, baud);
845 static int sc16is7xx_config_rs485(struct uart_port *port,
846 struct serial_rs485 *rs485)
848 const u32 mask = SC16IS7XX_EFCR_AUTO_RS485_BIT |
849 SC16IS7XX_EFCR_RTS_INVERT_BIT;
852 if (rs485->flags & SER_RS485_ENABLED) {
853 bool rts_during_rx, rts_during_tx;
855 rts_during_rx = rs485->flags & SER_RS485_RTS_AFTER_SEND;
856 rts_during_tx = rs485->flags & SER_RS485_RTS_ON_SEND;
858 efcr |= SC16IS7XX_EFCR_AUTO_RS485_BIT;
860 if (!rts_during_rx && rts_during_tx)
862 else if (rts_during_rx && !rts_during_tx)
863 efcr |= SC16IS7XX_EFCR_RTS_INVERT_BIT;
866 "unsupported RTS signalling on_send:%d after_send:%d - exactly one of RS485 RTS flags should be set\n",
867 rts_during_tx, rts_during_rx);
870 * RTS signal is handled by HW, it's timing can't be influenced.
871 * However, it's sometimes useful to delay TX even without RTS
872 * control therefore we try to handle .delay_rts_before_send.
874 if (rs485->delay_rts_after_send)
878 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, mask, efcr);
880 port->rs485 = *rs485;
885 static int sc16is7xx_startup(struct uart_port *port)
887 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
890 sc16is7xx_power(port, 1);
893 val = SC16IS7XX_FCR_RXRESET_BIT | SC16IS7XX_FCR_TXRESET_BIT;
894 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, val);
896 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG,
897 SC16IS7XX_FCR_FIFO_BIT);
900 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
901 SC16IS7XX_LCR_CONF_MODE_B);
903 regcache_cache_bypass(s->regmap, true);
905 /* Enable write access to enhanced features and internal clock div */
906 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG,
907 SC16IS7XX_EFR_ENABLE_BIT);
910 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
911 SC16IS7XX_MCR_TCRTLR_BIT,
912 SC16IS7XX_MCR_TCRTLR_BIT);
914 /* Configure flow control levels */
915 /* Flow control halt level 48, resume level 24 */
916 sc16is7xx_port_write(port, SC16IS7XX_TCR_REG,
917 SC16IS7XX_TCR_RX_RESUME(24) |
918 SC16IS7XX_TCR_RX_HALT(48));
920 regcache_cache_bypass(s->regmap, false);
922 /* Now, initialize the UART */
923 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_WORD_LEN_8);
925 /* Enable the Rx and Tx FIFO */
926 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
927 SC16IS7XX_EFCR_RXDISABLE_BIT |
928 SC16IS7XX_EFCR_TXDISABLE_BIT,
931 /* Enable RX, TX, CTS change interrupts */
932 val = SC16IS7XX_IER_RDI_BIT | SC16IS7XX_IER_THRI_BIT |
933 SC16IS7XX_IER_CTSI_BIT;
934 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val);
939 static void sc16is7xx_shutdown(struct uart_port *port)
941 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
943 /* Disable all interrupts */
944 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0);
946 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
947 SC16IS7XX_EFCR_RXDISABLE_BIT |
948 SC16IS7XX_EFCR_TXDISABLE_BIT,
949 SC16IS7XX_EFCR_RXDISABLE_BIT |
950 SC16IS7XX_EFCR_TXDISABLE_BIT);
952 sc16is7xx_power(port, 0);
954 flush_kthread_worker(&s->kworker);
957 static const char *sc16is7xx_type(struct uart_port *port)
959 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
961 return (port->type == PORT_SC16IS7XX) ? s->devtype->name : NULL;
964 static int sc16is7xx_request_port(struct uart_port *port)
970 static void sc16is7xx_config_port(struct uart_port *port, int flags)
972 if (flags & UART_CONFIG_TYPE)
973 port->type = PORT_SC16IS7XX;
976 static int sc16is7xx_verify_port(struct uart_port *port,
977 struct serial_struct *s)
979 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_SC16IS7XX))
981 if (s->irq != port->irq)
987 static void sc16is7xx_pm(struct uart_port *port, unsigned int state,
988 unsigned int oldstate)
990 sc16is7xx_power(port, (state == UART_PM_STATE_ON) ? 1 : 0);
993 static void sc16is7xx_null_void(struct uart_port *port)
998 static const struct uart_ops sc16is7xx_ops = {
999 .tx_empty = sc16is7xx_tx_empty,
1000 .set_mctrl = sc16is7xx_set_mctrl,
1001 .get_mctrl = sc16is7xx_get_mctrl,
1002 .stop_tx = sc16is7xx_stop_tx,
1003 .start_tx = sc16is7xx_start_tx,
1004 .stop_rx = sc16is7xx_stop_rx,
1005 .break_ctl = sc16is7xx_break_ctl,
1006 .startup = sc16is7xx_startup,
1007 .shutdown = sc16is7xx_shutdown,
1008 .set_termios = sc16is7xx_set_termios,
1009 .type = sc16is7xx_type,
1010 .request_port = sc16is7xx_request_port,
1011 .release_port = sc16is7xx_null_void,
1012 .config_port = sc16is7xx_config_port,
1013 .verify_port = sc16is7xx_verify_port,
1017 #ifdef CONFIG_GPIOLIB
1018 static int sc16is7xx_gpio_get(struct gpio_chip *chip, unsigned offset)
1021 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port,
1023 struct uart_port *port = &s->p[0].port;
1025 val = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG);
1027 return !!(val & BIT(offset));
1030 static void sc16is7xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
1032 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port,
1034 struct uart_port *port = &s->p[0].port;
1036 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset),
1037 val ? BIT(offset) : 0);
1040 static int sc16is7xx_gpio_direction_input(struct gpio_chip *chip,
1043 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port,
1045 struct uart_port *port = &s->p[0].port;
1047 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 0);
1052 static int sc16is7xx_gpio_direction_output(struct gpio_chip *chip,
1053 unsigned offset, int val)
1055 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port,
1057 struct uart_port *port = &s->p[0].port;
1059 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset),
1060 val ? BIT(offset) : 0);
1061 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset),
1068 static int sc16is7xx_probe(struct device *dev,
1069 struct sc16is7xx_devtype *devtype,
1070 struct regmap *regmap, int irq, unsigned long flags)
1072 struct sched_param sched_param = { .sched_priority = MAX_RT_PRIO / 2 };
1073 unsigned long freq, *pfreq = dev_get_platdata(dev);
1075 struct sc16is7xx_port *s;
1078 return PTR_ERR(regmap);
1080 /* Alloc port structure */
1081 s = devm_kzalloc(dev, sizeof(*s) +
1082 sizeof(struct sc16is7xx_one) * devtype->nr_uart,
1085 dev_err(dev, "Error allocating port structure\n");
1089 s->clk = devm_clk_get(dev, NULL);
1090 if (IS_ERR(s->clk)) {
1094 return PTR_ERR(s->clk);
1096 clk_prepare_enable(s->clk);
1097 freq = clk_get_rate(s->clk);
1101 s->devtype = devtype;
1102 dev_set_drvdata(dev, s);
1104 /* Register UART driver */
1105 s->uart.owner = THIS_MODULE;
1106 s->uart.dev_name = "ttySC";
1107 s->uart.nr = devtype->nr_uart;
1108 ret = uart_register_driver(&s->uart);
1110 dev_err(dev, "Registering UART driver failed\n");
1114 init_kthread_worker(&s->kworker);
1115 init_kthread_work(&s->irq_work, sc16is7xx_ist);
1116 s->kworker_task = kthread_run(kthread_worker_fn, &s->kworker,
1118 if (IS_ERR(s->kworker_task)) {
1119 ret = PTR_ERR(s->kworker_task);
1122 sched_setscheduler(s->kworker_task, SCHED_FIFO, &sched_param);
1124 #ifdef CONFIG_GPIOLIB
1125 if (devtype->nr_gpio) {
1126 /* Setup GPIO cotroller */
1127 s->gpio.owner = THIS_MODULE;
1129 s->gpio.label = dev_name(dev);
1130 s->gpio.direction_input = sc16is7xx_gpio_direction_input;
1131 s->gpio.get = sc16is7xx_gpio_get;
1132 s->gpio.direction_output = sc16is7xx_gpio_direction_output;
1133 s->gpio.set = sc16is7xx_gpio_set;
1135 s->gpio.ngpio = devtype->nr_gpio;
1136 s->gpio.can_sleep = 1;
1137 ret = gpiochip_add(&s->gpio);
1143 for (i = 0; i < devtype->nr_uart; ++i) {
1144 /* Initialize port data */
1145 s->p[i].port.line = i;
1146 s->p[i].port.dev = dev;
1147 s->p[i].port.irq = irq;
1148 s->p[i].port.type = PORT_SC16IS7XX;
1149 s->p[i].port.fifosize = SC16IS7XX_FIFO_SIZE;
1150 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY;
1151 s->p[i].port.iotype = UPIO_PORT;
1152 s->p[i].port.uartclk = freq;
1153 s->p[i].port.rs485_config = sc16is7xx_config_rs485;
1154 s->p[i].port.ops = &sc16is7xx_ops;
1155 /* Disable all interrupts */
1156 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_IER_REG, 0);
1158 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFCR_REG,
1159 SC16IS7XX_EFCR_RXDISABLE_BIT |
1160 SC16IS7XX_EFCR_TXDISABLE_BIT);
1161 /* Initialize kthread work structs */
1162 init_kthread_work(&s->p[i].tx_work, sc16is7xx_tx_proc);
1163 init_kthread_work(&s->p[i].reg_work, sc16is7xx_reg_proc);
1165 uart_add_one_port(&s->uart, &s->p[i].port);
1166 /* Go to suspend mode */
1167 sc16is7xx_power(&s->p[i].port, 0);
1170 /* Setup interrupt */
1171 ret = devm_request_irq(dev, irq, sc16is7xx_irq,
1172 IRQF_ONESHOT | flags, dev_name(dev), s);
1176 for (i = 0; i < s->uart.nr; i++)
1177 uart_remove_one_port(&s->uart, &s->p[i].port);
1179 #ifdef CONFIG_GPIOLIB
1180 if (devtype->nr_gpio)
1181 gpiochip_remove(&s->gpio);
1185 kthread_stop(s->kworker_task);
1188 uart_unregister_driver(&s->uart);
1191 if (!IS_ERR(s->clk))
1192 clk_disable_unprepare(s->clk);
1197 static int sc16is7xx_remove(struct device *dev)
1199 struct sc16is7xx_port *s = dev_get_drvdata(dev);
1202 #ifdef CONFIG_GPIOLIB
1203 if (s->devtype->nr_gpio)
1204 gpiochip_remove(&s->gpio);
1207 for (i = 0; i < s->uart.nr; i++) {
1208 uart_remove_one_port(&s->uart, &s->p[i].port);
1209 sc16is7xx_power(&s->p[i].port, 0);
1212 flush_kthread_worker(&s->kworker);
1213 kthread_stop(s->kworker_task);
1215 uart_unregister_driver(&s->uart);
1216 if (!IS_ERR(s->clk))
1217 clk_disable_unprepare(s->clk);
1222 static const struct of_device_id __maybe_unused sc16is7xx_dt_ids[] = {
1223 { .compatible = "nxp,sc16is740", .data = &sc16is74x_devtype, },
1224 { .compatible = "nxp,sc16is741", .data = &sc16is74x_devtype, },
1225 { .compatible = "nxp,sc16is750", .data = &sc16is750_devtype, },
1226 { .compatible = "nxp,sc16is752", .data = &sc16is752_devtype, },
1227 { .compatible = "nxp,sc16is760", .data = &sc16is760_devtype, },
1228 { .compatible = "nxp,sc16is762", .data = &sc16is762_devtype, },
1231 MODULE_DEVICE_TABLE(of, sc16is7xx_dt_ids);
1233 static struct regmap_config regcfg = {
1237 .cache_type = REGCACHE_RBTREE,
1238 .volatile_reg = sc16is7xx_regmap_volatile,
1239 .precious_reg = sc16is7xx_regmap_precious,
1242 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1243 static int sc16is7xx_spi_probe(struct spi_device *spi)
1245 struct sc16is7xx_devtype *devtype;
1246 unsigned long flags = 0;
1247 struct regmap *regmap;
1251 spi->bits_per_word = 8;
1252 /* only supports mode 0 on SC16IS762 */
1253 spi->mode = spi->mode ? : SPI_MODE_0;
1254 spi->max_speed_hz = spi->max_speed_hz ? : 15000000;
1255 ret = spi_setup(spi);
1259 if (spi->dev.of_node) {
1260 const struct of_device_id *of_id =
1261 of_match_device(sc16is7xx_dt_ids, &spi->dev);
1263 devtype = (struct sc16is7xx_devtype *)of_id->data;
1265 const struct spi_device_id *id_entry = spi_get_device_id(spi);
1267 devtype = (struct sc16is7xx_devtype *)id_entry->driver_data;
1268 flags = IRQF_TRIGGER_FALLING;
1271 regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) |
1272 (devtype->nr_uart - 1);
1273 regmap = devm_regmap_init_spi(spi, ®cfg);
1275 return sc16is7xx_probe(&spi->dev, devtype, regmap, spi->irq, flags);
1278 static int sc16is7xx_spi_remove(struct spi_device *spi)
1280 return sc16is7xx_remove(&spi->dev);
1283 static const struct spi_device_id sc16is7xx_spi_id_table[] = {
1284 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, },
1285 { "sc16is740", (kernel_ulong_t)&sc16is74x_devtype, },
1286 { "sc16is741", (kernel_ulong_t)&sc16is74x_devtype, },
1287 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, },
1288 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, },
1289 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, },
1290 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, },
1294 MODULE_DEVICE_TABLE(spi, sc16is7xx_spi_id_table);
1296 static struct spi_driver sc16is7xx_spi_uart_driver = {
1298 .name = SC16IS7XX_NAME,
1299 .owner = THIS_MODULE,
1300 .of_match_table = of_match_ptr(sc16is7xx_dt_ids),
1302 .probe = sc16is7xx_spi_probe,
1303 .remove = sc16is7xx_spi_remove,
1304 .id_table = sc16is7xx_spi_id_table,
1307 MODULE_ALIAS("spi:sc16is7xx");
1310 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1311 static int sc16is7xx_i2c_probe(struct i2c_client *i2c,
1312 const struct i2c_device_id *id)
1314 struct sc16is7xx_devtype *devtype;
1315 unsigned long flags = 0;
1316 struct regmap *regmap;
1318 if (i2c->dev.of_node) {
1319 const struct of_device_id *of_id =
1320 of_match_device(sc16is7xx_dt_ids, &i2c->dev);
1322 devtype = (struct sc16is7xx_devtype *)of_id->data;
1324 devtype = (struct sc16is7xx_devtype *)id->driver_data;
1325 flags = IRQF_TRIGGER_FALLING;
1328 regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) |
1329 (devtype->nr_uart - 1);
1330 regmap = devm_regmap_init_i2c(i2c, ®cfg);
1332 return sc16is7xx_probe(&i2c->dev, devtype, regmap, i2c->irq, flags);
1335 static int sc16is7xx_i2c_remove(struct i2c_client *client)
1337 return sc16is7xx_remove(&client->dev);
1340 static const struct i2c_device_id sc16is7xx_i2c_id_table[] = {
1341 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, },
1342 { "sc16is740", (kernel_ulong_t)&sc16is74x_devtype, },
1343 { "sc16is741", (kernel_ulong_t)&sc16is74x_devtype, },
1344 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, },
1345 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, },
1346 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, },
1347 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, },
1350 MODULE_DEVICE_TABLE(i2c, sc16is7xx_i2c_id_table);
1352 static struct i2c_driver sc16is7xx_i2c_uart_driver = {
1354 .name = SC16IS7XX_NAME,
1355 .owner = THIS_MODULE,
1356 .of_match_table = of_match_ptr(sc16is7xx_dt_ids),
1358 .probe = sc16is7xx_i2c_probe,
1359 .remove = sc16is7xx_i2c_remove,
1360 .id_table = sc16is7xx_i2c_id_table,
1363 MODULE_ALIAS("i2c:sc16is7xx");
1366 static int __init sc16is7xx_init(void)
1369 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1370 ret = i2c_add_driver(&sc16is7xx_i2c_uart_driver);
1372 pr_err("failed to init sc16is7xx i2c --> %d\n", ret);
1377 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1378 ret = spi_register_driver(&sc16is7xx_spi_uart_driver);
1380 pr_err("failed to init sc16is7xx spi --> %d\n", ret);
1386 module_init(sc16is7xx_init);
1388 static void __exit sc16is7xx_exit(void)
1390 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1391 i2c_del_driver(&sc16is7xx_i2c_uart_driver);
1394 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1395 spi_unregister_driver(&sc16is7xx_spi_uart_driver);
1398 module_exit(sc16is7xx_exit);
1400 MODULE_LICENSE("GPL");
1401 MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>");
1402 MODULE_DESCRIPTION("SC16IS7XX serial driver");