2 * NXP (Philips) SCC+++(SCN+++) serial driver
4 * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
6 * Based on sc26xx.c, by Thomas Bogendörfer (tsbogend@alpha.franken.de)
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
18 #include <linux/err.h>
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/console.h>
22 #include <linux/serial_core.h>
23 #include <linux/serial.h>
25 #include <linux/tty.h>
26 #include <linux/tty_flip.h>
27 #include <linux/spinlock.h>
28 #include <linux/platform_device.h>
29 #include <linux/platform_data/serial-sccnxp.h>
30 #include <linux/regulator/consumer.h>
32 #define SCCNXP_NAME "uart-sccnxp"
33 #define SCCNXP_MAJOR 204
34 #define SCCNXP_MINOR 205
36 #define SCCNXP_MR_REG (0x00)
37 # define MR0_BAUD_NORMAL (0 << 0)
38 # define MR0_BAUD_EXT1 (1 << 0)
39 # define MR0_BAUD_EXT2 (5 << 0)
40 # define MR0_FIFO (1 << 3)
41 # define MR0_TXLVL (1 << 4)
42 # define MR1_BITS_5 (0 << 0)
43 # define MR1_BITS_6 (1 << 0)
44 # define MR1_BITS_7 (2 << 0)
45 # define MR1_BITS_8 (3 << 0)
46 # define MR1_PAR_EVN (0 << 2)
47 # define MR1_PAR_ODD (1 << 2)
48 # define MR1_PAR_NO (4 << 2)
49 # define MR2_STOP1 (7 << 0)
50 # define MR2_STOP2 (0xf << 0)
51 #define SCCNXP_SR_REG (0x01)
52 #define SCCNXP_CSR_REG SCCNXP_SR_REG
53 # define SR_RXRDY (1 << 0)
54 # define SR_FULL (1 << 1)
55 # define SR_TXRDY (1 << 2)
56 # define SR_TXEMT (1 << 3)
57 # define SR_OVR (1 << 4)
58 # define SR_PE (1 << 5)
59 # define SR_FE (1 << 6)
60 # define SR_BRK (1 << 7)
61 #define SCCNXP_CR_REG (0x02)
62 # define CR_RX_ENABLE (1 << 0)
63 # define CR_RX_DISABLE (1 << 1)
64 # define CR_TX_ENABLE (1 << 2)
65 # define CR_TX_DISABLE (1 << 3)
66 # define CR_CMD_MRPTR1 (0x01 << 4)
67 # define CR_CMD_RX_RESET (0x02 << 4)
68 # define CR_CMD_TX_RESET (0x03 << 4)
69 # define CR_CMD_STATUS_RESET (0x04 << 4)
70 # define CR_CMD_BREAK_RESET (0x05 << 4)
71 # define CR_CMD_START_BREAK (0x06 << 4)
72 # define CR_CMD_STOP_BREAK (0x07 << 4)
73 # define CR_CMD_MRPTR0 (0x0b << 4)
74 #define SCCNXP_RHR_REG (0x03)
75 #define SCCNXP_THR_REG SCCNXP_RHR_REG
76 #define SCCNXP_IPCR_REG (0x04)
77 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
78 # define ACR_BAUD0 (0 << 7)
79 # define ACR_BAUD1 (1 << 7)
80 # define ACR_TIMER_MODE (6 << 4)
81 #define SCCNXP_ISR_REG (0x05)
82 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
83 # define IMR_TXRDY (1 << 0)
84 # define IMR_RXRDY (1 << 1)
85 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
86 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
87 #define SCCNXP_IPR_REG (0x0d)
88 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
89 #define SCCNXP_SOP_REG (0x0e)
90 #define SCCNXP_ROP_REG (0x0f)
93 #define MCTRL_MASK(sig) (0xf << (sig))
94 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
95 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
97 /* Supported chip types */
99 SCCNXP_TYPE_SC2681 = 2681,
100 SCCNXP_TYPE_SC2691 = 2691,
101 SCCNXP_TYPE_SC2692 = 2692,
102 SCCNXP_TYPE_SC2891 = 2891,
103 SCCNXP_TYPE_SC2892 = 2892,
104 SCCNXP_TYPE_SC28202 = 28202,
105 SCCNXP_TYPE_SC68681 = 68681,
106 SCCNXP_TYPE_SC68692 = 68692,
110 struct uart_driver uart;
111 struct uart_port port[SCCNXP_MAX_UARTS];
112 bool opened[SCCNXP_MAX_UARTS];
122 #define SCCNXP_HAVE_IO 0x00000001
123 #define SCCNXP_HAVE_MR0 0x00000002
125 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
126 struct console console;
132 struct timer_list timer;
134 struct sccnxp_pdata pdata;
136 struct regulator *regulator;
139 static inline u8 sccnxp_raw_read(void __iomem *base, u8 reg, u8 shift)
141 return readb(base + (reg << shift));
144 static inline void sccnxp_raw_write(void __iomem *base, u8 reg, u8 shift, u8 v)
146 writeb(v, base + (reg << shift));
149 static inline u8 sccnxp_read(struct uart_port *port, u8 reg)
151 struct sccnxp_port *s = dev_get_drvdata(port->dev);
153 return sccnxp_raw_read(port->membase, reg & s->addr_mask,
157 static inline void sccnxp_write(struct uart_port *port, u8 reg, u8 v)
159 struct sccnxp_port *s = dev_get_drvdata(port->dev);
161 sccnxp_raw_write(port->membase, reg & s->addr_mask, port->regshift, v);
164 static inline u8 sccnxp_port_read(struct uart_port *port, u8 reg)
166 return sccnxp_read(port, (port->line << 3) + reg);
169 static inline void sccnxp_port_write(struct uart_port *port, u8 reg, u8 v)
171 sccnxp_write(port, (port->line << 3) + reg, v);
174 static int sccnxp_update_best_err(int a, int b, int *besterr)
176 int err = abs(a - b);
178 if ((*besterr < 0) || (*besterr > err)) {
186 static const struct {
192 { 0, ACR_BAUD0, MR0_BAUD_NORMAL, 50, },
193 { 0, ACR_BAUD1, MR0_BAUD_NORMAL, 75, },
194 { 1, ACR_BAUD0, MR0_BAUD_NORMAL, 110, },
195 { 2, ACR_BAUD0, MR0_BAUD_NORMAL, 134, },
196 { 3, ACR_BAUD1, MR0_BAUD_NORMAL, 150, },
197 { 3, ACR_BAUD0, MR0_BAUD_NORMAL, 200, },
198 { 4, ACR_BAUD0, MR0_BAUD_NORMAL, 300, },
199 { 0, ACR_BAUD1, MR0_BAUD_EXT1, 450, },
200 { 1, ACR_BAUD0, MR0_BAUD_EXT2, 880, },
201 { 3, ACR_BAUD1, MR0_BAUD_EXT1, 900, },
202 { 5, ACR_BAUD0, MR0_BAUD_NORMAL, 600, },
203 { 7, ACR_BAUD0, MR0_BAUD_NORMAL, 1050, },
204 { 2, ACR_BAUD0, MR0_BAUD_EXT2, 1076, },
205 { 6, ACR_BAUD0, MR0_BAUD_NORMAL, 1200, },
206 { 10, ACR_BAUD1, MR0_BAUD_NORMAL, 1800, },
207 { 7, ACR_BAUD1, MR0_BAUD_NORMAL, 2000, },
208 { 8, ACR_BAUD0, MR0_BAUD_NORMAL, 2400, },
209 { 5, ACR_BAUD1, MR0_BAUD_EXT1, 3600, },
210 { 9, ACR_BAUD0, MR0_BAUD_NORMAL, 4800, },
211 { 10, ACR_BAUD0, MR0_BAUD_NORMAL, 7200, },
212 { 11, ACR_BAUD0, MR0_BAUD_NORMAL, 9600, },
213 { 8, ACR_BAUD0, MR0_BAUD_EXT1, 14400, },
214 { 12, ACR_BAUD1, MR0_BAUD_NORMAL, 19200, },
215 { 9, ACR_BAUD0, MR0_BAUD_EXT1, 28800, },
216 { 12, ACR_BAUD0, MR0_BAUD_NORMAL, 38400, },
217 { 11, ACR_BAUD0, MR0_BAUD_EXT1, 57600, },
218 { 12, ACR_BAUD1, MR0_BAUD_EXT1, 115200, },
219 { 12, ACR_BAUD0, MR0_BAUD_EXT1, 230400, },
223 static int sccnxp_set_baud(struct uart_port *port, int baud)
225 struct sccnxp_port *s = dev_get_drvdata(port->dev);
226 int div_std, tmp_baud, bestbaud = baud, besterr = -1;
227 u8 i, acr = 0, csr = 0, mr0 = 0;
229 /* Find best baud from table */
230 for (i = 0; baud_std[i].baud && besterr; i++) {
231 if (baud_std[i].mr0 && !(s->flags & SCCNXP_HAVE_MR0))
233 div_std = DIV_ROUND_CLOSEST(s->freq_std, baud_std[i].baud);
234 tmp_baud = DIV_ROUND_CLOSEST(port->uartclk, div_std);
235 if (!sccnxp_update_best_err(baud, tmp_baud, &besterr)) {
236 acr = baud_std[i].acr;
237 csr = baud_std[i].csr;
238 mr0 = baud_std[i].mr0;
243 if (s->flags & SCCNXP_HAVE_MR0) {
244 /* Enable FIFO, set half level for TX */
245 mr0 |= MR0_FIFO | MR0_TXLVL;
247 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR0);
248 sccnxp_port_write(port, SCCNXP_MR_REG, mr0);
251 sccnxp_port_write(port, SCCNXP_ACR_REG, acr | ACR_TIMER_MODE);
252 sccnxp_port_write(port, SCCNXP_CSR_REG, (csr << 4) | csr);
254 if (baud != bestbaud)
255 dev_dbg(port->dev, "Baudrate desired: %i, calculated: %i\n",
261 static void sccnxp_enable_irq(struct uart_port *port, int mask)
263 struct sccnxp_port *s = dev_get_drvdata(port->dev);
265 s->imr |= mask << (port->line * 4);
266 sccnxp_write(port, SCCNXP_IMR_REG, s->imr);
269 static void sccnxp_disable_irq(struct uart_port *port, int mask)
271 struct sccnxp_port *s = dev_get_drvdata(port->dev);
273 s->imr &= ~(mask << (port->line * 4));
274 sccnxp_write(port, SCCNXP_IMR_REG, s->imr);
277 static void sccnxp_set_bit(struct uart_port *port, int sig, int state)
280 struct sccnxp_port *s = dev_get_drvdata(port->dev);
282 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(sig)) {
283 bitmask = 1 << MCTRL_OBIT(s->pdata.mctrl_cfg[port->line], sig);
285 sccnxp_write(port, SCCNXP_SOP_REG, bitmask);
287 sccnxp_write(port, SCCNXP_ROP_REG, bitmask);
291 static void sccnxp_handle_rx(struct uart_port *port)
294 unsigned int ch, flag;
297 sr = sccnxp_port_read(port, SCCNXP_SR_REG);
298 if (!(sr & SR_RXRDY))
300 sr &= SR_PE | SR_FE | SR_OVR | SR_BRK;
302 ch = sccnxp_port_read(port, SCCNXP_RHR_REG);
310 sccnxp_port_write(port, SCCNXP_CR_REG,
312 if (uart_handle_break(port))
314 } else if (sr & SR_PE)
315 port->icount.parity++;
317 port->icount.frame++;
318 else if (sr & SR_OVR) {
319 port->icount.overrun++;
320 sccnxp_port_write(port, SCCNXP_CR_REG,
321 CR_CMD_STATUS_RESET);
324 sr &= port->read_status_mask;
331 else if (sr & SR_OVR)
335 if (uart_handle_sysrq_char(port, ch))
338 if (sr & port->ignore_status_mask)
341 uart_insert_char(port, sr, SR_OVR, ch, flag);
344 tty_flip_buffer_push(&port->state->port);
347 static void sccnxp_handle_tx(struct uart_port *port)
350 struct circ_buf *xmit = &port->state->xmit;
351 struct sccnxp_port *s = dev_get_drvdata(port->dev);
353 if (unlikely(port->x_char)) {
354 sccnxp_port_write(port, SCCNXP_THR_REG, port->x_char);
360 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
361 /* Disable TX if FIFO is empty */
362 if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXEMT) {
363 sccnxp_disable_irq(port, IMR_TXRDY);
365 /* Set direction to input */
366 if (s->flags & SCCNXP_HAVE_IO)
367 sccnxp_set_bit(port, DIR_OP, 0);
372 while (!uart_circ_empty(xmit)) {
373 sr = sccnxp_port_read(port, SCCNXP_SR_REG);
374 if (!(sr & SR_TXRDY))
377 sccnxp_port_write(port, SCCNXP_THR_REG, xmit->buf[xmit->tail]);
378 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
382 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
383 uart_write_wakeup(port);
386 static void sccnxp_handle_events(struct sccnxp_port *s)
392 isr = sccnxp_read(&s->port[0], SCCNXP_ISR_REG);
397 for (i = 0; i < s->uart.nr; i++) {
398 if (s->opened[i] && (isr & ISR_RXRDY(i)))
399 sccnxp_handle_rx(&s->port[i]);
400 if (s->opened[i] && (isr & ISR_TXRDY(i)))
401 sccnxp_handle_tx(&s->port[i]);
406 static void sccnxp_timer(unsigned long data)
408 struct sccnxp_port *s = (struct sccnxp_port *)data;
411 spin_lock_irqsave(&s->lock, flags);
412 sccnxp_handle_events(s);
413 spin_unlock_irqrestore(&s->lock, flags);
415 if (!timer_pending(&s->timer))
416 mod_timer(&s->timer, jiffies +
417 usecs_to_jiffies(s->pdata.poll_time_us));
420 static irqreturn_t sccnxp_ist(int irq, void *dev_id)
422 struct sccnxp_port *s = (struct sccnxp_port *)dev_id;
425 spin_lock_irqsave(&s->lock, flags);
426 sccnxp_handle_events(s);
427 spin_unlock_irqrestore(&s->lock, flags);
432 static void sccnxp_start_tx(struct uart_port *port)
434 struct sccnxp_port *s = dev_get_drvdata(port->dev);
437 spin_lock_irqsave(&s->lock, flags);
439 /* Set direction to output */
440 if (s->flags & SCCNXP_HAVE_IO)
441 sccnxp_set_bit(port, DIR_OP, 1);
443 sccnxp_enable_irq(port, IMR_TXRDY);
445 spin_unlock_irqrestore(&s->lock, flags);
448 static void sccnxp_stop_tx(struct uart_port *port)
453 static void sccnxp_stop_rx(struct uart_port *port)
455 struct sccnxp_port *s = dev_get_drvdata(port->dev);
458 spin_lock_irqsave(&s->lock, flags);
459 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE);
460 spin_unlock_irqrestore(&s->lock, flags);
463 static unsigned int sccnxp_tx_empty(struct uart_port *port)
467 struct sccnxp_port *s = dev_get_drvdata(port->dev);
469 spin_lock_irqsave(&s->lock, flags);
470 val = sccnxp_port_read(port, SCCNXP_SR_REG);
471 spin_unlock_irqrestore(&s->lock, flags);
473 return (val & SR_TXEMT) ? TIOCSER_TEMT : 0;
476 static void sccnxp_enable_ms(struct uart_port *port)
481 static void sccnxp_set_mctrl(struct uart_port *port, unsigned int mctrl)
483 struct sccnxp_port *s = dev_get_drvdata(port->dev);
486 if (!(s->flags & SCCNXP_HAVE_IO))
489 spin_lock_irqsave(&s->lock, flags);
491 sccnxp_set_bit(port, DTR_OP, mctrl & TIOCM_DTR);
492 sccnxp_set_bit(port, RTS_OP, mctrl & TIOCM_RTS);
494 spin_unlock_irqrestore(&s->lock, flags);
497 static unsigned int sccnxp_get_mctrl(struct uart_port *port)
501 struct sccnxp_port *s = dev_get_drvdata(port->dev);
502 unsigned int mctrl = TIOCM_DSR | TIOCM_CTS | TIOCM_CAR;
504 if (!(s->flags & SCCNXP_HAVE_IO))
507 spin_lock_irqsave(&s->lock, flags);
509 ipr = ~sccnxp_read(port, SCCNXP_IPCR_REG);
511 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DSR_IP)) {
512 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
515 mctrl |= (ipr & bitmask) ? TIOCM_DSR : 0;
517 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(CTS_IP)) {
518 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
521 mctrl |= (ipr & bitmask) ? TIOCM_CTS : 0;
523 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DCD_IP)) {
524 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
527 mctrl |= (ipr & bitmask) ? TIOCM_CAR : 0;
529 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(RNG_IP)) {
530 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
533 mctrl |= (ipr & bitmask) ? TIOCM_RNG : 0;
536 spin_unlock_irqrestore(&s->lock, flags);
541 static void sccnxp_break_ctl(struct uart_port *port, int break_state)
543 struct sccnxp_port *s = dev_get_drvdata(port->dev);
546 spin_lock_irqsave(&s->lock, flags);
547 sccnxp_port_write(port, SCCNXP_CR_REG, break_state ?
548 CR_CMD_START_BREAK : CR_CMD_STOP_BREAK);
549 spin_unlock_irqrestore(&s->lock, flags);
552 static void sccnxp_set_termios(struct uart_port *port,
553 struct ktermios *termios, struct ktermios *old)
555 struct sccnxp_port *s = dev_get_drvdata(port->dev);
560 spin_lock_irqsave(&s->lock, flags);
562 /* Mask termios capabilities we don't support */
563 termios->c_cflag &= ~CMSPAR;
565 /* Disable RX & TX, reset break condition, status and FIFOs */
566 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET |
567 CR_RX_DISABLE | CR_TX_DISABLE);
568 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET);
569 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET);
570 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET);
573 switch (termios->c_cflag & CSIZE) {
590 if (termios->c_cflag & PARENB) {
591 if (termios->c_cflag & PARODD)
597 mr2 = (termios->c_cflag & CSTOPB) ? MR2_STOP2 : MR2_STOP1;
599 /* Update desired format */
600 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR1);
601 sccnxp_port_write(port, SCCNXP_MR_REG, mr1);
602 sccnxp_port_write(port, SCCNXP_MR_REG, mr2);
604 /* Set read status mask */
605 port->read_status_mask = SR_OVR;
606 if (termios->c_iflag & INPCK)
607 port->read_status_mask |= SR_PE | SR_FE;
608 if (termios->c_iflag & (BRKINT | PARMRK))
609 port->read_status_mask |= SR_BRK;
611 /* Set status ignore mask */
612 port->ignore_status_mask = 0;
613 if (termios->c_iflag & IGNBRK)
614 port->ignore_status_mask |= SR_BRK;
615 if (!(termios->c_cflag & CREAD))
616 port->ignore_status_mask |= SR_PE | SR_OVR | SR_FE | SR_BRK;
619 baud = uart_get_baud_rate(port, termios, old, 50,
620 (s->flags & SCCNXP_HAVE_MR0) ?
622 baud = sccnxp_set_baud(port, baud);
624 /* Update timeout according to new baud rate */
625 uart_update_timeout(port, termios->c_cflag, baud);
627 /* Report actual baudrate back to core */
628 if (tty_termios_baud_rate(termios))
629 tty_termios_encode_baud_rate(termios, baud, baud);
632 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE);
634 spin_unlock_irqrestore(&s->lock, flags);
637 static int sccnxp_startup(struct uart_port *port)
639 struct sccnxp_port *s = dev_get_drvdata(port->dev);
642 spin_lock_irqsave(&s->lock, flags);
644 if (s->flags & SCCNXP_HAVE_IO) {
645 /* Outputs are controlled manually */
646 sccnxp_write(port, SCCNXP_OPCR_REG, 0);
649 /* Reset break condition, status and FIFOs */
650 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET);
651 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET);
652 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET);
653 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET);
656 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE);
658 /* Enable RX interrupt */
659 sccnxp_enable_irq(port, IMR_RXRDY);
661 s->opened[port->line] = 1;
663 spin_unlock_irqrestore(&s->lock, flags);
668 static void sccnxp_shutdown(struct uart_port *port)
670 struct sccnxp_port *s = dev_get_drvdata(port->dev);
673 spin_lock_irqsave(&s->lock, flags);
675 s->opened[port->line] = 0;
677 /* Disable interrupts */
678 sccnxp_disable_irq(port, IMR_TXRDY | IMR_RXRDY);
680 /* Disable TX & RX */
681 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE | CR_TX_DISABLE);
683 /* Leave direction to input */
684 if (s->flags & SCCNXP_HAVE_IO)
685 sccnxp_set_bit(port, DIR_OP, 0);
687 spin_unlock_irqrestore(&s->lock, flags);
690 static const char *sccnxp_type(struct uart_port *port)
692 struct sccnxp_port *s = dev_get_drvdata(port->dev);
694 return (port->type == PORT_SC26XX) ? s->name : NULL;
697 static void sccnxp_release_port(struct uart_port *port)
702 static int sccnxp_request_port(struct uart_port *port)
708 static void sccnxp_config_port(struct uart_port *port, int flags)
710 if (flags & UART_CONFIG_TYPE)
711 port->type = PORT_SC26XX;
714 static int sccnxp_verify_port(struct uart_port *port, struct serial_struct *s)
716 if ((s->type == PORT_UNKNOWN) || (s->type == PORT_SC26XX))
718 if (s->irq == port->irq)
724 static const struct uart_ops sccnxp_ops = {
725 .tx_empty = sccnxp_tx_empty,
726 .set_mctrl = sccnxp_set_mctrl,
727 .get_mctrl = sccnxp_get_mctrl,
728 .stop_tx = sccnxp_stop_tx,
729 .start_tx = sccnxp_start_tx,
730 .stop_rx = sccnxp_stop_rx,
731 .enable_ms = sccnxp_enable_ms,
732 .break_ctl = sccnxp_break_ctl,
733 .startup = sccnxp_startup,
734 .shutdown = sccnxp_shutdown,
735 .set_termios = sccnxp_set_termios,
737 .release_port = sccnxp_release_port,
738 .request_port = sccnxp_request_port,
739 .config_port = sccnxp_config_port,
740 .verify_port = sccnxp_verify_port,
743 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
744 static void sccnxp_console_putchar(struct uart_port *port, int c)
749 if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXRDY) {
750 sccnxp_port_write(port, SCCNXP_THR_REG, c);
757 static void sccnxp_console_write(struct console *co, const char *c, unsigned n)
759 struct sccnxp_port *s = (struct sccnxp_port *)co->data;
760 struct uart_port *port = &s->port[co->index];
763 spin_lock_irqsave(&s->lock, flags);
764 uart_console_write(port, c, n, sccnxp_console_putchar);
765 spin_unlock_irqrestore(&s->lock, flags);
768 static int sccnxp_console_setup(struct console *co, char *options)
770 struct sccnxp_port *s = (struct sccnxp_port *)co->data;
771 struct uart_port *port = &s->port[(co->index > 0) ? co->index : 0];
772 int baud = 9600, bits = 8, parity = 'n', flow = 'n';
775 uart_parse_options(options, &baud, &parity, &bits, &flow);
777 return uart_set_options(port, co, baud, parity, bits, flow);
781 static int sccnxp_probe(struct platform_device *pdev)
783 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
784 int chiptype = pdev->id_entry->driver_data;
785 struct sccnxp_pdata *pdata = dev_get_platdata(&pdev->dev);
786 int i, ret, fifosize, freq_min, freq_max;
787 struct sccnxp_port *s;
788 void __iomem *membase;
791 dev_err(&pdev->dev, "Missing memory resource data\n");
792 return -EADDRNOTAVAIL;
795 s = devm_kzalloc(&pdev->dev, sizeof(struct sccnxp_port), GFP_KERNEL);
797 dev_err(&pdev->dev, "Error allocating port structure\n");
800 platform_set_drvdata(pdev, s);
802 spin_lock_init(&s->lock);
804 /* Individual chip settings */
806 case SCCNXP_TYPE_SC2681:
809 s->freq_std = 3686400;
811 s->flags = SCCNXP_HAVE_IO;
816 case SCCNXP_TYPE_SC2691:
819 s->freq_std = 3686400;
826 case SCCNXP_TYPE_SC2692:
829 s->freq_std = 3686400;
831 s->flags = SCCNXP_HAVE_IO;
836 case SCCNXP_TYPE_SC2891:
839 s->freq_std = 3686400;
841 s->flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0;
846 case SCCNXP_TYPE_SC2892:
849 s->freq_std = 3686400;
851 s->flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0;
856 case SCCNXP_TYPE_SC28202:
859 s->freq_std = 14745600;
861 s->flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0;
866 case SCCNXP_TYPE_SC68681:
869 s->freq_std = 3686400;
871 s->flags = SCCNXP_HAVE_IO;
876 case SCCNXP_TYPE_SC68692:
879 s->freq_std = 3686400;
881 s->flags = SCCNXP_HAVE_IO;
887 dev_err(&pdev->dev, "Unsupported chip type %i\n", chiptype);
894 "No platform data supplied, using defaults\n");
895 s->pdata.frequency = s->freq_std;
897 memcpy(&s->pdata, pdata, sizeof(struct sccnxp_pdata));
899 if (s->pdata.poll_time_us) {
900 dev_info(&pdev->dev, "Using poll mode, resolution %u usecs\n",
901 s->pdata.poll_time_us);
906 s->irq = platform_get_irq(pdev, 0);
908 dev_err(&pdev->dev, "Missing irq resource data\n");
914 /* Check input frequency */
915 if ((s->pdata.frequency < freq_min) ||
916 (s->pdata.frequency > freq_max)) {
917 dev_err(&pdev->dev, "Frequency out of bounds\n");
922 s->regulator = devm_regulator_get(&pdev->dev, "VCC");
923 if (!IS_ERR(s->regulator)) {
924 ret = regulator_enable(s->regulator);
927 "Failed to enable regulator: %i\n", ret);
932 membase = devm_ioremap_resource(&pdev->dev, res);
933 if (IS_ERR(membase)) {
934 ret = PTR_ERR(membase);
938 s->uart.owner = THIS_MODULE;
939 s->uart.dev_name = "ttySC";
940 s->uart.major = SCCNXP_MAJOR;
941 s->uart.minor = SCCNXP_MINOR;
942 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
943 s->uart.cons = &s->console;
944 s->uart.cons->device = uart_console_device;
945 s->uart.cons->write = sccnxp_console_write;
946 s->uart.cons->setup = sccnxp_console_setup;
947 s->uart.cons->flags = CON_PRINTBUFFER;
948 s->uart.cons->index = -1;
949 s->uart.cons->data = s;
950 strcpy(s->uart.cons->name, "ttySC");
952 ret = uart_register_driver(&s->uart);
954 dev_err(&pdev->dev, "Registering UART driver failed\n");
958 for (i = 0; i < s->uart.nr; i++) {
960 s->port[i].dev = &pdev->dev;
961 s->port[i].irq = s->irq;
962 s->port[i].type = PORT_SC26XX;
963 s->port[i].fifosize = fifosize;
964 s->port[i].flags = UPF_SKIP_TEST | UPF_FIXED_TYPE;
965 s->port[i].iotype = UPIO_MEM;
966 s->port[i].mapbase = res->start;
967 s->port[i].membase = membase;
968 s->port[i].regshift = s->pdata.reg_shift;
969 s->port[i].uartclk = s->pdata.frequency;
970 s->port[i].ops = &sccnxp_ops;
971 uart_add_one_port(&s->uart, &s->port[i]);
972 /* Set direction to input */
973 if (s->flags & SCCNXP_HAVE_IO)
974 sccnxp_set_bit(&s->port[i], DIR_OP, 0);
977 /* Disable interrupts */
979 sccnxp_write(&s->port[0], SCCNXP_IMR_REG, 0);
982 ret = devm_request_threaded_irq(&pdev->dev, s->irq, NULL,
984 IRQF_TRIGGER_FALLING |
986 dev_name(&pdev->dev), s);
990 dev_err(&pdev->dev, "Unable to reguest IRQ %i\n", s->irq);
992 init_timer(&s->timer);
993 setup_timer(&s->timer, sccnxp_timer, (unsigned long)s);
994 mod_timer(&s->timer, jiffies +
995 usecs_to_jiffies(s->pdata.poll_time_us));
1000 platform_set_drvdata(pdev, NULL);
1005 static int sccnxp_remove(struct platform_device *pdev)
1008 struct sccnxp_port *s = platform_get_drvdata(pdev);
1011 devm_free_irq(&pdev->dev, s->irq, s);
1013 del_timer_sync(&s->timer);
1015 for (i = 0; i < s->uart.nr; i++)
1016 uart_remove_one_port(&s->uart, &s->port[i]);
1018 uart_unregister_driver(&s->uart);
1019 platform_set_drvdata(pdev, NULL);
1021 if (!IS_ERR(s->regulator))
1022 return regulator_disable(s->regulator);
1027 static const struct platform_device_id sccnxp_id_table[] = {
1028 { "sc2681", SCCNXP_TYPE_SC2681 },
1029 { "sc2691", SCCNXP_TYPE_SC2691 },
1030 { "sc2692", SCCNXP_TYPE_SC2692 },
1031 { "sc2891", SCCNXP_TYPE_SC2891 },
1032 { "sc2892", SCCNXP_TYPE_SC2892 },
1033 { "sc28202", SCCNXP_TYPE_SC28202 },
1034 { "sc68681", SCCNXP_TYPE_SC68681 },
1035 { "sc68692", SCCNXP_TYPE_SC68692 },
1038 MODULE_DEVICE_TABLE(platform, sccnxp_id_table);
1040 static struct platform_driver sccnxp_uart_driver = {
1042 .name = SCCNXP_NAME,
1043 .owner = THIS_MODULE,
1045 .probe = sccnxp_probe,
1046 .remove = sccnxp_remove,
1047 .id_table = sccnxp_id_table,
1049 module_platform_driver(sccnxp_uart_driver);
1051 MODULE_LICENSE("GPL v2");
1052 MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
1053 MODULE_DESCRIPTION("SCCNXP serial driver");