2 * NXP (Philips) SCC+++(SCN+++) serial driver
4 * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
6 * Based on sc26xx.c, by Thomas Bogendörfer (tsbogend@alpha.franken.de)
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
18 #include <linux/module.h>
19 #include <linux/device.h>
20 #include <linux/console.h>
21 #include <linux/serial_core.h>
22 #include <linux/serial.h>
24 #include <linux/tty.h>
25 #include <linux/tty_flip.h>
26 #include <linux/platform_device.h>
27 #include <linux/platform_data/sccnxp.h>
29 #define SCCNXP_NAME "uart-sccnxp"
30 #define SCCNXP_MAJOR 204
31 #define SCCNXP_MINOR 205
33 #define SCCNXP_MR_REG (0x00)
34 # define MR0_BAUD_NORMAL (0 << 0)
35 # define MR0_BAUD_EXT1 (1 << 0)
36 # define MR0_BAUD_EXT2 (5 << 0)
37 # define MR0_FIFO (1 << 3)
38 # define MR0_TXLVL (1 << 4)
39 # define MR1_BITS_5 (0 << 0)
40 # define MR1_BITS_6 (1 << 0)
41 # define MR1_BITS_7 (2 << 0)
42 # define MR1_BITS_8 (3 << 0)
43 # define MR1_PAR_EVN (0 << 2)
44 # define MR1_PAR_ODD (1 << 2)
45 # define MR1_PAR_NO (4 << 2)
46 # define MR2_STOP1 (7 << 0)
47 # define MR2_STOP2 (0xf << 0)
48 #define SCCNXP_SR_REG (0x01)
49 #define SCCNXP_CSR_REG SCCNXP_SR_REG
50 # define SR_RXRDY (1 << 0)
51 # define SR_FULL (1 << 1)
52 # define SR_TXRDY (1 << 2)
53 # define SR_TXEMT (1 << 3)
54 # define SR_OVR (1 << 4)
55 # define SR_PE (1 << 5)
56 # define SR_FE (1 << 6)
57 # define SR_BRK (1 << 7)
58 #define SCCNXP_CR_REG (0x02)
59 # define CR_RX_ENABLE (1 << 0)
60 # define CR_RX_DISABLE (1 << 1)
61 # define CR_TX_ENABLE (1 << 2)
62 # define CR_TX_DISABLE (1 << 3)
63 # define CR_CMD_MRPTR1 (0x01 << 4)
64 # define CR_CMD_RX_RESET (0x02 << 4)
65 # define CR_CMD_TX_RESET (0x03 << 4)
66 # define CR_CMD_STATUS_RESET (0x04 << 4)
67 # define CR_CMD_BREAK_RESET (0x05 << 4)
68 # define CR_CMD_START_BREAK (0x06 << 4)
69 # define CR_CMD_STOP_BREAK (0x07 << 4)
70 # define CR_CMD_MRPTR0 (0x0b << 4)
71 #define SCCNXP_RHR_REG (0x03)
72 #define SCCNXP_THR_REG SCCNXP_RHR_REG
73 #define SCCNXP_IPCR_REG (0x04)
74 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
75 # define ACR_BAUD0 (0 << 7)
76 # define ACR_BAUD1 (1 << 7)
77 # define ACR_TIMER_MODE (6 << 4)
78 #define SCCNXP_ISR_REG (0x05)
79 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
80 # define IMR_TXRDY (1 << 0)
81 # define IMR_RXRDY (1 << 1)
82 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
83 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
84 #define SCCNXP_IPR_REG (0x0d)
85 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
86 #define SCCNXP_SOP_REG (0x0e)
87 #define SCCNXP_ROP_REG (0x0f)
90 #define MCTRL_MASK(sig) (0xf << (sig))
91 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
92 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
94 /* Supported chip types */
96 SCCNXP_TYPE_SC2681 = 2681,
97 SCCNXP_TYPE_SC2691 = 2691,
98 SCCNXP_TYPE_SC2692 = 2692,
99 SCCNXP_TYPE_SC2891 = 2891,
100 SCCNXP_TYPE_SC2892 = 2892,
101 SCCNXP_TYPE_SC28202 = 28202,
102 SCCNXP_TYPE_SC68681 = 68681,
103 SCCNXP_TYPE_SC68692 = 68692,
107 struct uart_driver uart;
108 struct uart_port port[SCCNXP_MAX_UARTS];
118 #define SCCNXP_HAVE_IO 0x00000001
119 #define SCCNXP_HAVE_MR0 0x00000002
121 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
122 struct console console;
125 struct mutex sccnxp_mutex;
127 struct sccnxp_pdata pdata;
130 static inline u8 sccnxp_raw_read(void __iomem *base, u8 reg, u8 shift)
132 return readb(base + (reg << shift));
135 static inline void sccnxp_raw_write(void __iomem *base, u8 reg, u8 shift, u8 v)
137 writeb(v, base + (reg << shift));
140 static inline u8 sccnxp_read(struct uart_port *port, u8 reg)
142 struct sccnxp_port *s = dev_get_drvdata(port->dev);
144 return sccnxp_raw_read(port->membase, reg & s->addr_mask,
148 static inline void sccnxp_write(struct uart_port *port, u8 reg, u8 v)
150 struct sccnxp_port *s = dev_get_drvdata(port->dev);
152 sccnxp_raw_write(port->membase, reg & s->addr_mask, port->regshift, v);
155 static inline u8 sccnxp_port_read(struct uart_port *port, u8 reg)
157 return sccnxp_read(port, (port->line << 3) + reg);
160 static inline void sccnxp_port_write(struct uart_port *port, u8 reg, u8 v)
162 sccnxp_write(port, (port->line << 3) + reg, v);
165 static int sccnxp_update_best_err(int a, int b, int *besterr)
167 int err = abs(a - b);
169 if ((*besterr < 0) || (*besterr > err)) {
184 const struct baud_table baud_std[] = {
185 { 0, ACR_BAUD0, MR0_BAUD_NORMAL, 50, },
186 { 0, ACR_BAUD1, MR0_BAUD_NORMAL, 75, },
187 { 1, ACR_BAUD0, MR0_BAUD_NORMAL, 110, },
188 { 2, ACR_BAUD0, MR0_BAUD_NORMAL, 134, },
189 { 3, ACR_BAUD1, MR0_BAUD_NORMAL, 150, },
190 { 3, ACR_BAUD0, MR0_BAUD_NORMAL, 200, },
191 { 4, ACR_BAUD0, MR0_BAUD_NORMAL, 300, },
192 { 0, ACR_BAUD1, MR0_BAUD_EXT1, 450, },
193 { 1, ACR_BAUD0, MR0_BAUD_EXT2, 880, },
194 { 3, ACR_BAUD1, MR0_BAUD_EXT1, 900, },
195 { 5, ACR_BAUD0, MR0_BAUD_NORMAL, 600, },
196 { 7, ACR_BAUD0, MR0_BAUD_NORMAL, 1050, },
197 { 2, ACR_BAUD0, MR0_BAUD_EXT2, 1076, },
198 { 6, ACR_BAUD0, MR0_BAUD_NORMAL, 1200, },
199 { 10, ACR_BAUD1, MR0_BAUD_NORMAL, 1800, },
200 { 7, ACR_BAUD1, MR0_BAUD_NORMAL, 2000, },
201 { 8, ACR_BAUD0, MR0_BAUD_NORMAL, 2400, },
202 { 5, ACR_BAUD1, MR0_BAUD_EXT1, 3600, },
203 { 9, ACR_BAUD0, MR0_BAUD_NORMAL, 4800, },
204 { 10, ACR_BAUD0, MR0_BAUD_NORMAL, 7200, },
205 { 11, ACR_BAUD0, MR0_BAUD_NORMAL, 9600, },
206 { 8, ACR_BAUD0, MR0_BAUD_EXT1, 14400, },
207 { 12, ACR_BAUD1, MR0_BAUD_NORMAL, 19200, },
208 { 9, ACR_BAUD0, MR0_BAUD_EXT1, 28800, },
209 { 12, ACR_BAUD0, MR0_BAUD_NORMAL, 38400, },
210 { 11, ACR_BAUD0, MR0_BAUD_EXT1, 57600, },
211 { 12, ACR_BAUD1, MR0_BAUD_EXT1, 115200, },
212 { 12, ACR_BAUD0, MR0_BAUD_EXT1, 230400, },
216 static int sccnxp_set_baud(struct uart_port *port, int baud)
218 struct sccnxp_port *s = dev_get_drvdata(port->dev);
219 int div_std, tmp_baud, bestbaud = baud, besterr = -1;
220 u8 i, acr = 0, csr = 0, mr0 = 0;
222 /* Find best baud from table */
223 for (i = 0; baud_std[i].baud && besterr; i++) {
224 if (baud_std[i].mr0 && !(s->flags & SCCNXP_HAVE_MR0))
226 div_std = DIV_ROUND_CLOSEST(s->freq_std, baud_std[i].baud);
227 tmp_baud = DIV_ROUND_CLOSEST(port->uartclk, div_std);
228 if (!sccnxp_update_best_err(baud, tmp_baud, &besterr)) {
229 acr = baud_std[i].acr;
230 csr = baud_std[i].csr;
231 mr0 = baud_std[i].mr0;
236 if (s->flags & SCCNXP_HAVE_MR0) {
237 /* Enable FIFO, set half level for TX */
238 mr0 |= MR0_FIFO | MR0_TXLVL;
240 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR0);
241 sccnxp_port_write(port, SCCNXP_MR_REG, mr0);
244 sccnxp_port_write(port, SCCNXP_ACR_REG, acr | ACR_TIMER_MODE);
245 sccnxp_port_write(port, SCCNXP_CSR_REG, (csr << 4) | csr);
247 if (baud != bestbaud)
248 dev_dbg(port->dev, "Baudrate desired: %i, calculated: %i\n",
254 static void sccnxp_enable_irq(struct uart_port *port, int mask)
256 struct sccnxp_port *s = dev_get_drvdata(port->dev);
258 s->imr |= mask << (port->line * 4);
259 sccnxp_write(port, SCCNXP_IMR_REG, s->imr);
262 static void sccnxp_disable_irq(struct uart_port *port, int mask)
264 struct sccnxp_port *s = dev_get_drvdata(port->dev);
266 s->imr &= ~(mask << (port->line * 4));
267 sccnxp_write(port, SCCNXP_IMR_REG, s->imr);
270 static void sccnxp_set_bit(struct uart_port *port, int sig, int state)
273 struct sccnxp_port *s = dev_get_drvdata(port->dev);
275 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(sig)) {
276 bitmask = 1 << MCTRL_OBIT(s->pdata.mctrl_cfg[port->line], sig);
278 sccnxp_write(port, SCCNXP_SOP_REG, bitmask);
280 sccnxp_write(port, SCCNXP_ROP_REG, bitmask);
284 static void sccnxp_handle_rx(struct uart_port *port)
287 unsigned int ch, flag;
288 struct tty_struct *tty = tty_port_tty_get(&port->state->port);
294 sr = sccnxp_port_read(port, SCCNXP_SR_REG);
295 if (!(sr & SR_RXRDY))
297 sr &= SR_PE | SR_FE | SR_OVR | SR_BRK;
299 ch = sccnxp_port_read(port, SCCNXP_RHR_REG);
307 if (uart_handle_break(port))
309 } else if (sr & SR_PE)
310 port->icount.parity++;
312 port->icount.frame++;
313 else if (sr & SR_OVR)
314 port->icount.overrun++;
316 sr &= port->read_status_mask;
323 else if (sr & SR_OVR)
327 if (uart_handle_sysrq_char(port, ch))
330 if (sr & port->ignore_status_mask)
333 uart_insert_char(port, sr, SR_OVR, ch, flag);
336 tty_flip_buffer_push(tty);
341 static void sccnxp_handle_tx(struct uart_port *port)
344 struct circ_buf *xmit = &port->state->xmit;
345 struct sccnxp_port *s = dev_get_drvdata(port->dev);
347 if (unlikely(port->x_char)) {
348 sccnxp_port_write(port, SCCNXP_THR_REG, port->x_char);
354 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
355 /* Disable TX if FIFO is empty */
356 if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXEMT) {
357 sccnxp_disable_irq(port, IMR_TXRDY);
359 /* Set direction to input */
360 if (s->flags & SCCNXP_HAVE_IO)
361 sccnxp_set_bit(port, DIR_OP, 0);
366 while (!uart_circ_empty(xmit)) {
367 sr = sccnxp_port_read(port, SCCNXP_SR_REG);
368 if (!(sr & SR_TXRDY))
371 sccnxp_port_write(port, SCCNXP_THR_REG, xmit->buf[xmit->tail]);
372 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
376 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
377 uart_write_wakeup(port);
380 static irqreturn_t sccnxp_ist(int irq, void *dev_id)
384 struct sccnxp_port *s = (struct sccnxp_port *)dev_id;
386 mutex_lock(&s->sccnxp_mutex);
389 isr = sccnxp_read(&s->port[0], SCCNXP_ISR_REG);
394 dev_dbg(s->port[0].dev, "IRQ status: 0x%02x\n", isr);
396 for (i = 0; i < s->uart.nr; i++) {
397 if (isr & ISR_RXRDY(i))
398 sccnxp_handle_rx(&s->port[i]);
399 if (isr & ISR_TXRDY(i))
400 sccnxp_handle_tx(&s->port[i]);
404 mutex_unlock(&s->sccnxp_mutex);
409 static void sccnxp_start_tx(struct uart_port *port)
411 struct sccnxp_port *s = dev_get_drvdata(port->dev);
413 mutex_lock(&s->sccnxp_mutex);
415 /* Set direction to output */
416 if (s->flags & SCCNXP_HAVE_IO)
417 sccnxp_set_bit(port, DIR_OP, 1);
419 sccnxp_enable_irq(port, IMR_TXRDY);
421 mutex_unlock(&s->sccnxp_mutex);
424 static void sccnxp_stop_tx(struct uart_port *port)
429 static void sccnxp_stop_rx(struct uart_port *port)
431 struct sccnxp_port *s = dev_get_drvdata(port->dev);
433 mutex_lock(&s->sccnxp_mutex);
434 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE);
435 mutex_unlock(&s->sccnxp_mutex);
438 static unsigned int sccnxp_tx_empty(struct uart_port *port)
441 struct sccnxp_port *s = dev_get_drvdata(port->dev);
443 mutex_lock(&s->sccnxp_mutex);
444 val = sccnxp_port_read(port, SCCNXP_SR_REG);
445 mutex_unlock(&s->sccnxp_mutex);
447 return (val & SR_TXEMT) ? TIOCSER_TEMT : 0;
450 static void sccnxp_enable_ms(struct uart_port *port)
455 static void sccnxp_set_mctrl(struct uart_port *port, unsigned int mctrl)
457 struct sccnxp_port *s = dev_get_drvdata(port->dev);
459 if (!(s->flags & SCCNXP_HAVE_IO))
462 mutex_lock(&s->sccnxp_mutex);
464 sccnxp_set_bit(port, DTR_OP, mctrl & TIOCM_DTR);
465 sccnxp_set_bit(port, RTS_OP, mctrl & TIOCM_RTS);
467 mutex_unlock(&s->sccnxp_mutex);
470 static unsigned int sccnxp_get_mctrl(struct uart_port *port)
473 struct sccnxp_port *s = dev_get_drvdata(port->dev);
474 unsigned int mctrl = TIOCM_DSR | TIOCM_CTS | TIOCM_CAR;
476 if (!(s->flags & SCCNXP_HAVE_IO))
479 mutex_lock(&s->sccnxp_mutex);
481 ipr = ~sccnxp_read(port, SCCNXP_IPCR_REG);
483 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DSR_IP)) {
484 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
487 mctrl |= (ipr & bitmask) ? TIOCM_DSR : 0;
489 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(CTS_IP)) {
490 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
493 mctrl |= (ipr & bitmask) ? TIOCM_CTS : 0;
495 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DCD_IP)) {
496 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
499 mctrl |= (ipr & bitmask) ? TIOCM_CAR : 0;
501 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(RNG_IP)) {
502 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
505 mctrl |= (ipr & bitmask) ? TIOCM_RNG : 0;
508 mutex_unlock(&s->sccnxp_mutex);
513 static void sccnxp_break_ctl(struct uart_port *port, int break_state)
515 struct sccnxp_port *s = dev_get_drvdata(port->dev);
517 mutex_lock(&s->sccnxp_mutex);
518 sccnxp_port_write(port, SCCNXP_CR_REG, break_state ?
519 CR_CMD_START_BREAK : CR_CMD_STOP_BREAK);
520 mutex_unlock(&s->sccnxp_mutex);
523 static void sccnxp_set_termios(struct uart_port *port,
524 struct ktermios *termios, struct ktermios *old)
526 struct sccnxp_port *s = dev_get_drvdata(port->dev);
530 mutex_lock(&s->sccnxp_mutex);
532 /* Mask termios capabilities we don't support */
533 termios->c_cflag &= ~CMSPAR;
535 /* Disable RX & TX, reset break condition, status and FIFOs */
536 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET |
537 CR_RX_DISABLE | CR_TX_DISABLE);
538 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET);
539 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET);
540 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET);
543 switch (termios->c_cflag & CSIZE) {
560 if (termios->c_cflag & PARENB) {
561 if (termios->c_cflag & PARODD)
567 mr2 = (termios->c_cflag & CSTOPB) ? MR2_STOP2 : MR2_STOP1;
569 /* Update desired format */
570 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR1);
571 sccnxp_port_write(port, SCCNXP_MR_REG, mr1);
572 sccnxp_port_write(port, SCCNXP_MR_REG, mr2);
574 /* Set read status mask */
575 port->read_status_mask = SR_OVR;
576 if (termios->c_iflag & INPCK)
577 port->read_status_mask |= SR_PE | SR_FE;
578 if (termios->c_iflag & (BRKINT | PARMRK))
579 port->read_status_mask |= SR_BRK;
581 /* Set status ignore mask */
582 port->ignore_status_mask = 0;
583 if (termios->c_iflag & IGNBRK)
584 port->ignore_status_mask |= SR_BRK;
585 if (!(termios->c_cflag & CREAD))
586 port->ignore_status_mask |= SR_PE | SR_OVR | SR_FE | SR_BRK;
589 baud = uart_get_baud_rate(port, termios, old, 50,
590 (s->flags & SCCNXP_HAVE_MR0) ?
592 baud = sccnxp_set_baud(port, baud);
594 /* Update timeout according to new baud rate */
595 uart_update_timeout(port, termios->c_cflag, baud);
597 if (tty_termios_baud_rate(termios))
598 tty_termios_encode_baud_rate(termios, baud, baud);
601 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE);
603 mutex_unlock(&s->sccnxp_mutex);
606 static int sccnxp_startup(struct uart_port *port)
608 struct sccnxp_port *s = dev_get_drvdata(port->dev);
610 mutex_lock(&s->sccnxp_mutex);
612 if (s->flags & SCCNXP_HAVE_IO) {
613 /* Outputs are controlled manually */
614 sccnxp_write(port, SCCNXP_OPCR_REG, 0);
617 /* Reset break condition, status and FIFOs */
618 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET);
619 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET);
620 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET);
621 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET);
624 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE);
626 /* Enable RX interrupt */
627 sccnxp_enable_irq(port, IMR_RXRDY);
629 mutex_unlock(&s->sccnxp_mutex);
634 static void sccnxp_shutdown(struct uart_port *port)
636 struct sccnxp_port *s = dev_get_drvdata(port->dev);
638 mutex_lock(&s->sccnxp_mutex);
640 /* Disable interrupts */
641 sccnxp_disable_irq(port, IMR_TXRDY | IMR_RXRDY);
643 /* Disable TX & RX */
644 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE | CR_TX_DISABLE);
646 /* Leave direction to input */
647 if (s->flags & SCCNXP_HAVE_IO)
648 sccnxp_set_bit(port, DIR_OP, 0);
650 mutex_unlock(&s->sccnxp_mutex);
653 static const char *sccnxp_type(struct uart_port *port)
655 struct sccnxp_port *s = dev_get_drvdata(port->dev);
657 return (port->type == PORT_SC26XX) ? s->name : NULL;
660 static void sccnxp_release_port(struct uart_port *port)
665 static int sccnxp_request_port(struct uart_port *port)
671 static void sccnxp_config_port(struct uart_port *port, int flags)
673 if (flags & UART_CONFIG_TYPE)
674 port->type = PORT_SC26XX;
677 static int sccnxp_verify_port(struct uart_port *port, struct serial_struct *s)
679 if ((s->type == PORT_UNKNOWN) || (s->type == PORT_SC26XX))
681 if (s->irq == port->irq)
687 static const struct uart_ops sccnxp_ops = {
688 .tx_empty = sccnxp_tx_empty,
689 .set_mctrl = sccnxp_set_mctrl,
690 .get_mctrl = sccnxp_get_mctrl,
691 .stop_tx = sccnxp_stop_tx,
692 .start_tx = sccnxp_start_tx,
693 .stop_rx = sccnxp_stop_rx,
694 .enable_ms = sccnxp_enable_ms,
695 .break_ctl = sccnxp_break_ctl,
696 .startup = sccnxp_startup,
697 .shutdown = sccnxp_shutdown,
698 .set_termios = sccnxp_set_termios,
700 .release_port = sccnxp_release_port,
701 .request_port = sccnxp_request_port,
702 .config_port = sccnxp_config_port,
703 .verify_port = sccnxp_verify_port,
706 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
707 static void sccnxp_console_putchar(struct uart_port *port, int c)
712 if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXRDY) {
713 sccnxp_port_write(port, SCCNXP_THR_REG, c);
720 static void sccnxp_console_write(struct console *co, const char *c, unsigned n)
722 struct sccnxp_port *s = (struct sccnxp_port *)co->data;
723 struct uart_port *port = &s->port[co->index];
725 mutex_lock(&s->sccnxp_mutex);
726 uart_console_write(port, c, n, sccnxp_console_putchar);
727 mutex_unlock(&s->sccnxp_mutex);
730 static int sccnxp_console_setup(struct console *co, char *options)
732 struct sccnxp_port *s = (struct sccnxp_port *)co->data;
733 struct uart_port *port = &s->port[(co->index > 0) ? co->index : 0];
734 int baud = 9600, bits = 8, parity = 'n', flow = 'n';
737 uart_parse_options(options, &baud, &parity, &bits, &flow);
739 return uart_set_options(port, co, baud, parity, bits, flow);
743 static int sccnxp_probe(struct platform_device *pdev)
745 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
746 int chiptype = pdev->id_entry->driver_data;
747 struct sccnxp_pdata *pdata = dev_get_platdata(&pdev->dev);
748 int i, ret, fifosize, freq_min, freq_max;
749 struct sccnxp_port *s;
750 void __iomem *membase;
753 dev_err(&pdev->dev, "Missing memory resource data\n");
754 return -EADDRNOTAVAIL;
757 dev_set_name(&pdev->dev, SCCNXP_NAME);
759 s = devm_kzalloc(&pdev->dev, sizeof(struct sccnxp_port), GFP_KERNEL);
761 dev_err(&pdev->dev, "Error allocating port structure\n");
764 platform_set_drvdata(pdev, s);
766 mutex_init(&s->sccnxp_mutex);
768 /* Individual chip settings */
770 case SCCNXP_TYPE_SC2681:
773 s->freq_std = 3686400;
775 s->flags = SCCNXP_HAVE_IO;
780 case SCCNXP_TYPE_SC2691:
783 s->freq_std = 3686400;
790 case SCCNXP_TYPE_SC2692:
793 s->freq_std = 3686400;
795 s->flags = SCCNXP_HAVE_IO;
800 case SCCNXP_TYPE_SC2891:
803 s->freq_std = 3686400;
805 s->flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0;
810 case SCCNXP_TYPE_SC2892:
813 s->freq_std = 3686400;
815 s->flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0;
820 case SCCNXP_TYPE_SC28202:
823 s->freq_std = 14745600;
825 s->flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0;
830 case SCCNXP_TYPE_SC68681:
833 s->freq_std = 3686400;
835 s->flags = SCCNXP_HAVE_IO;
840 case SCCNXP_TYPE_SC68692:
843 s->freq_std = 3686400;
845 s->flags = SCCNXP_HAVE_IO;
851 dev_err(&pdev->dev, "Unsupported chip type %i\n", chiptype);
858 "No platform data supplied, using defaults\n");
859 s->pdata.frequency = s->freq_std;
861 memcpy(&s->pdata, pdata, sizeof(struct sccnxp_pdata));
863 s->irq = platform_get_irq(pdev, 0);
865 dev_err(&pdev->dev, "Missing irq resource data\n");
870 /* Check input frequency */
871 if ((s->pdata.frequency < freq_min) ||
872 (s->pdata.frequency > freq_max)) {
873 dev_err(&pdev->dev, "Frequency out of bounds\n");
878 membase = devm_request_and_ioremap(&pdev->dev, res);
880 dev_err(&pdev->dev, "Failed to ioremap\n");
885 s->uart.owner = THIS_MODULE;
886 s->uart.dev_name = "ttySC";
887 s->uart.major = SCCNXP_MAJOR;
888 s->uart.minor = SCCNXP_MINOR;
889 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
890 s->uart.cons = &s->console;
891 s->uart.cons->device = uart_console_device;
892 s->uart.cons->write = sccnxp_console_write;
893 s->uart.cons->setup = sccnxp_console_setup;
894 s->uart.cons->flags = CON_PRINTBUFFER;
895 s->uart.cons->index = -1;
896 s->uart.cons->data = s;
897 strcpy(s->uart.cons->name, "ttySC");
899 ret = uart_register_driver(&s->uart);
901 dev_err(&pdev->dev, "Registering UART driver failed\n");
905 for (i = 0; i < s->uart.nr; i++) {
907 s->port[i].dev = &pdev->dev;
908 s->port[i].irq = s->irq;
909 s->port[i].type = PORT_SC26XX;
910 s->port[i].fifosize = fifosize;
911 s->port[i].flags = UPF_SKIP_TEST | UPF_FIXED_TYPE;
912 s->port[i].iotype = UPIO_MEM;
913 s->port[i].mapbase = res->start;
914 s->port[i].membase = membase;
915 s->port[i].regshift = s->pdata.reg_shift;
916 s->port[i].uartclk = s->pdata.frequency;
917 s->port[i].ops = &sccnxp_ops;
918 uart_add_one_port(&s->uart, &s->port[i]);
919 /* Set direction to input */
920 if (s->flags & SCCNXP_HAVE_IO)
921 sccnxp_set_bit(&s->port[i], DIR_OP, 0);
924 /* Disable interrupts */
926 sccnxp_write(&s->port[0], SCCNXP_IMR_REG, 0);
928 /* Board specific configure */
932 ret = devm_request_threaded_irq(&pdev->dev, s->irq, NULL, sccnxp_ist,
933 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
934 dev_name(&pdev->dev), s);
938 dev_err(&pdev->dev, "Unable to reguest IRQ %i\n", s->irq);
941 platform_set_drvdata(pdev, NULL);
946 static int sccnxp_remove(struct platform_device *pdev)
949 struct sccnxp_port *s = platform_get_drvdata(pdev);
951 devm_free_irq(&pdev->dev, s->irq, s);
953 for (i = 0; i < s->uart.nr; i++)
954 uart_remove_one_port(&s->uart, &s->port[i]);
956 uart_unregister_driver(&s->uart);
957 platform_set_drvdata(pdev, NULL);
965 static const struct platform_device_id sccnxp_id_table[] = {
966 { "sc2681", SCCNXP_TYPE_SC2681 },
967 { "sc2691", SCCNXP_TYPE_SC2691 },
968 { "sc2692", SCCNXP_TYPE_SC2692 },
969 { "sc2891", SCCNXP_TYPE_SC2891 },
970 { "sc2892", SCCNXP_TYPE_SC2892 },
971 { "sc28202", SCCNXP_TYPE_SC28202 },
972 { "sc68681", SCCNXP_TYPE_SC68681 },
973 { "sc68692", SCCNXP_TYPE_SC68692 },
976 MODULE_DEVICE_TABLE(platform, sccnxp_id_table);
978 static struct platform_driver sccnxp_uart_driver = {
981 .owner = THIS_MODULE,
983 .probe = sccnxp_probe,
984 .remove = sccnxp_remove,
985 .id_table = sccnxp_id_table,
987 module_platform_driver(sccnxp_uart_driver);
989 MODULE_LICENSE("GPL v2");
990 MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
991 MODULE_DESCRIPTION("SCCNXP serial driver");