2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 * Copyright (C) 2002 - 2011 Paul Mundt
5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
7 * based off of the old drivers/char/sh-sci.c by:
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
14 * Removed SH7300 support (Jul 2007).
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
20 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
26 #include <linux/clk.h>
27 #include <linux/console.h>
28 #include <linux/ctype.h>
29 #include <linux/cpufreq.h>
30 #include <linux/delay.h>
31 #include <linux/dmaengine.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/err.h>
34 #include <linux/errno.h>
35 #include <linux/init.h>
36 #include <linux/interrupt.h>
37 #include <linux/ioport.h>
38 #include <linux/major.h>
39 #include <linux/module.h>
41 #include <linux/notifier.h>
43 #include <linux/platform_device.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/scatterlist.h>
46 #include <linux/serial.h>
47 #include <linux/serial_sci.h>
48 #include <linux/sh_dma.h>
49 #include <linux/slab.h>
50 #include <linux/string.h>
51 #include <linux/sysrq.h>
52 #include <linux/timer.h>
53 #include <linux/tty.h>
54 #include <linux/tty_flip.h>
57 #include <asm/sh_bios.h>
62 /* Offsets into the sci_port->irqs array */
70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
73 #define SCIx_IRQ_IS_MUXED(port) \
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
80 struct uart_port port;
82 /* Platform configuration */
83 struct plat_sci_port *cfg;
84 unsigned int overrun_reg;
85 unsigned int overrun_mask;
86 unsigned int error_mask;
87 unsigned int error_clear;
88 unsigned int sampling_rate;
89 resource_size_t reg_size;
92 struct timer_list break_timer;
100 int irqs[SCIx_NR_IRQS];
101 char *irqstr[SCIx_NR_IRQS];
103 struct dma_chan *chan_tx;
104 struct dma_chan *chan_rx;
106 #ifdef CONFIG_SERIAL_SH_SCI_DMA
107 struct dma_async_tx_descriptor *desc_tx;
108 struct dma_async_tx_descriptor *desc_rx[2];
109 dma_cookie_t cookie_tx;
110 dma_cookie_t cookie_rx[2];
111 dma_cookie_t active_rx;
112 struct scatterlist sg_tx;
113 unsigned int sg_len_tx;
114 struct scatterlist sg_rx[2];
116 struct sh_dmae_slave param_tx;
117 struct sh_dmae_slave param_rx;
118 struct work_struct work_tx;
119 struct work_struct work_rx;
120 struct timer_list rx_timer;
121 unsigned int rx_timeout;
124 struct notifier_block freq_transition;
127 /* Function prototypes */
128 static void sci_start_tx(struct uart_port *port);
129 static void sci_stop_tx(struct uart_port *port);
130 static void sci_start_rx(struct uart_port *port);
132 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
134 static struct sci_port sci_ports[SCI_NPORTS];
135 static struct uart_driver sci_uart_driver;
137 static inline struct sci_port *
138 to_sci_port(struct uart_port *uart)
140 return container_of(uart, struct sci_port, port);
143 struct plat_sci_reg {
147 /* Helper for invalidating specific entries of an inherited map. */
148 #define sci_reg_invalid { .offset = 0, .size = 0 }
150 static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
151 [SCIx_PROBE_REGTYPE] = {
152 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
156 * Common SCI definitions, dependent on the port's regshift
159 [SCIx_SCI_REGTYPE] = {
160 [SCSMR] = { 0x00, 8 },
161 [SCBRR] = { 0x01, 8 },
162 [SCSCR] = { 0x02, 8 },
163 [SCxTDR] = { 0x03, 8 },
164 [SCxSR] = { 0x04, 8 },
165 [SCxRDR] = { 0x05, 8 },
166 [SCFCR] = sci_reg_invalid,
167 [SCFDR] = sci_reg_invalid,
168 [SCTFDR] = sci_reg_invalid,
169 [SCRFDR] = sci_reg_invalid,
170 [SCSPTR] = sci_reg_invalid,
171 [SCLSR] = sci_reg_invalid,
172 [HSSRR] = sci_reg_invalid,
173 [SCPCR] = sci_reg_invalid,
174 [SCPDR] = sci_reg_invalid,
178 * Common definitions for legacy IrDA ports, dependent on
181 [SCIx_IRDA_REGTYPE] = {
182 [SCSMR] = { 0x00, 8 },
183 [SCBRR] = { 0x01, 8 },
184 [SCSCR] = { 0x02, 8 },
185 [SCxTDR] = { 0x03, 8 },
186 [SCxSR] = { 0x04, 8 },
187 [SCxRDR] = { 0x05, 8 },
188 [SCFCR] = { 0x06, 8 },
189 [SCFDR] = { 0x07, 16 },
190 [SCTFDR] = sci_reg_invalid,
191 [SCRFDR] = sci_reg_invalid,
192 [SCSPTR] = sci_reg_invalid,
193 [SCLSR] = sci_reg_invalid,
194 [HSSRR] = sci_reg_invalid,
195 [SCPCR] = sci_reg_invalid,
196 [SCPDR] = sci_reg_invalid,
200 * Common SCIFA definitions.
202 [SCIx_SCIFA_REGTYPE] = {
203 [SCSMR] = { 0x00, 16 },
204 [SCBRR] = { 0x04, 8 },
205 [SCSCR] = { 0x08, 16 },
206 [SCxTDR] = { 0x20, 8 },
207 [SCxSR] = { 0x14, 16 },
208 [SCxRDR] = { 0x24, 8 },
209 [SCFCR] = { 0x18, 16 },
210 [SCFDR] = { 0x1c, 16 },
211 [SCTFDR] = sci_reg_invalid,
212 [SCRFDR] = sci_reg_invalid,
213 [SCSPTR] = sci_reg_invalid,
214 [SCLSR] = sci_reg_invalid,
215 [HSSRR] = sci_reg_invalid,
216 [SCPCR] = { 0x30, 16 },
217 [SCPDR] = { 0x34, 16 },
221 * Common SCIFB definitions.
223 [SCIx_SCIFB_REGTYPE] = {
224 [SCSMR] = { 0x00, 16 },
225 [SCBRR] = { 0x04, 8 },
226 [SCSCR] = { 0x08, 16 },
227 [SCxTDR] = { 0x40, 8 },
228 [SCxSR] = { 0x14, 16 },
229 [SCxRDR] = { 0x60, 8 },
230 [SCFCR] = { 0x18, 16 },
231 [SCFDR] = sci_reg_invalid,
232 [SCTFDR] = { 0x38, 16 },
233 [SCRFDR] = { 0x3c, 16 },
234 [SCSPTR] = sci_reg_invalid,
235 [SCLSR] = sci_reg_invalid,
236 [HSSRR] = sci_reg_invalid,
237 [SCPCR] = { 0x30, 16 },
238 [SCPDR] = { 0x34, 16 },
242 * Common SH-2(A) SCIF definitions for ports with FIFO data
245 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
246 [SCSMR] = { 0x00, 16 },
247 [SCBRR] = { 0x04, 8 },
248 [SCSCR] = { 0x08, 16 },
249 [SCxTDR] = { 0x0c, 8 },
250 [SCxSR] = { 0x10, 16 },
251 [SCxRDR] = { 0x14, 8 },
252 [SCFCR] = { 0x18, 16 },
253 [SCFDR] = { 0x1c, 16 },
254 [SCTFDR] = sci_reg_invalid,
255 [SCRFDR] = sci_reg_invalid,
256 [SCSPTR] = { 0x20, 16 },
257 [SCLSR] = { 0x24, 16 },
258 [HSSRR] = sci_reg_invalid,
259 [SCPCR] = sci_reg_invalid,
260 [SCPDR] = sci_reg_invalid,
264 * Common SH-3 SCIF definitions.
266 [SCIx_SH3_SCIF_REGTYPE] = {
267 [SCSMR] = { 0x00, 8 },
268 [SCBRR] = { 0x02, 8 },
269 [SCSCR] = { 0x04, 8 },
270 [SCxTDR] = { 0x06, 8 },
271 [SCxSR] = { 0x08, 16 },
272 [SCxRDR] = { 0x0a, 8 },
273 [SCFCR] = { 0x0c, 8 },
274 [SCFDR] = { 0x0e, 16 },
275 [SCTFDR] = sci_reg_invalid,
276 [SCRFDR] = sci_reg_invalid,
277 [SCSPTR] = sci_reg_invalid,
278 [SCLSR] = sci_reg_invalid,
279 [HSSRR] = sci_reg_invalid,
280 [SCPCR] = sci_reg_invalid,
281 [SCPDR] = sci_reg_invalid,
285 * Common SH-4(A) SCIF(B) definitions.
287 [SCIx_SH4_SCIF_REGTYPE] = {
288 [SCSMR] = { 0x00, 16 },
289 [SCBRR] = { 0x04, 8 },
290 [SCSCR] = { 0x08, 16 },
291 [SCxTDR] = { 0x0c, 8 },
292 [SCxSR] = { 0x10, 16 },
293 [SCxRDR] = { 0x14, 8 },
294 [SCFCR] = { 0x18, 16 },
295 [SCFDR] = { 0x1c, 16 },
296 [SCTFDR] = sci_reg_invalid,
297 [SCRFDR] = sci_reg_invalid,
298 [SCSPTR] = { 0x20, 16 },
299 [SCLSR] = { 0x24, 16 },
300 [HSSRR] = sci_reg_invalid,
301 [SCPCR] = sci_reg_invalid,
302 [SCPDR] = sci_reg_invalid,
306 * Common HSCIF definitions.
308 [SCIx_HSCIF_REGTYPE] = {
309 [SCSMR] = { 0x00, 16 },
310 [SCBRR] = { 0x04, 8 },
311 [SCSCR] = { 0x08, 16 },
312 [SCxTDR] = { 0x0c, 8 },
313 [SCxSR] = { 0x10, 16 },
314 [SCxRDR] = { 0x14, 8 },
315 [SCFCR] = { 0x18, 16 },
316 [SCFDR] = { 0x1c, 16 },
317 [SCTFDR] = sci_reg_invalid,
318 [SCRFDR] = sci_reg_invalid,
319 [SCSPTR] = { 0x20, 16 },
320 [SCLSR] = { 0x24, 16 },
321 [HSSRR] = { 0x40, 16 },
322 [SCPCR] = sci_reg_invalid,
323 [SCPDR] = sci_reg_invalid,
327 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
330 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
331 [SCSMR] = { 0x00, 16 },
332 [SCBRR] = { 0x04, 8 },
333 [SCSCR] = { 0x08, 16 },
334 [SCxTDR] = { 0x0c, 8 },
335 [SCxSR] = { 0x10, 16 },
336 [SCxRDR] = { 0x14, 8 },
337 [SCFCR] = { 0x18, 16 },
338 [SCFDR] = { 0x1c, 16 },
339 [SCTFDR] = sci_reg_invalid,
340 [SCRFDR] = sci_reg_invalid,
341 [SCSPTR] = sci_reg_invalid,
342 [SCLSR] = { 0x24, 16 },
343 [HSSRR] = sci_reg_invalid,
344 [SCPCR] = sci_reg_invalid,
345 [SCPDR] = sci_reg_invalid,
349 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
352 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
353 [SCSMR] = { 0x00, 16 },
354 [SCBRR] = { 0x04, 8 },
355 [SCSCR] = { 0x08, 16 },
356 [SCxTDR] = { 0x0c, 8 },
357 [SCxSR] = { 0x10, 16 },
358 [SCxRDR] = { 0x14, 8 },
359 [SCFCR] = { 0x18, 16 },
360 [SCFDR] = { 0x1c, 16 },
361 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
362 [SCRFDR] = { 0x20, 16 },
363 [SCSPTR] = { 0x24, 16 },
364 [SCLSR] = { 0x28, 16 },
365 [HSSRR] = sci_reg_invalid,
366 [SCPCR] = sci_reg_invalid,
367 [SCPDR] = sci_reg_invalid,
371 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
374 [SCIx_SH7705_SCIF_REGTYPE] = {
375 [SCSMR] = { 0x00, 16 },
376 [SCBRR] = { 0x04, 8 },
377 [SCSCR] = { 0x08, 16 },
378 [SCxTDR] = { 0x20, 8 },
379 [SCxSR] = { 0x14, 16 },
380 [SCxRDR] = { 0x24, 8 },
381 [SCFCR] = { 0x18, 16 },
382 [SCFDR] = { 0x1c, 16 },
383 [SCTFDR] = sci_reg_invalid,
384 [SCRFDR] = sci_reg_invalid,
385 [SCSPTR] = sci_reg_invalid,
386 [SCLSR] = sci_reg_invalid,
387 [HSSRR] = sci_reg_invalid,
388 [SCPCR] = sci_reg_invalid,
389 [SCPDR] = sci_reg_invalid,
393 #define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
396 * The "offset" here is rather misleading, in that it refers to an enum
397 * value relative to the port mapping rather than the fixed offset
398 * itself, which needs to be manually retrieved from the platform's
399 * register map for the given port.
401 static unsigned int sci_serial_in(struct uart_port *p, int offset)
403 struct plat_sci_reg *reg = sci_getreg(p, offset);
406 return ioread8(p->membase + (reg->offset << p->regshift));
407 else if (reg->size == 16)
408 return ioread16(p->membase + (reg->offset << p->regshift));
410 WARN(1, "Invalid register access\n");
415 static void sci_serial_out(struct uart_port *p, int offset, int value)
417 struct plat_sci_reg *reg = sci_getreg(p, offset);
420 iowrite8(value, p->membase + (reg->offset << p->regshift));
421 else if (reg->size == 16)
422 iowrite16(value, p->membase + (reg->offset << p->regshift));
424 WARN(1, "Invalid register access\n");
427 static int sci_probe_regmap(struct plat_sci_port *cfg)
431 cfg->regtype = SCIx_SCI_REGTYPE;
434 cfg->regtype = SCIx_IRDA_REGTYPE;
437 cfg->regtype = SCIx_SCIFA_REGTYPE;
440 cfg->regtype = SCIx_SCIFB_REGTYPE;
444 * The SH-4 is a bit of a misnomer here, although that's
445 * where this particular port layout originated. This
446 * configuration (or some slight variation thereof)
447 * remains the dominant model for all SCIFs.
449 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
452 cfg->regtype = SCIx_HSCIF_REGTYPE;
455 pr_err("Can't probe register map for given port\n");
462 static void sci_port_enable(struct sci_port *sci_port)
464 if (!sci_port->port.dev)
467 pm_runtime_get_sync(sci_port->port.dev);
469 clk_prepare_enable(sci_port->iclk);
470 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
471 clk_prepare_enable(sci_port->fclk);
474 static void sci_port_disable(struct sci_port *sci_port)
476 if (!sci_port->port.dev)
479 /* Cancel the break timer to ensure that the timer handler will not try
480 * to access the hardware with clocks and power disabled. Reset the
481 * break flag to make the break debouncing state machine ready for the
484 del_timer_sync(&sci_port->break_timer);
485 sci_port->break_flag = 0;
487 clk_disable_unprepare(sci_port->fclk);
488 clk_disable_unprepare(sci_port->iclk);
490 pm_runtime_put_sync(sci_port->port.dev);
493 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
495 if (port->type == PORT_SCI) {
496 /* Just store the mask */
497 serial_port_out(port, SCxSR, mask);
498 } else if (to_sci_port(port)->overrun_mask == SCIFA_ORER) {
499 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
500 /* Only clear the status bits we want to clear */
501 serial_port_out(port, SCxSR,
502 serial_port_in(port, SCxSR) & mask);
504 /* Store the mask, clear parity/framing errors */
505 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
509 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
511 #ifdef CONFIG_CONSOLE_POLL
512 static int sci_poll_get_char(struct uart_port *port)
514 unsigned short status;
518 status = serial_port_in(port, SCxSR);
519 if (status & SCxSR_ERRORS(port)) {
520 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
526 if (!(status & SCxSR_RDxF(port)))
529 c = serial_port_in(port, SCxRDR);
532 serial_port_in(port, SCxSR);
533 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
539 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
541 unsigned short status;
544 status = serial_port_in(port, SCxSR);
545 } while (!(status & SCxSR_TDxE(port)));
547 serial_port_out(port, SCxTDR, c);
548 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
550 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
552 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
554 struct sci_port *s = to_sci_port(port);
555 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
558 * Use port-specific handler if provided.
560 if (s->cfg->ops && s->cfg->ops->init_pins) {
561 s->cfg->ops->init_pins(port, cflag);
566 * For the generic path SCSPTR is necessary. Bail out if that's
572 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
573 ((!(cflag & CRTSCTS)))) {
574 unsigned short status;
576 status = serial_port_in(port, SCSPTR);
577 status &= ~SCSPTR_CTSIO;
578 status |= SCSPTR_RTSIO;
579 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
583 static int sci_txfill(struct uart_port *port)
585 struct plat_sci_reg *reg;
587 reg = sci_getreg(port, SCTFDR);
589 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
591 reg = sci_getreg(port, SCFDR);
593 return serial_port_in(port, SCFDR) >> 8;
595 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
598 static int sci_txroom(struct uart_port *port)
600 return port->fifosize - sci_txfill(port);
603 static int sci_rxfill(struct uart_port *port)
605 struct plat_sci_reg *reg;
607 reg = sci_getreg(port, SCRFDR);
609 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
611 reg = sci_getreg(port, SCFDR);
613 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
615 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
619 * SCI helper for checking the state of the muxed port/RXD pins.
621 static inline int sci_rxd_in(struct uart_port *port)
623 struct sci_port *s = to_sci_port(port);
625 if (s->cfg->port_reg <= 0)
628 /* Cast for ARM damage */
629 return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
632 /* ********************************************************************** *
633 * the interrupt related routines *
634 * ********************************************************************** */
636 static void sci_transmit_chars(struct uart_port *port)
638 struct circ_buf *xmit = &port->state->xmit;
639 unsigned int stopped = uart_tx_stopped(port);
640 unsigned short status;
644 status = serial_port_in(port, SCxSR);
645 if (!(status & SCxSR_TDxE(port))) {
646 ctrl = serial_port_in(port, SCSCR);
647 if (uart_circ_empty(xmit))
651 serial_port_out(port, SCSCR, ctrl);
655 count = sci_txroom(port);
663 } else if (!uart_circ_empty(xmit) && !stopped) {
664 c = xmit->buf[xmit->tail];
665 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
670 serial_port_out(port, SCxTDR, c);
673 } while (--count > 0);
675 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
677 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
678 uart_write_wakeup(port);
679 if (uart_circ_empty(xmit)) {
682 ctrl = serial_port_in(port, SCSCR);
684 if (port->type != PORT_SCI) {
685 serial_port_in(port, SCxSR); /* Dummy read */
686 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
690 serial_port_out(port, SCSCR, ctrl);
694 /* On SH3, SCIF may read end-of-break as a space->mark char */
695 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
697 static void sci_receive_chars(struct uart_port *port)
699 struct sci_port *sci_port = to_sci_port(port);
700 struct tty_port *tport = &port->state->port;
701 int i, count, copied = 0;
702 unsigned short status;
705 status = serial_port_in(port, SCxSR);
706 if (!(status & SCxSR_RDxF(port)))
710 /* Don't copy more bytes than there is room for in the buffer */
711 count = tty_buffer_request_room(tport, sci_rxfill(port));
713 /* If for any reason we can't copy more data, we're done! */
717 if (port->type == PORT_SCI) {
718 char c = serial_port_in(port, SCxRDR);
719 if (uart_handle_sysrq_char(port, c) ||
720 sci_port->break_flag)
723 tty_insert_flip_char(tport, c, TTY_NORMAL);
725 for (i = 0; i < count; i++) {
726 char c = serial_port_in(port, SCxRDR);
728 status = serial_port_in(port, SCxSR);
729 #if defined(CONFIG_CPU_SH3)
730 /* Skip "chars" during break */
731 if (sci_port->break_flag) {
733 (status & SCxSR_FER(port))) {
738 /* Nonzero => end-of-break */
739 dev_dbg(port->dev, "debounce<%02x>\n", c);
740 sci_port->break_flag = 0;
747 #endif /* CONFIG_CPU_SH3 */
748 if (uart_handle_sysrq_char(port, c)) {
753 /* Store data and status */
754 if (status & SCxSR_FER(port)) {
756 port->icount.frame++;
757 dev_notice(port->dev, "frame error\n");
758 } else if (status & SCxSR_PER(port)) {
760 port->icount.parity++;
761 dev_notice(port->dev, "parity error\n");
765 tty_insert_flip_char(tport, c, flag);
769 serial_port_in(port, SCxSR); /* dummy read */
770 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
773 port->icount.rx += count;
777 /* Tell the rest of the system the news. New characters! */
778 tty_flip_buffer_push(tport);
780 serial_port_in(port, SCxSR); /* dummy read */
781 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
785 #define SCI_BREAK_JIFFIES (HZ/20)
788 * The sci generates interrupts during the break,
789 * 1 per millisecond or so during the break period, for 9600 baud.
790 * So dont bother disabling interrupts.
791 * But dont want more than 1 break event.
792 * Use a kernel timer to periodically poll the rx line until
793 * the break is finished.
795 static inline void sci_schedule_break_timer(struct sci_port *port)
797 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
800 /* Ensure that two consecutive samples find the break over. */
801 static void sci_break_timer(unsigned long data)
803 struct sci_port *port = (struct sci_port *)data;
805 if (sci_rxd_in(&port->port) == 0) {
806 port->break_flag = 1;
807 sci_schedule_break_timer(port);
808 } else if (port->break_flag == 1) {
810 port->break_flag = 2;
811 sci_schedule_break_timer(port);
813 port->break_flag = 0;
816 static int sci_handle_errors(struct uart_port *port)
819 unsigned short status = serial_port_in(port, SCxSR);
820 struct tty_port *tport = &port->state->port;
821 struct sci_port *s = to_sci_port(port);
823 /* Handle overruns */
824 if (status & s->overrun_mask) {
825 port->icount.overrun++;
828 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
831 dev_notice(port->dev, "overrun error\n");
834 if (status & SCxSR_FER(port)) {
835 if (sci_rxd_in(port) == 0) {
836 /* Notify of BREAK */
837 struct sci_port *sci_port = to_sci_port(port);
839 if (!sci_port->break_flag) {
842 sci_port->break_flag = 1;
843 sci_schedule_break_timer(sci_port);
845 /* Do sysrq handling. */
846 if (uart_handle_break(port))
849 dev_dbg(port->dev, "BREAK detected\n");
851 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
857 port->icount.frame++;
859 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
862 dev_notice(port->dev, "frame error\n");
866 if (status & SCxSR_PER(port)) {
868 port->icount.parity++;
870 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
873 dev_notice(port->dev, "parity error\n");
877 tty_flip_buffer_push(tport);
882 static int sci_handle_fifo_overrun(struct uart_port *port)
884 struct tty_port *tport = &port->state->port;
885 struct sci_port *s = to_sci_port(port);
886 struct plat_sci_reg *reg;
890 reg = sci_getreg(port, s->overrun_reg);
894 status = serial_port_in(port, s->overrun_reg);
895 if (status & s->overrun_mask) {
896 status &= ~s->overrun_mask;
897 serial_port_out(port, s->overrun_reg, status);
899 port->icount.overrun++;
901 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
902 tty_flip_buffer_push(tport);
904 dev_dbg(port->dev, "overrun error\n");
911 static int sci_handle_breaks(struct uart_port *port)
914 unsigned short status = serial_port_in(port, SCxSR);
915 struct tty_port *tport = &port->state->port;
916 struct sci_port *s = to_sci_port(port);
918 if (uart_handle_break(port))
921 if (!s->break_flag && status & SCxSR_BRK(port)) {
922 #if defined(CONFIG_CPU_SH3)
929 /* Notify of BREAK */
930 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
933 dev_dbg(port->dev, "BREAK detected\n");
937 tty_flip_buffer_push(tport);
939 copied += sci_handle_fifo_overrun(port);
944 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
946 #ifdef CONFIG_SERIAL_SH_SCI_DMA
947 struct uart_port *port = ptr;
948 struct sci_port *s = to_sci_port(port);
951 u16 scr = serial_port_in(port, SCSCR);
952 u16 ssr = serial_port_in(port, SCxSR);
954 /* Disable future Rx interrupts */
955 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
956 disable_irq_nosync(irq);
961 serial_port_out(port, SCSCR, scr);
962 /* Clear current interrupt */
963 serial_port_out(port, SCxSR,
964 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
965 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
966 jiffies, s->rx_timeout);
967 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
973 /* I think sci_receive_chars has to be called irrespective
974 * of whether the I_IXOFF is set, otherwise, how is the interrupt
977 sci_receive_chars(ptr);
982 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
984 struct uart_port *port = ptr;
987 spin_lock_irqsave(&port->lock, flags);
988 sci_transmit_chars(port);
989 spin_unlock_irqrestore(&port->lock, flags);
994 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
996 struct uart_port *port = ptr;
999 if (port->type == PORT_SCI) {
1000 if (sci_handle_errors(port)) {
1001 /* discard character in rx buffer */
1002 serial_port_in(port, SCxSR);
1003 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1006 sci_handle_fifo_overrun(port);
1007 sci_rx_interrupt(irq, ptr);
1010 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1012 /* Kick the transmission */
1013 sci_tx_interrupt(irq, ptr);
1018 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1020 struct uart_port *port = ptr;
1023 sci_handle_breaks(port);
1024 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1029 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
1032 * Not all ports (such as SCIFA) will support REIE. Rather than
1033 * special-casing the port type, we check the port initialization
1034 * IRQ enable mask to see whether the IRQ is desired at all. If
1035 * it's unset, it's logically inferred that there's no point in
1038 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
1041 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1043 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1044 struct uart_port *port = ptr;
1045 struct sci_port *s = to_sci_port(port);
1046 irqreturn_t ret = IRQ_NONE;
1048 ssr_status = serial_port_in(port, SCxSR);
1049 scr_status = serial_port_in(port, SCSCR);
1050 if (s->overrun_reg == SCxSR)
1051 orer_status = ssr_status;
1053 if (sci_getreg(port, s->overrun_reg)->size)
1054 orer_status = serial_port_in(port, s->overrun_reg);
1057 err_enabled = scr_status & port_rx_irq_mask(port);
1060 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1062 ret = sci_tx_interrupt(irq, ptr);
1065 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1068 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1069 (scr_status & SCSCR_RIE)) {
1070 if (port->type == PORT_SCIF || port->type == PORT_HSCIF)
1071 sci_handle_fifo_overrun(port);
1072 ret = sci_rx_interrupt(irq, ptr);
1075 /* Error Interrupt */
1076 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1077 ret = sci_er_interrupt(irq, ptr);
1079 /* Break Interrupt */
1080 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1081 ret = sci_br_interrupt(irq, ptr);
1083 /* Overrun Interrupt */
1084 if (orer_status & s->overrun_mask)
1085 sci_handle_fifo_overrun(port);
1091 * Here we define a transition notifier so that we can update all of our
1092 * ports' baud rate when the peripheral clock changes.
1094 static int sci_notifier(struct notifier_block *self,
1095 unsigned long phase, void *p)
1097 struct sci_port *sci_port;
1098 unsigned long flags;
1100 sci_port = container_of(self, struct sci_port, freq_transition);
1102 if (phase == CPUFREQ_POSTCHANGE) {
1103 struct uart_port *port = &sci_port->port;
1105 spin_lock_irqsave(&port->lock, flags);
1106 port->uartclk = clk_get_rate(sci_port->iclk);
1107 spin_unlock_irqrestore(&port->lock, flags);
1113 static const struct sci_irq_desc {
1115 irq_handler_t handler;
1116 } sci_irq_desc[] = {
1118 * Split out handlers, the default case.
1122 .handler = sci_er_interrupt,
1127 .handler = sci_rx_interrupt,
1132 .handler = sci_tx_interrupt,
1137 .handler = sci_br_interrupt,
1141 * Special muxed handler.
1145 .handler = sci_mpxed_interrupt,
1149 static int sci_request_irq(struct sci_port *port)
1151 struct uart_port *up = &port->port;
1154 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1155 const struct sci_irq_desc *desc;
1158 if (SCIx_IRQ_IS_MUXED(port)) {
1162 irq = port->irqs[i];
1165 * Certain port types won't support all of the
1166 * available interrupt sources.
1168 if (unlikely(irq < 0))
1172 desc = sci_irq_desc + i;
1173 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1174 dev_name(up->dev), desc->desc);
1175 if (!port->irqstr[j]) {
1176 dev_err(up->dev, "Failed to allocate %s IRQ string\n",
1181 ret = request_irq(irq, desc->handler, up->irqflags,
1182 port->irqstr[j], port);
1183 if (unlikely(ret)) {
1184 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1193 free_irq(port->irqs[i], port);
1197 kfree(port->irqstr[j]);
1202 static void sci_free_irq(struct sci_port *port)
1207 * Intentionally in reverse order so we iterate over the muxed
1210 for (i = 0; i < SCIx_NR_IRQS; i++) {
1211 int irq = port->irqs[i];
1214 * Certain port types won't support all of the available
1215 * interrupt sources.
1217 if (unlikely(irq < 0))
1220 free_irq(port->irqs[i], port);
1221 kfree(port->irqstr[i]);
1223 if (SCIx_IRQ_IS_MUXED(port)) {
1224 /* If there's only one IRQ, we're done. */
1230 static unsigned int sci_tx_empty(struct uart_port *port)
1232 unsigned short status = serial_port_in(port, SCxSR);
1233 unsigned short in_tx_fifo = sci_txfill(port);
1235 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1239 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1240 * CTS/RTS is supported in hardware by at least one port and controlled
1241 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1242 * handled via the ->init_pins() op, which is a bit of a one-way street,
1243 * lacking any ability to defer pin control -- this will later be
1244 * converted over to the GPIO framework).
1246 * Other modes (such as loopback) are supported generically on certain
1247 * port types, but not others. For these it's sufficient to test for the
1248 * existence of the support register and simply ignore the port type.
1250 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1252 if (mctrl & TIOCM_LOOP) {
1253 struct plat_sci_reg *reg;
1256 * Standard loopback mode for SCFCR ports.
1258 reg = sci_getreg(port, SCFCR);
1260 serial_port_out(port, SCFCR,
1261 serial_port_in(port, SCFCR) |
1266 static unsigned int sci_get_mctrl(struct uart_port *port)
1269 * CTS/RTS is handled in hardware when supported, while nothing
1270 * else is wired up. Keep it simple and simply assert DSR/CAR.
1272 return TIOCM_DSR | TIOCM_CAR;
1275 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1276 static void sci_dma_tx_complete(void *arg)
1278 struct sci_port *s = arg;
1279 struct uart_port *port = &s->port;
1280 struct circ_buf *xmit = &port->state->xmit;
1281 unsigned long flags;
1283 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1285 spin_lock_irqsave(&port->lock, flags);
1287 xmit->tail += sg_dma_len(&s->sg_tx);
1288 xmit->tail &= UART_XMIT_SIZE - 1;
1290 port->icount.tx += sg_dma_len(&s->sg_tx);
1292 async_tx_ack(s->desc_tx);
1295 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1296 uart_write_wakeup(port);
1298 if (!uart_circ_empty(xmit)) {
1300 schedule_work(&s->work_tx);
1302 s->cookie_tx = -EINVAL;
1303 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1304 u16 ctrl = serial_port_in(port, SCSCR);
1305 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1309 spin_unlock_irqrestore(&port->lock, flags);
1312 /* Locking: called with port lock held */
1313 static int sci_dma_rx_push(struct sci_port *s, size_t count)
1315 struct uart_port *port = &s->port;
1316 struct tty_port *tport = &port->state->port;
1317 int i, active, room;
1319 room = tty_buffer_request_room(tport, count);
1321 if (s->active_rx == s->cookie_rx[0]) {
1323 } else if (s->active_rx == s->cookie_rx[1]) {
1326 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1331 dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n",
1336 for (i = 0; i < room; i++)
1337 tty_insert_flip_char(tport, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
1340 port->icount.rx += room;
1345 static void sci_dma_rx_complete(void *arg)
1347 struct sci_port *s = arg;
1348 struct uart_port *port = &s->port;
1349 unsigned long flags;
1352 dev_dbg(port->dev, "%s(%d) active #%d\n",
1353 __func__, port->line, s->active_rx);
1355 spin_lock_irqsave(&port->lock, flags);
1357 count = sci_dma_rx_push(s, s->buf_len_rx);
1359 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1361 spin_unlock_irqrestore(&port->lock, flags);
1364 tty_flip_buffer_push(&port->state->port);
1366 schedule_work(&s->work_rx);
1369 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1371 struct dma_chan *chan = s->chan_rx;
1372 struct uart_port *port = &s->port;
1375 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1376 dma_release_channel(chan);
1377 if (sg_dma_address(&s->sg_rx[0]))
1378 dma_free_coherent(port->dev, s->buf_len_rx * 2,
1379 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
1384 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1386 struct dma_chan *chan = s->chan_tx;
1387 struct uart_port *port = &s->port;
1390 s->cookie_tx = -EINVAL;
1391 dma_release_channel(chan);
1396 static void sci_submit_rx(struct sci_port *s)
1398 struct dma_chan *chan = s->chan_rx;
1401 for (i = 0; i < 2; i++) {
1402 struct scatterlist *sg = &s->sg_rx[i];
1403 struct dma_async_tx_descriptor *desc;
1405 desc = dmaengine_prep_slave_sg(chan,
1406 sg, 1, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1409 s->desc_rx[i] = desc;
1410 desc->callback = sci_dma_rx_complete;
1411 desc->callback_param = s;
1412 s->cookie_rx[i] = desc->tx_submit(desc);
1415 if (!desc || s->cookie_rx[i] < 0) {
1417 async_tx_ack(s->desc_rx[0]);
1418 s->cookie_rx[0] = -EINVAL;
1422 s->cookie_rx[i] = -EINVAL;
1424 dev_warn(s->port.dev,
1425 "failed to re-start DMA, using PIO\n");
1426 sci_rx_dma_release(s, true);
1429 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n",
1430 __func__, s->cookie_rx[i], i);
1433 s->active_rx = s->cookie_rx[0];
1435 dma_async_issue_pending(chan);
1438 static void work_fn_rx(struct work_struct *work)
1440 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1441 struct uart_port *port = &s->port;
1442 struct dma_async_tx_descriptor *desc;
1445 if (s->active_rx == s->cookie_rx[0]) {
1447 } else if (s->active_rx == s->cookie_rx[1]) {
1450 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1453 desc = s->desc_rx[new];
1455 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) !=
1457 /* Handle incomplete DMA receive */
1458 struct dma_chan *chan = s->chan_rx;
1459 struct shdma_desc *sh_desc = container_of(desc,
1460 struct shdma_desc, async_tx);
1461 unsigned long flags;
1464 dmaengine_terminate_all(chan);
1465 dev_dbg(port->dev, "Read %zu bytes with cookie %d\n",
1466 sh_desc->partial, sh_desc->cookie);
1468 spin_lock_irqsave(&port->lock, flags);
1469 count = sci_dma_rx_push(s, sh_desc->partial);
1470 spin_unlock_irqrestore(&port->lock, flags);
1473 tty_flip_buffer_push(&port->state->port);
1480 s->cookie_rx[new] = desc->tx_submit(desc);
1481 if (s->cookie_rx[new] < 0) {
1482 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1483 sci_rx_dma_release(s, true);
1487 s->active_rx = s->cookie_rx[!new];
1489 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n",
1490 __func__, s->cookie_rx[new], new, s->active_rx);
1493 static void work_fn_tx(struct work_struct *work)
1495 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1496 struct dma_async_tx_descriptor *desc;
1497 struct dma_chan *chan = s->chan_tx;
1498 struct uart_port *port = &s->port;
1499 struct circ_buf *xmit = &port->state->xmit;
1500 struct scatterlist *sg = &s->sg_tx;
1504 * Port xmit buffer is already mapped, and it is one page... Just adjust
1505 * offsets and lengths. Since it is a circular buffer, we have to
1506 * transmit till the end, and then the rest. Take the port lock to get a
1507 * consistent xmit buffer state.
1509 spin_lock_irq(&port->lock);
1510 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
1511 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
1513 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1514 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1515 spin_unlock_irq(&port->lock);
1517 BUG_ON(!sg_dma_len(sg));
1519 desc = dmaengine_prep_slave_sg(chan,
1520 sg, s->sg_len_tx, DMA_MEM_TO_DEV,
1521 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1524 sci_tx_dma_release(s, true);
1528 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
1530 spin_lock_irq(&port->lock);
1532 desc->callback = sci_dma_tx_complete;
1533 desc->callback_param = s;
1534 spin_unlock_irq(&port->lock);
1535 s->cookie_tx = desc->tx_submit(desc);
1536 if (s->cookie_tx < 0) {
1537 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1539 sci_tx_dma_release(s, true);
1543 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1544 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1546 dma_async_issue_pending(chan);
1550 static void sci_start_tx(struct uart_port *port)
1552 struct sci_port *s = to_sci_port(port);
1553 unsigned short ctrl;
1555 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1556 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1557 u16 new, scr = serial_port_in(port, SCSCR);
1559 new = scr | SCSCR_TDRQE;
1561 new = scr & ~SCSCR_TDRQE;
1563 serial_port_out(port, SCSCR, new);
1566 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
1569 schedule_work(&s->work_tx);
1573 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1574 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
1575 ctrl = serial_port_in(port, SCSCR);
1576 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
1580 static void sci_stop_tx(struct uart_port *port)
1582 unsigned short ctrl;
1584 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
1585 ctrl = serial_port_in(port, SCSCR);
1587 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1588 ctrl &= ~SCSCR_TDRQE;
1592 serial_port_out(port, SCSCR, ctrl);
1595 static void sci_start_rx(struct uart_port *port)
1597 unsigned short ctrl;
1599 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
1601 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1602 ctrl &= ~SCSCR_RDRQE;
1604 serial_port_out(port, SCSCR, ctrl);
1607 static void sci_stop_rx(struct uart_port *port)
1609 unsigned short ctrl;
1611 ctrl = serial_port_in(port, SCSCR);
1613 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1614 ctrl &= ~SCSCR_RDRQE;
1616 ctrl &= ~port_rx_irq_mask(port);
1618 serial_port_out(port, SCSCR, ctrl);
1621 static void sci_break_ctl(struct uart_port *port, int break_state)
1623 struct sci_port *s = to_sci_port(port);
1624 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1625 unsigned short scscr, scsptr;
1627 /* check wheter the port has SCSPTR */
1630 * Not supported by hardware. Most parts couple break and rx
1631 * interrupts together, with break detection always enabled.
1636 scsptr = serial_port_in(port, SCSPTR);
1637 scscr = serial_port_in(port, SCSCR);
1639 if (break_state == -1) {
1640 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1643 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1647 serial_port_out(port, SCSPTR, scsptr);
1648 serial_port_out(port, SCSCR, scscr);
1651 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1652 static bool filter(struct dma_chan *chan, void *slave)
1654 struct sh_dmae_slave *param = slave;
1656 dev_dbg(chan->device->dev, "%s: slave ID %d\n",
1657 __func__, param->shdma_slave.slave_id);
1659 chan->private = ¶m->shdma_slave;
1663 static void rx_timer_fn(unsigned long arg)
1665 struct sci_port *s = (struct sci_port *)arg;
1666 struct uart_port *port = &s->port;
1667 u16 scr = serial_port_in(port, SCSCR);
1669 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1670 scr &= ~SCSCR_RDRQE;
1671 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1673 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1674 dev_dbg(port->dev, "DMA Rx timed out\n");
1675 schedule_work(&s->work_rx);
1678 static void sci_request_dma(struct uart_port *port)
1680 struct sci_port *s = to_sci_port(port);
1681 struct sh_dmae_slave *param;
1682 struct dma_chan *chan;
1683 dma_cap_mask_t mask;
1686 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1688 if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0)
1692 dma_cap_set(DMA_SLAVE, mask);
1694 param = &s->param_tx;
1696 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
1697 param->shdma_slave.slave_id = s->cfg->dma_slave_tx;
1699 s->cookie_tx = -EINVAL;
1700 chan = dma_request_channel(mask, filter, param);
1701 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1704 sg_init_table(&s->sg_tx, 1);
1705 /* UART circular tx buffer is an aligned page. */
1706 BUG_ON((uintptr_t)port->state->xmit.buf & ~PAGE_MASK);
1707 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf),
1709 (uintptr_t)port->state->xmit.buf & ~PAGE_MASK);
1710 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE);
1712 sci_tx_dma_release(s, false);
1714 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n",
1716 sg_dma_len(&s->sg_tx), port->state->xmit.buf,
1717 &sg_dma_address(&s->sg_tx));
1719 s->sg_len_tx = nent;
1721 INIT_WORK(&s->work_tx, work_fn_tx);
1724 param = &s->param_rx;
1726 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
1727 param->shdma_slave.slave_id = s->cfg->dma_slave_rx;
1729 chan = dma_request_channel(mask, filter, param);
1730 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1738 s->buf_len_rx = 2 * max(16, (int)port->fifosize);
1739 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2,
1740 &dma[0], GFP_KERNEL);
1744 "failed to allocate dma buffer, using PIO\n");
1745 sci_rx_dma_release(s, true);
1749 buf[1] = buf[0] + s->buf_len_rx;
1750 dma[1] = dma[0] + s->buf_len_rx;
1752 for (i = 0; i < 2; i++) {
1753 struct scatterlist *sg = &s->sg_rx[i];
1755 sg_init_table(sg, 1);
1756 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
1757 (uintptr_t)buf[i] & ~PAGE_MASK);
1758 sg_dma_address(sg) = dma[i];
1761 INIT_WORK(&s->work_rx, work_fn_rx);
1762 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1768 static void sci_free_dma(struct uart_port *port)
1770 struct sci_port *s = to_sci_port(port);
1773 sci_tx_dma_release(s, false);
1775 sci_rx_dma_release(s, false);
1778 static inline void sci_request_dma(struct uart_port *port)
1782 static inline void sci_free_dma(struct uart_port *port)
1787 static int sci_startup(struct uart_port *port)
1789 struct sci_port *s = to_sci_port(port);
1790 unsigned long flags;
1793 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1795 ret = sci_request_irq(s);
1796 if (unlikely(ret < 0))
1799 sci_request_dma(port);
1801 spin_lock_irqsave(&port->lock, flags);
1804 spin_unlock_irqrestore(&port->lock, flags);
1809 static void sci_shutdown(struct uart_port *port)
1811 struct sci_port *s = to_sci_port(port);
1812 unsigned long flags;
1814 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1816 spin_lock_irqsave(&port->lock, flags);
1819 spin_unlock_irqrestore(&port->lock, flags);
1825 static unsigned int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
1828 if (s->sampling_rate)
1829 return DIV_ROUND_CLOSEST(freq, s->sampling_rate * bps) - 1;
1831 /* Warn, but use a safe default */
1834 return ((freq + 16 * bps) / (32 * bps) - 1);
1837 /* calculate frame length from SMR */
1838 static int sci_baud_calc_frame_len(unsigned int smr_val)
1842 if (smr_val & SCSMR_CHR)
1844 if (smr_val & SCSMR_PE)
1846 if (smr_val & SCSMR_STOP)
1853 /* calculate sample rate, BRR, and clock select for HSCIF */
1854 static void sci_baud_calc_hscif(unsigned int bps, unsigned long freq,
1855 int *brr, unsigned int *srr,
1856 unsigned int *cks, int frame_len)
1858 int sr, c, br, err, recv_margin;
1859 int min_err = 1000; /* 100% */
1860 int recv_max_margin = 0;
1862 /* Find the combination of sample rate and clock select with the
1863 smallest deviation from the desired baud rate. */
1864 for (sr = 8; sr <= 32; sr++) {
1865 for (c = 0; c <= 3; c++) {
1866 /* integerized formulas from HSCIF documentation */
1867 br = DIV_ROUND_CLOSEST(freq, (sr *
1868 (1 << (2 * c + 1)) * bps)) - 1;
1869 br = clamp(br, 0, 255);
1870 err = DIV_ROUND_CLOSEST(freq, ((br + 1) * bps * sr *
1871 (1 << (2 * c + 1)) / 1000)) -
1874 * M: Receive margin (%)
1875 * N: Ratio of bit rate to clock (N = sampling rate)
1876 * D: Clock duty (D = 0 to 1.0)
1877 * L: Frame length (L = 9 to 12)
1878 * F: Absolute value of clock frequency deviation
1880 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
1881 * (|D - 0.5| / N * (1 + F))|
1882 * NOTE: Usually, treat D for 0.5, F is 0 by this
1885 recv_margin = abs((500 -
1886 DIV_ROUND_CLOSEST(1000, sr << 1)) / 10);
1887 if (abs(min_err) > abs(err)) {
1889 recv_max_margin = recv_margin;
1890 } else if ((min_err == err) &&
1891 (recv_margin > recv_max_margin))
1892 recv_max_margin = recv_margin;
1902 if (min_err == 1000) {
1911 static void sci_reset(struct uart_port *port)
1913 struct plat_sci_reg *reg;
1914 unsigned int status;
1917 status = serial_port_in(port, SCxSR);
1918 } while (!(status & SCxSR_TEND(port)));
1920 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1922 reg = sci_getreg(port, SCFCR);
1924 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1927 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1928 struct ktermios *old)
1930 struct sci_port *s = to_sci_port(port);
1931 struct plat_sci_reg *reg;
1932 unsigned int baud, smr_val = 0, max_baud, cks = 0;
1934 unsigned int srr = 15;
1936 if ((termios->c_cflag & CSIZE) == CS7)
1937 smr_val |= SCSMR_CHR;
1938 if (termios->c_cflag & PARENB)
1939 smr_val |= SCSMR_PE;
1940 if (termios->c_cflag & PARODD)
1941 smr_val |= SCSMR_PE | SCSMR_ODD;
1942 if (termios->c_cflag & CSTOPB)
1943 smr_val |= SCSMR_STOP;
1946 * earlyprintk comes here early on with port->uartclk set to zero.
1947 * the clock framework is not up and running at this point so here
1948 * we assume that 115200 is the maximum baud rate. please note that
1949 * the baud rate is not programmed during earlyprintk - it is assumed
1950 * that the previous boot loader has enabled required clocks and
1951 * setup the baud rate generator hardware for us already.
1953 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1955 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1956 if (likely(baud && port->uartclk)) {
1957 if (s->cfg->type == PORT_HSCIF) {
1958 int frame_len = sci_baud_calc_frame_len(smr_val);
1959 sci_baud_calc_hscif(baud, port->uartclk, &t, &srr,
1962 t = sci_scbrr_calc(s, baud, port->uartclk);
1963 for (cks = 0; t >= 256 && cks <= 3; cks++)
1972 smr_val |= serial_port_in(port, SCSMR) & SCSMR_CKS;
1974 uart_update_timeout(port, termios->c_cflag, baud);
1976 dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
1977 __func__, smr_val, cks, t, s->cfg->scscr);
1980 serial_port_out(port, SCSMR, (smr_val & ~SCSMR_CKS) | cks);
1981 serial_port_out(port, SCBRR, t);
1982 reg = sci_getreg(port, HSSRR);
1984 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
1985 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1987 serial_port_out(port, SCSMR, smr_val);
1989 sci_init_pins(port, termios->c_cflag);
1991 reg = sci_getreg(port, SCFCR);
1993 unsigned short ctrl = serial_port_in(port, SCFCR);
1995 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
1996 if (termios->c_cflag & CRTSCTS)
2003 * As we've done a sci_reset() above, ensure we don't
2004 * interfere with the FIFOs while toggling MCE. As the
2005 * reset values could still be set, simply mask them out.
2007 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2009 serial_port_out(port, SCFCR, ctrl);
2012 serial_port_out(port, SCSCR, s->cfg->scscr);
2014 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2016 * Calculate delay for 2 DMA buffers (4 FIFO).
2017 * See serial_core.c::uart_update_timeout(). With 10
2018 * bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function
2019 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)."
2020 * Then below we calculate 5 jiffies (20ms) for 2 DMA buffers (4 FIFO
2021 * sizes), but when performing a faster transfer, value obtained by
2022 * this formula is may not enough. Therefore, if value is smaller than
2023 * 20msec, this sets 20msec as timeout of DMA.
2028 /* byte size and parity */
2029 switch (termios->c_cflag & CSIZE) {
2044 if (termios->c_cflag & CSTOPB)
2046 if (termios->c_cflag & PARENB)
2048 s->rx_timeout = DIV_ROUND_UP((s->buf_len_rx * 2 * bits * HZ) /
2050 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
2051 s->rx_timeout * 1000 / HZ, port->timeout);
2052 if (s->rx_timeout < msecs_to_jiffies(20))
2053 s->rx_timeout = msecs_to_jiffies(20);
2057 if ((termios->c_cflag & CREAD) != 0)
2060 sci_port_disable(s);
2063 static void sci_pm(struct uart_port *port, unsigned int state,
2064 unsigned int oldstate)
2066 struct sci_port *sci_port = to_sci_port(port);
2069 case UART_PM_STATE_OFF:
2070 sci_port_disable(sci_port);
2073 sci_port_enable(sci_port);
2078 static const char *sci_type(struct uart_port *port)
2080 switch (port->type) {
2098 static int sci_remap_port(struct uart_port *port)
2100 struct sci_port *sport = to_sci_port(port);
2103 * Nothing to do if there's already an established membase.
2108 if (port->flags & UPF_IOREMAP) {
2109 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
2110 if (unlikely(!port->membase)) {
2111 dev_err(port->dev, "can't remap port#%d\n", port->line);
2116 * For the simple (and majority of) cases where we don't
2117 * need to do any remapping, just cast the cookie
2120 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2126 static void sci_release_port(struct uart_port *port)
2128 struct sci_port *sport = to_sci_port(port);
2130 if (port->flags & UPF_IOREMAP) {
2131 iounmap(port->membase);
2132 port->membase = NULL;
2135 release_mem_region(port->mapbase, sport->reg_size);
2138 static int sci_request_port(struct uart_port *port)
2140 struct resource *res;
2141 struct sci_port *sport = to_sci_port(port);
2144 res = request_mem_region(port->mapbase, sport->reg_size,
2145 dev_name(port->dev));
2146 if (unlikely(res == NULL)) {
2147 dev_err(port->dev, "request_mem_region failed.");
2151 ret = sci_remap_port(port);
2152 if (unlikely(ret != 0)) {
2153 release_resource(res);
2160 static void sci_config_port(struct uart_port *port, int flags)
2162 if (flags & UART_CONFIG_TYPE) {
2163 struct sci_port *sport = to_sci_port(port);
2165 port->type = sport->cfg->type;
2166 sci_request_port(port);
2170 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2172 if (ser->baud_base < 2400)
2173 /* No paper tape reader for Mitch.. */
2179 static struct uart_ops sci_uart_ops = {
2180 .tx_empty = sci_tx_empty,
2181 .set_mctrl = sci_set_mctrl,
2182 .get_mctrl = sci_get_mctrl,
2183 .start_tx = sci_start_tx,
2184 .stop_tx = sci_stop_tx,
2185 .stop_rx = sci_stop_rx,
2186 .break_ctl = sci_break_ctl,
2187 .startup = sci_startup,
2188 .shutdown = sci_shutdown,
2189 .set_termios = sci_set_termios,
2192 .release_port = sci_release_port,
2193 .request_port = sci_request_port,
2194 .config_port = sci_config_port,
2195 .verify_port = sci_verify_port,
2196 #ifdef CONFIG_CONSOLE_POLL
2197 .poll_get_char = sci_poll_get_char,
2198 .poll_put_char = sci_poll_put_char,
2202 static int sci_init_single(struct platform_device *dev,
2203 struct sci_port *sci_port, unsigned int index,
2204 struct plat_sci_port *p, bool early)
2206 struct uart_port *port = &sci_port->port;
2207 const struct resource *res;
2213 port->ops = &sci_uart_ops;
2214 port->iotype = UPIO_MEM;
2217 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2221 port->mapbase = res->start;
2222 sci_port->reg_size = resource_size(res);
2224 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2225 sci_port->irqs[i] = platform_get_irq(dev, i);
2227 /* The SCI generates several interrupts. They can be muxed together or
2228 * connected to different interrupt lines. In the muxed case only one
2229 * interrupt resource is specified. In the non-muxed case three or four
2230 * interrupt resources are specified, as the BRI interrupt is optional.
2232 if (sci_port->irqs[0] < 0)
2235 if (sci_port->irqs[1] < 0) {
2236 sci_port->irqs[1] = sci_port->irqs[0];
2237 sci_port->irqs[2] = sci_port->irqs[0];
2238 sci_port->irqs[3] = sci_port->irqs[0];
2241 if (p->regtype == SCIx_PROBE_REGTYPE) {
2242 ret = sci_probe_regmap(p);
2249 port->fifosize = 256;
2250 sci_port->overrun_reg = SCxSR;
2251 sci_port->overrun_mask = SCIFA_ORER;
2252 sci_port->sampling_rate = 16;
2255 port->fifosize = 128;
2256 sci_port->overrun_reg = SCLSR;
2257 sci_port->overrun_mask = SCLSR_ORER;
2258 sci_port->sampling_rate = 0;
2261 port->fifosize = 64;
2262 sci_port->overrun_reg = SCxSR;
2263 sci_port->overrun_mask = SCIFA_ORER;
2264 sci_port->sampling_rate = 16;
2267 port->fifosize = 16;
2268 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) {
2269 sci_port->overrun_reg = SCxSR;
2270 sci_port->overrun_mask = SCIFA_ORER;
2271 sci_port->sampling_rate = 16;
2273 sci_port->overrun_reg = SCLSR;
2274 sci_port->overrun_mask = SCLSR_ORER;
2275 sci_port->sampling_rate = 32;
2280 sci_port->overrun_reg = SCxSR;
2281 sci_port->overrun_mask = SCI_ORER;
2282 sci_port->sampling_rate = 32;
2286 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2287 * match the SoC datasheet, this should be investigated. Let platform
2288 * data override the sampling rate for now.
2290 if (p->sampling_rate)
2291 sci_port->sampling_rate = p->sampling_rate;
2294 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
2295 if (IS_ERR(sci_port->iclk)) {
2296 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
2297 if (IS_ERR(sci_port->iclk)) {
2298 dev_err(&dev->dev, "can't get iclk\n");
2299 return PTR_ERR(sci_port->iclk);
2304 * The function clock is optional, ignore it if we can't
2307 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
2308 if (IS_ERR(sci_port->fclk))
2309 sci_port->fclk = NULL;
2311 port->dev = &dev->dev;
2313 pm_runtime_enable(&dev->dev);
2316 sci_port->break_timer.data = (unsigned long)sci_port;
2317 sci_port->break_timer.function = sci_break_timer;
2318 init_timer(&sci_port->break_timer);
2321 * Establish some sensible defaults for the error detection.
2323 if (p->type == PORT_SCI) {
2324 sci_port->error_mask = SCI_DEFAULT_ERROR_MASK;
2325 sci_port->error_clear = SCI_ERROR_CLEAR;
2327 sci_port->error_mask = SCIF_DEFAULT_ERROR_MASK;
2328 sci_port->error_clear = SCIF_ERROR_CLEAR;
2332 * Make the error mask inclusive of overrun detection, if
2335 if (sci_port->overrun_reg == SCxSR) {
2336 sci_port->error_mask |= sci_port->overrun_mask;
2337 sci_port->error_clear &= ~sci_port->overrun_mask;
2340 port->type = p->type;
2341 port->flags = UPF_FIXED_PORT | p->flags;
2342 port->regshift = p->regshift;
2345 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2346 * for the multi-IRQ ports, which is where we are primarily
2347 * concerned with the shutdown path synchronization.
2349 * For the muxed case there's nothing more to do.
2351 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
2354 port->serial_in = sci_serial_in;
2355 port->serial_out = sci_serial_out;
2357 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2358 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2359 p->dma_slave_tx, p->dma_slave_rx);
2364 static void sci_cleanup_single(struct sci_port *port)
2366 clk_put(port->iclk);
2367 clk_put(port->fclk);
2369 pm_runtime_disable(port->port.dev);
2372 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2373 static void serial_console_putchar(struct uart_port *port, int ch)
2375 sci_poll_put_char(port, ch);
2379 * Print a string to the serial port trying not to disturb
2380 * any possible real use of the port...
2382 static void serial_console_write(struct console *co, const char *s,
2385 struct sci_port *sci_port = &sci_ports[co->index];
2386 struct uart_port *port = &sci_port->port;
2387 unsigned short bits, ctrl;
2388 unsigned long flags;
2391 local_irq_save(flags);
2394 else if (oops_in_progress)
2395 locked = spin_trylock(&port->lock);
2397 spin_lock(&port->lock);
2399 /* first save the SCSCR then disable the interrupts */
2400 ctrl = serial_port_in(port, SCSCR);
2401 serial_port_out(port, SCSCR, sci_port->cfg->scscr);
2403 uart_console_write(port, s, count, serial_console_putchar);
2405 /* wait until fifo is empty and last bit has been transmitted */
2406 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
2407 while ((serial_port_in(port, SCxSR) & bits) != bits)
2410 /* restore the SCSCR */
2411 serial_port_out(port, SCSCR, ctrl);
2414 spin_unlock(&port->lock);
2415 local_irq_restore(flags);
2418 static int serial_console_setup(struct console *co, char *options)
2420 struct sci_port *sci_port;
2421 struct uart_port *port;
2429 * Refuse to handle any bogus ports.
2431 if (co->index < 0 || co->index >= SCI_NPORTS)
2434 sci_port = &sci_ports[co->index];
2435 port = &sci_port->port;
2438 * Refuse to handle uninitialized ports.
2443 ret = sci_remap_port(port);
2444 if (unlikely(ret != 0))
2448 uart_parse_options(options, &baud, &parity, &bits, &flow);
2450 return uart_set_options(port, co, baud, parity, bits, flow);
2453 static struct console serial_console = {
2455 .device = uart_console_device,
2456 .write = serial_console_write,
2457 .setup = serial_console_setup,
2458 .flags = CON_PRINTBUFFER,
2460 .data = &sci_uart_driver,
2463 static struct console early_serial_console = {
2464 .name = "early_ttySC",
2465 .write = serial_console_write,
2466 .flags = CON_PRINTBUFFER,
2470 static char early_serial_buf[32];
2472 static int sci_probe_earlyprintk(struct platform_device *pdev)
2474 struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
2476 if (early_serial_console.data)
2479 early_serial_console.index = pdev->id;
2481 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
2483 serial_console_setup(&early_serial_console, early_serial_buf);
2485 if (!strstr(early_serial_buf, "keep"))
2486 early_serial_console.flags |= CON_BOOT;
2488 register_console(&early_serial_console);
2492 #define SCI_CONSOLE (&serial_console)
2495 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
2500 #define SCI_CONSOLE NULL
2502 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
2504 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
2506 static struct uart_driver sci_uart_driver = {
2507 .owner = THIS_MODULE,
2508 .driver_name = "sci",
2509 .dev_name = "ttySC",
2511 .minor = SCI_MINOR_START,
2513 .cons = SCI_CONSOLE,
2516 static int sci_remove(struct platform_device *dev)
2518 struct sci_port *port = platform_get_drvdata(dev);
2520 cpufreq_unregister_notifier(&port->freq_transition,
2521 CPUFREQ_TRANSITION_NOTIFIER);
2523 uart_remove_one_port(&sci_uart_driver, &port->port);
2525 sci_cleanup_single(port);
2530 struct sci_port_info {
2532 unsigned int regtype;
2535 static const struct of_device_id of_sci_match[] = {
2537 .compatible = "renesas,scif",
2538 .data = &(const struct sci_port_info) {
2540 .regtype = SCIx_SH4_SCIF_REGTYPE,
2543 .compatible = "renesas,scifa",
2544 .data = &(const struct sci_port_info) {
2546 .regtype = SCIx_SCIFA_REGTYPE,
2549 .compatible = "renesas,scifb",
2550 .data = &(const struct sci_port_info) {
2552 .regtype = SCIx_SCIFB_REGTYPE,
2555 .compatible = "renesas,hscif",
2556 .data = &(const struct sci_port_info) {
2558 .regtype = SCIx_HSCIF_REGTYPE,
2561 .compatible = "renesas,sci",
2562 .data = &(const struct sci_port_info) {
2564 .regtype = SCIx_SCI_REGTYPE,
2570 MODULE_DEVICE_TABLE(of, of_sci_match);
2572 static struct plat_sci_port *
2573 sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id)
2575 struct device_node *np = pdev->dev.of_node;
2576 const struct of_device_id *match;
2577 const struct sci_port_info *info;
2578 struct plat_sci_port *p;
2581 if (!IS_ENABLED(CONFIG_OF) || !np)
2584 match = of_match_node(of_sci_match, pdev->dev.of_node);
2590 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
2592 dev_err(&pdev->dev, "failed to allocate DT config data\n");
2596 /* Get the line number for the aliases node. */
2597 id = of_alias_get_id(np, "serial");
2599 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
2605 p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
2606 p->type = info->type;
2607 p->regtype = info->regtype;
2608 p->scscr = SCSCR_RE | SCSCR_TE;
2613 static int sci_probe_single(struct platform_device *dev,
2615 struct plat_sci_port *p,
2616 struct sci_port *sciport)
2621 if (unlikely(index >= SCI_NPORTS)) {
2622 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
2623 index+1, SCI_NPORTS);
2624 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
2628 ret = sci_init_single(dev, sciport, index, p, false);
2632 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2634 sci_cleanup_single(sciport);
2641 static int sci_probe(struct platform_device *dev)
2643 struct plat_sci_port *p;
2644 struct sci_port *sp;
2645 unsigned int dev_id;
2649 * If we've come here via earlyprintk initialization, head off to
2650 * the special early probe. We don't have sufficient device state
2651 * to make it beyond this yet.
2653 if (is_early_platform_device(dev))
2654 return sci_probe_earlyprintk(dev);
2656 if (dev->dev.of_node) {
2657 p = sci_parse_dt(dev, &dev_id);
2661 p = dev->dev.platform_data;
2663 dev_err(&dev->dev, "no platform data supplied\n");
2670 sp = &sci_ports[dev_id];
2671 platform_set_drvdata(dev, sp);
2673 ret = sci_probe_single(dev, dev_id, p, sp);
2677 sp->freq_transition.notifier_call = sci_notifier;
2679 ret = cpufreq_register_notifier(&sp->freq_transition,
2680 CPUFREQ_TRANSITION_NOTIFIER);
2681 if (unlikely(ret < 0)) {
2682 uart_remove_one_port(&sci_uart_driver, &sp->port);
2683 sci_cleanup_single(sp);
2687 #ifdef CONFIG_SH_STANDARD_BIOS
2688 sh_bios_gdb_detach();
2694 static __maybe_unused int sci_suspend(struct device *dev)
2696 struct sci_port *sport = dev_get_drvdata(dev);
2699 uart_suspend_port(&sci_uart_driver, &sport->port);
2704 static __maybe_unused int sci_resume(struct device *dev)
2706 struct sci_port *sport = dev_get_drvdata(dev);
2709 uart_resume_port(&sci_uart_driver, &sport->port);
2714 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
2716 static struct platform_driver sci_driver = {
2718 .remove = sci_remove,
2721 .pm = &sci_dev_pm_ops,
2722 .of_match_table = of_match_ptr(of_sci_match),
2726 static int __init sci_init(void)
2730 pr_info("%s\n", banner);
2732 ret = uart_register_driver(&sci_uart_driver);
2733 if (likely(ret == 0)) {
2734 ret = platform_driver_register(&sci_driver);
2736 uart_unregister_driver(&sci_uart_driver);
2742 static void __exit sci_exit(void)
2744 platform_driver_unregister(&sci_driver);
2745 uart_unregister_driver(&sci_uart_driver);
2748 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2749 early_platform_init_buffer("earlyprintk", &sci_driver,
2750 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2752 module_init(sci_init);
2753 module_exit(sci_exit);
2755 MODULE_LICENSE("GPL");
2756 MODULE_ALIAS("platform:sh-sci");
2757 MODULE_AUTHOR("Paul Mundt");
2758 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");