2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 * Copyright (C) 2002 - 2011 Paul Mundt
5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
7 * based off of the old drivers/char/sh-sci.c by:
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
14 * Removed SH7300 support (Jul 2007).
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
20 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
26 #include <linux/clk.h>
27 #include <linux/console.h>
28 #include <linux/ctype.h>
29 #include <linux/cpufreq.h>
30 #include <linux/delay.h>
31 #include <linux/dmaengine.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/err.h>
34 #include <linux/errno.h>
35 #include <linux/init.h>
36 #include <linux/interrupt.h>
37 #include <linux/ioport.h>
38 #include <linux/major.h>
39 #include <linux/module.h>
41 #include <linux/notifier.h>
43 #include <linux/platform_device.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/scatterlist.h>
46 #include <linux/serial.h>
47 #include <linux/serial_sci.h>
48 #include <linux/sh_dma.h>
49 #include <linux/slab.h>
50 #include <linux/string.h>
51 #include <linux/sysrq.h>
52 #include <linux/timer.h>
53 #include <linux/tty.h>
54 #include <linux/tty_flip.h>
57 #include <asm/sh_bios.h>
62 /* Offsets into the sci_port->irqs array */
70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
73 #define SCIx_IRQ_IS_MUXED(port) \
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
80 struct uart_port port;
82 /* Platform configuration */
83 struct plat_sci_port *cfg;
84 unsigned int overrun_reg;
85 unsigned int overrun_mask;
86 unsigned int error_mask;
87 unsigned int error_clear;
88 unsigned int sampling_rate;
89 resource_size_t reg_size;
92 struct timer_list break_timer;
100 int irqs[SCIx_NR_IRQS];
101 char *irqstr[SCIx_NR_IRQS];
103 struct dma_chan *chan_tx;
104 struct dma_chan *chan_rx;
106 #ifdef CONFIG_SERIAL_SH_SCI_DMA
107 dma_cookie_t cookie_tx;
108 dma_cookie_t cookie_rx[2];
109 dma_cookie_t active_rx;
110 dma_addr_t tx_dma_addr;
111 unsigned int tx_dma_len;
112 struct scatterlist sg_rx[2];
115 struct sh_dmae_slave param_tx;
116 struct sh_dmae_slave param_rx;
117 struct work_struct work_tx;
118 struct work_struct work_rx;
119 struct timer_list rx_timer;
120 unsigned int rx_timeout;
123 struct notifier_block freq_transition;
126 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
128 static struct sci_port sci_ports[SCI_NPORTS];
129 static struct uart_driver sci_uart_driver;
131 static inline struct sci_port *
132 to_sci_port(struct uart_port *uart)
134 return container_of(uart, struct sci_port, port);
137 struct plat_sci_reg {
141 /* Helper for invalidating specific entries of an inherited map. */
142 #define sci_reg_invalid { .offset = 0, .size = 0 }
144 static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
145 [SCIx_PROBE_REGTYPE] = {
146 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
150 * Common SCI definitions, dependent on the port's regshift
153 [SCIx_SCI_REGTYPE] = {
154 [SCSMR] = { 0x00, 8 },
155 [SCBRR] = { 0x01, 8 },
156 [SCSCR] = { 0x02, 8 },
157 [SCxTDR] = { 0x03, 8 },
158 [SCxSR] = { 0x04, 8 },
159 [SCxRDR] = { 0x05, 8 },
160 [SCFCR] = sci_reg_invalid,
161 [SCFDR] = sci_reg_invalid,
162 [SCTFDR] = sci_reg_invalid,
163 [SCRFDR] = sci_reg_invalid,
164 [SCSPTR] = sci_reg_invalid,
165 [SCLSR] = sci_reg_invalid,
166 [HSSRR] = sci_reg_invalid,
167 [SCPCR] = sci_reg_invalid,
168 [SCPDR] = sci_reg_invalid,
172 * Common definitions for legacy IrDA ports, dependent on
175 [SCIx_IRDA_REGTYPE] = {
176 [SCSMR] = { 0x00, 8 },
177 [SCBRR] = { 0x01, 8 },
178 [SCSCR] = { 0x02, 8 },
179 [SCxTDR] = { 0x03, 8 },
180 [SCxSR] = { 0x04, 8 },
181 [SCxRDR] = { 0x05, 8 },
182 [SCFCR] = { 0x06, 8 },
183 [SCFDR] = { 0x07, 16 },
184 [SCTFDR] = sci_reg_invalid,
185 [SCRFDR] = sci_reg_invalid,
186 [SCSPTR] = sci_reg_invalid,
187 [SCLSR] = sci_reg_invalid,
188 [HSSRR] = sci_reg_invalid,
189 [SCPCR] = sci_reg_invalid,
190 [SCPDR] = sci_reg_invalid,
194 * Common SCIFA definitions.
196 [SCIx_SCIFA_REGTYPE] = {
197 [SCSMR] = { 0x00, 16 },
198 [SCBRR] = { 0x04, 8 },
199 [SCSCR] = { 0x08, 16 },
200 [SCxTDR] = { 0x20, 8 },
201 [SCxSR] = { 0x14, 16 },
202 [SCxRDR] = { 0x24, 8 },
203 [SCFCR] = { 0x18, 16 },
204 [SCFDR] = { 0x1c, 16 },
205 [SCTFDR] = sci_reg_invalid,
206 [SCRFDR] = sci_reg_invalid,
207 [SCSPTR] = sci_reg_invalid,
208 [SCLSR] = sci_reg_invalid,
209 [HSSRR] = sci_reg_invalid,
210 [SCPCR] = { 0x30, 16 },
211 [SCPDR] = { 0x34, 16 },
215 * Common SCIFB definitions.
217 [SCIx_SCIFB_REGTYPE] = {
218 [SCSMR] = { 0x00, 16 },
219 [SCBRR] = { 0x04, 8 },
220 [SCSCR] = { 0x08, 16 },
221 [SCxTDR] = { 0x40, 8 },
222 [SCxSR] = { 0x14, 16 },
223 [SCxRDR] = { 0x60, 8 },
224 [SCFCR] = { 0x18, 16 },
225 [SCFDR] = sci_reg_invalid,
226 [SCTFDR] = { 0x38, 16 },
227 [SCRFDR] = { 0x3c, 16 },
228 [SCSPTR] = sci_reg_invalid,
229 [SCLSR] = sci_reg_invalid,
230 [HSSRR] = sci_reg_invalid,
231 [SCPCR] = { 0x30, 16 },
232 [SCPDR] = { 0x34, 16 },
236 * Common SH-2(A) SCIF definitions for ports with FIFO data
239 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
240 [SCSMR] = { 0x00, 16 },
241 [SCBRR] = { 0x04, 8 },
242 [SCSCR] = { 0x08, 16 },
243 [SCxTDR] = { 0x0c, 8 },
244 [SCxSR] = { 0x10, 16 },
245 [SCxRDR] = { 0x14, 8 },
246 [SCFCR] = { 0x18, 16 },
247 [SCFDR] = { 0x1c, 16 },
248 [SCTFDR] = sci_reg_invalid,
249 [SCRFDR] = sci_reg_invalid,
250 [SCSPTR] = { 0x20, 16 },
251 [SCLSR] = { 0x24, 16 },
252 [HSSRR] = sci_reg_invalid,
253 [SCPCR] = sci_reg_invalid,
254 [SCPDR] = sci_reg_invalid,
258 * Common SH-3 SCIF definitions.
260 [SCIx_SH3_SCIF_REGTYPE] = {
261 [SCSMR] = { 0x00, 8 },
262 [SCBRR] = { 0x02, 8 },
263 [SCSCR] = { 0x04, 8 },
264 [SCxTDR] = { 0x06, 8 },
265 [SCxSR] = { 0x08, 16 },
266 [SCxRDR] = { 0x0a, 8 },
267 [SCFCR] = { 0x0c, 8 },
268 [SCFDR] = { 0x0e, 16 },
269 [SCTFDR] = sci_reg_invalid,
270 [SCRFDR] = sci_reg_invalid,
271 [SCSPTR] = sci_reg_invalid,
272 [SCLSR] = sci_reg_invalid,
273 [HSSRR] = sci_reg_invalid,
274 [SCPCR] = sci_reg_invalid,
275 [SCPDR] = sci_reg_invalid,
279 * Common SH-4(A) SCIF(B) definitions.
281 [SCIx_SH4_SCIF_REGTYPE] = {
282 [SCSMR] = { 0x00, 16 },
283 [SCBRR] = { 0x04, 8 },
284 [SCSCR] = { 0x08, 16 },
285 [SCxTDR] = { 0x0c, 8 },
286 [SCxSR] = { 0x10, 16 },
287 [SCxRDR] = { 0x14, 8 },
288 [SCFCR] = { 0x18, 16 },
289 [SCFDR] = { 0x1c, 16 },
290 [SCTFDR] = sci_reg_invalid,
291 [SCRFDR] = sci_reg_invalid,
292 [SCSPTR] = { 0x20, 16 },
293 [SCLSR] = { 0x24, 16 },
294 [HSSRR] = sci_reg_invalid,
295 [SCPCR] = sci_reg_invalid,
296 [SCPDR] = sci_reg_invalid,
300 * Common HSCIF definitions.
302 [SCIx_HSCIF_REGTYPE] = {
303 [SCSMR] = { 0x00, 16 },
304 [SCBRR] = { 0x04, 8 },
305 [SCSCR] = { 0x08, 16 },
306 [SCxTDR] = { 0x0c, 8 },
307 [SCxSR] = { 0x10, 16 },
308 [SCxRDR] = { 0x14, 8 },
309 [SCFCR] = { 0x18, 16 },
310 [SCFDR] = { 0x1c, 16 },
311 [SCTFDR] = sci_reg_invalid,
312 [SCRFDR] = sci_reg_invalid,
313 [SCSPTR] = { 0x20, 16 },
314 [SCLSR] = { 0x24, 16 },
315 [HSSRR] = { 0x40, 16 },
316 [SCPCR] = sci_reg_invalid,
317 [SCPDR] = sci_reg_invalid,
321 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
324 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
325 [SCSMR] = { 0x00, 16 },
326 [SCBRR] = { 0x04, 8 },
327 [SCSCR] = { 0x08, 16 },
328 [SCxTDR] = { 0x0c, 8 },
329 [SCxSR] = { 0x10, 16 },
330 [SCxRDR] = { 0x14, 8 },
331 [SCFCR] = { 0x18, 16 },
332 [SCFDR] = { 0x1c, 16 },
333 [SCTFDR] = sci_reg_invalid,
334 [SCRFDR] = sci_reg_invalid,
335 [SCSPTR] = sci_reg_invalid,
336 [SCLSR] = { 0x24, 16 },
337 [HSSRR] = sci_reg_invalid,
338 [SCPCR] = sci_reg_invalid,
339 [SCPDR] = sci_reg_invalid,
343 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
346 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
347 [SCSMR] = { 0x00, 16 },
348 [SCBRR] = { 0x04, 8 },
349 [SCSCR] = { 0x08, 16 },
350 [SCxTDR] = { 0x0c, 8 },
351 [SCxSR] = { 0x10, 16 },
352 [SCxRDR] = { 0x14, 8 },
353 [SCFCR] = { 0x18, 16 },
354 [SCFDR] = { 0x1c, 16 },
355 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
356 [SCRFDR] = { 0x20, 16 },
357 [SCSPTR] = { 0x24, 16 },
358 [SCLSR] = { 0x28, 16 },
359 [HSSRR] = sci_reg_invalid,
360 [SCPCR] = sci_reg_invalid,
361 [SCPDR] = sci_reg_invalid,
365 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
368 [SCIx_SH7705_SCIF_REGTYPE] = {
369 [SCSMR] = { 0x00, 16 },
370 [SCBRR] = { 0x04, 8 },
371 [SCSCR] = { 0x08, 16 },
372 [SCxTDR] = { 0x20, 8 },
373 [SCxSR] = { 0x14, 16 },
374 [SCxRDR] = { 0x24, 8 },
375 [SCFCR] = { 0x18, 16 },
376 [SCFDR] = { 0x1c, 16 },
377 [SCTFDR] = sci_reg_invalid,
378 [SCRFDR] = sci_reg_invalid,
379 [SCSPTR] = sci_reg_invalid,
380 [SCLSR] = sci_reg_invalid,
381 [HSSRR] = sci_reg_invalid,
382 [SCPCR] = sci_reg_invalid,
383 [SCPDR] = sci_reg_invalid,
387 #define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
390 * The "offset" here is rather misleading, in that it refers to an enum
391 * value relative to the port mapping rather than the fixed offset
392 * itself, which needs to be manually retrieved from the platform's
393 * register map for the given port.
395 static unsigned int sci_serial_in(struct uart_port *p, int offset)
397 const struct plat_sci_reg *reg = sci_getreg(p, offset);
400 return ioread8(p->membase + (reg->offset << p->regshift));
401 else if (reg->size == 16)
402 return ioread16(p->membase + (reg->offset << p->regshift));
404 WARN(1, "Invalid register access\n");
409 static void sci_serial_out(struct uart_port *p, int offset, int value)
411 const struct plat_sci_reg *reg = sci_getreg(p, offset);
414 iowrite8(value, p->membase + (reg->offset << p->regshift));
415 else if (reg->size == 16)
416 iowrite16(value, p->membase + (reg->offset << p->regshift));
418 WARN(1, "Invalid register access\n");
421 static int sci_probe_regmap(struct plat_sci_port *cfg)
425 cfg->regtype = SCIx_SCI_REGTYPE;
428 cfg->regtype = SCIx_IRDA_REGTYPE;
431 cfg->regtype = SCIx_SCIFA_REGTYPE;
434 cfg->regtype = SCIx_SCIFB_REGTYPE;
438 * The SH-4 is a bit of a misnomer here, although that's
439 * where this particular port layout originated. This
440 * configuration (or some slight variation thereof)
441 * remains the dominant model for all SCIFs.
443 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
446 cfg->regtype = SCIx_HSCIF_REGTYPE;
449 pr_err("Can't probe register map for given port\n");
456 static void sci_port_enable(struct sci_port *sci_port)
458 if (!sci_port->port.dev)
461 pm_runtime_get_sync(sci_port->port.dev);
463 clk_prepare_enable(sci_port->iclk);
464 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
465 clk_prepare_enable(sci_port->fclk);
468 static void sci_port_disable(struct sci_port *sci_port)
470 if (!sci_port->port.dev)
473 /* Cancel the break timer to ensure that the timer handler will not try
474 * to access the hardware with clocks and power disabled. Reset the
475 * break flag to make the break debouncing state machine ready for the
478 del_timer_sync(&sci_port->break_timer);
479 sci_port->break_flag = 0;
481 clk_disable_unprepare(sci_port->fclk);
482 clk_disable_unprepare(sci_port->iclk);
484 pm_runtime_put_sync(sci_port->port.dev);
487 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
490 * Not all ports (such as SCIFA) will support REIE. Rather than
491 * special-casing the port type, we check the port initialization
492 * IRQ enable mask to see whether the IRQ is desired at all. If
493 * it's unset, it's logically inferred that there's no point in
496 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
499 static void sci_start_tx(struct uart_port *port)
501 struct sci_port *s = to_sci_port(port);
504 #ifdef CONFIG_SERIAL_SH_SCI_DMA
505 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
506 u16 new, scr = serial_port_in(port, SCSCR);
508 new = scr | SCSCR_TDRQE;
510 new = scr & ~SCSCR_TDRQE;
512 serial_port_out(port, SCSCR, new);
515 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
516 dma_submit_error(s->cookie_tx)) {
518 schedule_work(&s->work_tx);
522 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
523 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
524 ctrl = serial_port_in(port, SCSCR);
525 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
529 static void sci_stop_tx(struct uart_port *port)
533 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
534 ctrl = serial_port_in(port, SCSCR);
536 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
537 ctrl &= ~SCSCR_TDRQE;
541 serial_port_out(port, SCSCR, ctrl);
544 static void sci_start_rx(struct uart_port *port)
548 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
550 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
551 ctrl &= ~SCSCR_RDRQE;
553 serial_port_out(port, SCSCR, ctrl);
556 static void sci_stop_rx(struct uart_port *port)
560 ctrl = serial_port_in(port, SCSCR);
562 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
563 ctrl &= ~SCSCR_RDRQE;
565 ctrl &= ~port_rx_irq_mask(port);
567 serial_port_out(port, SCSCR, ctrl);
570 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
572 if (port->type == PORT_SCI) {
573 /* Just store the mask */
574 serial_port_out(port, SCxSR, mask);
575 } else if (to_sci_port(port)->overrun_mask == SCIFA_ORER) {
576 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
577 /* Only clear the status bits we want to clear */
578 serial_port_out(port, SCxSR,
579 serial_port_in(port, SCxSR) & mask);
581 /* Store the mask, clear parity/framing errors */
582 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
586 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
588 #ifdef CONFIG_CONSOLE_POLL
589 static int sci_poll_get_char(struct uart_port *port)
591 unsigned short status;
595 status = serial_port_in(port, SCxSR);
596 if (status & SCxSR_ERRORS(port)) {
597 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
603 if (!(status & SCxSR_RDxF(port)))
606 c = serial_port_in(port, SCxRDR);
609 serial_port_in(port, SCxSR);
610 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
616 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
618 unsigned short status;
621 status = serial_port_in(port, SCxSR);
622 } while (!(status & SCxSR_TDxE(port)));
624 serial_port_out(port, SCxTDR, c);
625 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
627 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
629 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
631 struct sci_port *s = to_sci_port(port);
632 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
635 * Use port-specific handler if provided.
637 if (s->cfg->ops && s->cfg->ops->init_pins) {
638 s->cfg->ops->init_pins(port, cflag);
643 * For the generic path SCSPTR is necessary. Bail out if that's
649 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
650 ((!(cflag & CRTSCTS)))) {
651 unsigned short status;
653 status = serial_port_in(port, SCSPTR);
654 status &= ~SCSPTR_CTSIO;
655 status |= SCSPTR_RTSIO;
656 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
660 static int sci_txfill(struct uart_port *port)
662 const struct plat_sci_reg *reg;
664 reg = sci_getreg(port, SCTFDR);
666 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
668 reg = sci_getreg(port, SCFDR);
670 return serial_port_in(port, SCFDR) >> 8;
672 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
675 static int sci_txroom(struct uart_port *port)
677 return port->fifosize - sci_txfill(port);
680 static int sci_rxfill(struct uart_port *port)
682 const struct plat_sci_reg *reg;
684 reg = sci_getreg(port, SCRFDR);
686 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
688 reg = sci_getreg(port, SCFDR);
690 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
692 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
696 * SCI helper for checking the state of the muxed port/RXD pins.
698 static inline int sci_rxd_in(struct uart_port *port)
700 struct sci_port *s = to_sci_port(port);
702 if (s->cfg->port_reg <= 0)
705 /* Cast for ARM damage */
706 return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
709 /* ********************************************************************** *
710 * the interrupt related routines *
711 * ********************************************************************** */
713 static void sci_transmit_chars(struct uart_port *port)
715 struct circ_buf *xmit = &port->state->xmit;
716 unsigned int stopped = uart_tx_stopped(port);
717 unsigned short status;
721 status = serial_port_in(port, SCxSR);
722 if (!(status & SCxSR_TDxE(port))) {
723 ctrl = serial_port_in(port, SCSCR);
724 if (uart_circ_empty(xmit))
728 serial_port_out(port, SCSCR, ctrl);
732 count = sci_txroom(port);
740 } else if (!uart_circ_empty(xmit) && !stopped) {
741 c = xmit->buf[xmit->tail];
742 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
747 serial_port_out(port, SCxTDR, c);
750 } while (--count > 0);
752 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
754 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
755 uart_write_wakeup(port);
756 if (uart_circ_empty(xmit)) {
759 ctrl = serial_port_in(port, SCSCR);
761 if (port->type != PORT_SCI) {
762 serial_port_in(port, SCxSR); /* Dummy read */
763 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
767 serial_port_out(port, SCSCR, ctrl);
771 /* On SH3, SCIF may read end-of-break as a space->mark char */
772 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
774 static void sci_receive_chars(struct uart_port *port)
776 struct sci_port *sci_port = to_sci_port(port);
777 struct tty_port *tport = &port->state->port;
778 int i, count, copied = 0;
779 unsigned short status;
782 status = serial_port_in(port, SCxSR);
783 if (!(status & SCxSR_RDxF(port)))
787 /* Don't copy more bytes than there is room for in the buffer */
788 count = tty_buffer_request_room(tport, sci_rxfill(port));
790 /* If for any reason we can't copy more data, we're done! */
794 if (port->type == PORT_SCI) {
795 char c = serial_port_in(port, SCxRDR);
796 if (uart_handle_sysrq_char(port, c) ||
797 sci_port->break_flag)
800 tty_insert_flip_char(tport, c, TTY_NORMAL);
802 for (i = 0; i < count; i++) {
803 char c = serial_port_in(port, SCxRDR);
805 status = serial_port_in(port, SCxSR);
806 #if defined(CONFIG_CPU_SH3)
807 /* Skip "chars" during break */
808 if (sci_port->break_flag) {
810 (status & SCxSR_FER(port))) {
815 /* Nonzero => end-of-break */
816 dev_dbg(port->dev, "debounce<%02x>\n", c);
817 sci_port->break_flag = 0;
824 #endif /* CONFIG_CPU_SH3 */
825 if (uart_handle_sysrq_char(port, c)) {
830 /* Store data and status */
831 if (status & SCxSR_FER(port)) {
833 port->icount.frame++;
834 dev_notice(port->dev, "frame error\n");
835 } else if (status & SCxSR_PER(port)) {
837 port->icount.parity++;
838 dev_notice(port->dev, "parity error\n");
842 tty_insert_flip_char(tport, c, flag);
846 serial_port_in(port, SCxSR); /* dummy read */
847 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
850 port->icount.rx += count;
854 /* Tell the rest of the system the news. New characters! */
855 tty_flip_buffer_push(tport);
857 serial_port_in(port, SCxSR); /* dummy read */
858 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
862 #define SCI_BREAK_JIFFIES (HZ/20)
865 * The sci generates interrupts during the break,
866 * 1 per millisecond or so during the break period, for 9600 baud.
867 * So dont bother disabling interrupts.
868 * But dont want more than 1 break event.
869 * Use a kernel timer to periodically poll the rx line until
870 * the break is finished.
872 static inline void sci_schedule_break_timer(struct sci_port *port)
874 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
877 /* Ensure that two consecutive samples find the break over. */
878 static void sci_break_timer(unsigned long data)
880 struct sci_port *port = (struct sci_port *)data;
882 if (sci_rxd_in(&port->port) == 0) {
883 port->break_flag = 1;
884 sci_schedule_break_timer(port);
885 } else if (port->break_flag == 1) {
887 port->break_flag = 2;
888 sci_schedule_break_timer(port);
890 port->break_flag = 0;
893 static int sci_handle_errors(struct uart_port *port)
896 unsigned short status = serial_port_in(port, SCxSR);
897 struct tty_port *tport = &port->state->port;
898 struct sci_port *s = to_sci_port(port);
900 /* Handle overruns */
901 if (status & s->overrun_mask) {
902 port->icount.overrun++;
905 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
908 dev_notice(port->dev, "overrun error\n");
911 if (status & SCxSR_FER(port)) {
912 if (sci_rxd_in(port) == 0) {
913 /* Notify of BREAK */
914 struct sci_port *sci_port = to_sci_port(port);
916 if (!sci_port->break_flag) {
919 sci_port->break_flag = 1;
920 sci_schedule_break_timer(sci_port);
922 /* Do sysrq handling. */
923 if (uart_handle_break(port))
926 dev_dbg(port->dev, "BREAK detected\n");
928 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
934 port->icount.frame++;
936 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
939 dev_notice(port->dev, "frame error\n");
943 if (status & SCxSR_PER(port)) {
945 port->icount.parity++;
947 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
950 dev_notice(port->dev, "parity error\n");
954 tty_flip_buffer_push(tport);
959 static int sci_handle_fifo_overrun(struct uart_port *port)
961 struct tty_port *tport = &port->state->port;
962 struct sci_port *s = to_sci_port(port);
963 const struct plat_sci_reg *reg;
967 reg = sci_getreg(port, s->overrun_reg);
971 status = serial_port_in(port, s->overrun_reg);
972 if (status & s->overrun_mask) {
973 status &= ~s->overrun_mask;
974 serial_port_out(port, s->overrun_reg, status);
976 port->icount.overrun++;
978 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
979 tty_flip_buffer_push(tport);
981 dev_dbg(port->dev, "overrun error\n");
988 static int sci_handle_breaks(struct uart_port *port)
991 unsigned short status = serial_port_in(port, SCxSR);
992 struct tty_port *tport = &port->state->port;
993 struct sci_port *s = to_sci_port(port);
995 if (uart_handle_break(port))
998 if (!s->break_flag && status & SCxSR_BRK(port)) {
999 #if defined(CONFIG_CPU_SH3)
1000 /* Debounce break */
1006 /* Notify of BREAK */
1007 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
1010 dev_dbg(port->dev, "BREAK detected\n");
1014 tty_flip_buffer_push(tport);
1016 copied += sci_handle_fifo_overrun(port);
1021 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1022 static void sci_dma_tx_complete(void *arg)
1024 struct sci_port *s = arg;
1025 struct uart_port *port = &s->port;
1026 struct circ_buf *xmit = &port->state->xmit;
1027 unsigned long flags;
1029 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1031 spin_lock_irqsave(&port->lock, flags);
1033 xmit->tail += s->tx_dma_len;
1034 xmit->tail &= UART_XMIT_SIZE - 1;
1036 port->icount.tx += s->tx_dma_len;
1038 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1039 uart_write_wakeup(port);
1041 if (!uart_circ_empty(xmit)) {
1043 schedule_work(&s->work_tx);
1045 s->cookie_tx = -EINVAL;
1046 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1047 u16 ctrl = serial_port_in(port, SCSCR);
1048 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1052 spin_unlock_irqrestore(&port->lock, flags);
1055 /* Locking: called with port lock held */
1056 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1058 struct uart_port *port = &s->port;
1059 struct tty_port *tport = &port->state->port;
1062 copied = tty_insert_flip_string(tport, buf, count);
1063 if (copied < count) {
1064 dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n",
1066 port->icount.buf_overrun++;
1069 port->icount.rx += copied;
1074 static int sci_dma_rx_find_active(struct sci_port *s)
1078 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1079 if (s->active_rx == s->cookie_rx[i])
1082 dev_err(s->port.dev, "%s: Rx cookie %d not found!\n", __func__,
1087 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1089 struct dma_chan *chan = s->chan_rx;
1090 struct uart_port *port = &s->port;
1091 unsigned long flags;
1093 spin_lock_irqsave(&port->lock, flags);
1095 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1096 spin_unlock_irqrestore(&port->lock, flags);
1097 dmaengine_terminate_all(chan);
1098 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1099 sg_dma_address(&s->sg_rx[0]));
1100 dma_release_channel(chan);
1105 static void sci_dma_rx_complete(void *arg)
1107 struct sci_port *s = arg;
1108 struct uart_port *port = &s->port;
1109 unsigned long flags;
1110 int active, count = 0;
1112 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1115 spin_lock_irqsave(&port->lock, flags);
1117 active = sci_dma_rx_find_active(s);
1119 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1121 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1123 spin_unlock_irqrestore(&port->lock, flags);
1126 tty_flip_buffer_push(&port->state->port);
1128 schedule_work(&s->work_rx);
1131 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1133 struct dma_chan *chan = s->chan_tx;
1134 struct uart_port *port = &s->port;
1135 unsigned long flags;
1137 spin_lock_irqsave(&port->lock, flags);
1139 s->cookie_tx = -EINVAL;
1140 spin_unlock_irqrestore(&port->lock, flags);
1141 dmaengine_terminate_all(chan);
1142 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1144 dma_release_channel(chan);
1149 static void sci_submit_rx(struct sci_port *s)
1151 struct dma_chan *chan = s->chan_rx;
1154 for (i = 0; i < 2; i++) {
1155 struct scatterlist *sg = &s->sg_rx[i];
1156 struct dma_async_tx_descriptor *desc;
1158 desc = dmaengine_prep_slave_sg(chan,
1159 sg, 1, DMA_DEV_TO_MEM,
1160 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1164 desc->callback = sci_dma_rx_complete;
1165 desc->callback_param = s;
1166 s->cookie_rx[i] = dmaengine_submit(desc);
1167 if (dma_submit_error(s->cookie_rx[i]))
1170 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1171 s->cookie_rx[i], i);
1174 s->active_rx = s->cookie_rx[0];
1176 dma_async_issue_pending(chan);
1181 dmaengine_terminate_all(chan);
1182 for (i = 0; i < 2; i++)
1183 s->cookie_rx[i] = -EINVAL;
1184 s->active_rx = -EINVAL;
1185 dev_warn(s->port.dev, "Failed to re-start Rx DMA, using PIO\n");
1186 sci_rx_dma_release(s, true);
1189 static void work_fn_rx(struct work_struct *work)
1191 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1192 struct uart_port *port = &s->port;
1193 struct dma_async_tx_descriptor *desc;
1194 struct dma_tx_state state;
1195 enum dma_status status;
1196 unsigned long flags;
1199 spin_lock_irqsave(&port->lock, flags);
1200 new = sci_dma_rx_find_active(s);
1202 spin_unlock_irqrestore(&port->lock, flags);
1206 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1207 if (status != DMA_COMPLETE) {
1208 /* Handle incomplete DMA receive */
1209 struct dma_chan *chan = s->chan_rx;
1213 dmaengine_terminate_all(chan);
1214 read = sg_dma_len(&s->sg_rx[new]) - state.residue;
1215 dev_dbg(port->dev, "Read %u bytes with cookie %d\n", read,
1219 count = sci_dma_rx_push(s, s->rx_buf[new], read);
1221 tty_flip_buffer_push(&port->state->port);
1224 spin_unlock_irqrestore(&port->lock, flags);
1230 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[new], 1,
1232 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1236 desc->callback = sci_dma_rx_complete;
1237 desc->callback_param = s;
1238 s->cookie_rx[new] = dmaengine_submit(desc);
1239 if (dma_submit_error(s->cookie_rx[new]))
1242 s->active_rx = s->cookie_rx[!new];
1244 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1245 __func__, s->cookie_rx[new], new, s->active_rx);
1246 spin_unlock_irqrestore(&port->lock, flags);
1250 spin_unlock_irqrestore(&port->lock, flags);
1251 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1252 sci_rx_dma_release(s, true);
1255 static void work_fn_tx(struct work_struct *work)
1257 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1258 struct dma_async_tx_descriptor *desc;
1259 struct dma_chan *chan = s->chan_tx;
1260 struct uart_port *port = &s->port;
1261 struct circ_buf *xmit = &port->state->xmit;
1266 * Port xmit buffer is already mapped, and it is one page... Just adjust
1267 * offsets and lengths. Since it is a circular buffer, we have to
1268 * transmit till the end, and then the rest. Take the port lock to get a
1269 * consistent xmit buffer state.
1271 spin_lock_irq(&port->lock);
1272 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1));
1273 s->tx_dma_len = min_t(unsigned int,
1274 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1275 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1276 spin_unlock_irq(&port->lock);
1278 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1280 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1282 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1284 sci_tx_dma_release(s, true);
1288 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1291 spin_lock_irq(&port->lock);
1292 desc->callback = sci_dma_tx_complete;
1293 desc->callback_param = s;
1294 spin_unlock_irq(&port->lock);
1295 s->cookie_tx = dmaengine_submit(desc);
1296 if (dma_submit_error(s->cookie_tx)) {
1297 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1299 sci_tx_dma_release(s, true);
1303 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1304 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1306 dma_async_issue_pending(chan);
1309 static bool filter(struct dma_chan *chan, void *slave)
1311 struct sh_dmae_slave *param = slave;
1313 dev_dbg(chan->device->dev, "%s: slave ID %d\n",
1314 __func__, param->shdma_slave.slave_id);
1316 chan->private = ¶m->shdma_slave;
1320 static void rx_timer_fn(unsigned long arg)
1322 struct sci_port *s = (struct sci_port *)arg;
1323 struct uart_port *port = &s->port;
1324 u16 scr = serial_port_in(port, SCSCR);
1326 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1327 scr &= ~SCSCR_RDRQE;
1328 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1330 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1331 dev_dbg(port->dev, "DMA Rx timed out\n");
1332 schedule_work(&s->work_rx);
1335 static void sci_request_dma(struct uart_port *port)
1337 struct sci_port *s = to_sci_port(port);
1338 struct sh_dmae_slave *param;
1339 struct dma_chan *chan;
1340 dma_cap_mask_t mask;
1342 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1344 if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0)
1348 dma_cap_set(DMA_SLAVE, mask);
1350 param = &s->param_tx;
1352 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
1353 param->shdma_slave.slave_id = s->cfg->dma_slave_tx;
1355 s->cookie_tx = -EINVAL;
1356 chan = dma_request_channel(mask, filter, param);
1357 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1360 /* UART circular tx buffer is an aligned page. */
1361 s->tx_dma_addr = dma_map_single(chan->device->dev,
1362 port->state->xmit.buf,
1365 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1366 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1367 dma_release_channel(chan);
1370 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1371 __func__, UART_XMIT_SIZE,
1372 port->state->xmit.buf, &s->tx_dma_addr);
1375 INIT_WORK(&s->work_tx, work_fn_tx);
1378 param = &s->param_rx;
1380 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
1381 param->shdma_slave.slave_id = s->cfg->dma_slave_rx;
1383 chan = dma_request_channel(mask, filter, param);
1384 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1392 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1393 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1397 "Failed to allocate Rx dma buffer, using PIO\n");
1398 dma_release_channel(chan);
1404 for (i = 0; i < 2; i++) {
1405 struct scatterlist *sg = &s->sg_rx[i];
1407 sg_init_table(sg, 1);
1409 sg_dma_address(sg) = dma;
1410 sg->length = s->buf_len_rx;
1412 buf += s->buf_len_rx;
1413 dma += s->buf_len_rx;
1416 INIT_WORK(&s->work_rx, work_fn_rx);
1417 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1423 static void sci_free_dma(struct uart_port *port)
1425 struct sci_port *s = to_sci_port(port);
1428 sci_tx_dma_release(s, false);
1430 sci_rx_dma_release(s, false);
1433 static inline void sci_request_dma(struct uart_port *port)
1437 static inline void sci_free_dma(struct uart_port *port)
1442 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1444 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1445 struct uart_port *port = ptr;
1446 struct sci_port *s = to_sci_port(port);
1449 u16 scr = serial_port_in(port, SCSCR);
1450 u16 ssr = serial_port_in(port, SCxSR);
1452 /* Disable future Rx interrupts */
1453 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1454 disable_irq_nosync(irq);
1459 serial_port_out(port, SCSCR, scr);
1460 /* Clear current interrupt */
1461 serial_port_out(port, SCxSR,
1462 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1463 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
1464 jiffies, s->rx_timeout);
1465 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1471 /* I think sci_receive_chars has to be called irrespective
1472 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1475 sci_receive_chars(ptr);
1480 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1482 struct uart_port *port = ptr;
1483 unsigned long flags;
1485 spin_lock_irqsave(&port->lock, flags);
1486 sci_transmit_chars(port);
1487 spin_unlock_irqrestore(&port->lock, flags);
1492 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1494 struct uart_port *port = ptr;
1495 struct sci_port *s = to_sci_port(port);
1498 if (port->type == PORT_SCI) {
1499 if (sci_handle_errors(port)) {
1500 /* discard character in rx buffer */
1501 serial_port_in(port, SCxSR);
1502 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1505 sci_handle_fifo_overrun(port);
1507 sci_receive_chars(ptr);
1510 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1512 /* Kick the transmission */
1514 sci_tx_interrupt(irq, ptr);
1519 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1521 struct uart_port *port = ptr;
1524 sci_handle_breaks(port);
1525 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1530 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1532 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1533 struct uart_port *port = ptr;
1534 struct sci_port *s = to_sci_port(port);
1535 irqreturn_t ret = IRQ_NONE;
1537 ssr_status = serial_port_in(port, SCxSR);
1538 scr_status = serial_port_in(port, SCSCR);
1539 if (s->overrun_reg == SCxSR)
1540 orer_status = ssr_status;
1542 if (sci_getreg(port, s->overrun_reg)->size)
1543 orer_status = serial_port_in(port, s->overrun_reg);
1546 err_enabled = scr_status & port_rx_irq_mask(port);
1549 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1551 ret = sci_tx_interrupt(irq, ptr);
1554 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1557 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1558 (scr_status & SCSCR_RIE))
1559 ret = sci_rx_interrupt(irq, ptr);
1561 /* Error Interrupt */
1562 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1563 ret = sci_er_interrupt(irq, ptr);
1565 /* Break Interrupt */
1566 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1567 ret = sci_br_interrupt(irq, ptr);
1569 /* Overrun Interrupt */
1570 if (orer_status & s->overrun_mask) {
1571 sci_handle_fifo_overrun(port);
1579 * Here we define a transition notifier so that we can update all of our
1580 * ports' baud rate when the peripheral clock changes.
1582 static int sci_notifier(struct notifier_block *self,
1583 unsigned long phase, void *p)
1585 struct sci_port *sci_port;
1586 unsigned long flags;
1588 sci_port = container_of(self, struct sci_port, freq_transition);
1590 if (phase == CPUFREQ_POSTCHANGE) {
1591 struct uart_port *port = &sci_port->port;
1593 spin_lock_irqsave(&port->lock, flags);
1594 port->uartclk = clk_get_rate(sci_port->iclk);
1595 spin_unlock_irqrestore(&port->lock, flags);
1601 static const struct sci_irq_desc {
1603 irq_handler_t handler;
1604 } sci_irq_desc[] = {
1606 * Split out handlers, the default case.
1610 .handler = sci_er_interrupt,
1615 .handler = sci_rx_interrupt,
1620 .handler = sci_tx_interrupt,
1625 .handler = sci_br_interrupt,
1629 * Special muxed handler.
1633 .handler = sci_mpxed_interrupt,
1637 static int sci_request_irq(struct sci_port *port)
1639 struct uart_port *up = &port->port;
1642 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1643 const struct sci_irq_desc *desc;
1646 if (SCIx_IRQ_IS_MUXED(port)) {
1650 irq = port->irqs[i];
1653 * Certain port types won't support all of the
1654 * available interrupt sources.
1656 if (unlikely(irq < 0))
1660 desc = sci_irq_desc + i;
1661 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1662 dev_name(up->dev), desc->desc);
1663 if (!port->irqstr[j])
1666 ret = request_irq(irq, desc->handler, up->irqflags,
1667 port->irqstr[j], port);
1668 if (unlikely(ret)) {
1669 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1678 free_irq(port->irqs[i], port);
1682 kfree(port->irqstr[j]);
1687 static void sci_free_irq(struct sci_port *port)
1692 * Intentionally in reverse order so we iterate over the muxed
1695 for (i = 0; i < SCIx_NR_IRQS; i++) {
1696 int irq = port->irqs[i];
1699 * Certain port types won't support all of the available
1700 * interrupt sources.
1702 if (unlikely(irq < 0))
1705 free_irq(port->irqs[i], port);
1706 kfree(port->irqstr[i]);
1708 if (SCIx_IRQ_IS_MUXED(port)) {
1709 /* If there's only one IRQ, we're done. */
1715 static unsigned int sci_tx_empty(struct uart_port *port)
1717 unsigned short status = serial_port_in(port, SCxSR);
1718 unsigned short in_tx_fifo = sci_txfill(port);
1720 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1724 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1725 * CTS/RTS is supported in hardware by at least one port and controlled
1726 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1727 * handled via the ->init_pins() op, which is a bit of a one-way street,
1728 * lacking any ability to defer pin control -- this will later be
1729 * converted over to the GPIO framework).
1731 * Other modes (such as loopback) are supported generically on certain
1732 * port types, but not others. For these it's sufficient to test for the
1733 * existence of the support register and simply ignore the port type.
1735 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1737 if (mctrl & TIOCM_LOOP) {
1738 const struct plat_sci_reg *reg;
1741 * Standard loopback mode for SCFCR ports.
1743 reg = sci_getreg(port, SCFCR);
1745 serial_port_out(port, SCFCR,
1746 serial_port_in(port, SCFCR) |
1751 static unsigned int sci_get_mctrl(struct uart_port *port)
1754 * CTS/RTS is handled in hardware when supported, while nothing
1755 * else is wired up. Keep it simple and simply assert DSR/CAR.
1757 return TIOCM_DSR | TIOCM_CAR;
1760 static void sci_break_ctl(struct uart_port *port, int break_state)
1762 struct sci_port *s = to_sci_port(port);
1763 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1764 unsigned short scscr, scsptr;
1766 /* check wheter the port has SCSPTR */
1769 * Not supported by hardware. Most parts couple break and rx
1770 * interrupts together, with break detection always enabled.
1775 scsptr = serial_port_in(port, SCSPTR);
1776 scscr = serial_port_in(port, SCSCR);
1778 if (break_state == -1) {
1779 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1782 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1786 serial_port_out(port, SCSPTR, scsptr);
1787 serial_port_out(port, SCSCR, scscr);
1790 static int sci_startup(struct uart_port *port)
1792 struct sci_port *s = to_sci_port(port);
1793 unsigned long flags;
1796 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1798 ret = sci_request_irq(s);
1799 if (unlikely(ret < 0))
1802 sci_request_dma(port);
1804 spin_lock_irqsave(&port->lock, flags);
1807 spin_unlock_irqrestore(&port->lock, flags);
1812 static void sci_shutdown(struct uart_port *port)
1814 struct sci_port *s = to_sci_port(port);
1815 unsigned long flags;
1817 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1819 spin_lock_irqsave(&port->lock, flags);
1822 spin_unlock_irqrestore(&port->lock, flags);
1828 static unsigned int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
1831 if (s->sampling_rate)
1832 return DIV_ROUND_CLOSEST(freq, s->sampling_rate * bps) - 1;
1834 /* Warn, but use a safe default */
1837 return ((freq + 16 * bps) / (32 * bps) - 1);
1840 /* calculate frame length from SMR */
1841 static int sci_baud_calc_frame_len(unsigned int smr_val)
1845 if (smr_val & SCSMR_CHR)
1847 if (smr_val & SCSMR_PE)
1849 if (smr_val & SCSMR_STOP)
1856 /* calculate sample rate, BRR, and clock select for HSCIF */
1857 static void sci_baud_calc_hscif(unsigned int bps, unsigned long freq,
1858 int *brr, unsigned int *srr,
1859 unsigned int *cks, int frame_len)
1861 int sr, c, br, err, recv_margin;
1862 int min_err = 1000; /* 100% */
1863 int recv_max_margin = 0;
1865 /* Find the combination of sample rate and clock select with the
1866 smallest deviation from the desired baud rate. */
1867 for (sr = 8; sr <= 32; sr++) {
1868 for (c = 0; c <= 3; c++) {
1869 /* integerized formulas from HSCIF documentation */
1870 br = DIV_ROUND_CLOSEST(freq, (sr *
1871 (1 << (2 * c + 1)) * bps)) - 1;
1872 br = clamp(br, 0, 255);
1873 err = DIV_ROUND_CLOSEST(freq, ((br + 1) * bps * sr *
1874 (1 << (2 * c + 1)) / 1000)) -
1877 * M: Receive margin (%)
1878 * N: Ratio of bit rate to clock (N = sampling rate)
1879 * D: Clock duty (D = 0 to 1.0)
1880 * L: Frame length (L = 9 to 12)
1881 * F: Absolute value of clock frequency deviation
1883 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
1884 * (|D - 0.5| / N * (1 + F))|
1885 * NOTE: Usually, treat D for 0.5, F is 0 by this
1888 recv_margin = abs((500 -
1889 DIV_ROUND_CLOSEST(1000, sr << 1)) / 10);
1890 if (abs(min_err) > abs(err)) {
1892 recv_max_margin = recv_margin;
1893 } else if ((min_err == err) &&
1894 (recv_margin > recv_max_margin))
1895 recv_max_margin = recv_margin;
1905 if (min_err == 1000) {
1914 static void sci_reset(struct uart_port *port)
1916 const struct plat_sci_reg *reg;
1917 unsigned int status;
1920 status = serial_port_in(port, SCxSR);
1921 } while (!(status & SCxSR_TEND(port)));
1923 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1925 reg = sci_getreg(port, SCFCR);
1927 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1930 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1931 struct ktermios *old)
1933 struct sci_port *s = to_sci_port(port);
1934 const struct plat_sci_reg *reg;
1935 unsigned int baud, smr_val = 0, max_baud, cks = 0;
1937 unsigned int srr = 15;
1939 if ((termios->c_cflag & CSIZE) == CS7)
1940 smr_val |= SCSMR_CHR;
1941 if (termios->c_cflag & PARENB)
1942 smr_val |= SCSMR_PE;
1943 if (termios->c_cflag & PARODD)
1944 smr_val |= SCSMR_PE | SCSMR_ODD;
1945 if (termios->c_cflag & CSTOPB)
1946 smr_val |= SCSMR_STOP;
1949 * earlyprintk comes here early on with port->uartclk set to zero.
1950 * the clock framework is not up and running at this point so here
1951 * we assume that 115200 is the maximum baud rate. please note that
1952 * the baud rate is not programmed during earlyprintk - it is assumed
1953 * that the previous boot loader has enabled required clocks and
1954 * setup the baud rate generator hardware for us already.
1956 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1958 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1959 if (likely(baud && port->uartclk)) {
1960 if (s->cfg->type == PORT_HSCIF) {
1961 int frame_len = sci_baud_calc_frame_len(smr_val);
1962 sci_baud_calc_hscif(baud, port->uartclk, &t, &srr,
1965 t = sci_scbrr_calc(s, baud, port->uartclk);
1966 for (cks = 0; t >= 256 && cks <= 3; cks++)
1975 smr_val |= serial_port_in(port, SCSMR) & SCSMR_CKS;
1977 uart_update_timeout(port, termios->c_cflag, baud);
1979 dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
1980 __func__, smr_val, cks, t, s->cfg->scscr);
1983 serial_port_out(port, SCSMR, (smr_val & ~SCSMR_CKS) | cks);
1984 serial_port_out(port, SCBRR, t);
1985 reg = sci_getreg(port, HSSRR);
1987 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
1988 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1990 serial_port_out(port, SCSMR, smr_val);
1992 sci_init_pins(port, termios->c_cflag);
1994 reg = sci_getreg(port, SCFCR);
1996 unsigned short ctrl = serial_port_in(port, SCFCR);
1998 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
1999 if (termios->c_cflag & CRTSCTS)
2006 * As we've done a sci_reset() above, ensure we don't
2007 * interfere with the FIFOs while toggling MCE. As the
2008 * reset values could still be set, simply mask them out.
2010 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2012 serial_port_out(port, SCFCR, ctrl);
2015 serial_port_out(port, SCSCR, s->cfg->scscr);
2017 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2019 * Calculate delay for 2 DMA buffers (4 FIFO).
2020 * See serial_core.c::uart_update_timeout().
2021 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2022 * function calculates 1 jiffie for the data plus 5 jiffies for the
2023 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2024 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2025 * value obtained by this formula is too small. Therefore, if the value
2026 * is smaller than 20ms, use 20ms as the timeout value for DMA.
2031 /* byte size and parity */
2032 switch (termios->c_cflag & CSIZE) {
2047 if (termios->c_cflag & CSTOPB)
2049 if (termios->c_cflag & PARENB)
2051 s->rx_timeout = DIV_ROUND_UP((s->buf_len_rx * 2 * bits * HZ) /
2053 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
2054 s->rx_timeout * 1000 / HZ, port->timeout);
2055 if (s->rx_timeout < msecs_to_jiffies(20))
2056 s->rx_timeout = msecs_to_jiffies(20);
2060 if ((termios->c_cflag & CREAD) != 0)
2063 sci_port_disable(s);
2066 static void sci_pm(struct uart_port *port, unsigned int state,
2067 unsigned int oldstate)
2069 struct sci_port *sci_port = to_sci_port(port);
2072 case UART_PM_STATE_OFF:
2073 sci_port_disable(sci_port);
2076 sci_port_enable(sci_port);
2081 static const char *sci_type(struct uart_port *port)
2083 switch (port->type) {
2101 static int sci_remap_port(struct uart_port *port)
2103 struct sci_port *sport = to_sci_port(port);
2106 * Nothing to do if there's already an established membase.
2111 if (port->flags & UPF_IOREMAP) {
2112 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
2113 if (unlikely(!port->membase)) {
2114 dev_err(port->dev, "can't remap port#%d\n", port->line);
2119 * For the simple (and majority of) cases where we don't
2120 * need to do any remapping, just cast the cookie
2123 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2129 static void sci_release_port(struct uart_port *port)
2131 struct sci_port *sport = to_sci_port(port);
2133 if (port->flags & UPF_IOREMAP) {
2134 iounmap(port->membase);
2135 port->membase = NULL;
2138 release_mem_region(port->mapbase, sport->reg_size);
2141 static int sci_request_port(struct uart_port *port)
2143 struct resource *res;
2144 struct sci_port *sport = to_sci_port(port);
2147 res = request_mem_region(port->mapbase, sport->reg_size,
2148 dev_name(port->dev));
2149 if (unlikely(res == NULL)) {
2150 dev_err(port->dev, "request_mem_region failed.");
2154 ret = sci_remap_port(port);
2155 if (unlikely(ret != 0)) {
2156 release_resource(res);
2163 static void sci_config_port(struct uart_port *port, int flags)
2165 if (flags & UART_CONFIG_TYPE) {
2166 struct sci_port *sport = to_sci_port(port);
2168 port->type = sport->cfg->type;
2169 sci_request_port(port);
2173 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2175 if (ser->baud_base < 2400)
2176 /* No paper tape reader for Mitch.. */
2182 static struct uart_ops sci_uart_ops = {
2183 .tx_empty = sci_tx_empty,
2184 .set_mctrl = sci_set_mctrl,
2185 .get_mctrl = sci_get_mctrl,
2186 .start_tx = sci_start_tx,
2187 .stop_tx = sci_stop_tx,
2188 .stop_rx = sci_stop_rx,
2189 .break_ctl = sci_break_ctl,
2190 .startup = sci_startup,
2191 .shutdown = sci_shutdown,
2192 .set_termios = sci_set_termios,
2195 .release_port = sci_release_port,
2196 .request_port = sci_request_port,
2197 .config_port = sci_config_port,
2198 .verify_port = sci_verify_port,
2199 #ifdef CONFIG_CONSOLE_POLL
2200 .poll_get_char = sci_poll_get_char,
2201 .poll_put_char = sci_poll_put_char,
2205 static int sci_init_single(struct platform_device *dev,
2206 struct sci_port *sci_port, unsigned int index,
2207 struct plat_sci_port *p, bool early)
2209 struct uart_port *port = &sci_port->port;
2210 const struct resource *res;
2216 port->ops = &sci_uart_ops;
2217 port->iotype = UPIO_MEM;
2220 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2224 port->mapbase = res->start;
2225 sci_port->reg_size = resource_size(res);
2227 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2228 sci_port->irqs[i] = platform_get_irq(dev, i);
2230 /* The SCI generates several interrupts. They can be muxed together or
2231 * connected to different interrupt lines. In the muxed case only one
2232 * interrupt resource is specified. In the non-muxed case three or four
2233 * interrupt resources are specified, as the BRI interrupt is optional.
2235 if (sci_port->irqs[0] < 0)
2238 if (sci_port->irqs[1] < 0) {
2239 sci_port->irqs[1] = sci_port->irqs[0];
2240 sci_port->irqs[2] = sci_port->irqs[0];
2241 sci_port->irqs[3] = sci_port->irqs[0];
2244 if (p->regtype == SCIx_PROBE_REGTYPE) {
2245 ret = sci_probe_regmap(p);
2252 port->fifosize = 256;
2253 sci_port->overrun_reg = SCxSR;
2254 sci_port->overrun_mask = SCIFA_ORER;
2255 sci_port->sampling_rate = 16;
2258 port->fifosize = 128;
2259 sci_port->overrun_reg = SCLSR;
2260 sci_port->overrun_mask = SCLSR_ORER;
2261 sci_port->sampling_rate = 0;
2264 port->fifosize = 64;
2265 sci_port->overrun_reg = SCxSR;
2266 sci_port->overrun_mask = SCIFA_ORER;
2267 sci_port->sampling_rate = 16;
2270 port->fifosize = 16;
2271 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) {
2272 sci_port->overrun_reg = SCxSR;
2273 sci_port->overrun_mask = SCIFA_ORER;
2274 sci_port->sampling_rate = 16;
2276 sci_port->overrun_reg = SCLSR;
2277 sci_port->overrun_mask = SCLSR_ORER;
2278 sci_port->sampling_rate = 32;
2283 sci_port->overrun_reg = SCxSR;
2284 sci_port->overrun_mask = SCI_ORER;
2285 sci_port->sampling_rate = 32;
2289 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2290 * match the SoC datasheet, this should be investigated. Let platform
2291 * data override the sampling rate for now.
2293 if (p->sampling_rate)
2294 sci_port->sampling_rate = p->sampling_rate;
2297 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
2298 if (IS_ERR(sci_port->iclk)) {
2299 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
2300 if (IS_ERR(sci_port->iclk)) {
2301 dev_err(&dev->dev, "can't get iclk\n");
2302 return PTR_ERR(sci_port->iclk);
2307 * The function clock is optional, ignore it if we can't
2310 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
2311 if (IS_ERR(sci_port->fclk))
2312 sci_port->fclk = NULL;
2314 port->dev = &dev->dev;
2316 pm_runtime_enable(&dev->dev);
2319 sci_port->break_timer.data = (unsigned long)sci_port;
2320 sci_port->break_timer.function = sci_break_timer;
2321 init_timer(&sci_port->break_timer);
2324 * Establish some sensible defaults for the error detection.
2326 if (p->type == PORT_SCI) {
2327 sci_port->error_mask = SCI_DEFAULT_ERROR_MASK;
2328 sci_port->error_clear = SCI_ERROR_CLEAR;
2330 sci_port->error_mask = SCIF_DEFAULT_ERROR_MASK;
2331 sci_port->error_clear = SCIF_ERROR_CLEAR;
2335 * Make the error mask inclusive of overrun detection, if
2338 if (sci_port->overrun_reg == SCxSR) {
2339 sci_port->error_mask |= sci_port->overrun_mask;
2340 sci_port->error_clear &= ~sci_port->overrun_mask;
2343 port->type = p->type;
2344 port->flags = UPF_FIXED_PORT | p->flags;
2345 port->regshift = p->regshift;
2348 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2349 * for the multi-IRQ ports, which is where we are primarily
2350 * concerned with the shutdown path synchronization.
2352 * For the muxed case there's nothing more to do.
2354 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
2357 port->serial_in = sci_serial_in;
2358 port->serial_out = sci_serial_out;
2360 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2361 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2362 p->dma_slave_tx, p->dma_slave_rx);
2367 static void sci_cleanup_single(struct sci_port *port)
2369 clk_put(port->iclk);
2370 clk_put(port->fclk);
2372 pm_runtime_disable(port->port.dev);
2375 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2376 static void serial_console_putchar(struct uart_port *port, int ch)
2378 sci_poll_put_char(port, ch);
2382 * Print a string to the serial port trying not to disturb
2383 * any possible real use of the port...
2385 static void serial_console_write(struct console *co, const char *s,
2388 struct sci_port *sci_port = &sci_ports[co->index];
2389 struct uart_port *port = &sci_port->port;
2390 unsigned short bits, ctrl;
2391 unsigned long flags;
2394 local_irq_save(flags);
2397 else if (oops_in_progress)
2398 locked = spin_trylock(&port->lock);
2400 spin_lock(&port->lock);
2402 /* first save the SCSCR then disable the interrupts */
2403 ctrl = serial_port_in(port, SCSCR);
2404 serial_port_out(port, SCSCR, sci_port->cfg->scscr);
2406 uart_console_write(port, s, count, serial_console_putchar);
2408 /* wait until fifo is empty and last bit has been transmitted */
2409 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
2410 while ((serial_port_in(port, SCxSR) & bits) != bits)
2413 /* restore the SCSCR */
2414 serial_port_out(port, SCSCR, ctrl);
2417 spin_unlock(&port->lock);
2418 local_irq_restore(flags);
2421 static int serial_console_setup(struct console *co, char *options)
2423 struct sci_port *sci_port;
2424 struct uart_port *port;
2432 * Refuse to handle any bogus ports.
2434 if (co->index < 0 || co->index >= SCI_NPORTS)
2437 sci_port = &sci_ports[co->index];
2438 port = &sci_port->port;
2441 * Refuse to handle uninitialized ports.
2446 ret = sci_remap_port(port);
2447 if (unlikely(ret != 0))
2451 uart_parse_options(options, &baud, &parity, &bits, &flow);
2453 return uart_set_options(port, co, baud, parity, bits, flow);
2456 static struct console serial_console = {
2458 .device = uart_console_device,
2459 .write = serial_console_write,
2460 .setup = serial_console_setup,
2461 .flags = CON_PRINTBUFFER,
2463 .data = &sci_uart_driver,
2466 static struct console early_serial_console = {
2467 .name = "early_ttySC",
2468 .write = serial_console_write,
2469 .flags = CON_PRINTBUFFER,
2473 static char early_serial_buf[32];
2475 static int sci_probe_earlyprintk(struct platform_device *pdev)
2477 struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
2479 if (early_serial_console.data)
2482 early_serial_console.index = pdev->id;
2484 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
2486 serial_console_setup(&early_serial_console, early_serial_buf);
2488 if (!strstr(early_serial_buf, "keep"))
2489 early_serial_console.flags |= CON_BOOT;
2491 register_console(&early_serial_console);
2495 #define SCI_CONSOLE (&serial_console)
2498 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
2503 #define SCI_CONSOLE NULL
2505 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
2507 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
2509 static struct uart_driver sci_uart_driver = {
2510 .owner = THIS_MODULE,
2511 .driver_name = "sci",
2512 .dev_name = "ttySC",
2514 .minor = SCI_MINOR_START,
2516 .cons = SCI_CONSOLE,
2519 static int sci_remove(struct platform_device *dev)
2521 struct sci_port *port = platform_get_drvdata(dev);
2523 cpufreq_unregister_notifier(&port->freq_transition,
2524 CPUFREQ_TRANSITION_NOTIFIER);
2526 uart_remove_one_port(&sci_uart_driver, &port->port);
2528 sci_cleanup_single(port);
2533 struct sci_port_info {
2535 unsigned int regtype;
2538 static const struct of_device_id of_sci_match[] = {
2540 .compatible = "renesas,scif",
2541 .data = &(const struct sci_port_info) {
2543 .regtype = SCIx_SH4_SCIF_REGTYPE,
2546 .compatible = "renesas,scifa",
2547 .data = &(const struct sci_port_info) {
2549 .regtype = SCIx_SCIFA_REGTYPE,
2552 .compatible = "renesas,scifb",
2553 .data = &(const struct sci_port_info) {
2555 .regtype = SCIx_SCIFB_REGTYPE,
2558 .compatible = "renesas,hscif",
2559 .data = &(const struct sci_port_info) {
2561 .regtype = SCIx_HSCIF_REGTYPE,
2564 .compatible = "renesas,sci",
2565 .data = &(const struct sci_port_info) {
2567 .regtype = SCIx_SCI_REGTYPE,
2573 MODULE_DEVICE_TABLE(of, of_sci_match);
2575 static struct plat_sci_port *
2576 sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id)
2578 struct device_node *np = pdev->dev.of_node;
2579 const struct of_device_id *match;
2580 const struct sci_port_info *info;
2581 struct plat_sci_port *p;
2584 if (!IS_ENABLED(CONFIG_OF) || !np)
2587 match = of_match_node(of_sci_match, pdev->dev.of_node);
2593 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
2597 /* Get the line number for the aliases node. */
2598 id = of_alias_get_id(np, "serial");
2600 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
2606 p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
2607 p->type = info->type;
2608 p->regtype = info->regtype;
2609 p->scscr = SCSCR_RE | SCSCR_TE;
2614 static int sci_probe_single(struct platform_device *dev,
2616 struct plat_sci_port *p,
2617 struct sci_port *sciport)
2622 if (unlikely(index >= SCI_NPORTS)) {
2623 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
2624 index+1, SCI_NPORTS);
2625 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
2629 ret = sci_init_single(dev, sciport, index, p, false);
2633 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2635 sci_cleanup_single(sciport);
2642 static int sci_probe(struct platform_device *dev)
2644 struct plat_sci_port *p;
2645 struct sci_port *sp;
2646 unsigned int dev_id;
2650 * If we've come here via earlyprintk initialization, head off to
2651 * the special early probe. We don't have sufficient device state
2652 * to make it beyond this yet.
2654 if (is_early_platform_device(dev))
2655 return sci_probe_earlyprintk(dev);
2657 if (dev->dev.of_node) {
2658 p = sci_parse_dt(dev, &dev_id);
2662 p = dev->dev.platform_data;
2664 dev_err(&dev->dev, "no platform data supplied\n");
2671 sp = &sci_ports[dev_id];
2672 platform_set_drvdata(dev, sp);
2674 ret = sci_probe_single(dev, dev_id, p, sp);
2678 sp->freq_transition.notifier_call = sci_notifier;
2680 ret = cpufreq_register_notifier(&sp->freq_transition,
2681 CPUFREQ_TRANSITION_NOTIFIER);
2682 if (unlikely(ret < 0)) {
2683 uart_remove_one_port(&sci_uart_driver, &sp->port);
2684 sci_cleanup_single(sp);
2688 #ifdef CONFIG_SH_STANDARD_BIOS
2689 sh_bios_gdb_detach();
2695 static __maybe_unused int sci_suspend(struct device *dev)
2697 struct sci_port *sport = dev_get_drvdata(dev);
2700 uart_suspend_port(&sci_uart_driver, &sport->port);
2705 static __maybe_unused int sci_resume(struct device *dev)
2707 struct sci_port *sport = dev_get_drvdata(dev);
2710 uart_resume_port(&sci_uart_driver, &sport->port);
2715 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
2717 static struct platform_driver sci_driver = {
2719 .remove = sci_remove,
2722 .pm = &sci_dev_pm_ops,
2723 .of_match_table = of_match_ptr(of_sci_match),
2727 static int __init sci_init(void)
2731 pr_info("%s\n", banner);
2733 ret = uart_register_driver(&sci_uart_driver);
2734 if (likely(ret == 0)) {
2735 ret = platform_driver_register(&sci_driver);
2737 uart_unregister_driver(&sci_uart_driver);
2743 static void __exit sci_exit(void)
2745 platform_driver_unregister(&sci_driver);
2746 uart_unregister_driver(&sci_uart_driver);
2749 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2750 early_platform_init_buffer("earlyprintk", &sci_driver,
2751 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2753 module_init(sci_init);
2754 module_exit(sci_exit);
2756 MODULE_LICENSE("GPL");
2757 MODULE_ALIAS("platform:sh-sci");
2758 MODULE_AUTHOR("Paul Mundt");
2759 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");